1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_mdio.h> 14 #include <linux/of_net.h> 15 #include <linux/of_platform.h> 16 #include <linux/phylink.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/gpio/consumer.h> 21 #include <net/dsa.h> 22 23 #include "mt7530.h" 24 25 /* String, offset, and register size in bytes if different from 4 bytes */ 26 static const struct mt7530_mib_desc mt7530_mib[] = { 27 MIB_DESC(1, 0x00, "TxDrop"), 28 MIB_DESC(1, 0x04, "TxCrcErr"), 29 MIB_DESC(1, 0x08, "TxUnicast"), 30 MIB_DESC(1, 0x0c, "TxMulticast"), 31 MIB_DESC(1, 0x10, "TxBroadcast"), 32 MIB_DESC(1, 0x14, "TxCollision"), 33 MIB_DESC(1, 0x18, "TxSingleCollision"), 34 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 35 MIB_DESC(1, 0x20, "TxDeferred"), 36 MIB_DESC(1, 0x24, "TxLateCollision"), 37 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 38 MIB_DESC(1, 0x2c, "TxPause"), 39 MIB_DESC(1, 0x30, "TxPktSz64"), 40 MIB_DESC(1, 0x34, "TxPktSz65To127"), 41 MIB_DESC(1, 0x38, "TxPktSz128To255"), 42 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 43 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 44 MIB_DESC(1, 0x44, "Tx1024ToMax"), 45 MIB_DESC(2, 0x48, "TxBytes"), 46 MIB_DESC(1, 0x60, "RxDrop"), 47 MIB_DESC(1, 0x64, "RxFiltering"), 48 MIB_DESC(1, 0x6c, "RxMulticast"), 49 MIB_DESC(1, 0x70, "RxBroadcast"), 50 MIB_DESC(1, 0x74, "RxAlignErr"), 51 MIB_DESC(1, 0x78, "RxCrcErr"), 52 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 53 MIB_DESC(1, 0x80, "RxFragErr"), 54 MIB_DESC(1, 0x84, "RxOverSzErr"), 55 MIB_DESC(1, 0x88, "RxJabberErr"), 56 MIB_DESC(1, 0x8c, "RxPause"), 57 MIB_DESC(1, 0x90, "RxPktSz64"), 58 MIB_DESC(1, 0x94, "RxPktSz65To127"), 59 MIB_DESC(1, 0x98, "RxPktSz128To255"), 60 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 61 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 62 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 63 MIB_DESC(2, 0xa8, "RxBytes"), 64 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 65 MIB_DESC(1, 0xb4, "RxIngressDrop"), 66 MIB_DESC(1, 0xb8, "RxArlDrop"), 67 }; 68 69 static int 70 mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val) 71 { 72 int ret; 73 74 ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val); 75 if (ret < 0) 76 dev_err(priv->dev, 77 "failed to priv write register\n"); 78 return ret; 79 } 80 81 static u32 82 mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg) 83 { 84 int ret; 85 u32 val; 86 87 ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val); 88 if (ret < 0) { 89 dev_err(priv->dev, 90 "failed to priv read register\n"); 91 return ret; 92 } 93 94 return val; 95 } 96 97 static void 98 mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg, 99 u32 mask, u32 set) 100 { 101 u32 val; 102 103 val = mt7623_trgmii_read(priv, reg); 104 val &= ~mask; 105 val |= set; 106 mt7623_trgmii_write(priv, reg, val); 107 } 108 109 static void 110 mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val) 111 { 112 mt7623_trgmii_rmw(priv, reg, 0, val); 113 } 114 115 static void 116 mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val) 117 { 118 mt7623_trgmii_rmw(priv, reg, val, 0); 119 } 120 121 static int 122 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 123 { 124 struct mii_bus *bus = priv->bus; 125 int value, ret; 126 127 /* Write the desired MMD Devad */ 128 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 129 if (ret < 0) 130 goto err; 131 132 /* Write the desired MMD register address */ 133 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 134 if (ret < 0) 135 goto err; 136 137 /* Select the Function : DATA with no post increment */ 138 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 139 if (ret < 0) 140 goto err; 141 142 /* Read the content of the MMD's selected register */ 143 value = bus->read(bus, 0, MII_MMD_DATA); 144 145 return value; 146 err: 147 dev_err(&bus->dev, "failed to read mmd register\n"); 148 149 return ret; 150 } 151 152 static int 153 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 154 int devad, u32 data) 155 { 156 struct mii_bus *bus = priv->bus; 157 int ret; 158 159 /* Write the desired MMD Devad */ 160 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 161 if (ret < 0) 162 goto err; 163 164 /* Write the desired MMD register address */ 165 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 166 if (ret < 0) 167 goto err; 168 169 /* Select the Function : DATA with no post increment */ 170 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 171 if (ret < 0) 172 goto err; 173 174 /* Write the data into MMD's selected register */ 175 ret = bus->write(bus, 0, MII_MMD_DATA, data); 176 err: 177 if (ret < 0) 178 dev_err(&bus->dev, 179 "failed to write mmd register\n"); 180 return ret; 181 } 182 183 static void 184 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 185 { 186 struct mii_bus *bus = priv->bus; 187 188 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 189 190 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 191 192 mutex_unlock(&bus->mdio_lock); 193 } 194 195 static void 196 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 197 { 198 struct mii_bus *bus = priv->bus; 199 u32 val; 200 201 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 202 203 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 204 val &= ~mask; 205 val |= set; 206 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 207 208 mutex_unlock(&bus->mdio_lock); 209 } 210 211 static void 212 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 213 { 214 core_rmw(priv, reg, 0, val); 215 } 216 217 static void 218 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 219 { 220 core_rmw(priv, reg, val, 0); 221 } 222 223 static int 224 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 225 { 226 struct mii_bus *bus = priv->bus; 227 u16 page, r, lo, hi; 228 int ret; 229 230 page = (reg >> 6) & 0x3ff; 231 r = (reg >> 2) & 0xf; 232 lo = val & 0xffff; 233 hi = val >> 16; 234 235 /* MT7530 uses 31 as the pseudo port */ 236 ret = bus->write(bus, 0x1f, 0x1f, page); 237 if (ret < 0) 238 goto err; 239 240 ret = bus->write(bus, 0x1f, r, lo); 241 if (ret < 0) 242 goto err; 243 244 ret = bus->write(bus, 0x1f, 0x10, hi); 245 err: 246 if (ret < 0) 247 dev_err(&bus->dev, 248 "failed to write mt7530 register\n"); 249 return ret; 250 } 251 252 static u32 253 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 254 { 255 struct mii_bus *bus = priv->bus; 256 u16 page, r, lo, hi; 257 int ret; 258 259 page = (reg >> 6) & 0x3ff; 260 r = (reg >> 2) & 0xf; 261 262 /* MT7530 uses 31 as the pseudo port */ 263 ret = bus->write(bus, 0x1f, 0x1f, page); 264 if (ret < 0) { 265 dev_err(&bus->dev, 266 "failed to read mt7530 register\n"); 267 return ret; 268 } 269 270 lo = bus->read(bus, 0x1f, r); 271 hi = bus->read(bus, 0x1f, 0x10); 272 273 return (hi << 16) | (lo & 0xffff); 274 } 275 276 static void 277 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 278 { 279 struct mii_bus *bus = priv->bus; 280 281 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 282 283 mt7530_mii_write(priv, reg, val); 284 285 mutex_unlock(&bus->mdio_lock); 286 } 287 288 static u32 289 _mt7530_read(struct mt7530_dummy_poll *p) 290 { 291 struct mii_bus *bus = p->priv->bus; 292 u32 val; 293 294 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 295 296 val = mt7530_mii_read(p->priv, p->reg); 297 298 mutex_unlock(&bus->mdio_lock); 299 300 return val; 301 } 302 303 static u32 304 mt7530_read(struct mt7530_priv *priv, u32 reg) 305 { 306 struct mt7530_dummy_poll p; 307 308 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 309 return _mt7530_read(&p); 310 } 311 312 static void 313 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 314 u32 mask, u32 set) 315 { 316 struct mii_bus *bus = priv->bus; 317 u32 val; 318 319 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 320 321 val = mt7530_mii_read(priv, reg); 322 val &= ~mask; 323 val |= set; 324 mt7530_mii_write(priv, reg, val); 325 326 mutex_unlock(&bus->mdio_lock); 327 } 328 329 static void 330 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 331 { 332 mt7530_rmw(priv, reg, 0, val); 333 } 334 335 static void 336 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 337 { 338 mt7530_rmw(priv, reg, val, 0); 339 } 340 341 static int 342 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 343 { 344 u32 val; 345 int ret; 346 struct mt7530_dummy_poll p; 347 348 /* Set the command operating upon the MAC address entries */ 349 val = ATC_BUSY | ATC_MAT(0) | cmd; 350 mt7530_write(priv, MT7530_ATC, val); 351 352 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 353 ret = readx_poll_timeout(_mt7530_read, &p, val, 354 !(val & ATC_BUSY), 20, 20000); 355 if (ret < 0) { 356 dev_err(priv->dev, "reset timeout\n"); 357 return ret; 358 } 359 360 /* Additional sanity for read command if the specified 361 * entry is invalid 362 */ 363 val = mt7530_read(priv, MT7530_ATC); 364 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 365 return -EINVAL; 366 367 if (rsp) 368 *rsp = val; 369 370 return 0; 371 } 372 373 static void 374 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 375 { 376 u32 reg[3]; 377 int i; 378 379 /* Read from ARL table into an array */ 380 for (i = 0; i < 3; i++) { 381 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 382 383 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 384 __func__, __LINE__, i, reg[i]); 385 } 386 387 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 388 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 389 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 390 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 391 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 392 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 393 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 394 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 395 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 396 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 397 } 398 399 static void 400 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 401 u8 port_mask, const u8 *mac, 402 u8 aging, u8 type) 403 { 404 u32 reg[3] = { 0 }; 405 int i; 406 407 reg[1] |= vid & CVID_MASK; 408 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 409 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 410 /* STATIC_ENT indicate that entry is static wouldn't 411 * be aged out and STATIC_EMP specified as erasing an 412 * entry 413 */ 414 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 415 reg[1] |= mac[5] << MAC_BYTE_5; 416 reg[1] |= mac[4] << MAC_BYTE_4; 417 reg[0] |= mac[3] << MAC_BYTE_3; 418 reg[0] |= mac[2] << MAC_BYTE_2; 419 reg[0] |= mac[1] << MAC_BYTE_1; 420 reg[0] |= mac[0] << MAC_BYTE_0; 421 422 /* Write array into the ARL table */ 423 for (i = 0; i < 3; i++) 424 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 425 } 426 427 static int 428 mt7530_pad_clk_setup(struct dsa_switch *ds, int mode) 429 { 430 struct mt7530_priv *priv = ds->priv; 431 u32 ncpo1, ssc_delta, trgint, i, xtal; 432 433 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 434 435 if (xtal == HWTRAP_XTAL_20MHZ) { 436 dev_err(priv->dev, 437 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 438 __func__); 439 return -EINVAL; 440 } 441 442 switch (mode) { 443 case PHY_INTERFACE_MODE_RGMII: 444 trgint = 0; 445 /* PLL frequency: 125MHz */ 446 ncpo1 = 0x0c80; 447 break; 448 case PHY_INTERFACE_MODE_TRGMII: 449 trgint = 1; 450 if (priv->id == ID_MT7621) { 451 /* PLL frequency: 150MHz: 1.2GBit */ 452 if (xtal == HWTRAP_XTAL_40MHZ) 453 ncpo1 = 0x0780; 454 if (xtal == HWTRAP_XTAL_25MHZ) 455 ncpo1 = 0x0a00; 456 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 457 if (xtal == HWTRAP_XTAL_40MHZ) 458 ncpo1 = 0x0c80; 459 if (xtal == HWTRAP_XTAL_25MHZ) 460 ncpo1 = 0x1400; 461 } 462 break; 463 default: 464 dev_err(priv->dev, "xMII mode %d not supported\n", mode); 465 return -EINVAL; 466 } 467 468 if (xtal == HWTRAP_XTAL_25MHZ) 469 ssc_delta = 0x57; 470 else 471 ssc_delta = 0x87; 472 473 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 474 P6_INTF_MODE(trgint)); 475 476 /* Lower Tx Driving for TRGMII path */ 477 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 478 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 479 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 480 481 /* Setup core clock for MT7530 */ 482 if (!trgint) { 483 /* Disable MT7530 core clock */ 484 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 485 486 /* Disable PLL, since phy_device has not yet been created 487 * provided for phy_[read,write]_mmd_indirect is called, we 488 * provide our own core_write_mmd_indirect to complete this 489 * function. 490 */ 491 core_write_mmd_indirect(priv, 492 CORE_GSWPLL_GRP1, 493 MDIO_MMD_VEND2, 494 0); 495 496 /* Set core clock into 500Mhz */ 497 core_write(priv, CORE_GSWPLL_GRP2, 498 RG_GSWPLL_POSDIV_500M(1) | 499 RG_GSWPLL_FBKDIV_500M(25)); 500 501 /* Enable PLL */ 502 core_write(priv, CORE_GSWPLL_GRP1, 503 RG_GSWPLL_EN_PRE | 504 RG_GSWPLL_POSDIV_200M(2) | 505 RG_GSWPLL_FBKDIV_200M(32)); 506 507 /* Enable MT7530 core clock */ 508 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 509 } 510 511 /* Setup the MT7530 TRGMII Tx Clock */ 512 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 513 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 514 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 515 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 516 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 517 core_write(priv, CORE_PLL_GROUP4, 518 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 519 RG_SYSPLL_BIAS_LPF_EN); 520 core_write(priv, CORE_PLL_GROUP2, 521 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 522 RG_SYSPLL_POSDIV(1)); 523 core_write(priv, CORE_PLL_GROUP7, 524 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 525 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 526 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 527 REG_GSWCK_EN | REG_TRGMIICK_EN); 528 529 if (!trgint) 530 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 531 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 532 RD_TAP_MASK, RD_TAP(16)); 533 else 534 if (priv->id != ID_MT7621) 535 mt7623_trgmii_set(priv, GSW_INTF_MODE, 536 INTF_MODE_TRGMII); 537 538 return 0; 539 } 540 541 static int 542 mt7623_pad_clk_setup(struct dsa_switch *ds) 543 { 544 struct mt7530_priv *priv = ds->priv; 545 int i; 546 547 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 548 mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i), 549 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 550 551 mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST | RXC_DQSISEL); 552 mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST); 553 554 return 0; 555 } 556 557 static void 558 mt7530_mib_reset(struct dsa_switch *ds) 559 { 560 struct mt7530_priv *priv = ds->priv; 561 562 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 563 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 564 } 565 566 static void 567 mt7530_port_set_status(struct mt7530_priv *priv, int port, int enable) 568 { 569 u32 mask = PMCR_TX_EN | PMCR_RX_EN; 570 571 if (enable) 572 mt7530_set(priv, MT7530_PMCR_P(port), mask); 573 else 574 mt7530_clear(priv, MT7530_PMCR_P(port), mask); 575 } 576 577 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum) 578 { 579 struct mt7530_priv *priv = ds->priv; 580 581 return mdiobus_read_nested(priv->bus, port, regnum); 582 } 583 584 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, 585 u16 val) 586 { 587 struct mt7530_priv *priv = ds->priv; 588 589 return mdiobus_write_nested(priv->bus, port, regnum, val); 590 } 591 592 static void 593 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 594 uint8_t *data) 595 { 596 int i; 597 598 if (stringset != ETH_SS_STATS) 599 return; 600 601 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 602 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 603 ETH_GSTRING_LEN); 604 } 605 606 static void 607 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 608 uint64_t *data) 609 { 610 struct mt7530_priv *priv = ds->priv; 611 const struct mt7530_mib_desc *mib; 612 u32 reg, i; 613 u64 hi; 614 615 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 616 mib = &mt7530_mib[i]; 617 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 618 619 data[i] = mt7530_read(priv, reg); 620 if (mib->size == 2) { 621 hi = mt7530_read(priv, reg + 4); 622 data[i] |= hi << 32; 623 } 624 } 625 } 626 627 static int 628 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 629 { 630 if (sset != ETH_SS_STATS) 631 return 0; 632 633 return ARRAY_SIZE(mt7530_mib); 634 } 635 636 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 637 { 638 struct mt7530_priv *priv = ds->priv; 639 u8 tx_delay = 0; 640 int val; 641 642 mutex_lock(&priv->reg_mutex); 643 644 val = mt7530_read(priv, MT7530_MHWTRAP); 645 646 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 647 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 648 649 switch (priv->p5_intf_sel) { 650 case P5_INTF_SEL_PHY_P0: 651 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 652 val |= MHWTRAP_PHY0_SEL; 653 /* fall through */ 654 case P5_INTF_SEL_PHY_P4: 655 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 656 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 657 658 /* Setup the MAC by default for the cpu port */ 659 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 660 break; 661 case P5_INTF_SEL_GMAC5: 662 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 663 val &= ~MHWTRAP_P5_DIS; 664 break; 665 case P5_DISABLED: 666 interface = PHY_INTERFACE_MODE_NA; 667 break; 668 default: 669 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 670 priv->p5_intf_sel); 671 goto unlock_exit; 672 } 673 674 /* Setup RGMII settings */ 675 if (phy_interface_mode_is_rgmii(interface)) { 676 val |= MHWTRAP_P5_RGMII_MODE; 677 678 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 679 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 680 681 /* Don't set delay in DSA mode */ 682 if (!dsa_is_dsa_port(priv->ds, 5) && 683 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 684 interface == PHY_INTERFACE_MODE_RGMII_ID)) 685 tx_delay = 4; /* n * 0.5 ns */ 686 687 /* P5 RGMII TX Clock Control: delay x */ 688 mt7530_write(priv, MT7530_P5RGMIITXCR, 689 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 690 691 /* reduce P5 RGMII Tx driving, 8mA */ 692 mt7530_write(priv, MT7530_IO_DRV_CR, 693 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 694 } 695 696 mt7530_write(priv, MT7530_MHWTRAP, val); 697 698 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 699 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 700 701 priv->p5_interface = interface; 702 703 unlock_exit: 704 mutex_unlock(&priv->reg_mutex); 705 } 706 707 static int 708 mt7530_cpu_port_enable(struct mt7530_priv *priv, 709 int port) 710 { 711 /* Enable Mediatek header mode on the cpu port */ 712 mt7530_write(priv, MT7530_PVC_P(port), 713 PORT_SPEC_TAG); 714 715 /* Disable auto learning on the cpu port */ 716 mt7530_set(priv, MT7530_PSC_P(port), SA_DIS); 717 718 /* Unknown unicast frame fordwarding to the cpu port */ 719 mt7530_set(priv, MT7530_MFC, UNU_FFP(BIT(port))); 720 721 /* Set CPU port number */ 722 if (priv->id == ID_MT7621) 723 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 724 725 /* CPU port gets connected to all user ports of 726 * the switch 727 */ 728 mt7530_write(priv, MT7530_PCR_P(port), 729 PCR_MATRIX(dsa_user_ports(priv->ds))); 730 731 return 0; 732 } 733 734 static int 735 mt7530_port_enable(struct dsa_switch *ds, int port, 736 struct phy_device *phy) 737 { 738 struct mt7530_priv *priv = ds->priv; 739 740 if (!dsa_is_user_port(ds, port)) 741 return 0; 742 743 mutex_lock(&priv->reg_mutex); 744 745 /* Allow the user port gets connected to the cpu port and also 746 * restore the port matrix if the port is the member of a certain 747 * bridge. 748 */ 749 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); 750 priv->ports[port].enable = true; 751 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 752 priv->ports[port].pm); 753 mt7530_port_set_status(priv, port, 0); 754 755 mutex_unlock(&priv->reg_mutex); 756 757 return 0; 758 } 759 760 static void 761 mt7530_port_disable(struct dsa_switch *ds, int port) 762 { 763 struct mt7530_priv *priv = ds->priv; 764 765 if (!dsa_is_user_port(ds, port)) 766 return; 767 768 mutex_lock(&priv->reg_mutex); 769 770 /* Clear up all port matrix which could be restored in the next 771 * enablement for the port. 772 */ 773 priv->ports[port].enable = false; 774 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 775 PCR_MATRIX_CLR); 776 mt7530_port_set_status(priv, port, 0); 777 778 mutex_unlock(&priv->reg_mutex); 779 } 780 781 static void 782 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 783 { 784 struct mt7530_priv *priv = ds->priv; 785 u32 stp_state; 786 787 switch (state) { 788 case BR_STATE_DISABLED: 789 stp_state = MT7530_STP_DISABLED; 790 break; 791 case BR_STATE_BLOCKING: 792 stp_state = MT7530_STP_BLOCKING; 793 break; 794 case BR_STATE_LISTENING: 795 stp_state = MT7530_STP_LISTENING; 796 break; 797 case BR_STATE_LEARNING: 798 stp_state = MT7530_STP_LEARNING; 799 break; 800 case BR_STATE_FORWARDING: 801 default: 802 stp_state = MT7530_STP_FORWARDING; 803 break; 804 } 805 806 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state); 807 } 808 809 static int 810 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 811 struct net_device *bridge) 812 { 813 struct mt7530_priv *priv = ds->priv; 814 u32 port_bitmap = BIT(MT7530_CPU_PORT); 815 int i; 816 817 mutex_lock(&priv->reg_mutex); 818 819 for (i = 0; i < MT7530_NUM_PORTS; i++) { 820 /* Add this port to the port matrix of the other ports in the 821 * same bridge. If the port is disabled, port matrix is kept 822 * and not being setup until the port becomes enabled. 823 */ 824 if (dsa_is_user_port(ds, i) && i != port) { 825 if (dsa_to_port(ds, i)->bridge_dev != bridge) 826 continue; 827 if (priv->ports[i].enable) 828 mt7530_set(priv, MT7530_PCR_P(i), 829 PCR_MATRIX(BIT(port))); 830 priv->ports[i].pm |= PCR_MATRIX(BIT(port)); 831 832 port_bitmap |= BIT(i); 833 } 834 } 835 836 /* Add the all other ports to this port matrix. */ 837 if (priv->ports[port].enable) 838 mt7530_rmw(priv, MT7530_PCR_P(port), 839 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 840 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 841 842 mutex_unlock(&priv->reg_mutex); 843 844 return 0; 845 } 846 847 static void 848 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 849 { 850 struct mt7530_priv *priv = ds->priv; 851 bool all_user_ports_removed = true; 852 int i; 853 854 /* When a port is removed from the bridge, the port would be set up 855 * back to the default as is at initial boot which is a VLAN-unaware 856 * port. 857 */ 858 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 859 MT7530_PORT_MATRIX_MODE); 860 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 861 VLAN_ATTR(MT7530_VLAN_TRANSPARENT)); 862 863 for (i = 0; i < MT7530_NUM_PORTS; i++) { 864 if (dsa_is_user_port(ds, i) && 865 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 866 all_user_ports_removed = false; 867 break; 868 } 869 } 870 871 /* CPU port also does the same thing until all user ports belonging to 872 * the CPU port get out of VLAN filtering mode. 873 */ 874 if (all_user_ports_removed) { 875 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), 876 PCR_MATRIX(dsa_user_ports(priv->ds))); 877 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), 878 PORT_SPEC_TAG); 879 } 880 } 881 882 static void 883 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 884 { 885 struct mt7530_priv *priv = ds->priv; 886 887 /* The real fabric path would be decided on the membership in the 888 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS 889 * means potential VLAN can be consisting of certain subset of all 890 * ports. 891 */ 892 mt7530_rmw(priv, MT7530_PCR_P(port), 893 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS)); 894 895 /* Trapped into security mode allows packet forwarding through VLAN 896 * table lookup. 897 */ 898 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 899 MT7530_PORT_SECURITY_MODE); 900 901 /* Set the port as a user port which is to be able to recognize VID 902 * from incoming packets before fetching entry within the VLAN table. 903 */ 904 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 905 VLAN_ATTR(MT7530_VLAN_USER)); 906 } 907 908 static void 909 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 910 struct net_device *bridge) 911 { 912 struct mt7530_priv *priv = ds->priv; 913 int i; 914 915 mutex_lock(&priv->reg_mutex); 916 917 for (i = 0; i < MT7530_NUM_PORTS; i++) { 918 /* Remove this port from the port matrix of the other ports 919 * in the same bridge. If the port is disabled, port matrix 920 * is kept and not being setup until the port becomes enabled. 921 * And the other port's port matrix cannot be broken when the 922 * other port is still a VLAN-aware port. 923 */ 924 if (dsa_is_user_port(ds, i) && i != port && 925 !dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 926 if (dsa_to_port(ds, i)->bridge_dev != bridge) 927 continue; 928 if (priv->ports[i].enable) 929 mt7530_clear(priv, MT7530_PCR_P(i), 930 PCR_MATRIX(BIT(port))); 931 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); 932 } 933 } 934 935 /* Set the cpu port to be the only one in the port matrix of 936 * this port. 937 */ 938 if (priv->ports[port].enable) 939 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 940 PCR_MATRIX(BIT(MT7530_CPU_PORT))); 941 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); 942 943 mutex_unlock(&priv->reg_mutex); 944 } 945 946 static int 947 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 948 const unsigned char *addr, u16 vid) 949 { 950 struct mt7530_priv *priv = ds->priv; 951 int ret; 952 u8 port_mask = BIT(port); 953 954 mutex_lock(&priv->reg_mutex); 955 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 956 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 957 mutex_unlock(&priv->reg_mutex); 958 959 return ret; 960 } 961 962 static int 963 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 964 const unsigned char *addr, u16 vid) 965 { 966 struct mt7530_priv *priv = ds->priv; 967 int ret; 968 u8 port_mask = BIT(port); 969 970 mutex_lock(&priv->reg_mutex); 971 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 972 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 973 mutex_unlock(&priv->reg_mutex); 974 975 return ret; 976 } 977 978 static int 979 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 980 dsa_fdb_dump_cb_t *cb, void *data) 981 { 982 struct mt7530_priv *priv = ds->priv; 983 struct mt7530_fdb _fdb = { 0 }; 984 int cnt = MT7530_NUM_FDB_RECORDS; 985 int ret = 0; 986 u32 rsp = 0; 987 988 mutex_lock(&priv->reg_mutex); 989 990 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 991 if (ret < 0) 992 goto err; 993 994 do { 995 if (rsp & ATC_SRCH_HIT) { 996 mt7530_fdb_read(priv, &_fdb); 997 if (_fdb.port_mask & BIT(port)) { 998 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 999 data); 1000 if (ret < 0) 1001 break; 1002 } 1003 } 1004 } while (--cnt && 1005 !(rsp & ATC_SRCH_END) && 1006 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1007 err: 1008 mutex_unlock(&priv->reg_mutex); 1009 1010 return 0; 1011 } 1012 1013 static int 1014 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1015 { 1016 struct mt7530_dummy_poll p; 1017 u32 val; 1018 int ret; 1019 1020 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1021 mt7530_write(priv, MT7530_VTCR, val); 1022 1023 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1024 ret = readx_poll_timeout(_mt7530_read, &p, val, 1025 !(val & VTCR_BUSY), 20, 20000); 1026 if (ret < 0) { 1027 dev_err(priv->dev, "poll timeout\n"); 1028 return ret; 1029 } 1030 1031 val = mt7530_read(priv, MT7530_VTCR); 1032 if (val & VTCR_INVALID) { 1033 dev_err(priv->dev, "read VTCR invalid\n"); 1034 return -EINVAL; 1035 } 1036 1037 return 0; 1038 } 1039 1040 static int 1041 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, 1042 bool vlan_filtering) 1043 { 1044 if (vlan_filtering) { 1045 /* The port is being kept as VLAN-unaware port when bridge is 1046 * set up with vlan_filtering not being set, Otherwise, the 1047 * port and the corresponding CPU port is required the setup 1048 * for becoming a VLAN-aware port. 1049 */ 1050 mt7530_port_set_vlan_aware(ds, port); 1051 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); 1052 } else { 1053 mt7530_port_set_vlan_unaware(ds, port); 1054 } 1055 1056 return 0; 1057 } 1058 1059 static int 1060 mt7530_port_vlan_prepare(struct dsa_switch *ds, int port, 1061 const struct switchdev_obj_port_vlan *vlan) 1062 { 1063 /* nothing needed */ 1064 1065 return 0; 1066 } 1067 1068 static void 1069 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1070 struct mt7530_hw_vlan_entry *entry) 1071 { 1072 u8 new_members; 1073 u32 val; 1074 1075 new_members = entry->old_members | BIT(entry->port) | 1076 BIT(MT7530_CPU_PORT); 1077 1078 /* Validate the entry with independent learning, create egress tag per 1079 * VLAN and joining the port as one of the port members. 1080 */ 1081 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID; 1082 mt7530_write(priv, MT7530_VAWD1, val); 1083 1084 /* Decide whether adding tag or not for those outgoing packets from the 1085 * port inside the VLAN. 1086 */ 1087 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : 1088 MT7530_VLAN_EGRESS_TAG; 1089 mt7530_rmw(priv, MT7530_VAWD2, 1090 ETAG_CTRL_P_MASK(entry->port), 1091 ETAG_CTRL_P(entry->port, val)); 1092 1093 /* CPU port is always taken as a tagged port for serving more than one 1094 * VLANs across and also being applied with egress type stack mode for 1095 * that VLAN tags would be appended after hardware special tag used as 1096 * DSA tag. 1097 */ 1098 mt7530_rmw(priv, MT7530_VAWD2, 1099 ETAG_CTRL_P_MASK(MT7530_CPU_PORT), 1100 ETAG_CTRL_P(MT7530_CPU_PORT, 1101 MT7530_VLAN_EGRESS_STACK)); 1102 } 1103 1104 static void 1105 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1106 struct mt7530_hw_vlan_entry *entry) 1107 { 1108 u8 new_members; 1109 u32 val; 1110 1111 new_members = entry->old_members & ~BIT(entry->port); 1112 1113 val = mt7530_read(priv, MT7530_VAWD1); 1114 if (!(val & VLAN_VALID)) { 1115 dev_err(priv->dev, 1116 "Cannot be deleted due to invalid entry\n"); 1117 return; 1118 } 1119 1120 /* If certain member apart from CPU port is still alive in the VLAN, 1121 * the entry would be kept valid. Otherwise, the entry is got to be 1122 * disabled. 1123 */ 1124 if (new_members && new_members != BIT(MT7530_CPU_PORT)) { 1125 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1126 VLAN_VALID; 1127 mt7530_write(priv, MT7530_VAWD1, val); 1128 } else { 1129 mt7530_write(priv, MT7530_VAWD1, 0); 1130 mt7530_write(priv, MT7530_VAWD2, 0); 1131 } 1132 } 1133 1134 static void 1135 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1136 struct mt7530_hw_vlan_entry *entry, 1137 mt7530_vlan_op vlan_op) 1138 { 1139 u32 val; 1140 1141 /* Fetch entry */ 1142 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1143 1144 val = mt7530_read(priv, MT7530_VAWD1); 1145 1146 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1147 1148 /* Manipulate entry */ 1149 vlan_op(priv, entry); 1150 1151 /* Flush result to hardware */ 1152 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1153 } 1154 1155 static void 1156 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1157 const struct switchdev_obj_port_vlan *vlan) 1158 { 1159 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1160 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1161 struct mt7530_hw_vlan_entry new_entry; 1162 struct mt7530_priv *priv = ds->priv; 1163 u16 vid; 1164 1165 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not 1166 * being set. 1167 */ 1168 if (!dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1169 return; 1170 1171 mutex_lock(&priv->reg_mutex); 1172 1173 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1174 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1175 mt7530_hw_vlan_update(priv, vid, &new_entry, 1176 mt7530_hw_vlan_add); 1177 } 1178 1179 if (pvid) { 1180 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1181 G0_PORT_VID(vlan->vid_end)); 1182 priv->ports[port].pvid = vlan->vid_end; 1183 } 1184 1185 mutex_unlock(&priv->reg_mutex); 1186 } 1187 1188 static int 1189 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1190 const struct switchdev_obj_port_vlan *vlan) 1191 { 1192 struct mt7530_hw_vlan_entry target_entry; 1193 struct mt7530_priv *priv = ds->priv; 1194 u16 vid, pvid; 1195 1196 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not 1197 * being set. 1198 */ 1199 if (!dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1200 return 0; 1201 1202 mutex_lock(&priv->reg_mutex); 1203 1204 pvid = priv->ports[port].pvid; 1205 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1206 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1207 mt7530_hw_vlan_update(priv, vid, &target_entry, 1208 mt7530_hw_vlan_del); 1209 1210 /* PVID is being restored to the default whenever the PVID port 1211 * is being removed from the VLAN. 1212 */ 1213 if (pvid == vid) 1214 pvid = G0_PORT_VID_DEF; 1215 } 1216 1217 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid); 1218 priv->ports[port].pvid = pvid; 1219 1220 mutex_unlock(&priv->reg_mutex); 1221 1222 return 0; 1223 } 1224 1225 static enum dsa_tag_protocol 1226 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1227 enum dsa_tag_protocol mp) 1228 { 1229 struct mt7530_priv *priv = ds->priv; 1230 1231 if (port != MT7530_CPU_PORT) { 1232 dev_warn(priv->dev, 1233 "port not matched with tagging CPU port\n"); 1234 return DSA_TAG_PROTO_NONE; 1235 } else { 1236 return DSA_TAG_PROTO_MTK; 1237 } 1238 } 1239 1240 static int 1241 mt7530_setup(struct dsa_switch *ds) 1242 { 1243 struct mt7530_priv *priv = ds->priv; 1244 struct device_node *phy_node; 1245 struct device_node *mac_np; 1246 struct mt7530_dummy_poll p; 1247 phy_interface_t interface; 1248 struct device_node *dn; 1249 u32 id, val; 1250 int ret, i; 1251 1252 /* The parent node of master netdev which holds the common system 1253 * controller also is the container for two GMACs nodes representing 1254 * as two netdev instances. 1255 */ 1256 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; 1257 1258 if (priv->id == ID_MT7530) { 1259 priv->ethernet = syscon_node_to_regmap(dn); 1260 if (IS_ERR(priv->ethernet)) 1261 return PTR_ERR(priv->ethernet); 1262 1263 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 1264 ret = regulator_enable(priv->core_pwr); 1265 if (ret < 0) { 1266 dev_err(priv->dev, 1267 "Failed to enable core power: %d\n", ret); 1268 return ret; 1269 } 1270 1271 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 1272 ret = regulator_enable(priv->io_pwr); 1273 if (ret < 0) { 1274 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 1275 ret); 1276 return ret; 1277 } 1278 } 1279 1280 /* Reset whole chip through gpio pin or memory-mapped registers for 1281 * different type of hardware 1282 */ 1283 if (priv->mcm) { 1284 reset_control_assert(priv->rstc); 1285 usleep_range(1000, 1100); 1286 reset_control_deassert(priv->rstc); 1287 } else { 1288 gpiod_set_value_cansleep(priv->reset, 0); 1289 usleep_range(1000, 1100); 1290 gpiod_set_value_cansleep(priv->reset, 1); 1291 } 1292 1293 /* Waiting for MT7530 got to stable */ 1294 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 1295 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 1296 20, 1000000); 1297 if (ret < 0) { 1298 dev_err(priv->dev, "reset timeout\n"); 1299 return ret; 1300 } 1301 1302 id = mt7530_read(priv, MT7530_CREV); 1303 id >>= CHIP_NAME_SHIFT; 1304 if (id != MT7530_ID) { 1305 dev_err(priv->dev, "chip %x can't be supported\n", id); 1306 return -ENODEV; 1307 } 1308 1309 /* Reset the switch through internal reset */ 1310 mt7530_write(priv, MT7530_SYS_CTRL, 1311 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 1312 SYS_CTRL_REG_RST); 1313 1314 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 1315 val = mt7530_read(priv, MT7530_MHWTRAP); 1316 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 1317 val |= MHWTRAP_MANUAL; 1318 mt7530_write(priv, MT7530_MHWTRAP, val); 1319 1320 priv->p6_interface = PHY_INTERFACE_MODE_NA; 1321 1322 /* Enable and reset MIB counters */ 1323 mt7530_mib_reset(ds); 1324 1325 mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK); 1326 1327 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1328 /* Disable forwarding by default on all ports */ 1329 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 1330 PCR_MATRIX_CLR); 1331 1332 if (dsa_is_cpu_port(ds, i)) 1333 mt7530_cpu_port_enable(priv, i); 1334 else 1335 mt7530_port_disable(ds, i); 1336 } 1337 1338 /* Setup port 5 */ 1339 priv->p5_intf_sel = P5_DISABLED; 1340 interface = PHY_INTERFACE_MODE_NA; 1341 1342 if (!dsa_is_unused_port(ds, 5)) { 1343 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 1344 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 1345 if (ret && ret != -ENODEV) 1346 return ret; 1347 } else { 1348 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 1349 for_each_child_of_node(dn, mac_np) { 1350 if (!of_device_is_compatible(mac_np, 1351 "mediatek,eth-mac")) 1352 continue; 1353 1354 ret = of_property_read_u32(mac_np, "reg", &id); 1355 if (ret < 0 || id != 1) 1356 continue; 1357 1358 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 1359 if (phy_node->parent == priv->dev->of_node->parent) { 1360 ret = of_get_phy_mode(mac_np, &interface); 1361 if (ret && ret != -ENODEV) 1362 return ret; 1363 id = of_mdio_parse_addr(ds->dev, phy_node); 1364 if (id == 0) 1365 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 1366 if (id == 4) 1367 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 1368 } 1369 of_node_put(phy_node); 1370 break; 1371 } 1372 } 1373 1374 mt7530_setup_port5(ds, interface); 1375 1376 /* Flush the FDB table */ 1377 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 1378 if (ret < 0) 1379 return ret; 1380 1381 return 0; 1382 } 1383 1384 static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port, 1385 unsigned int mode, 1386 const struct phylink_link_state *state) 1387 { 1388 struct mt7530_priv *priv = ds->priv; 1389 u32 mcr_cur, mcr_new; 1390 1391 switch (port) { 1392 case 0: /* Internal phy */ 1393 case 1: 1394 case 2: 1395 case 3: 1396 case 4: 1397 if (state->interface != PHY_INTERFACE_MODE_GMII) 1398 return; 1399 break; 1400 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 1401 if (priv->p5_interface == state->interface) 1402 break; 1403 if (!phy_interface_mode_is_rgmii(state->interface) && 1404 state->interface != PHY_INTERFACE_MODE_MII && 1405 state->interface != PHY_INTERFACE_MODE_GMII) 1406 return; 1407 1408 mt7530_setup_port5(ds, state->interface); 1409 break; 1410 case 6: /* 1st cpu port */ 1411 if (priv->p6_interface == state->interface) 1412 break; 1413 1414 if (state->interface != PHY_INTERFACE_MODE_RGMII && 1415 state->interface != PHY_INTERFACE_MODE_TRGMII) 1416 return; 1417 1418 /* Setup TX circuit incluing relevant PAD and driving */ 1419 mt7530_pad_clk_setup(ds, state->interface); 1420 1421 if (priv->id == ID_MT7530) { 1422 /* Setup RX circuit, relevant PAD and driving on the 1423 * host which must be placed after the setup on the 1424 * device side is all finished. 1425 */ 1426 mt7623_pad_clk_setup(ds); 1427 } 1428 1429 priv->p6_interface = state->interface; 1430 break; 1431 default: 1432 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port); 1433 return; 1434 } 1435 1436 if (phylink_autoneg_inband(mode)) { 1437 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", 1438 __func__); 1439 return; 1440 } 1441 1442 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 1443 mcr_new = mcr_cur; 1444 mcr_new &= ~(PMCR_FORCE_SPEED_1000 | PMCR_FORCE_SPEED_100 | 1445 PMCR_FORCE_FDX | PMCR_TX_FC_EN | PMCR_RX_FC_EN); 1446 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 1447 PMCR_BACKPR_EN | PMCR_FORCE_MODE | PMCR_FORCE_LNK; 1448 1449 /* Are we connected to external phy */ 1450 if (port == 5 && dsa_is_user_port(ds, 5)) 1451 mcr_new |= PMCR_EXT_PHY; 1452 1453 switch (state->speed) { 1454 case SPEED_1000: 1455 mcr_new |= PMCR_FORCE_SPEED_1000; 1456 break; 1457 case SPEED_100: 1458 mcr_new |= PMCR_FORCE_SPEED_100; 1459 break; 1460 } 1461 if (state->duplex == DUPLEX_FULL) { 1462 mcr_new |= PMCR_FORCE_FDX; 1463 if (state->pause & MLO_PAUSE_TX) 1464 mcr_new |= PMCR_TX_FC_EN; 1465 if (state->pause & MLO_PAUSE_RX) 1466 mcr_new |= PMCR_RX_FC_EN; 1467 } 1468 1469 if (mcr_new != mcr_cur) 1470 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 1471 } 1472 1473 static void mt7530_phylink_mac_link_down(struct dsa_switch *ds, int port, 1474 unsigned int mode, 1475 phy_interface_t interface) 1476 { 1477 struct mt7530_priv *priv = ds->priv; 1478 1479 mt7530_port_set_status(priv, port, 0); 1480 } 1481 1482 static void mt7530_phylink_mac_link_up(struct dsa_switch *ds, int port, 1483 unsigned int mode, 1484 phy_interface_t interface, 1485 struct phy_device *phydev) 1486 { 1487 struct mt7530_priv *priv = ds->priv; 1488 1489 mt7530_port_set_status(priv, port, 1); 1490 } 1491 1492 static void mt7530_phylink_validate(struct dsa_switch *ds, int port, 1493 unsigned long *supported, 1494 struct phylink_link_state *state) 1495 { 1496 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1497 1498 switch (port) { 1499 case 0: /* Internal phy */ 1500 case 1: 1501 case 2: 1502 case 3: 1503 case 4: 1504 if (state->interface != PHY_INTERFACE_MODE_NA && 1505 state->interface != PHY_INTERFACE_MODE_GMII) 1506 goto unsupported; 1507 break; 1508 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 1509 if (state->interface != PHY_INTERFACE_MODE_NA && 1510 !phy_interface_mode_is_rgmii(state->interface) && 1511 state->interface != PHY_INTERFACE_MODE_MII && 1512 state->interface != PHY_INTERFACE_MODE_GMII) 1513 goto unsupported; 1514 break; 1515 case 6: /* 1st cpu port */ 1516 if (state->interface != PHY_INTERFACE_MODE_NA && 1517 state->interface != PHY_INTERFACE_MODE_RGMII && 1518 state->interface != PHY_INTERFACE_MODE_TRGMII) 1519 goto unsupported; 1520 break; 1521 default: 1522 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port); 1523 unsupported: 1524 linkmode_zero(supported); 1525 return; 1526 } 1527 1528 phylink_set_port_modes(mask); 1529 phylink_set(mask, Autoneg); 1530 1531 if (state->interface == PHY_INTERFACE_MODE_TRGMII) { 1532 phylink_set(mask, 1000baseT_Full); 1533 } else { 1534 phylink_set(mask, 10baseT_Half); 1535 phylink_set(mask, 10baseT_Full); 1536 phylink_set(mask, 100baseT_Half); 1537 phylink_set(mask, 100baseT_Full); 1538 1539 if (state->interface != PHY_INTERFACE_MODE_MII) { 1540 phylink_set(mask, 1000baseT_Half); 1541 phylink_set(mask, 1000baseT_Full); 1542 if (port == 5) 1543 phylink_set(mask, 1000baseX_Full); 1544 } 1545 } 1546 1547 phylink_set(mask, Pause); 1548 phylink_set(mask, Asym_Pause); 1549 1550 linkmode_and(supported, supported, mask); 1551 linkmode_and(state->advertising, state->advertising, mask); 1552 } 1553 1554 static int 1555 mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port, 1556 struct phylink_link_state *state) 1557 { 1558 struct mt7530_priv *priv = ds->priv; 1559 u32 pmsr; 1560 1561 if (port < 0 || port >= MT7530_NUM_PORTS) 1562 return -EINVAL; 1563 1564 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 1565 1566 state->link = (pmsr & PMSR_LINK); 1567 state->an_complete = state->link; 1568 state->duplex = !!(pmsr & PMSR_DPX); 1569 1570 switch (pmsr & PMSR_SPEED_MASK) { 1571 case PMSR_SPEED_10: 1572 state->speed = SPEED_10; 1573 break; 1574 case PMSR_SPEED_100: 1575 state->speed = SPEED_100; 1576 break; 1577 case PMSR_SPEED_1000: 1578 state->speed = SPEED_1000; 1579 break; 1580 default: 1581 state->speed = SPEED_UNKNOWN; 1582 break; 1583 } 1584 1585 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 1586 if (pmsr & PMSR_RX_FC) 1587 state->pause |= MLO_PAUSE_RX; 1588 if (pmsr & PMSR_TX_FC) 1589 state->pause |= MLO_PAUSE_TX; 1590 1591 return 1; 1592 } 1593 1594 static const struct dsa_switch_ops mt7530_switch_ops = { 1595 .get_tag_protocol = mtk_get_tag_protocol, 1596 .setup = mt7530_setup, 1597 .get_strings = mt7530_get_strings, 1598 .phy_read = mt7530_phy_read, 1599 .phy_write = mt7530_phy_write, 1600 .get_ethtool_stats = mt7530_get_ethtool_stats, 1601 .get_sset_count = mt7530_get_sset_count, 1602 .port_enable = mt7530_port_enable, 1603 .port_disable = mt7530_port_disable, 1604 .port_stp_state_set = mt7530_stp_state_set, 1605 .port_bridge_join = mt7530_port_bridge_join, 1606 .port_bridge_leave = mt7530_port_bridge_leave, 1607 .port_fdb_add = mt7530_port_fdb_add, 1608 .port_fdb_del = mt7530_port_fdb_del, 1609 .port_fdb_dump = mt7530_port_fdb_dump, 1610 .port_vlan_filtering = mt7530_port_vlan_filtering, 1611 .port_vlan_prepare = mt7530_port_vlan_prepare, 1612 .port_vlan_add = mt7530_port_vlan_add, 1613 .port_vlan_del = mt7530_port_vlan_del, 1614 .phylink_validate = mt7530_phylink_validate, 1615 .phylink_mac_link_state = mt7530_phylink_mac_link_state, 1616 .phylink_mac_config = mt7530_phylink_mac_config, 1617 .phylink_mac_link_down = mt7530_phylink_mac_link_down, 1618 .phylink_mac_link_up = mt7530_phylink_mac_link_up, 1619 }; 1620 1621 static const struct of_device_id mt7530_of_match[] = { 1622 { .compatible = "mediatek,mt7621", .data = (void *)ID_MT7621, }, 1623 { .compatible = "mediatek,mt7530", .data = (void *)ID_MT7530, }, 1624 { /* sentinel */ }, 1625 }; 1626 MODULE_DEVICE_TABLE(of, mt7530_of_match); 1627 1628 static int 1629 mt7530_probe(struct mdio_device *mdiodev) 1630 { 1631 struct mt7530_priv *priv; 1632 struct device_node *dn; 1633 1634 dn = mdiodev->dev.of_node; 1635 1636 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 1637 if (!priv) 1638 return -ENOMEM; 1639 1640 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); 1641 if (!priv->ds) 1642 return -ENOMEM; 1643 1644 priv->ds->dev = &mdiodev->dev; 1645 priv->ds->num_ports = DSA_MAX_PORTS; 1646 1647 /* Use medatek,mcm property to distinguish hardware type that would 1648 * casues a little bit differences on power-on sequence. 1649 */ 1650 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 1651 if (priv->mcm) { 1652 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 1653 1654 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 1655 if (IS_ERR(priv->rstc)) { 1656 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 1657 return PTR_ERR(priv->rstc); 1658 } 1659 } 1660 1661 /* Get the hardware identifier from the devicetree node. 1662 * We will need it for some of the clock and regulator setup. 1663 */ 1664 priv->id = (unsigned int)(unsigned long) 1665 of_device_get_match_data(&mdiodev->dev); 1666 1667 if (priv->id == ID_MT7530) { 1668 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 1669 if (IS_ERR(priv->core_pwr)) 1670 return PTR_ERR(priv->core_pwr); 1671 1672 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 1673 if (IS_ERR(priv->io_pwr)) 1674 return PTR_ERR(priv->io_pwr); 1675 } 1676 1677 /* Not MCM that indicates switch works as the remote standalone 1678 * integrated circuit so the GPIO pin would be used to complete 1679 * the reset, otherwise memory-mapped register accessing used 1680 * through syscon provides in the case of MCM. 1681 */ 1682 if (!priv->mcm) { 1683 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 1684 GPIOD_OUT_LOW); 1685 if (IS_ERR(priv->reset)) { 1686 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 1687 return PTR_ERR(priv->reset); 1688 } 1689 } 1690 1691 priv->bus = mdiodev->bus; 1692 priv->dev = &mdiodev->dev; 1693 priv->ds->priv = priv; 1694 priv->ds->ops = &mt7530_switch_ops; 1695 mutex_init(&priv->reg_mutex); 1696 dev_set_drvdata(&mdiodev->dev, priv); 1697 1698 return dsa_register_switch(priv->ds); 1699 } 1700 1701 static void 1702 mt7530_remove(struct mdio_device *mdiodev) 1703 { 1704 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 1705 int ret = 0; 1706 1707 ret = regulator_disable(priv->core_pwr); 1708 if (ret < 0) 1709 dev_err(priv->dev, 1710 "Failed to disable core power: %d\n", ret); 1711 1712 ret = regulator_disable(priv->io_pwr); 1713 if (ret < 0) 1714 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 1715 ret); 1716 1717 dsa_unregister_switch(priv->ds); 1718 mutex_destroy(&priv->reg_mutex); 1719 } 1720 1721 static struct mdio_driver mt7530_mdio_driver = { 1722 .probe = mt7530_probe, 1723 .remove = mt7530_remove, 1724 .mdiodrv.driver = { 1725 .name = "mt7530", 1726 .of_match_table = mt7530_of_match, 1727 }, 1728 }; 1729 1730 mdio_module_driver(mt7530_mdio_driver); 1731 1732 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 1733 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 1734 MODULE_LICENSE("GPL"); 1735