1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mp-clock.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11#include "imx8mp-pinfunc.h" 12 13/ { 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 ethernet0 = &fec; 20 gpio0 = &gpio1; 21 gpio1 = &gpio2; 22 gpio2 = &gpio3; 23 gpio3 = &gpio4; 24 gpio4 = &gpio5; 25 mmc0 = &usdhc1; 26 mmc1 = &usdhc2; 27 mmc2 = &usdhc3; 28 serial0 = &uart1; 29 serial1 = &uart2; 30 serial2 = &uart3; 31 serial3 = &uart4; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 A53_0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0x0>; 42 clock-latency = <61036>; 43 clocks = <&clk IMX8MP_CLK_ARM>; 44 enable-method = "psci"; 45 next-level-cache = <&A53_L2>; 46 }; 47 48 A53_1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 reg = <0x1>; 52 clock-latency = <61036>; 53 clocks = <&clk IMX8MP_CLK_ARM>; 54 enable-method = "psci"; 55 next-level-cache = <&A53_L2>; 56 }; 57 58 A53_2: cpu@2 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a53"; 61 reg = <0x2>; 62 clock-latency = <61036>; 63 clocks = <&clk IMX8MP_CLK_ARM>; 64 enable-method = "psci"; 65 next-level-cache = <&A53_L2>; 66 }; 67 68 A53_3: cpu@3 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x3>; 72 clock-latency = <61036>; 73 clocks = <&clk IMX8MP_CLK_ARM>; 74 enable-method = "psci"; 75 next-level-cache = <&A53_L2>; 76 }; 77 78 A53_L2: l2-cache0 { 79 compatible = "cache"; 80 }; 81 }; 82 83 osc_32k: clock-osc-32k { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency = <32768>; 87 clock-output-names = "osc_32k"; 88 }; 89 90 osc_24m: clock-osc-24m { 91 compatible = "fixed-clock"; 92 #clock-cells = <0>; 93 clock-frequency = <24000000>; 94 clock-output-names = "osc_24m"; 95 }; 96 97 clk_ext1: clock-ext1 { 98 compatible = "fixed-clock"; 99 #clock-cells = <0>; 100 clock-frequency = <133000000>; 101 clock-output-names = "clk_ext1"; 102 }; 103 104 clk_ext2: clock-ext2 { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 clock-frequency = <133000000>; 108 clock-output-names = "clk_ext2"; 109 }; 110 111 clk_ext3: clock-ext3 { 112 compatible = "fixed-clock"; 113 #clock-cells = <0>; 114 clock-frequency = <133000000>; 115 clock-output-names = "clk_ext3"; 116 }; 117 118 clk_ext4: clock-ext4 { 119 compatible = "fixed-clock"; 120 #clock-cells = <0>; 121 clock-frequency= <133000000>; 122 clock-output-names = "clk_ext4"; 123 }; 124 125 psci { 126 compatible = "arm,psci-1.0"; 127 method = "smc"; 128 }; 129 130 timer { 131 compatible = "arm,armv8-timer"; 132 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 133 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 134 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 135 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 136 clock-frequency = <8000000>; 137 arm,no-tick-in-suspend; 138 }; 139 140 soc@0 { 141 compatible = "simple-bus"; 142 #address-cells = <1>; 143 #size-cells = <1>; 144 ranges = <0x0 0x0 0x0 0x3e000000>; 145 146 aips1: bus@30000000 { 147 compatible = "fsl,aips-bus", "simple-bus"; 148 reg = <0x301f0000 0x10000>; 149 #address-cells = <1>; 150 #size-cells = <1>; 151 ranges; 152 153 gpio1: gpio@30200000 { 154 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 155 reg = <0x30200000 0x10000>; 156 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 158 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; 159 gpio-controller; 160 #gpio-cells = <2>; 161 interrupt-controller; 162 #interrupt-cells = <2>; 163 gpio-ranges = <&iomuxc 0 5 30>; 164 }; 165 166 gpio2: gpio@30210000 { 167 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 168 reg = <0x30210000 0x10000>; 169 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 171 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; 172 gpio-controller; 173 #gpio-cells = <2>; 174 interrupt-controller; 175 #interrupt-cells = <2>; 176 gpio-ranges = <&iomuxc 0 35 21>; 177 }; 178 179 gpio3: gpio@30220000 { 180 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 181 reg = <0x30220000 0x10000>; 182 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 184 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; 185 gpio-controller; 186 #gpio-cells = <2>; 187 interrupt-controller; 188 #interrupt-cells = <2>; 189 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 0 144 4>; 190 }; 191 192 gpio4: gpio@30230000 { 193 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 194 reg = <0x30230000 0x10000>; 195 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; 198 gpio-controller; 199 #gpio-cells = <2>; 200 interrupt-controller; 201 #interrupt-cells = <2>; 202 gpio-ranges = <&iomuxc 0 82 32>; 203 }; 204 205 gpio5: gpio@30240000 { 206 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 207 reg = <0x30240000 0x10000>; 208 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; 211 gpio-controller; 212 #gpio-cells = <2>; 213 interrupt-controller; 214 #interrupt-cells = <2>; 215 gpio-ranges = <&iomuxc 0 114 30>; 216 }; 217 218 wdog1: watchdog@30280000 { 219 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 220 reg = <0x30280000 0x10000>; 221 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; 223 status = "disabled"; 224 }; 225 226 iomuxc: pinctrl@30330000 { 227 compatible = "fsl,imx8mp-iomuxc"; 228 reg = <0x30330000 0x10000>; 229 }; 230 231 gpr: iomuxc-gpr@30340000 { 232 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; 233 reg = <0x30340000 0x10000>; 234 }; 235 236 ocotp: ocotp-ctrl@30350000 { 237 compatible = "fsl,imx8mp-ocotp", "syscon"; 238 reg = <0x30350000 0x10000>; 239 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; 240 /* For nvmem subnodes */ 241 #address-cells = <1>; 242 #size-cells = <1>; 243 244 cpu_speed_grade: speed-grade@10 { 245 reg = <0x10 4>; 246 }; 247 }; 248 249 anatop: anatop@30360000 { 250 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop", 251 "syscon"; 252 reg = <0x30360000 0x10000>; 253 }; 254 255 snvs: snvs@30370000 { 256 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 257 reg = <0x30370000 0x10000>; 258 259 snvs_rtc: snvs-rtc-lp { 260 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 261 regmap =<&snvs>; 262 offset = <0x34>; 263 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 266 clock-names = "snvs-rtc"; 267 }; 268 269 snvs_pwrkey: snvs-powerkey { 270 compatible = "fsl,sec-v4.0-pwrkey"; 271 regmap = <&snvs>; 272 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 274 clock-names = "snvs-pwrkey"; 275 linux,keycode = <KEY_POWER>; 276 wakeup-source; 277 status = "disabled"; 278 }; 279 }; 280 281 clk: clock-controller@30380000 { 282 compatible = "fsl,imx8mp-ccm"; 283 reg = <0x30380000 0x10000>; 284 #clock-cells = <1>; 285 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 286 <&clk_ext3>, <&clk_ext4>; 287 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 288 "clk_ext3", "clk_ext4"; 289 assigned-clocks = <&clk IMX8MP_CLK_NOC>, 290 <&clk IMX8MP_CLK_NOC_IO>, 291 <&clk IMX8MP_CLK_GIC>, 292 <&clk IMX8MP_CLK_AUDIO_AHB>, 293 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, 294 <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, 295 <&clk IMX8MP_AUDIO_PLL1>, 296 <&clk IMX8MP_AUDIO_PLL2>; 297 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 298 <&clk IMX8MP_SYS_PLL1_800M>, 299 <&clk IMX8MP_SYS_PLL2_500M>, 300 <&clk IMX8MP_SYS_PLL1_800M>, 301 <&clk IMX8MP_SYS_PLL1_800M>; 302 assigned-clock-rates = <1000000000>, 303 <800000000>, 304 <500000000>, 305 <400000000>, 306 <800000000>, 307 <400000000>, 308 <393216000>, 309 <361267200>; 310 }; 311 312 src: reset-controller@30390000 { 313 compatible = "fsl,imx8mp-src", "syscon"; 314 reg = <0x30390000 0x10000>; 315 #reset-cells = <1>; 316 }; 317 }; 318 319 aips2: bus@30400000 { 320 compatible = "fsl,aips-bus", "simple-bus"; 321 reg = <0x305f0000 0x400000>; 322 #address-cells = <1>; 323 #size-cells = <1>; 324 ranges; 325 326 pwm1: pwm@30660000 { 327 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 328 reg = <0x30660000 0x10000>; 329 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, 331 <&clk IMX8MP_CLK_PWM1_ROOT>; 332 clock-names = "ipg", "per"; 333 #pwm-cells = <2>; 334 status = "disabled"; 335 }; 336 337 pwm2: pwm@30670000 { 338 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 339 reg = <0x30670000 0x10000>; 340 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, 342 <&clk IMX8MP_CLK_PWM2_ROOT>; 343 clock-names = "ipg", "per"; 344 #pwm-cells = <2>; 345 status = "disabled"; 346 }; 347 348 pwm3: pwm@30680000 { 349 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 350 reg = <0x30680000 0x10000>; 351 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, 353 <&clk IMX8MP_CLK_PWM3_ROOT>; 354 clock-names = "ipg", "per"; 355 #pwm-cells = <2>; 356 status = "disabled"; 357 }; 358 359 pwm4: pwm@30690000 { 360 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 361 reg = <0x30690000 0x10000>; 362 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, 364 <&clk IMX8MP_CLK_PWM4_ROOT>; 365 clock-names = "ipg", "per"; 366 #pwm-cells = <2>; 367 status = "disabled"; 368 }; 369 370 system_counter: timer@306a0000 { 371 compatible = "nxp,sysctr-timer"; 372 reg = <0x306a0000 0x20000>; 373 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&osc_24m>; 375 clock-names = "per"; 376 }; 377 }; 378 379 aips3: bus@30800000 { 380 compatible = "fsl,aips-bus", "simple-bus"; 381 reg = <0x309f0000 0x400000>; 382 #address-cells = <1>; 383 #size-cells = <1>; 384 ranges; 385 386 ecspi1: spi@30820000 { 387 #address-cells = <1>; 388 #size-cells = <0>; 389 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; 390 reg = <0x30820000 0x10000>; 391 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, 393 <&clk IMX8MP_CLK_ECSPI1_ROOT>; 394 clock-names = "ipg", "per"; 395 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 396 dma-names = "rx", "tx"; 397 status = "disabled"; 398 }; 399 400 ecspi2: spi@30830000 { 401 #address-cells = <1>; 402 #size-cells = <0>; 403 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; 404 reg = <0x30830000 0x10000>; 405 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, 407 <&clk IMX8MP_CLK_ECSPI2_ROOT>; 408 clock-names = "ipg", "per"; 409 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 410 dma-names = "rx", "tx"; 411 status = "disabled"; 412 }; 413 414 ecspi3: spi@30840000 { 415 #address-cells = <1>; 416 #size-cells = <0>; 417 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi"; 418 reg = <0x30840000 0x10000>; 419 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, 421 <&clk IMX8MP_CLK_ECSPI3_ROOT>; 422 clock-names = "ipg", "per"; 423 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 424 dma-names = "rx", "tx"; 425 status = "disabled"; 426 }; 427 428 uart1: serial@30860000 { 429 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 430 reg = <0x30860000 0x10000>; 431 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&clk IMX8MP_CLK_UART1_ROOT>, 433 <&clk IMX8MP_CLK_UART1_ROOT>; 434 clock-names = "ipg", "per"; 435 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 436 dma-names = "rx", "tx"; 437 status = "disabled"; 438 }; 439 440 uart3: serial@30880000 { 441 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 442 reg = <0x30880000 0x10000>; 443 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&clk IMX8MP_CLK_UART3_ROOT>, 445 <&clk IMX8MP_CLK_UART3_ROOT>; 446 clock-names = "ipg", "per"; 447 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 448 dma-names = "rx", "tx"; 449 status = "disabled"; 450 }; 451 452 uart2: serial@30890000 { 453 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 454 reg = <0x30890000 0x10000>; 455 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&clk IMX8MP_CLK_UART2_ROOT>, 457 <&clk IMX8MP_CLK_UART2_ROOT>; 458 clock-names = "ipg", "per"; 459 status = "disabled"; 460 }; 461 462 crypto: crypto@30900000 { 463 compatible = "fsl,sec-v4.0"; 464 #address-cells = <1>; 465 #size-cells = <1>; 466 reg = <0x30900000 0x40000>; 467 ranges = <0 0x30900000 0x40000>; 468 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&clk IMX8MP_CLK_AHB>, 470 <&clk IMX8MP_CLK_IPG_ROOT>; 471 clock-names = "aclk", "ipg"; 472 473 sec_jr0: jr@1000 { 474 compatible = "fsl,sec-v4.0-job-ring"; 475 reg = <0x1000 0x1000>; 476 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 477 }; 478 479 sec_jr1: jr@2000 { 480 compatible = "fsl,sec-v4.0-job-ring"; 481 reg = <0x2000 0x1000>; 482 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 483 }; 484 485 sec_jr2: jr@3000 { 486 compatible = "fsl,sec-v4.0-job-ring"; 487 reg = <0x3000 0x1000>; 488 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 489 }; 490 }; 491 492 i2c1: i2c@30a20000 { 493 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 reg = <0x30a20000 0x10000>; 497 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; 499 status = "disabled"; 500 }; 501 502 i2c2: i2c@30a30000 { 503 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 reg = <0x30a30000 0x10000>; 507 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; 509 status = "disabled"; 510 }; 511 512 i2c3: i2c@30a40000 { 513 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 reg = <0x30a40000 0x10000>; 517 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; 519 status = "disabled"; 520 }; 521 522 i2c4: i2c@30a50000 { 523 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 reg = <0x30a50000 0x10000>; 527 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; 529 status = "disabled"; 530 }; 531 532 uart4: serial@30a60000 { 533 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 534 reg = <0x30a60000 0x10000>; 535 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&clk IMX8MP_CLK_UART4_ROOT>, 537 <&clk IMX8MP_CLK_UART4_ROOT>; 538 clock-names = "ipg", "per"; 539 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 540 dma-names = "rx", "tx"; 541 status = "disabled"; 542 }; 543 544 i2c5: i2c@30ad0000 { 545 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 reg = <0x30ad0000 0x10000>; 549 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; 551 status = "disabled"; 552 }; 553 554 i2c6: i2c@30ae0000 { 555 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 reg = <0x30ae0000 0x10000>; 559 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; 561 status = "disabled"; 562 }; 563 564 usdhc1: mmc@30b40000 { 565 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; 566 reg = <0x30b40000 0x10000>; 567 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&clk IMX8MP_CLK_DUMMY>, 569 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 570 <&clk IMX8MP_CLK_USDHC1_ROOT>; 571 clock-names = "ipg", "ahb", "per"; 572 fsl,tuning-start-tap = <20>; 573 fsl,tuning-step= <2>; 574 bus-width = <4>; 575 status = "disabled"; 576 }; 577 578 usdhc2: mmc@30b50000 { 579 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; 580 reg = <0x30b50000 0x10000>; 581 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&clk IMX8MP_CLK_DUMMY>, 583 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 584 <&clk IMX8MP_CLK_USDHC2_ROOT>; 585 clock-names = "ipg", "ahb", "per"; 586 fsl,tuning-start-tap = <20>; 587 fsl,tuning-step= <2>; 588 bus-width = <4>; 589 status = "disabled"; 590 }; 591 592 usdhc3: mmc@30b60000 { 593 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; 594 reg = <0x30b60000 0x10000>; 595 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&clk IMX8MP_CLK_DUMMY>, 597 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 598 <&clk IMX8MP_CLK_USDHC3_ROOT>; 599 clock-names = "ipg", "ahb", "per"; 600 fsl,tuning-start-tap = <20>; 601 fsl,tuning-step= <2>; 602 bus-width = <4>; 603 status = "disabled"; 604 }; 605 606 sdma1: dma-controller@30bd0000 { 607 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 608 reg = <0x30bd0000 0x10000>; 609 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, 611 <&clk IMX8MP_CLK_SDMA1_ROOT>; 612 clock-names = "ipg", "ahb"; 613 #dma-cells = <3>; 614 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 615 }; 616 617 fec: ethernet@30be0000 { 618 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec"; 619 reg = <0x30be0000 0x10000>; 620 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, 624 <&clk IMX8MP_CLK_SIM_ENET_ROOT>, 625 <&clk IMX8MP_CLK_ENET_TIMER>, 626 <&clk IMX8MP_CLK_ENET_REF>, 627 <&clk IMX8MP_CLK_ENET_PHY_REF>; 628 clock-names = "ipg", "ahb", "ptp", 629 "enet_clk_ref", "enet_out"; 630 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 631 <&clk IMX8MP_CLK_ENET_TIMER>, 632 <&clk IMX8MP_CLK_ENET_REF>, 633 <&clk IMX8MP_CLK_ENET_TIMER>; 634 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 635 <&clk IMX8MP_SYS_PLL2_100M>, 636 <&clk IMX8MP_SYS_PLL2_125M>; 637 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; 638 fsl,num-tx-queues = <3>; 639 fsl,num-rx-queues = <3>; 640 status = "disabled"; 641 }; 642 }; 643 644 gic: interrupt-controller@38800000 { 645 compatible = "arm,gic-v3"; 646 reg = <0x38800000 0x10000>, 647 <0x38880000 0xc0000>; 648 #interrupt-cells = <3>; 649 interrupt-controller; 650 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 651 interrupt-parent = <&gic>; 652 }; 653 }; 654}; 655