1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell OcteonTx2 RVU Ethernet driver 3 * 4 * Copyright (C) 2020 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/etherdevice.h> 12 #include <net/ip.h> 13 #include <net/tso.h> 14 15 #include "otx2_reg.h" 16 #include "otx2_common.h" 17 #include "otx2_struct.h" 18 #include "otx2_txrx.h" 19 20 #define CQE_ADDR(CQ, idx) ((CQ)->cqe_base + ((CQ)->cqe_size * (idx))) 21 22 static struct nix_cqe_hdr_s *otx2_get_next_cqe(struct otx2_cq_queue *cq) 23 { 24 struct nix_cqe_hdr_s *cqe_hdr; 25 26 cqe_hdr = (struct nix_cqe_hdr_s *)CQE_ADDR(cq, cq->cq_head); 27 if (cqe_hdr->cqe_type == NIX_XQE_TYPE_INVALID) 28 return NULL; 29 30 cq->cq_head++; 31 cq->cq_head &= (cq->cqe_cnt - 1); 32 33 return cqe_hdr; 34 } 35 36 static unsigned int frag_num(unsigned int i) 37 { 38 #ifdef __BIG_ENDIAN 39 return (i & ~3) + 3 - (i & 3); 40 #else 41 return i; 42 #endif 43 } 44 45 static dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf, 46 struct sk_buff *skb, int seg, int *len) 47 { 48 const skb_frag_t *frag; 49 struct page *page; 50 int offset; 51 52 /* First segment is always skb->data */ 53 if (!seg) { 54 page = virt_to_page(skb->data); 55 offset = offset_in_page(skb->data); 56 *len = skb_headlen(skb); 57 } else { 58 frag = &skb_shinfo(skb)->frags[seg - 1]; 59 page = skb_frag_page(frag); 60 offset = skb_frag_off(frag); 61 *len = skb_frag_size(frag); 62 } 63 return otx2_dma_map_page(pfvf, page, offset, *len, DMA_TO_DEVICE); 64 } 65 66 static void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg) 67 { 68 int seg; 69 70 for (seg = 0; seg < sg->num_segs; seg++) { 71 otx2_dma_unmap_page(pfvf, sg->dma_addr[seg], 72 sg->size[seg], DMA_TO_DEVICE); 73 } 74 sg->num_segs = 0; 75 } 76 77 static void otx2_snd_pkt_handler(struct otx2_nic *pfvf, 78 struct otx2_cq_queue *cq, 79 struct otx2_snd_queue *sq, 80 struct nix_cqe_tx_s *cqe, 81 int budget, int *tx_pkts, int *tx_bytes) 82 { 83 struct nix_send_comp_s *snd_comp = &cqe->comp; 84 struct sk_buff *skb = NULL; 85 struct sg_list *sg; 86 87 if (unlikely(snd_comp->status) && netif_msg_tx_err(pfvf)) 88 net_err_ratelimited("%s: TX%d: Error in send CQ status:%x\n", 89 pfvf->netdev->name, cq->cint_idx, 90 snd_comp->status); 91 92 sg = &sq->sg[snd_comp->sqe_id]; 93 skb = (struct sk_buff *)sg->skb; 94 if (unlikely(!skb)) 95 return; 96 97 *tx_bytes += skb->len; 98 (*tx_pkts)++; 99 otx2_dma_unmap_skb_frags(pfvf, sg); 100 napi_consume_skb(skb, budget); 101 sg->skb = (u64)NULL; 102 } 103 104 static void otx2_skb_add_frag(struct otx2_nic *pfvf, struct sk_buff *skb, 105 u64 iova, int len) 106 { 107 struct page *page; 108 void *va; 109 110 va = phys_to_virt(otx2_iova_to_phys(pfvf->iommu_domain, iova)); 111 page = virt_to_page(va); 112 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 113 va - page_address(page), len, pfvf->rbsize); 114 115 otx2_dma_unmap_page(pfvf, iova - OTX2_HEAD_ROOM, 116 pfvf->rbsize, DMA_FROM_DEVICE); 117 } 118 119 static void otx2_set_rxhash(struct otx2_nic *pfvf, 120 struct nix_cqe_rx_s *cqe, struct sk_buff *skb) 121 { 122 enum pkt_hash_types hash_type = PKT_HASH_TYPE_NONE; 123 struct otx2_rss_info *rss; 124 u32 hash = 0; 125 126 if (!(pfvf->netdev->features & NETIF_F_RXHASH)) 127 return; 128 129 rss = &pfvf->hw.rss_info; 130 if (rss->flowkey_cfg) { 131 if (rss->flowkey_cfg & 132 ~(NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6)) 133 hash_type = PKT_HASH_TYPE_L4; 134 else 135 hash_type = PKT_HASH_TYPE_L3; 136 hash = cqe->hdr.flow_tag; 137 } 138 skb_set_hash(skb, hash, hash_type); 139 } 140 141 static void otx2_free_rcv_seg(struct otx2_nic *pfvf, struct nix_cqe_rx_s *cqe, 142 int qidx) 143 { 144 struct nix_rx_sg_s *sg = &cqe->sg; 145 void *end, *start; 146 u64 *seg_addr; 147 int seg; 148 149 start = (void *)sg; 150 end = start + ((cqe->parse.desc_sizem1 + 1) * 16); 151 while (start < end) { 152 sg = (struct nix_rx_sg_s *)start; 153 seg_addr = &sg->seg_addr; 154 for (seg = 0; seg < sg->segs; seg++, seg_addr++) 155 otx2_aura_freeptr(pfvf, qidx, *seg_addr & ~0x07ULL); 156 start += sizeof(*sg); 157 } 158 } 159 160 static bool otx2_check_rcv_errors(struct otx2_nic *pfvf, 161 struct nix_cqe_rx_s *cqe, int qidx) 162 { 163 struct otx2_drv_stats *stats = &pfvf->hw.drv_stats; 164 struct nix_rx_parse_s *parse = &cqe->parse; 165 166 if (netif_msg_rx_err(pfvf)) 167 netdev_err(pfvf->netdev, 168 "RQ%d: Error pkt with errlev:0x%x errcode:0x%x\n", 169 qidx, parse->errlev, parse->errcode); 170 171 if (parse->errlev == NPC_ERRLVL_RE) { 172 switch (parse->errcode) { 173 case ERRCODE_FCS: 174 case ERRCODE_FCS_RCV: 175 atomic_inc(&stats->rx_fcs_errs); 176 break; 177 case ERRCODE_UNDERSIZE: 178 atomic_inc(&stats->rx_undersize_errs); 179 break; 180 case ERRCODE_OVERSIZE: 181 atomic_inc(&stats->rx_oversize_errs); 182 break; 183 case ERRCODE_OL2_LEN_MISMATCH: 184 atomic_inc(&stats->rx_len_errs); 185 break; 186 default: 187 atomic_inc(&stats->rx_other_errs); 188 break; 189 } 190 } else if (parse->errlev == NPC_ERRLVL_NIX) { 191 switch (parse->errcode) { 192 case ERRCODE_OL3_LEN: 193 case ERRCODE_OL4_LEN: 194 case ERRCODE_IL3_LEN: 195 case ERRCODE_IL4_LEN: 196 atomic_inc(&stats->rx_len_errs); 197 break; 198 case ERRCODE_OL4_CSUM: 199 case ERRCODE_IL4_CSUM: 200 atomic_inc(&stats->rx_csum_errs); 201 break; 202 default: 203 atomic_inc(&stats->rx_other_errs); 204 break; 205 } 206 } else { 207 atomic_inc(&stats->rx_other_errs); 208 /* For now ignore all the NPC parser errors and 209 * pass the packets to stack. 210 */ 211 if (cqe->sg.segs == 1) 212 return false; 213 } 214 215 /* If RXALL is enabled pass on packets to stack. */ 216 if (cqe->sg.segs == 1 && (pfvf->netdev->features & NETIF_F_RXALL)) 217 return false; 218 219 /* Free buffer back to pool */ 220 if (cqe->sg.segs) 221 otx2_free_rcv_seg(pfvf, cqe, qidx); 222 return true; 223 } 224 225 static void otx2_rcv_pkt_handler(struct otx2_nic *pfvf, 226 struct napi_struct *napi, 227 struct otx2_cq_queue *cq, 228 struct nix_cqe_rx_s *cqe) 229 { 230 struct nix_rx_parse_s *parse = &cqe->parse; 231 struct sk_buff *skb = NULL; 232 233 if (unlikely(parse->errlev || parse->errcode || cqe->sg.segs > 1)) { 234 if (otx2_check_rcv_errors(pfvf, cqe, cq->cq_idx)) 235 return; 236 } 237 238 skb = napi_get_frags(napi); 239 if (unlikely(!skb)) 240 return; 241 242 otx2_skb_add_frag(pfvf, skb, cqe->sg.seg_addr, cqe->sg.seg_size); 243 cq->pool_ptrs++; 244 245 otx2_set_rxhash(pfvf, cqe, skb); 246 247 skb_record_rx_queue(skb, cq->cq_idx); 248 if (pfvf->netdev->features & NETIF_F_RXCSUM) 249 skb->ip_summed = CHECKSUM_UNNECESSARY; 250 251 napi_gro_frags(napi); 252 } 253 254 static int otx2_rx_napi_handler(struct otx2_nic *pfvf, 255 struct napi_struct *napi, 256 struct otx2_cq_queue *cq, int budget) 257 { 258 struct nix_cqe_rx_s *cqe; 259 int processed_cqe = 0; 260 s64 bufptr; 261 262 while (likely(processed_cqe < budget)) { 263 cqe = (struct nix_cqe_rx_s *)CQE_ADDR(cq, cq->cq_head); 264 if (cqe->hdr.cqe_type == NIX_XQE_TYPE_INVALID || 265 !cqe->sg.seg_addr) { 266 if (!processed_cqe) 267 return 0; 268 break; 269 } 270 cq->cq_head++; 271 cq->cq_head &= (cq->cqe_cnt - 1); 272 273 otx2_rcv_pkt_handler(pfvf, napi, cq, cqe); 274 275 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID; 276 cqe->sg.seg_addr = 0x00; 277 processed_cqe++; 278 } 279 280 /* Free CQEs to HW */ 281 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 282 ((u64)cq->cq_idx << 32) | processed_cqe); 283 284 if (unlikely(!cq->pool_ptrs)) 285 return 0; 286 287 /* Refill pool with new buffers */ 288 while (cq->pool_ptrs) { 289 bufptr = __otx2_alloc_rbuf(pfvf, cq->rbpool); 290 if (unlikely(bufptr <= 0)) { 291 struct refill_work *work; 292 struct delayed_work *dwork; 293 294 work = &pfvf->refill_wrk[cq->cq_idx]; 295 dwork = &work->pool_refill_work; 296 /* Schedule a task if no other task is running */ 297 if (!cq->refill_task_sched) { 298 cq->refill_task_sched = true; 299 schedule_delayed_work(dwork, 300 msecs_to_jiffies(100)); 301 } 302 break; 303 } 304 otx2_aura_freeptr(pfvf, cq->cq_idx, bufptr + OTX2_HEAD_ROOM); 305 cq->pool_ptrs--; 306 } 307 308 return processed_cqe; 309 } 310 311 static int otx2_tx_napi_handler(struct otx2_nic *pfvf, 312 struct otx2_cq_queue *cq, int budget) 313 { 314 int tx_pkts = 0, tx_bytes = 0; 315 struct nix_cqe_tx_s *cqe; 316 int processed_cqe = 0; 317 318 while (likely(processed_cqe < budget)) { 319 cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq); 320 if (unlikely(!cqe)) { 321 if (!processed_cqe) 322 return 0; 323 break; 324 } 325 otx2_snd_pkt_handler(pfvf, cq, &pfvf->qset.sq[cq->cint_idx], 326 cqe, budget, &tx_pkts, &tx_bytes); 327 328 cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID; 329 processed_cqe++; 330 } 331 332 /* Free CQEs to HW */ 333 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 334 ((u64)cq->cq_idx << 32) | processed_cqe); 335 336 if (likely(tx_pkts)) { 337 struct netdev_queue *txq; 338 339 txq = netdev_get_tx_queue(pfvf->netdev, cq->cint_idx); 340 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes); 341 /* Check if queue was stopped earlier due to ring full */ 342 smp_mb(); 343 if (netif_tx_queue_stopped(txq) && 344 netif_carrier_ok(pfvf->netdev)) 345 netif_tx_wake_queue(txq); 346 } 347 return 0; 348 } 349 350 int otx2_napi_handler(struct napi_struct *napi, int budget) 351 { 352 struct otx2_cq_poll *cq_poll; 353 int workdone = 0, cq_idx, i; 354 struct otx2_cq_queue *cq; 355 struct otx2_qset *qset; 356 struct otx2_nic *pfvf; 357 358 cq_poll = container_of(napi, struct otx2_cq_poll, napi); 359 pfvf = (struct otx2_nic *)cq_poll->dev; 360 qset = &pfvf->qset; 361 362 for (i = CQS_PER_CINT - 1; i >= 0; i--) { 363 cq_idx = cq_poll->cq_ids[i]; 364 if (unlikely(cq_idx == CINT_INVALID_CQ)) 365 continue; 366 cq = &qset->cq[cq_idx]; 367 if (cq->cq_type == CQ_RX) { 368 /* If the RQ refill WQ task is running, skip napi 369 * scheduler for this queue. 370 */ 371 if (cq->refill_task_sched) 372 continue; 373 workdone += otx2_rx_napi_handler(pfvf, napi, 374 cq, budget); 375 } else { 376 workdone += otx2_tx_napi_handler(pfvf, cq, budget); 377 } 378 } 379 380 /* Clear the IRQ */ 381 otx2_write64(pfvf, NIX_LF_CINTX_INT(cq_poll->cint_idx), BIT_ULL(0)); 382 383 if (workdone < budget && napi_complete_done(napi, workdone)) { 384 /* If interface is going down, don't re-enable IRQ */ 385 if (pfvf->flags & OTX2_FLAG_INTF_DOWN) 386 return workdone; 387 388 /* Re-enable interrupts */ 389 otx2_write64(pfvf, NIX_LF_CINTX_ENA_W1S(cq_poll->cint_idx), 390 BIT_ULL(0)); 391 } 392 return workdone; 393 } 394 395 static void otx2_sqe_flush(struct otx2_snd_queue *sq, int size) 396 { 397 u64 status; 398 399 /* Packet data stores should finish before SQE is flushed to HW */ 400 dma_wmb(); 401 402 do { 403 memcpy(sq->lmt_addr, sq->sqe_base, size); 404 status = otx2_lmt_flush(sq->io_addr); 405 } while (status == 0); 406 407 sq->head++; 408 sq->head &= (sq->sqe_cnt - 1); 409 } 410 411 #define MAX_SEGS_PER_SG 3 412 /* Add SQE scatter/gather subdescriptor structure */ 413 static bool otx2_sqe_add_sg(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 414 struct sk_buff *skb, int num_segs, int *offset) 415 { 416 struct nix_sqe_sg_s *sg = NULL; 417 u64 dma_addr, *iova = NULL; 418 u16 *sg_lens = NULL; 419 int seg, len; 420 421 sq->sg[sq->head].num_segs = 0; 422 423 for (seg = 0; seg < num_segs; seg++) { 424 if ((seg % MAX_SEGS_PER_SG) == 0) { 425 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset); 426 sg->ld_type = NIX_SEND_LDTYPE_LDD; 427 sg->subdc = NIX_SUBDC_SG; 428 sg->segs = 0; 429 sg_lens = (void *)sg; 430 iova = (void *)sg + sizeof(*sg); 431 /* Next subdc always starts at a 16byte boundary. 432 * So if sg->segs is whether 2 or 3, offset += 16bytes. 433 */ 434 if ((num_segs - seg) >= (MAX_SEGS_PER_SG - 1)) 435 *offset += sizeof(*sg) + (3 * sizeof(u64)); 436 else 437 *offset += sizeof(*sg) + sizeof(u64); 438 } 439 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len); 440 if (dma_mapping_error(pfvf->dev, dma_addr)) 441 return false; 442 443 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = len; 444 sg->segs++; 445 *iova++ = dma_addr; 446 447 /* Save DMA mapping info for later unmapping */ 448 sq->sg[sq->head].dma_addr[seg] = dma_addr; 449 sq->sg[sq->head].size[seg] = len; 450 sq->sg[sq->head].num_segs++; 451 } 452 453 sq->sg[sq->head].skb = (u64)skb; 454 return true; 455 } 456 457 /* Add SQE extended header subdescriptor */ 458 static void otx2_sqe_add_ext(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 459 struct sk_buff *skb, int *offset) 460 { 461 struct nix_sqe_ext_s *ext; 462 463 ext = (struct nix_sqe_ext_s *)(sq->sqe_base + *offset); 464 ext->subdc = NIX_SUBDC_EXT; 465 if (skb_shinfo(skb)->gso_size) { 466 ext->lso = 1; 467 ext->lso_sb = skb_transport_offset(skb) + tcp_hdrlen(skb); 468 ext->lso_mps = skb_shinfo(skb)->gso_size; 469 470 /* Only TSOv4 and TSOv6 GSO offloads are supported */ 471 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) { 472 ext->lso_format = pfvf->hw.lso_tsov4_idx; 473 474 /* HW adds payload size to 'ip_hdr->tot_len' while 475 * sending TSO segment, hence set payload length 476 * in IP header of the packet to just header length. 477 */ 478 ip_hdr(skb)->tot_len = 479 htons(ext->lso_sb - skb_network_offset(skb)); 480 } else { 481 ext->lso_format = pfvf->hw.lso_tsov6_idx; 482 ipv6_hdr(skb)->payload_len = 483 htons(ext->lso_sb - skb_network_offset(skb)); 484 } 485 } 486 *offset += sizeof(*ext); 487 } 488 489 /* Add SQE header subdescriptor structure */ 490 static void otx2_sqe_add_hdr(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 491 struct nix_sqe_hdr_s *sqe_hdr, 492 struct sk_buff *skb, u16 qidx) 493 { 494 int proto = 0; 495 496 /* Check if SQE was framed before, if yes then no need to 497 * set these constants again and again. 498 */ 499 if (!sqe_hdr->total) { 500 /* Don't free Tx buffers to Aura */ 501 sqe_hdr->df = 1; 502 sqe_hdr->aura = sq->aura_id; 503 /* Post a CQE Tx after pkt transmission */ 504 sqe_hdr->pnc = 1; 505 sqe_hdr->sq = qidx; 506 } 507 sqe_hdr->total = skb->len; 508 /* Set SQE identifier which will be used later for freeing SKB */ 509 sqe_hdr->sqe_id = sq->head; 510 511 /* Offload TCP/UDP checksum to HW */ 512 if (skb->ip_summed == CHECKSUM_PARTIAL) { 513 sqe_hdr->ol3ptr = skb_network_offset(skb); 514 sqe_hdr->ol4ptr = skb_transport_offset(skb); 515 /* get vlan protocol Ethertype */ 516 if (eth_type_vlan(skb->protocol)) 517 skb->protocol = vlan_get_protocol(skb); 518 519 if (skb->protocol == htons(ETH_P_IP)) { 520 proto = ip_hdr(skb)->protocol; 521 /* In case of TSO, HW needs this to be explicitly set. 522 * So set this always, instead of adding a check. 523 */ 524 sqe_hdr->ol3type = NIX_SENDL3TYPE_IP4_CKSUM; 525 } else if (skb->protocol == htons(ETH_P_IPV6)) { 526 proto = ipv6_hdr(skb)->nexthdr; 527 } 528 529 if (proto == IPPROTO_TCP) 530 sqe_hdr->ol4type = NIX_SENDL4TYPE_TCP_CKSUM; 531 else if (proto == IPPROTO_UDP) 532 sqe_hdr->ol4type = NIX_SENDL4TYPE_UDP_CKSUM; 533 } 534 } 535 536 static int otx2_dma_map_tso_skb(struct otx2_nic *pfvf, 537 struct otx2_snd_queue *sq, 538 struct sk_buff *skb, int sqe, int hdr_len) 539 { 540 int num_segs = skb_shinfo(skb)->nr_frags + 1; 541 struct sg_list *sg = &sq->sg[sqe]; 542 u64 dma_addr; 543 int seg, len; 544 545 sg->num_segs = 0; 546 547 /* Get payload length at skb->data */ 548 len = skb_headlen(skb) - hdr_len; 549 550 for (seg = 0; seg < num_segs; seg++) { 551 /* Skip skb->data, if there is no payload */ 552 if (!seg && !len) 553 continue; 554 dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len); 555 if (dma_mapping_error(pfvf->dev, dma_addr)) 556 goto unmap; 557 558 /* Save DMA mapping info for later unmapping */ 559 sg->dma_addr[sg->num_segs] = dma_addr; 560 sg->size[sg->num_segs] = len; 561 sg->num_segs++; 562 } 563 return 0; 564 unmap: 565 otx2_dma_unmap_skb_frags(pfvf, sg); 566 return -EINVAL; 567 } 568 569 static u64 otx2_tso_frag_dma_addr(struct otx2_snd_queue *sq, 570 struct sk_buff *skb, int seg, 571 u64 seg_addr, int hdr_len, int sqe) 572 { 573 struct sg_list *sg = &sq->sg[sqe]; 574 const skb_frag_t *frag; 575 int offset; 576 577 if (seg < 0) 578 return sg->dma_addr[0] + (seg_addr - (u64)skb->data); 579 580 frag = &skb_shinfo(skb)->frags[seg]; 581 offset = seg_addr - (u64)skb_frag_address(frag); 582 if (skb_headlen(skb) - hdr_len) 583 seg++; 584 return sg->dma_addr[seg] + offset; 585 } 586 587 static void otx2_sqe_tso_add_sg(struct otx2_snd_queue *sq, 588 struct sg_list *list, int *offset) 589 { 590 struct nix_sqe_sg_s *sg = NULL; 591 u16 *sg_lens = NULL; 592 u64 *iova = NULL; 593 int seg; 594 595 /* Add SG descriptors with buffer addresses */ 596 for (seg = 0; seg < list->num_segs; seg++) { 597 if ((seg % MAX_SEGS_PER_SG) == 0) { 598 sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset); 599 sg->ld_type = NIX_SEND_LDTYPE_LDD; 600 sg->subdc = NIX_SUBDC_SG; 601 sg->segs = 0; 602 sg_lens = (void *)sg; 603 iova = (void *)sg + sizeof(*sg); 604 /* Next subdc always starts at a 16byte boundary. 605 * So if sg->segs is whether 2 or 3, offset += 16bytes. 606 */ 607 if ((list->num_segs - seg) >= (MAX_SEGS_PER_SG - 1)) 608 *offset += sizeof(*sg) + (3 * sizeof(u64)); 609 else 610 *offset += sizeof(*sg) + sizeof(u64); 611 } 612 sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = list->size[seg]; 613 *iova++ = list->dma_addr[seg]; 614 sg->segs++; 615 } 616 } 617 618 static void otx2_sq_append_tso(struct otx2_nic *pfvf, struct otx2_snd_queue *sq, 619 struct sk_buff *skb, u16 qidx) 620 { 621 struct netdev_queue *txq = netdev_get_tx_queue(pfvf->netdev, qidx); 622 int hdr_len, tcp_data, seg_len, pkt_len, offset; 623 struct nix_sqe_hdr_s *sqe_hdr; 624 int first_sqe = sq->head; 625 struct sg_list list; 626 struct tso_t tso; 627 628 hdr_len = tso_start(skb, &tso); 629 630 /* Map SKB's fragments to DMA. 631 * It's done here to avoid mapping for every TSO segment's packet. 632 */ 633 if (otx2_dma_map_tso_skb(pfvf, sq, skb, first_sqe, hdr_len)) { 634 dev_kfree_skb_any(skb); 635 return; 636 } 637 638 netdev_tx_sent_queue(txq, skb->len); 639 640 tcp_data = skb->len - hdr_len; 641 while (tcp_data > 0) { 642 char *hdr; 643 644 seg_len = min_t(int, skb_shinfo(skb)->gso_size, tcp_data); 645 tcp_data -= seg_len; 646 647 /* Set SQE's SEND_HDR */ 648 memset(sq->sqe_base, 0, sq->sqe_size); 649 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base); 650 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx); 651 offset = sizeof(*sqe_hdr); 652 653 /* Add TSO segment's pkt header */ 654 hdr = sq->tso_hdrs->base + (sq->head * TSO_HEADER_SIZE); 655 tso_build_hdr(skb, hdr, &tso, seg_len, tcp_data == 0); 656 list.dma_addr[0] = 657 sq->tso_hdrs->iova + (sq->head * TSO_HEADER_SIZE); 658 list.size[0] = hdr_len; 659 list.num_segs = 1; 660 661 /* Add TSO segment's payload data fragments */ 662 pkt_len = hdr_len; 663 while (seg_len > 0) { 664 int size; 665 666 size = min_t(int, tso.size, seg_len); 667 668 list.size[list.num_segs] = size; 669 list.dma_addr[list.num_segs] = 670 otx2_tso_frag_dma_addr(sq, skb, 671 tso.next_frag_idx - 1, 672 (u64)tso.data, hdr_len, 673 first_sqe); 674 list.num_segs++; 675 pkt_len += size; 676 seg_len -= size; 677 tso_build_data(skb, &tso, size); 678 } 679 sqe_hdr->total = pkt_len; 680 otx2_sqe_tso_add_sg(sq, &list, &offset); 681 682 /* DMA mappings and skb needs to be freed only after last 683 * TSO segment is transmitted out. So set 'PNC' only for 684 * last segment. Also point last segment's sqe_id to first 685 * segment's SQE index where skb address and DMA mappings 686 * are saved. 687 */ 688 if (!tcp_data) { 689 sqe_hdr->pnc = 1; 690 sqe_hdr->sqe_id = first_sqe; 691 sq->sg[first_sqe].skb = (u64)skb; 692 } else { 693 sqe_hdr->pnc = 0; 694 } 695 696 sqe_hdr->sizem1 = (offset / 16) - 1; 697 698 /* Flush SQE to HW */ 699 otx2_sqe_flush(sq, offset); 700 } 701 } 702 703 static bool is_hw_tso_supported(struct otx2_nic *pfvf, 704 struct sk_buff *skb) 705 { 706 int payload_len, last_seg_size; 707 708 if (!pfvf->hw.hw_tso) 709 return false; 710 711 /* HW has an issue due to which when the payload of the last LSO 712 * segment is shorter than 16 bytes, some header fields may not 713 * be correctly modified, hence don't offload such TSO segments. 714 */ 715 if (!is_96xx_B0(pfvf->pdev)) 716 return true; 717 718 payload_len = skb->len - (skb_transport_offset(skb) + tcp_hdrlen(skb)); 719 last_seg_size = payload_len % skb_shinfo(skb)->gso_size; 720 if (last_seg_size && last_seg_size < 16) 721 return false; 722 723 return true; 724 } 725 726 static int otx2_get_sqe_count(struct otx2_nic *pfvf, struct sk_buff *skb) 727 { 728 if (!skb_shinfo(skb)->gso_size) 729 return 1; 730 731 /* HW TSO */ 732 if (is_hw_tso_supported(pfvf, skb)) 733 return 1; 734 735 /* SW TSO */ 736 return skb_shinfo(skb)->gso_segs; 737 } 738 739 bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq, 740 struct sk_buff *skb, u16 qidx) 741 { 742 struct netdev_queue *txq = netdev_get_tx_queue(netdev, qidx); 743 struct otx2_nic *pfvf = netdev_priv(netdev); 744 int offset, num_segs, free_sqe; 745 struct nix_sqe_hdr_s *sqe_hdr; 746 747 /* Check if there is room for new SQE. 748 * 'Num of SQBs freed to SQ's pool - SQ's Aura count' 749 * will give free SQE count. 750 */ 751 free_sqe = (sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb; 752 753 if (free_sqe < sq->sqe_thresh || 754 free_sqe < otx2_get_sqe_count(pfvf, skb)) 755 return false; 756 757 num_segs = skb_shinfo(skb)->nr_frags + 1; 758 759 /* If SKB doesn't fit in a single SQE, linearize it. 760 * TODO: Consider adding JUMP descriptor instead. 761 */ 762 if (unlikely(num_segs > OTX2_MAX_FRAGS_IN_SQE)) { 763 if (__skb_linearize(skb)) { 764 dev_kfree_skb_any(skb); 765 return true; 766 } 767 num_segs = skb_shinfo(skb)->nr_frags + 1; 768 } 769 770 if (skb_shinfo(skb)->gso_size && !is_hw_tso_supported(pfvf, skb)) { 771 otx2_sq_append_tso(pfvf, sq, skb, qidx); 772 return true; 773 } 774 775 /* Set SQE's SEND_HDR. 776 * Do not clear the first 64bit as it contains constant info. 777 */ 778 memset(sq->sqe_base + 8, 0, sq->sqe_size - 8); 779 sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base); 780 otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx); 781 offset = sizeof(*sqe_hdr); 782 783 /* Add extended header if needed */ 784 otx2_sqe_add_ext(pfvf, sq, skb, &offset); 785 786 /* Add SG subdesc with data frags */ 787 if (!otx2_sqe_add_sg(pfvf, sq, skb, num_segs, &offset)) { 788 otx2_dma_unmap_skb_frags(pfvf, &sq->sg[sq->head]); 789 return false; 790 } 791 792 sqe_hdr->sizem1 = (offset / 16) - 1; 793 794 netdev_tx_sent_queue(txq, skb->len); 795 796 /* Flush SQE to HW */ 797 otx2_sqe_flush(sq, offset); 798 799 return true; 800 } 801 EXPORT_SYMBOL(otx2_sq_append_skb); 802 803 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq) 804 { 805 struct nix_cqe_rx_s *cqe; 806 int processed_cqe = 0; 807 u64 iova, pa; 808 809 while ((cqe = (struct nix_cqe_rx_s *)otx2_get_next_cqe(cq))) { 810 if (!cqe->sg.subdc) 811 continue; 812 processed_cqe++; 813 if (cqe->sg.segs > 1) { 814 otx2_free_rcv_seg(pfvf, cqe, cq->cq_idx); 815 continue; 816 } 817 iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM; 818 pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); 819 otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize, DMA_FROM_DEVICE); 820 put_page(virt_to_page(phys_to_virt(pa))); 821 } 822 823 /* Free CQEs to HW */ 824 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 825 ((u64)cq->cq_idx << 32) | processed_cqe); 826 } 827 828 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq) 829 { 830 struct sk_buff *skb = NULL; 831 struct otx2_snd_queue *sq; 832 struct nix_cqe_tx_s *cqe; 833 int processed_cqe = 0; 834 struct sg_list *sg; 835 836 sq = &pfvf->qset.sq[cq->cint_idx]; 837 838 while ((cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq))) { 839 sg = &sq->sg[cqe->comp.sqe_id]; 840 skb = (struct sk_buff *)sg->skb; 841 if (skb) { 842 otx2_dma_unmap_skb_frags(pfvf, sg); 843 dev_kfree_skb_any(skb); 844 sg->skb = (u64)NULL; 845 } 846 processed_cqe++; 847 } 848 849 /* Free CQEs to HW */ 850 otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, 851 ((u64)cq->cq_idx << 32) | processed_cqe); 852 } 853 854 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable) 855 { 856 struct msg_req *msg; 857 int err; 858 859 mutex_lock(&pfvf->mbox.lock); 860 if (enable) 861 msg = otx2_mbox_alloc_msg_nix_lf_start_rx(&pfvf->mbox); 862 else 863 msg = otx2_mbox_alloc_msg_nix_lf_stop_rx(&pfvf->mbox); 864 865 if (!msg) { 866 mutex_unlock(&pfvf->mbox.lock); 867 return -ENOMEM; 868 } 869 870 err = otx2_sync_mbox_msg(&pfvf->mbox); 871 mutex_unlock(&pfvf->mbox.lock); 872 return err; 873 } 874