1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: System Reset Controller on Intel Gateway SoCs
8
9maintainers:
10  - Dilip Kota <eswara.kota@linux.intel.com>
11
12properties:
13  compatible:
14    enum:
15      - intel,rcu-lgm
16      - intel,rcu-xrx200
17
18  reg:
19    description: Reset controller registers.
20    maxItems: 1
21
22  intel,global-reset:
23    description: Global reset register offset and bit offset.
24    allOf:
25      - $ref: /schemas/types.yaml#/definitions/uint32-array
26      - maxItems: 2
27
28  "#reset-cells":
29    minimum: 2
30    maximum: 3
31    description: |
32      First cell is reset request register offset.
33      Second cell is bit offset in reset request register.
34      Third cell is bit offset in reset status register.
35      For LGM SoC, reset cell count is 2 as bit offset in
36      reset request and reset status registers is same. Whereas
37      3 for legacy SoCs as bit offset differs.
38
39required:
40  - compatible
41  - reg
42  - intel,global-reset
43  - "#reset-cells"
44
45additionalProperties: false
46
47examples:
48  - |
49    rcu0: reset-controller@e0000000 {
50        compatible = "intel,rcu-lgm";
51        reg = <0xe0000000 0x20000>;
52        intel,global-reset = <0x10 30>;
53        #reset-cells = <2>;
54    };
55
56    pwm: pwm@e0d00000 {
57        status = "disabled";
58        compatible = "intel,lgm-pwm";
59        reg = <0xe0d00000 0x30>;
60        clocks = <&cgu0 1>;
61        #pwm-cells = <2>;
62        resets = <&rcu0 0x30 21>;
63    };
64