1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV architectural definitions 7 * 8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. 9 */ 10 11 #ifndef _ASM_X86_UV_UV_HUB_H 12 #define _ASM_X86_UV_UV_HUB_H 13 14 #ifdef CONFIG_X86_64 15 #include <linux/numa.h> 16 #include <linux/percpu.h> 17 #include <linux/timer.h> 18 #include <linux/io.h> 19 #include <linux/topology.h> 20 #include <asm/types.h> 21 #include <asm/percpu.h> 22 #include <asm/uv/uv.h> 23 #include <asm/uv/uv_mmrs.h> 24 #include <asm/uv/bios.h> 25 #include <asm/irq_vectors.h> 26 #include <asm/io_apic.h> 27 28 29 /* 30 * Addressing Terminology 31 * 32 * M - The low M bits of a physical address represent the offset 33 * into the blade local memory. RAM memory on a blade is physically 34 * contiguous (although various IO spaces may punch holes in 35 * it).. 36 * 37 * N - Number of bits in the node portion of a socket physical 38 * address. 39 * 40 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of 41 * routers always have low bit of 1, C/MBricks have low bit 42 * equal to 0. Most addressing macros that target UV hub chips 43 * right shift the NASID by 1 to exclude the always-zero bit. 44 * NASIDs contain up to 15 bits. 45 * 46 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead 47 * of nasids. 48 * 49 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant 50 * of the nasid for socket usage. 51 * 52 * GPA - (global physical address) a socket physical address converted 53 * so that it can be used by the GRU as a global address. Socket 54 * physical addresses 1) need additional NASID (node) bits added 55 * to the high end of the address, and 2) unaliased if the 56 * partition does not have a physical address 0. In addition, on 57 * UV2 rev 1, GPAs need the gnode left shifted to bits 39 or 40. 58 * 59 * 60 * NumaLink Global Physical Address Format: 61 * +--------------------------------+---------------------+ 62 * |00..000| GNODE | NodeOffset | 63 * +--------------------------------+---------------------+ 64 * |<-------53 - M bits --->|<--------M bits -----> 65 * 66 * M - number of node offset bits (35 .. 40) 67 * 68 * 69 * Memory/UV-HUB Processor Socket Address Format: 70 * +----------------+---------------+---------------------+ 71 * |00..000000000000| PNODE | NodeOffset | 72 * +----------------+---------------+---------------------+ 73 * <--- N bits --->|<--------M bits -----> 74 * 75 * M - number of node offset bits (35 .. 40) 76 * N - number of PNODE bits (0 .. 10) 77 * 78 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). 79 * The actual values are configuration dependent and are set at 80 * boot time. M & N values are set by the hardware/BIOS at boot. 81 * 82 * 83 * APICID format 84 * NOTE!!!!!! This is the current format of the APICID. However, code 85 * should assume that this will change in the future. Use functions 86 * in this file for all APICID bit manipulations and conversion. 87 * 88 * 1111110000000000 89 * 5432109876543210 90 * pppppppppplc0cch Nehalem-EX (12 bits in hdw reg) 91 * ppppppppplcc0cch Westmere-EX (12 bits in hdw reg) 92 * pppppppppppcccch SandyBridge (15 bits in hdw reg) 93 * sssssssssss 94 * 95 * p = pnode bits 96 * l = socket number on board 97 * c = core 98 * h = hyperthread 99 * s = bits that are in the SOCKET_ID CSR 100 * 101 * Note: Processor may support fewer bits in the APICID register. The ACPI 102 * tables hold all 16 bits. Software needs to be aware of this. 103 * 104 * Unless otherwise specified, all references to APICID refer to 105 * the FULL value contained in ACPI tables, not the subset in the 106 * processor APICID register. 107 */ 108 109 /* 110 * Maximum number of bricks in all partitions and in all coherency domains. 111 * This is the total number of bricks accessible in the numalink fabric. It 112 * includes all C & M bricks. Routers are NOT included. 113 * 114 * This value is also the value of the maximum number of non-router NASIDs 115 * in the numalink fabric. 116 * 117 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. 118 */ 119 #define UV_MAX_NUMALINK_BLADES 16384 120 121 /* 122 * Maximum number of C/Mbricks within a software SSI (hardware may support 123 * more). 124 */ 125 #define UV_MAX_SSI_BLADES 256 126 127 /* 128 * The largest possible NASID of a C or M brick (+ 2) 129 */ 130 #define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2) 131 132 /* System Controller Interface Reg info */ 133 struct uv_scir_s { 134 struct timer_list timer; 135 unsigned long offset; 136 unsigned long last; 137 unsigned long idle_on; 138 unsigned long idle_off; 139 unsigned char state; 140 unsigned char enabled; 141 }; 142 143 /* GAM (globally addressed memory) range table */ 144 struct uv_gam_range_s { 145 u32 limit; /* PA bits 56:26 (GAM_RANGE_SHFT) */ 146 u16 nasid; /* node's global physical address */ 147 s8 base; /* entry index of node's base addr */ 148 u8 reserved; 149 }; 150 151 /* 152 * The following defines attributes of the HUB chip. These attributes are 153 * frequently referenced and are kept in a common per hub struct. 154 * After setup, the struct is read only, so it should be readily 155 * available in the L3 cache on the cpu socket for the node. 156 */ 157 struct uv_hub_info_s { 158 unsigned long global_mmr_base; 159 unsigned long global_mmr_shift; 160 unsigned long gpa_mask; 161 unsigned short *socket_to_node; 162 unsigned short *socket_to_pnode; 163 unsigned short *pnode_to_socket; 164 struct uv_gam_range_s *gr_table; 165 unsigned short min_socket; 166 unsigned short min_pnode; 167 unsigned char m_val; 168 unsigned char n_val; 169 unsigned char gr_table_len; 170 unsigned char hub_revision; 171 unsigned char apic_pnode_shift; 172 unsigned char gpa_shift; 173 unsigned char m_shift; 174 unsigned char n_lshift; 175 unsigned int gnode_extra; 176 unsigned long gnode_upper; 177 unsigned long lowmem_remap_top; 178 unsigned long lowmem_remap_base; 179 unsigned long global_gru_base; 180 unsigned long global_gru_shift; 181 unsigned short pnode; 182 unsigned short pnode_mask; 183 unsigned short coherency_domain_number; 184 unsigned short numa_blade_id; 185 unsigned short nr_possible_cpus; 186 unsigned short nr_online_cpus; 187 short memory_nid; 188 }; 189 190 /* CPU specific info with a pointer to the hub common info struct */ 191 struct uv_cpu_info_s { 192 void *p_uv_hub_info; 193 unsigned char blade_cpu_id; 194 struct uv_scir_s scir; 195 }; 196 DECLARE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); 197 198 #define uv_cpu_info this_cpu_ptr(&__uv_cpu_info) 199 #define uv_cpu_info_per(cpu) (&per_cpu(__uv_cpu_info, cpu)) 200 201 #define uv_scir_info (&uv_cpu_info->scir) 202 #define uv_cpu_scir_info(cpu) (&uv_cpu_info_per(cpu)->scir) 203 204 /* Node specific hub common info struct */ 205 extern void **__uv_hub_info_list; 206 static inline struct uv_hub_info_s *uv_hub_info_list(int node) 207 { 208 return (struct uv_hub_info_s *)__uv_hub_info_list[node]; 209 } 210 211 static inline struct uv_hub_info_s *_uv_hub_info(void) 212 { 213 return (struct uv_hub_info_s *)uv_cpu_info->p_uv_hub_info; 214 } 215 #define uv_hub_info _uv_hub_info() 216 217 static inline struct uv_hub_info_s *uv_cpu_hub_info(int cpu) 218 { 219 return (struct uv_hub_info_s *)uv_cpu_info_per(cpu)->p_uv_hub_info; 220 } 221 222 /* 223 * HUB revision ranges for each UV HUB architecture. 224 * This is a software convention - NOT the hardware revision numbers in 225 * the hub chip. 226 */ 227 #define UV2_HUB_REVISION_BASE 3 228 #define UV3_HUB_REVISION_BASE 5 229 #define UV4_HUB_REVISION_BASE 7 230 #define UV4A_HUB_REVISION_BASE 8 /* UV4 (fixed) rev 2 */ 231 232 static inline int is_uv2_hub(void) 233 { 234 return is_uv_hubbed(uv(2)); 235 } 236 237 static inline int is_uv3_hub(void) 238 { 239 return is_uv_hubbed(uv(3)); 240 } 241 242 /* First test "is UV4A", then "is UV4" */ 243 static inline int is_uv4a_hub(void) 244 { 245 if (is_uv_hubbed(uv(4))) 246 return (uv_hub_info->hub_revision == UV4A_HUB_REVISION_BASE); 247 return 0; 248 } 249 250 static inline int is_uv4_hub(void) 251 { 252 return is_uv_hubbed(uv(4)); 253 } 254 255 static inline int is_uvx_hub(void) 256 { 257 return (is_uv_hubbed(-2) >= uv(2)); 258 } 259 260 static inline int is_uv_hub(void) 261 { 262 return is_uvx_hub(); 263 } 264 265 union uvh_apicid { 266 unsigned long v; 267 struct uvh_apicid_s { 268 unsigned long local_apic_mask : 24; 269 unsigned long local_apic_shift : 5; 270 unsigned long unused1 : 3; 271 unsigned long pnode_mask : 24; 272 unsigned long pnode_shift : 5; 273 unsigned long unused2 : 3; 274 } s; 275 }; 276 277 /* 278 * Local & Global MMR space macros. 279 * Note: macros are intended to be used ONLY by inline functions 280 * in this file - not by other kernel code. 281 * n - NASID (full 15-bit global nasid) 282 * g - GNODE (full 15-bit global nasid, right shifted 1) 283 * p - PNODE (local part of nsids, right shifted 1) 284 */ 285 #define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) 286 #define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra) 287 #define UV_PNODE_TO_NASID(p) (UV_PNODE_TO_GNODE(p) << 1) 288 289 #define UV2_LOCAL_MMR_BASE 0xfa000000UL 290 #define UV2_GLOBAL_MMR32_BASE 0xfc000000UL 291 #define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 292 #define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) 293 294 #define UV3_LOCAL_MMR_BASE 0xfa000000UL 295 #define UV3_GLOBAL_MMR32_BASE 0xfc000000UL 296 #define UV3_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 297 #define UV3_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) 298 299 #define UV4_LOCAL_MMR_BASE 0xfa000000UL 300 #define UV4_GLOBAL_MMR32_BASE 0xfc000000UL 301 #define UV4_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 302 #define UV4_GLOBAL_MMR32_SIZE (16UL * 1024 * 1024) 303 304 #define UV_LOCAL_MMR_BASE ( \ 305 is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \ 306 is_uv3_hub() ? UV3_LOCAL_MMR_BASE : \ 307 /*is_uv4_hub*/ UV4_LOCAL_MMR_BASE) 308 309 #define UV_GLOBAL_MMR32_BASE ( \ 310 is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE : \ 311 is_uv3_hub() ? UV3_GLOBAL_MMR32_BASE : \ 312 /*is_uv4_hub*/ UV4_GLOBAL_MMR32_BASE) 313 314 #define UV_LOCAL_MMR_SIZE ( \ 315 is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \ 316 is_uv3_hub() ? UV3_LOCAL_MMR_SIZE : \ 317 /*is_uv4_hub*/ UV4_LOCAL_MMR_SIZE) 318 319 #define UV_GLOBAL_MMR32_SIZE ( \ 320 is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE : \ 321 is_uv3_hub() ? UV3_GLOBAL_MMR32_SIZE : \ 322 /*is_uv4_hub*/ UV4_GLOBAL_MMR32_SIZE) 323 324 #define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) 325 326 #define UV_GLOBAL_GRU_MMR_BASE 0x4000000 327 328 #define UV_GLOBAL_MMR32_PNODE_SHIFT 15 329 #define _UV_GLOBAL_MMR64_PNODE_SHIFT 26 330 #define UV_GLOBAL_MMR64_PNODE_SHIFT (uv_hub_info->global_mmr_shift) 331 332 #define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) 333 334 #define UV_GLOBAL_MMR64_PNODE_BITS(p) \ 335 (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT) 336 337 #define UVH_APICID 0x002D0E00L 338 #define UV_APIC_PNODE_SHIFT 6 339 340 /* Local Bus from cpu's perspective */ 341 #define LOCAL_BUS_BASE 0x1c00000 342 #define LOCAL_BUS_SIZE (4 * 1024 * 1024) 343 344 /* 345 * System Controller Interface Reg 346 * 347 * Note there are NO leds on a UV system. This register is only 348 * used by the system controller to monitor system-wide operation. 349 * There are 64 regs per node. With Nahelem cpus (2 cores per node, 350 * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on 351 * a node. 352 * 353 * The window is located at top of ACPI MMR space 354 */ 355 #define SCIR_WINDOW_COUNT 64 356 #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ 357 LOCAL_BUS_SIZE - \ 358 SCIR_WINDOW_COUNT) 359 360 #define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ 361 #define SCIR_CPU_ACTIVITY 0x02 /* not idle */ 362 #define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ 363 364 /* Loop through all installed blades */ 365 #define for_each_possible_blade(bid) \ 366 for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++) 367 368 /* 369 * Macros for converting between kernel virtual addresses, socket local physical 370 * addresses, and UV global physical addresses. 371 * Note: use the standard __pa() & __va() macros for converting 372 * between socket virtual and socket physical addresses. 373 */ 374 375 /* global bits offset - number of local address bits in gpa for this UV arch */ 376 static inline unsigned int uv_gpa_shift(void) 377 { 378 return uv_hub_info->gpa_shift; 379 } 380 #define _uv_gpa_shift 381 382 /* Find node that has the address range that contains global address */ 383 static inline struct uv_gam_range_s *uv_gam_range(unsigned long pa) 384 { 385 struct uv_gam_range_s *gr = uv_hub_info->gr_table; 386 unsigned long pal = (pa & uv_hub_info->gpa_mask) >> UV_GAM_RANGE_SHFT; 387 int i, num = uv_hub_info->gr_table_len; 388 389 if (gr) { 390 for (i = 0; i < num; i++, gr++) { 391 if (pal < gr->limit) 392 return gr; 393 } 394 } 395 pr_crit("UV: GAM Range for 0x%lx not found at %p!\n", pa, gr); 396 BUG(); 397 } 398 399 /* Return base address of node that contains global address */ 400 static inline unsigned long uv_gam_range_base(unsigned long pa) 401 { 402 struct uv_gam_range_s *gr = uv_gam_range(pa); 403 int base = gr->base; 404 405 if (base < 0) 406 return 0UL; 407 408 return uv_hub_info->gr_table[base].limit; 409 } 410 411 /* socket phys RAM --> UV global NASID (UV4+) */ 412 static inline unsigned long uv_soc_phys_ram_to_nasid(unsigned long paddr) 413 { 414 return uv_gam_range(paddr)->nasid; 415 } 416 #define _uv_soc_phys_ram_to_nasid 417 418 /* socket virtual --> UV global NASID (UV4+) */ 419 static inline unsigned long uv_gpa_nasid(void *v) 420 { 421 return uv_soc_phys_ram_to_nasid(__pa(v)); 422 } 423 424 /* socket phys RAM --> UV global physical address */ 425 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) 426 { 427 unsigned int m_val = uv_hub_info->m_val; 428 429 if (paddr < uv_hub_info->lowmem_remap_top) 430 paddr |= uv_hub_info->lowmem_remap_base; 431 432 if (m_val) { 433 paddr |= uv_hub_info->gnode_upper; 434 paddr = ((paddr << uv_hub_info->m_shift) 435 >> uv_hub_info->m_shift) | 436 ((paddr >> uv_hub_info->m_val) 437 << uv_hub_info->n_lshift); 438 } else { 439 paddr |= uv_soc_phys_ram_to_nasid(paddr) 440 << uv_hub_info->gpa_shift; 441 } 442 return paddr; 443 } 444 445 /* socket virtual --> UV global physical address */ 446 static inline unsigned long uv_gpa(void *v) 447 { 448 return uv_soc_phys_ram_to_gpa(__pa(v)); 449 } 450 451 /* Top two bits indicate the requested address is in MMR space. */ 452 static inline int 453 uv_gpa_in_mmr_space(unsigned long gpa) 454 { 455 return (gpa >> 62) == 0x3UL; 456 } 457 458 /* UV global physical address --> socket phys RAM */ 459 static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa) 460 { 461 unsigned long paddr; 462 unsigned long remap_base = uv_hub_info->lowmem_remap_base; 463 unsigned long remap_top = uv_hub_info->lowmem_remap_top; 464 unsigned int m_val = uv_hub_info->m_val; 465 466 if (m_val) 467 gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | 468 ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val); 469 470 paddr = gpa & uv_hub_info->gpa_mask; 471 if (paddr >= remap_base && paddr < remap_base + remap_top) 472 paddr -= remap_base; 473 return paddr; 474 } 475 476 /* gpa -> gnode */ 477 static inline unsigned long uv_gpa_to_gnode(unsigned long gpa) 478 { 479 unsigned int n_lshift = uv_hub_info->n_lshift; 480 481 if (n_lshift) 482 return gpa >> n_lshift; 483 484 return uv_gam_range(gpa)->nasid >> 1; 485 } 486 487 /* gpa -> pnode */ 488 static inline int uv_gpa_to_pnode(unsigned long gpa) 489 { 490 return uv_gpa_to_gnode(gpa) & uv_hub_info->pnode_mask; 491 } 492 493 /* gpa -> node offset */ 494 static inline unsigned long uv_gpa_to_offset(unsigned long gpa) 495 { 496 unsigned int m_shift = uv_hub_info->m_shift; 497 498 if (m_shift) 499 return (gpa << m_shift) >> m_shift; 500 501 return (gpa & uv_hub_info->gpa_mask) - uv_gam_range_base(gpa); 502 } 503 504 /* Convert socket to node */ 505 static inline int _uv_socket_to_node(int socket, unsigned short *s2nid) 506 { 507 return s2nid ? s2nid[socket - uv_hub_info->min_socket] : socket; 508 } 509 510 static inline int uv_socket_to_node(int socket) 511 { 512 return _uv_socket_to_node(socket, uv_hub_info->socket_to_node); 513 } 514 515 /* pnode, offset --> socket virtual */ 516 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) 517 { 518 unsigned int m_val = uv_hub_info->m_val; 519 unsigned long base; 520 unsigned short sockid, node, *p2s; 521 522 if (m_val) 523 return __va(((unsigned long)pnode << m_val) | offset); 524 525 p2s = uv_hub_info->pnode_to_socket; 526 sockid = p2s ? p2s[pnode - uv_hub_info->min_pnode] : pnode; 527 node = uv_socket_to_node(sockid); 528 529 /* limit address of previous socket is our base, except node 0 is 0 */ 530 if (!node) 531 return __va((unsigned long)offset); 532 533 base = (unsigned long)(uv_hub_info->gr_table[node - 1].limit); 534 return __va(base << UV_GAM_RANGE_SHFT | offset); 535 } 536 537 /* Extract/Convert a PNODE from an APICID (full apicid, not processor subset) */ 538 static inline int uv_apicid_to_pnode(int apicid) 539 { 540 int pnode = apicid >> uv_hub_info->apic_pnode_shift; 541 unsigned short *s2pn = uv_hub_info->socket_to_pnode; 542 543 return s2pn ? s2pn[pnode - uv_hub_info->min_socket] : pnode; 544 } 545 546 /* 547 * Access global MMRs using the low memory MMR32 space. This region supports 548 * faster MMR access but not all MMRs are accessible in this space. 549 */ 550 static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset) 551 { 552 return __va(UV_GLOBAL_MMR32_BASE | 553 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); 554 } 555 556 static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) 557 { 558 writeq(val, uv_global_mmr32_address(pnode, offset)); 559 } 560 561 static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset) 562 { 563 return readq(uv_global_mmr32_address(pnode, offset)); 564 } 565 566 /* 567 * Access Global MMR space using the MMR space located at the top of physical 568 * memory. 569 */ 570 static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset) 571 { 572 return __va(UV_GLOBAL_MMR64_BASE | 573 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); 574 } 575 576 static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val) 577 { 578 writeq(val, uv_global_mmr64_address(pnode, offset)); 579 } 580 581 static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset) 582 { 583 return readq(uv_global_mmr64_address(pnode, offset)); 584 } 585 586 static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val) 587 { 588 writeb(val, uv_global_mmr64_address(pnode, offset)); 589 } 590 591 static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset) 592 { 593 return readb(uv_global_mmr64_address(pnode, offset)); 594 } 595 596 /* 597 * Access hub local MMRs. Faster than using global space but only local MMRs 598 * are accessible. 599 */ 600 static inline unsigned long *uv_local_mmr_address(unsigned long offset) 601 { 602 return __va(UV_LOCAL_MMR_BASE | offset); 603 } 604 605 static inline unsigned long uv_read_local_mmr(unsigned long offset) 606 { 607 return readq(uv_local_mmr_address(offset)); 608 } 609 610 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) 611 { 612 writeq(val, uv_local_mmr_address(offset)); 613 } 614 615 static inline unsigned char uv_read_local_mmr8(unsigned long offset) 616 { 617 return readb(uv_local_mmr_address(offset)); 618 } 619 620 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) 621 { 622 writeb(val, uv_local_mmr_address(offset)); 623 } 624 625 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ 626 static inline int uv_blade_processor_id(void) 627 { 628 return uv_cpu_info->blade_cpu_id; 629 } 630 631 /* Blade-local cpu number of cpu N. Numbered 0 .. <# cpus on the blade> */ 632 static inline int uv_cpu_blade_processor_id(int cpu) 633 { 634 return uv_cpu_info_per(cpu)->blade_cpu_id; 635 } 636 637 /* Blade number to Node number (UV2..UV4 is 1:1) */ 638 static inline int uv_blade_to_node(int blade) 639 { 640 return blade; 641 } 642 643 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ 644 static inline int uv_numa_blade_id(void) 645 { 646 return uv_hub_info->numa_blade_id; 647 } 648 649 /* 650 * Convert linux node number to the UV blade number. 651 * .. Currently for UV2 thru UV4 the node and the blade are identical. 652 * .. If this changes then you MUST check references to this function! 653 */ 654 static inline int uv_node_to_blade_id(int nid) 655 { 656 return nid; 657 } 658 659 /* Convert a CPU number to the UV blade number */ 660 static inline int uv_cpu_to_blade_id(int cpu) 661 { 662 return uv_node_to_blade_id(cpu_to_node(cpu)); 663 } 664 665 /* Convert a blade id to the PNODE of the blade */ 666 static inline int uv_blade_to_pnode(int bid) 667 { 668 return uv_hub_info_list(uv_blade_to_node(bid))->pnode; 669 } 670 671 /* Nid of memory node on blade. -1 if no blade-local memory */ 672 static inline int uv_blade_to_memory_nid(int bid) 673 { 674 return uv_hub_info_list(uv_blade_to_node(bid))->memory_nid; 675 } 676 677 /* Determine the number of possible cpus on a blade */ 678 static inline int uv_blade_nr_possible_cpus(int bid) 679 { 680 return uv_hub_info_list(uv_blade_to_node(bid))->nr_possible_cpus; 681 } 682 683 /* Determine the number of online cpus on a blade */ 684 static inline int uv_blade_nr_online_cpus(int bid) 685 { 686 return uv_hub_info_list(uv_blade_to_node(bid))->nr_online_cpus; 687 } 688 689 /* Convert a cpu id to the PNODE of the blade containing the cpu */ 690 static inline int uv_cpu_to_pnode(int cpu) 691 { 692 return uv_cpu_hub_info(cpu)->pnode; 693 } 694 695 /* Convert a linux node number to the PNODE of the blade */ 696 static inline int uv_node_to_pnode(int nid) 697 { 698 return uv_hub_info_list(nid)->pnode; 699 } 700 701 /* Maximum possible number of blades */ 702 extern short uv_possible_blades; 703 static inline int uv_num_possible_blades(void) 704 { 705 return uv_possible_blades; 706 } 707 708 /* Per Hub NMI support */ 709 extern void uv_nmi_setup(void); 710 extern void uv_nmi_setup_hubless(void); 711 712 /* BIOS/Kernel flags exchange MMR */ 713 #define UVH_BIOS_KERNEL_MMR UVH_SCRATCH5 714 #define UVH_BIOS_KERNEL_MMR_ALIAS UVH_SCRATCH5_ALIAS 715 #define UVH_BIOS_KERNEL_MMR_ALIAS_2 UVH_SCRATCH5_ALIAS_2 716 717 /* TSC sync valid, set by BIOS */ 718 #define UVH_TSC_SYNC_MMR UVH_BIOS_KERNEL_MMR 719 #define UVH_TSC_SYNC_SHIFT 10 720 #define UVH_TSC_SYNC_SHIFT_UV2K 16 /* UV2/3k have different bits */ 721 #define UVH_TSC_SYNC_MASK 3 /* 0011 */ 722 #define UVH_TSC_SYNC_VALID 3 /* 0011 */ 723 #define UVH_TSC_SYNC_INVALID 2 /* 0010 */ 724 725 /* BMC sets a bit this MMR non-zero before sending an NMI */ 726 #define UVH_NMI_MMR UVH_BIOS_KERNEL_MMR 727 #define UVH_NMI_MMR_CLEAR UVH_BIOS_KERNEL_MMR_ALIAS 728 #define UVH_NMI_MMR_SHIFT 63 729 #define UVH_NMI_MMR_TYPE "SCRATCH5" 730 731 /* Newer SMM NMI handler, not present in all systems */ 732 #define UVH_NMI_MMRX UVH_EVENT_OCCURRED0 733 #define UVH_NMI_MMRX_CLEAR UVH_EVENT_OCCURRED0_ALIAS 734 #define UVH_NMI_MMRX_SHIFT UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 735 #define UVH_NMI_MMRX_TYPE "EXTIO_INT0" 736 737 /* Non-zero indicates newer SMM NMI handler present */ 738 #define UVH_NMI_MMRX_SUPPORTED UVH_EXTIO_INT0_BROADCAST 739 740 /* Indicates to BIOS that we want to use the newer SMM NMI handler */ 741 #define UVH_NMI_MMRX_REQ UVH_BIOS_KERNEL_MMR_ALIAS_2 742 #define UVH_NMI_MMRX_REQ_SHIFT 62 743 744 struct uv_hub_nmi_s { 745 raw_spinlock_t nmi_lock; 746 atomic_t in_nmi; /* flag this node in UV NMI IRQ */ 747 atomic_t cpu_owner; /* last locker of this struct */ 748 atomic_t read_mmr_count; /* count of MMR reads */ 749 atomic_t nmi_count; /* count of true UV NMIs */ 750 unsigned long nmi_value; /* last value read from NMI MMR */ 751 bool hub_present; /* false means UV hubless system */ 752 bool pch_owner; /* indicates this hub owns PCH */ 753 }; 754 755 struct uv_cpu_nmi_s { 756 struct uv_hub_nmi_s *hub; 757 int state; 758 int pinging; 759 int queries; 760 int pings; 761 }; 762 763 DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi); 764 765 #define uv_hub_nmi this_cpu_read(uv_cpu_nmi.hub) 766 #define uv_cpu_nmi_per(cpu) (per_cpu(uv_cpu_nmi, cpu)) 767 #define uv_hub_nmi_per(cpu) (uv_cpu_nmi_per(cpu).hub) 768 769 /* uv_cpu_nmi_states */ 770 #define UV_NMI_STATE_OUT 0 771 #define UV_NMI_STATE_IN 1 772 #define UV_NMI_STATE_DUMP 2 773 #define UV_NMI_STATE_DUMP_DONE 3 774 775 /* Update SCIR state */ 776 static inline void uv_set_scir_bits(unsigned char value) 777 { 778 if (uv_scir_info->state != value) { 779 uv_scir_info->state = value; 780 uv_write_local_mmr8(uv_scir_info->offset, value); 781 } 782 } 783 784 static inline unsigned long uv_scir_offset(int apicid) 785 { 786 return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f); 787 } 788 789 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) 790 { 791 if (uv_cpu_scir_info(cpu)->state != value) { 792 uv_write_global_mmr8(uv_cpu_to_pnode(cpu), 793 uv_cpu_scir_info(cpu)->offset, value); 794 uv_cpu_scir_info(cpu)->state = value; 795 } 796 } 797 798 /* 799 * Get the minimum revision number of the hub chips within the partition. 800 * (See UVx_HUB_REVISION_BASE above for specific values.) 801 */ 802 static inline int uv_get_min_hub_revision_id(void) 803 { 804 return uv_hub_info->hub_revision; 805 } 806 807 #endif /* CONFIG_X86_64 */ 808 #endif /* _ASM_X86_UV_UV_HUB_H */ 809