1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * PowerPC version 4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 5 * Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP 6 * Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com> 7 * Adapted for Power Macintosh by Paul Mackerras. 8 * Low-level exception handlers and MMU support 9 * rewritten by Paul Mackerras. 10 * Copyright (C) 1996 Paul Mackerras. 11 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). 12 * 13 * This file contains the system call entry code, context switch 14 * code, and exception/interrupt return code for PowerPC. 15 */ 16 17#include <linux/errno.h> 18#include <linux/err.h> 19#include <linux/sys.h> 20#include <linux/threads.h> 21#include <asm/reg.h> 22#include <asm/page.h> 23#include <asm/mmu.h> 24#include <asm/cputable.h> 25#include <asm/thread_info.h> 26#include <asm/ppc_asm.h> 27#include <asm/asm-offsets.h> 28#include <asm/unistd.h> 29#include <asm/ptrace.h> 30#include <asm/export.h> 31#include <asm/feature-fixups.h> 32#include <asm/barrier.h> 33#include <asm/kup.h> 34#include <asm/bug.h> 35 36#include "head_32.h" 37 38/* 39 * Align to 4k in order to ensure that all functions modyfing srr0/srr1 40 * fit into one page in order to not encounter a TLB miss between the 41 * modification of srr0/srr1 and the associated rfi. 42 */ 43 .align 12 44 45#ifdef CONFIG_BOOKE 46 .globl mcheck_transfer_to_handler 47mcheck_transfer_to_handler: 48 mfspr r0,SPRN_DSRR0 49 stw r0,_DSRR0(r11) 50 mfspr r0,SPRN_DSRR1 51 stw r0,_DSRR1(r11) 52 /* fall through */ 53_ASM_NOKPROBE_SYMBOL(mcheck_transfer_to_handler) 54 55 .globl debug_transfer_to_handler 56debug_transfer_to_handler: 57 mfspr r0,SPRN_CSRR0 58 stw r0,_CSRR0(r11) 59 mfspr r0,SPRN_CSRR1 60 stw r0,_CSRR1(r11) 61 /* fall through */ 62_ASM_NOKPROBE_SYMBOL(debug_transfer_to_handler) 63 64 .globl crit_transfer_to_handler 65crit_transfer_to_handler: 66#ifdef CONFIG_PPC_BOOK3E_MMU 67 mfspr r0,SPRN_MAS0 68 stw r0,MAS0(r11) 69 mfspr r0,SPRN_MAS1 70 stw r0,MAS1(r11) 71 mfspr r0,SPRN_MAS2 72 stw r0,MAS2(r11) 73 mfspr r0,SPRN_MAS3 74 stw r0,MAS3(r11) 75 mfspr r0,SPRN_MAS6 76 stw r0,MAS6(r11) 77#ifdef CONFIG_PHYS_64BIT 78 mfspr r0,SPRN_MAS7 79 stw r0,MAS7(r11) 80#endif /* CONFIG_PHYS_64BIT */ 81#endif /* CONFIG_PPC_BOOK3E_MMU */ 82#ifdef CONFIG_44x 83 mfspr r0,SPRN_MMUCR 84 stw r0,MMUCR(r11) 85#endif 86 mfspr r0,SPRN_SRR0 87 stw r0,_SRR0(r11) 88 mfspr r0,SPRN_SRR1 89 stw r0,_SRR1(r11) 90 91 /* set the stack limit to the current stack */ 92 mfspr r8,SPRN_SPRG_THREAD 93 lwz r0,KSP_LIMIT(r8) 94 stw r0,SAVED_KSP_LIMIT(r11) 95 rlwinm r0,r1,0,0,(31 - THREAD_SHIFT) 96 stw r0,KSP_LIMIT(r8) 97 /* fall through */ 98_ASM_NOKPROBE_SYMBOL(crit_transfer_to_handler) 99#endif 100 101#ifdef CONFIG_40x 102 .globl crit_transfer_to_handler 103crit_transfer_to_handler: 104 lwz r0,crit_r10@l(0) 105 stw r0,GPR10(r11) 106 lwz r0,crit_r11@l(0) 107 stw r0,GPR11(r11) 108 mfspr r0,SPRN_SRR0 109 stw r0,crit_srr0@l(0) 110 mfspr r0,SPRN_SRR1 111 stw r0,crit_srr1@l(0) 112 113 /* set the stack limit to the current stack */ 114 mfspr r8,SPRN_SPRG_THREAD 115 lwz r0,KSP_LIMIT(r8) 116 stw r0,saved_ksp_limit@l(0) 117 rlwinm r0,r1,0,0,(31 - THREAD_SHIFT) 118 stw r0,KSP_LIMIT(r8) 119 /* fall through */ 120_ASM_NOKPROBE_SYMBOL(crit_transfer_to_handler) 121#endif 122 123/* 124 * This code finishes saving the registers to the exception frame 125 * and jumps to the appropriate handler for the exception, turning 126 * on address translation. 127 * Note that we rely on the caller having set cr0.eq iff the exception 128 * occurred in kernel mode (i.e. MSR:PR = 0). 129 */ 130 .globl transfer_to_handler_full 131transfer_to_handler_full: 132 SAVE_NVGPRS(r11) 133_ASM_NOKPROBE_SYMBOL(transfer_to_handler_full) 134 /* fall through */ 135 136 .globl transfer_to_handler 137transfer_to_handler: 138 stw r2,GPR2(r11) 139 stw r12,_NIP(r11) 140 stw r9,_MSR(r11) 141 andi. r2,r9,MSR_PR 142 mfctr r12 143 mfspr r2,SPRN_XER 144 stw r12,_CTR(r11) 145 stw r2,_XER(r11) 146 mfspr r12,SPRN_SPRG_THREAD 147 tovirt_vmstack r12, r12 148 beq 2f /* if from user, fix up THREAD.regs */ 149 addi r2, r12, -THREAD 150 addi r11,r1,STACK_FRAME_OVERHEAD 151 stw r11,PT_REGS(r12) 152#if defined(CONFIG_40x) || defined(CONFIG_BOOKE) 153 /* Check to see if the dbcr0 register is set up to debug. Use the 154 internal debug mode bit to do this. */ 155 lwz r12,THREAD_DBCR0(r12) 156 andis. r12,r12,DBCR0_IDM@h 157#endif 158 ACCOUNT_CPU_USER_ENTRY(r2, r11, r12) 159#ifdef CONFIG_PPC_BOOK3S_32 160 kuep_lock r11, r12 161#endif 162#if defined(CONFIG_40x) || defined(CONFIG_BOOKE) 163 beq+ 3f 164 /* From user and task is ptraced - load up global dbcr0 */ 165 li r12,-1 /* clear all pending debug events */ 166 mtspr SPRN_DBSR,r12 167 lis r11,global_dbcr0@ha 168 tophys(r11,r11) 169 addi r11,r11,global_dbcr0@l 170#ifdef CONFIG_SMP 171 lwz r9,TASK_CPU(r2) 172 slwi r9,r9,3 173 add r11,r11,r9 174#endif 175 lwz r12,0(r11) 176 mtspr SPRN_DBCR0,r12 177 lwz r12,4(r11) 178 addi r12,r12,-1 179 stw r12,4(r11) 180#endif 181 182 b 3f 183 1842: /* if from kernel, check interrupted DOZE/NAP mode and 185 * check for stack overflow 186 */ 187 kuap_save_and_lock r11, r12, r9, r2, r6 188 addi r2, r12, -THREAD 189#ifndef CONFIG_VMAP_STACK 190 lwz r9,KSP_LIMIT(r12) 191 cmplw r1,r9 /* if r1 <= ksp_limit */ 192 ble- stack_ovf /* then the kernel stack overflowed */ 193#endif 1945: 195#if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500) 196 lwz r12,TI_LOCAL_FLAGS(r2) 197 mtcrf 0x01,r12 198 bt- 31-TLF_NAPPING,4f 199 bt- 31-TLF_SLEEPING,7f 200#endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_E500 */ 201 .globl transfer_to_handler_cont 202transfer_to_handler_cont: 2033: 204 mflr r9 205 tovirt_novmstack r2, r2 /* set r2 to current */ 206 tovirt_vmstack r9, r9 207 lwz r11,0(r9) /* virtual address of handler */ 208 lwz r9,4(r9) /* where to go when done */ 209#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS) 210 mtspr SPRN_NRI, r0 211#endif 212#ifdef CONFIG_TRACE_IRQFLAGS 213 /* 214 * When tracing IRQ state (lockdep) we enable the MMU before we call 215 * the IRQ tracing functions as they might access vmalloc space or 216 * perform IOs for console output. 217 * 218 * To speed up the syscall path where interrupts stay on, let's check 219 * first if we are changing the MSR value at all. 220 */ 221 tophys_novmstack r12, r1 222 lwz r12,_MSR(r12) 223 andi. r12,r12,MSR_EE 224 bne 1f 225 226 /* MSR isn't changing, just transition directly */ 227#endif 228 mtspr SPRN_SRR0,r11 229 mtspr SPRN_SRR1,r10 230 mtlr r9 231 SYNC 232 RFI /* jump to handler, enable MMU */ 233 234#if defined (CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500) 2354: rlwinm r12,r12,0,~_TLF_NAPPING 236 stw r12,TI_LOCAL_FLAGS(r2) 237 b power_save_ppc32_restore 238 2397: rlwinm r12,r12,0,~_TLF_SLEEPING 240 stw r12,TI_LOCAL_FLAGS(r2) 241 lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */ 242 rlwinm r9,r9,0,~MSR_EE 243 lwz r12,_LINK(r11) /* and return to address in LR */ 244 kuap_restore r11, r2, r3, r4, r5 245 lwz r2, GPR2(r11) 246 b fast_exception_return 247#endif 248_ASM_NOKPROBE_SYMBOL(transfer_to_handler) 249_ASM_NOKPROBE_SYMBOL(transfer_to_handler_cont) 250 251#ifdef CONFIG_TRACE_IRQFLAGS 2521: /* MSR is changing, re-enable MMU so we can notify lockdep. We need to 253 * keep interrupts disabled at this point otherwise we might risk 254 * taking an interrupt before we tell lockdep they are enabled. 255 */ 256 lis r12,reenable_mmu@h 257 ori r12,r12,reenable_mmu@l 258 LOAD_REG_IMMEDIATE(r0, MSR_KERNEL) 259 mtspr SPRN_SRR0,r12 260 mtspr SPRN_SRR1,r0 261 SYNC 262 RFI 263 264reenable_mmu: 265 /* 266 * We save a bunch of GPRs, 267 * r3 can be different from GPR3(r1) at this point, r9 and r11 268 * contains the old MSR and handler address respectively, 269 * r4 & r5 can contain page fault arguments that need to be passed 270 * along as well. r0, r6-r8, r12, CCR, CTR, XER etc... are left 271 * clobbered as they aren't useful past this point. 272 */ 273 274 stwu r1,-32(r1) 275 stw r9,8(r1) 276 stw r11,12(r1) 277 stw r3,16(r1) 278 stw r4,20(r1) 279 stw r5,24(r1) 280 281 /* If we are disabling interrupts (normal case), simply log it with 282 * lockdep 283 */ 2841: bl trace_hardirqs_off 285 lwz r5,24(r1) 286 lwz r4,20(r1) 287 lwz r3,16(r1) 288 lwz r11,12(r1) 289 lwz r9,8(r1) 290 addi r1,r1,32 291 mtctr r11 292 mtlr r9 293 bctr /* jump to handler */ 294#endif /* CONFIG_TRACE_IRQFLAGS */ 295 296#ifndef CONFIG_VMAP_STACK 297/* 298 * On kernel stack overflow, load up an initial stack pointer 299 * and call StackOverflow(regs), which should not return. 300 */ 301stack_ovf: 302 /* sometimes we use a statically-allocated stack, which is OK. */ 303 lis r12,_end@h 304 ori r12,r12,_end@l 305 cmplw r1,r12 306 ble 5b /* r1 <= &_end is OK */ 307 SAVE_NVGPRS(r11) 308 addi r3,r1,STACK_FRAME_OVERHEAD 309 lis r1,init_thread_union@ha 310 addi r1,r1,init_thread_union@l 311 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD 312 lis r9,StackOverflow@ha 313 addi r9,r9,StackOverflow@l 314 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL) 315#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS) 316 mtspr SPRN_NRI, r0 317#endif 318 mtspr SPRN_SRR0,r9 319 mtspr SPRN_SRR1,r10 320 SYNC 321 RFI 322_ASM_NOKPROBE_SYMBOL(stack_ovf) 323#endif 324 325#ifdef CONFIG_TRACE_IRQFLAGS 326trace_syscall_entry_irq_off: 327 /* 328 * Syscall shouldn't happen while interrupts are disabled, 329 * so let's do a warning here. 330 */ 3310: trap 332 EMIT_BUG_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING 333 bl trace_hardirqs_on 334 335 /* Now enable for real */ 336 LOAD_REG_IMMEDIATE(r10, MSR_KERNEL | MSR_EE) 337 mtmsr r10 338 339 REST_GPR(0, r1) 340 REST_4GPRS(3, r1) 341 REST_2GPRS(7, r1) 342 b DoSyscall 343#endif /* CONFIG_TRACE_IRQFLAGS */ 344 345 .globl transfer_to_syscall 346transfer_to_syscall: 347#ifdef CONFIG_TRACE_IRQFLAGS 348 andi. r12,r9,MSR_EE 349 beq- trace_syscall_entry_irq_off 350#endif /* CONFIG_TRACE_IRQFLAGS */ 351 352/* 353 * Handle a system call. 354 */ 355 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f 356 .stabs "entry_32.S",N_SO,0,0,0f 3570: 358 359_GLOBAL(DoSyscall) 360 stw r3,ORIG_GPR3(r1) 361 li r12,0 362 stw r12,RESULT(r1) 363#ifdef CONFIG_TRACE_IRQFLAGS 364 /* Make sure interrupts are enabled */ 365 mfmsr r11 366 andi. r12,r11,MSR_EE 367 /* We came in with interrupts disabled, we WARN and mark them enabled 368 * for lockdep now */ 3690: tweqi r12, 0 370 EMIT_BUG_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING 371#endif /* CONFIG_TRACE_IRQFLAGS */ 372 lwz r11,TI_FLAGS(r2) 373 andi. r11,r11,_TIF_SYSCALL_DOTRACE 374 bne- syscall_dotrace 375syscall_dotrace_cont: 376 cmplwi 0,r0,NR_syscalls 377 lis r10,sys_call_table@h 378 ori r10,r10,sys_call_table@l 379 slwi r0,r0,2 380 bge- 66f 381 382 barrier_nospec_asm 383 /* 384 * Prevent the load of the handler below (based on the user-passed 385 * system call number) being speculatively executed until the test 386 * against NR_syscalls and branch to .66f above has 387 * committed. 388 */ 389 390 lwzx r10,r10,r0 /* Fetch system call handler [ptr] */ 391 mtlr r10 392 addi r9,r1,STACK_FRAME_OVERHEAD 393 PPC440EP_ERR42 394 blrl /* Call handler */ 395 .globl ret_from_syscall 396ret_from_syscall: 397#ifdef CONFIG_DEBUG_RSEQ 398 /* Check whether the syscall is issued inside a restartable sequence */ 399 stw r3,GPR3(r1) 400 addi r3,r1,STACK_FRAME_OVERHEAD 401 bl rseq_syscall 402 lwz r3,GPR3(r1) 403#endif 404 mr r6,r3 405 /* disable interrupts so current_thread_info()->flags can't change */ 406 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL) /* doesn't include MSR_EE */ 407 /* Note: We don't bother telling lockdep about it */ 408 SYNC 409 mtmsr r10 410 lwz r9,TI_FLAGS(r2) 411 li r8,-MAX_ERRNO 412 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP|_TIF_USER_WORK_MASK|_TIF_PERSYSCALL_MASK) 413 bne- syscall_exit_work 414 cmplw 0,r3,r8 415 blt+ syscall_exit_cont 416 lwz r11,_CCR(r1) /* Load CR */ 417 neg r3,r3 418 oris r11,r11,0x1000 /* Set SO bit in CR */ 419 stw r11,_CCR(r1) 420syscall_exit_cont: 421 lwz r8,_MSR(r1) 422#ifdef CONFIG_TRACE_IRQFLAGS 423 /* If we are going to return from the syscall with interrupts 424 * off, we trace that here. It shouldn't normally happen. 425 */ 426 andi. r10,r8,MSR_EE 427 bne+ 1f 428 stw r3,GPR3(r1) 429 bl trace_hardirqs_off 430 lwz r3,GPR3(r1) 4311: 432#endif /* CONFIG_TRACE_IRQFLAGS */ 433#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 434 /* If the process has its own DBCR0 value, load it up. The internal 435 debug mode bit tells us that dbcr0 should be loaded. */ 436 lwz r0,THREAD+THREAD_DBCR0(r2) 437 andis. r10,r0,DBCR0_IDM@h 438 bnel- load_dbcr0 439#endif 440#ifdef CONFIG_44x 441BEGIN_MMU_FTR_SECTION 442 lis r4,icache_44x_need_flush@ha 443 lwz r5,icache_44x_need_flush@l(r4) 444 cmplwi cr0,r5,0 445 bne- 2f 4461: 447END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_47x) 448#endif /* CONFIG_44x */ 449BEGIN_FTR_SECTION 450 lwarx r7,0,r1 451END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) 452 stwcx. r0,0,r1 /* to clear the reservation */ 453 ACCOUNT_CPU_USER_EXIT(r2, r5, r7) 454#ifdef CONFIG_PPC_BOOK3S_32 455 kuep_unlock r5, r7 456#endif 457 kuap_check r2, r4 458 lwz r4,_LINK(r1) 459 lwz r5,_CCR(r1) 460 mtlr r4 461 mtcr r5 462 lwz r7,_NIP(r1) 463 lwz r2,GPR2(r1) 464 lwz r1,GPR1(r1) 465syscall_exit_finish: 466#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS) 467 mtspr SPRN_NRI, r0 468#endif 469 mtspr SPRN_SRR0,r7 470 mtspr SPRN_SRR1,r8 471 SYNC 472 RFI 473_ASM_NOKPROBE_SYMBOL(syscall_exit_finish) 474#ifdef CONFIG_44x 4752: li r7,0 476 iccci r0,r0 477 stw r7,icache_44x_need_flush@l(r4) 478 b 1b 479#endif /* CONFIG_44x */ 480 48166: li r3,-ENOSYS 482 b ret_from_syscall 483 484 .globl ret_from_fork 485ret_from_fork: 486 REST_NVGPRS(r1) 487 bl schedule_tail 488 li r3,0 489 b ret_from_syscall 490 491 .globl ret_from_kernel_thread 492ret_from_kernel_thread: 493 REST_NVGPRS(r1) 494 bl schedule_tail 495 mtlr r14 496 mr r3,r15 497 PPC440EP_ERR42 498 blrl 499 li r3,0 500 b ret_from_syscall 501 502/* Traced system call support */ 503syscall_dotrace: 504 SAVE_NVGPRS(r1) 505 li r0,0xc00 506 stw r0,_TRAP(r1) 507 addi r3,r1,STACK_FRAME_OVERHEAD 508 bl do_syscall_trace_enter 509 /* 510 * Restore argument registers possibly just changed. 511 * We use the return value of do_syscall_trace_enter 512 * for call number to look up in the table (r0). 513 */ 514 mr r0,r3 515 lwz r3,GPR3(r1) 516 lwz r4,GPR4(r1) 517 lwz r5,GPR5(r1) 518 lwz r6,GPR6(r1) 519 lwz r7,GPR7(r1) 520 lwz r8,GPR8(r1) 521 REST_NVGPRS(r1) 522 523 cmplwi r0,NR_syscalls 524 /* Return code is already in r3 thanks to do_syscall_trace_enter() */ 525 bge- ret_from_syscall 526 b syscall_dotrace_cont 527 528syscall_exit_work: 529 andi. r0,r9,_TIF_RESTOREALL 530 beq+ 0f 531 REST_NVGPRS(r1) 532 b 2f 5330: cmplw 0,r3,r8 534 blt+ 1f 535 andi. r0,r9,_TIF_NOERROR 536 bne- 1f 537 lwz r11,_CCR(r1) /* Load CR */ 538 neg r3,r3 539 oris r11,r11,0x1000 /* Set SO bit in CR */ 540 stw r11,_CCR(r1) 541 5421: stw r6,RESULT(r1) /* Save result */ 543 stw r3,GPR3(r1) /* Update return value */ 5442: andi. r0,r9,(_TIF_PERSYSCALL_MASK) 545 beq 4f 546 547 /* Clear per-syscall TIF flags if any are set. */ 548 549 li r11,_TIF_PERSYSCALL_MASK 550 addi r12,r2,TI_FLAGS 5513: lwarx r8,0,r12 552 andc r8,r8,r11 553 stwcx. r8,0,r12 554 bne- 3b 555 5564: /* Anything which requires enabling interrupts? */ 557 andi. r0,r9,(_TIF_SYSCALL_DOTRACE|_TIF_SINGLESTEP) 558 beq ret_from_except 559 560 /* Re-enable interrupts. There is no need to trace that with 561 * lockdep as we are supposed to have IRQs on at this point 562 */ 563 ori r10,r10,MSR_EE 564 SYNC 565 mtmsr r10 566 567 /* Save NVGPRS if they're not saved already */ 568 lwz r4,_TRAP(r1) 569 andi. r4,r4,1 570 beq 5f 571 SAVE_NVGPRS(r1) 572 li r4,0xc00 573 stw r4,_TRAP(r1) 5745: 575 addi r3,r1,STACK_FRAME_OVERHEAD 576 bl do_syscall_trace_leave 577 b ret_from_except_full 578 579 /* 580 * System call was called from kernel. We get here with SRR1 in r9. 581 * Mark the exception as recoverable once we have retrieved SRR0, 582 * trap a warning and return ENOSYS with CR[SO] set. 583 */ 584 .globl ret_from_kernel_syscall 585ret_from_kernel_syscall: 586 mfspr r9, SPRN_SRR0 587 mfspr r10, SPRN_SRR1 588#if !defined(CONFIG_4xx) && !defined(CONFIG_BOOKE) 589 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~(MSR_IR|MSR_DR)) 590 mtmsr r11 591#endif 592 5930: trap 594 EMIT_BUG_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING 595 596 li r3, ENOSYS 597 crset so 598#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS) 599 mtspr SPRN_NRI, r0 600#endif 601 mtspr SPRN_SRR0, r9 602 mtspr SPRN_SRR1, r10 603 SYNC 604 RFI 605_ASM_NOKPROBE_SYMBOL(ret_from_kernel_syscall) 606 607/* 608 * The fork/clone functions need to copy the full register set into 609 * the child process. Therefore we need to save all the nonvolatile 610 * registers (r13 - r31) before calling the C code. 611 */ 612 .globl ppc_fork 613ppc_fork: 614 SAVE_NVGPRS(r1) 615 lwz r0,_TRAP(r1) 616 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */ 617 stw r0,_TRAP(r1) /* register set saved */ 618 b sys_fork 619 620 .globl ppc_vfork 621ppc_vfork: 622 SAVE_NVGPRS(r1) 623 lwz r0,_TRAP(r1) 624 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */ 625 stw r0,_TRAP(r1) /* register set saved */ 626 b sys_vfork 627 628 .globl ppc_clone 629ppc_clone: 630 SAVE_NVGPRS(r1) 631 lwz r0,_TRAP(r1) 632 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */ 633 stw r0,_TRAP(r1) /* register set saved */ 634 b sys_clone 635 636 .globl ppc_clone3 637ppc_clone3: 638 SAVE_NVGPRS(r1) 639 lwz r0,_TRAP(r1) 640 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */ 641 stw r0,_TRAP(r1) /* register set saved */ 642 b sys_clone3 643 644 .globl ppc_swapcontext 645ppc_swapcontext: 646 SAVE_NVGPRS(r1) 647 lwz r0,_TRAP(r1) 648 rlwinm r0,r0,0,0,30 /* clear LSB to indicate full */ 649 stw r0,_TRAP(r1) /* register set saved */ 650 b sys_swapcontext 651 652/* 653 * Top-level page fault handling. 654 * This is in assembler because if do_page_fault tells us that 655 * it is a bad kernel page fault, we want to save the non-volatile 656 * registers before calling bad_page_fault. 657 */ 658 .globl handle_page_fault 659handle_page_fault: 660 addi r3,r1,STACK_FRAME_OVERHEAD 661#ifdef CONFIG_PPC_BOOK3S_32 662 andis. r0,r5,DSISR_DABRMATCH@h 663 bne- handle_dabr_fault 664#endif 665 bl do_page_fault 666 cmpwi r3,0 667 beq+ ret_from_except 668 SAVE_NVGPRS(r1) 669 lwz r0,_TRAP(r1) 670 clrrwi r0,r0,1 671 stw r0,_TRAP(r1) 672 mr r5,r3 673 addi r3,r1,STACK_FRAME_OVERHEAD 674 lwz r4,_DAR(r1) 675 bl bad_page_fault 676 b ret_from_except_full 677 678#ifdef CONFIG_PPC_BOOK3S_32 679 /* We have a data breakpoint exception - handle it */ 680handle_dabr_fault: 681 SAVE_NVGPRS(r1) 682 lwz r0,_TRAP(r1) 683 clrrwi r0,r0,1 684 stw r0,_TRAP(r1) 685 bl do_break 686 b ret_from_except_full 687#endif 688 689/* 690 * This routine switches between two different tasks. The process 691 * state of one is saved on its kernel stack. Then the state 692 * of the other is restored from its kernel stack. The memory 693 * management hardware is updated to the second process's state. 694 * Finally, we can return to the second process. 695 * On entry, r3 points to the THREAD for the current task, r4 696 * points to the THREAD for the new task. 697 * 698 * This routine is always called with interrupts disabled. 699 * 700 * Note: there are two ways to get to the "going out" portion 701 * of this code; either by coming in via the entry (_switch) 702 * or via "fork" which must set up an environment equivalent 703 * to the "_switch" path. If you change this , you'll have to 704 * change the fork code also. 705 * 706 * The code which creates the new task context is in 'copy_thread' 707 * in arch/ppc/kernel/process.c 708 */ 709_GLOBAL(_switch) 710 stwu r1,-INT_FRAME_SIZE(r1) 711 mflr r0 712 stw r0,INT_FRAME_SIZE+4(r1) 713 /* r3-r12 are caller saved -- Cort */ 714 SAVE_NVGPRS(r1) 715 stw r0,_NIP(r1) /* Return to switch caller */ 716 mfmsr r11 717 li r0,MSR_FP /* Disable floating-point */ 718#ifdef CONFIG_ALTIVEC 719BEGIN_FTR_SECTION 720 oris r0,r0,MSR_VEC@h /* Disable altivec */ 721 mfspr r12,SPRN_VRSAVE /* save vrsave register value */ 722 stw r12,THREAD+THREAD_VRSAVE(r2) 723END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 724#endif /* CONFIG_ALTIVEC */ 725#ifdef CONFIG_SPE 726BEGIN_FTR_SECTION 727 oris r0,r0,MSR_SPE@h /* Disable SPE */ 728 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */ 729 stw r12,THREAD+THREAD_SPEFSCR(r2) 730END_FTR_SECTION_IFSET(CPU_FTR_SPE) 731#endif /* CONFIG_SPE */ 732 and. r0,r0,r11 /* FP or altivec or SPE enabled? */ 733 beq+ 1f 734 andc r11,r11,r0 735 mtmsr r11 736 isync 7371: stw r11,_MSR(r1) 738 mfcr r10 739 stw r10,_CCR(r1) 740 stw r1,KSP(r3) /* Set old stack pointer */ 741 742 kuap_check r2, r0 743#ifdef CONFIG_SMP 744 /* We need a sync somewhere here to make sure that if the 745 * previous task gets rescheduled on another CPU, it sees all 746 * stores it has performed on this one. 747 */ 748 sync 749#endif /* CONFIG_SMP */ 750 751 tophys(r0,r4) 752 mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */ 753 lwz r1,KSP(r4) /* Load new stack pointer */ 754 755 /* save the old current 'last' for return value */ 756 mr r3,r2 757 addi r2,r4,-THREAD /* Update current */ 758 759#ifdef CONFIG_ALTIVEC 760BEGIN_FTR_SECTION 761 lwz r0,THREAD+THREAD_VRSAVE(r2) 762 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */ 763END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 764#endif /* CONFIG_ALTIVEC */ 765#ifdef CONFIG_SPE 766BEGIN_FTR_SECTION 767 lwz r0,THREAD+THREAD_SPEFSCR(r2) 768 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */ 769END_FTR_SECTION_IFSET(CPU_FTR_SPE) 770#endif /* CONFIG_SPE */ 771 772 lwz r0,_CCR(r1) 773 mtcrf 0xFF,r0 774 /* r3-r12 are destroyed -- Cort */ 775 REST_NVGPRS(r1) 776 777 lwz r4,_NIP(r1) /* Return to _switch caller in new task */ 778 mtlr r4 779 addi r1,r1,INT_FRAME_SIZE 780 blr 781 782 .globl fast_exception_return 783fast_exception_return: 784#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) 785 andi. r10,r9,MSR_RI /* check for recoverable interrupt */ 786 beq 1f /* if not, we've got problems */ 787#endif 788 7892: REST_4GPRS(3, r11) 790 lwz r10,_CCR(r11) 791 REST_GPR(1, r11) 792 mtcr r10 793 lwz r10,_LINK(r11) 794 mtlr r10 795 /* Clear the exception_marker on the stack to avoid confusing stacktrace */ 796 li r10, 0 797 stw r10, 8(r11) 798 REST_GPR(10, r11) 799#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS) 800 mtspr SPRN_NRI, r0 801#endif 802 mtspr SPRN_SRR1,r9 803 mtspr SPRN_SRR0,r12 804 REST_GPR(9, r11) 805 REST_GPR(12, r11) 806 lwz r11,GPR11(r11) 807 SYNC 808 RFI 809_ASM_NOKPROBE_SYMBOL(fast_exception_return) 810 811#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) 812/* check if the exception happened in a restartable section */ 8131: lis r3,exc_exit_restart_end@ha 814 addi r3,r3,exc_exit_restart_end@l 815 cmplw r12,r3 816#ifdef CONFIG_PPC_BOOK3S_601 817 bge 2b 818#else 819 bge 3f 820#endif 821 lis r4,exc_exit_restart@ha 822 addi r4,r4,exc_exit_restart@l 823 cmplw r12,r4 824#ifdef CONFIG_PPC_BOOK3S_601 825 blt 2b 826#else 827 blt 3f 828#endif 829 lis r3,fee_restarts@ha 830 tophys(r3,r3) 831 lwz r5,fee_restarts@l(r3) 832 addi r5,r5,1 833 stw r5,fee_restarts@l(r3) 834 mr r12,r4 /* restart at exc_exit_restart */ 835 b 2b 836 837 .section .bss 838 .align 2 839fee_restarts: 840 .space 4 841 .previous 842 843/* aargh, a nonrecoverable interrupt, panic */ 844/* aargh, we don't know which trap this is */ 845/* but the 601 doesn't implement the RI bit, so assume it's OK */ 8463: 847 li r10,-1 848 stw r10,_TRAP(r11) 849 addi r3,r1,STACK_FRAME_OVERHEAD 850 lis r10,MSR_KERNEL@h 851 ori r10,r10,MSR_KERNEL@l 852 bl transfer_to_handler_full 853 .long unrecoverable_exception 854 .long ret_from_except 855#endif 856 857 .globl ret_from_except_full 858ret_from_except_full: 859 REST_NVGPRS(r1) 860 /* fall through */ 861 862 .globl ret_from_except 863ret_from_except: 864 /* Hard-disable interrupts so that current_thread_info()->flags 865 * can't change between when we test it and when we return 866 * from the interrupt. */ 867 /* Note: We don't bother telling lockdep about it */ 868 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL) 869 SYNC /* Some chip revs have problems here... */ 870 mtmsr r10 /* disable interrupts */ 871 872 lwz r3,_MSR(r1) /* Returning to user mode? */ 873 andi. r0,r3,MSR_PR 874 beq resume_kernel 875 876user_exc_return: /* r10 contains MSR_KERNEL here */ 877 /* Check current_thread_info()->flags */ 878 lwz r9,TI_FLAGS(r2) 879 andi. r0,r9,_TIF_USER_WORK_MASK 880 bne do_work 881 882restore_user: 883#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 884 /* Check whether this process has its own DBCR0 value. The internal 885 debug mode bit tells us that dbcr0 should be loaded. */ 886 lwz r0,THREAD+THREAD_DBCR0(r2) 887 andis. r10,r0,DBCR0_IDM@h 888 bnel- load_dbcr0 889#endif 890 ACCOUNT_CPU_USER_EXIT(r2, r10, r11) 891#ifdef CONFIG_PPC_BOOK3S_32 892 kuep_unlock r10, r11 893#endif 894 895 b restore 896 897/* N.B. the only way to get here is from the beq following ret_from_except. */ 898resume_kernel: 899 /* check current_thread_info, _TIF_EMULATE_STACK_STORE */ 900 lwz r8,TI_FLAGS(r2) 901 andis. r0,r8,_TIF_EMULATE_STACK_STORE@h 902 beq+ 1f 903 904 addi r8,r1,INT_FRAME_SIZE /* Get the kprobed function entry */ 905 906 lwz r3,GPR1(r1) 907 subi r3,r3,INT_FRAME_SIZE /* dst: Allocate a trampoline exception frame */ 908 mr r4,r1 /* src: current exception frame */ 909 mr r1,r3 /* Reroute the trampoline frame to r1 */ 910 911 /* Copy from the original to the trampoline. */ 912 li r5,INT_FRAME_SIZE/4 /* size: INT_FRAME_SIZE */ 913 li r6,0 /* start offset: 0 */ 914 mtctr r5 9152: lwzx r0,r6,r4 916 stwx r0,r6,r3 917 addi r6,r6,4 918 bdnz 2b 919 920 /* Do real store operation to complete stwu */ 921 lwz r5,GPR1(r1) 922 stw r8,0(r5) 923 924 /* Clear _TIF_EMULATE_STACK_STORE flag */ 925 lis r11,_TIF_EMULATE_STACK_STORE@h 926 addi r5,r2,TI_FLAGS 9270: lwarx r8,0,r5 928 andc r8,r8,r11 929 stwcx. r8,0,r5 930 bne- 0b 9311: 932 933#ifdef CONFIG_PREEMPTION 934 /* check current_thread_info->preempt_count */ 935 lwz r0,TI_PREEMPT(r2) 936 cmpwi 0,r0,0 /* if non-zero, just restore regs and return */ 937 bne restore_kuap 938 andi. r8,r8,_TIF_NEED_RESCHED 939 beq+ restore_kuap 940 lwz r3,_MSR(r1) 941 andi. r0,r3,MSR_EE /* interrupts off? */ 942 beq restore_kuap /* don't schedule if so */ 943#ifdef CONFIG_TRACE_IRQFLAGS 944 /* Lockdep thinks irqs are enabled, we need to call 945 * preempt_schedule_irq with IRQs off, so we inform lockdep 946 * now that we -did- turn them off already 947 */ 948 bl trace_hardirqs_off 949#endif 950 bl preempt_schedule_irq 951#ifdef CONFIG_TRACE_IRQFLAGS 952 /* And now, to properly rebalance the above, we tell lockdep they 953 * are being turned back on, which will happen when we return 954 */ 955 bl trace_hardirqs_on 956#endif 957#endif /* CONFIG_PREEMPTION */ 958restore_kuap: 959 kuap_restore r1, r2, r9, r10, r0 960 961 /* interrupts are hard-disabled at this point */ 962restore: 963#ifdef CONFIG_44x 964BEGIN_MMU_FTR_SECTION 965 b 1f 966END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_47x) 967 lis r4,icache_44x_need_flush@ha 968 lwz r5,icache_44x_need_flush@l(r4) 969 cmplwi cr0,r5,0 970 beq+ 1f 971 li r6,0 972 iccci r0,r0 973 stw r6,icache_44x_need_flush@l(r4) 9741: 975#endif /* CONFIG_44x */ 976 977 lwz r9,_MSR(r1) 978#ifdef CONFIG_TRACE_IRQFLAGS 979 /* Lockdep doesn't know about the fact that IRQs are temporarily turned 980 * off in this assembly code while peeking at TI_FLAGS() and such. However 981 * we need to inform it if the exception turned interrupts off, and we 982 * are about to trun them back on. 983 */ 984 andi. r10,r9,MSR_EE 985 beq 1f 986 stwu r1,-32(r1) 987 mflr r0 988 stw r0,4(r1) 989 bl trace_hardirqs_on 990 addi r1, r1, 32 991 lwz r9,_MSR(r1) 9921: 993#endif /* CONFIG_TRACE_IRQFLAGS */ 994 995 lwz r0,GPR0(r1) 996 lwz r2,GPR2(r1) 997 REST_4GPRS(3, r1) 998 REST_2GPRS(7, r1) 999 1000 lwz r10,_XER(r1) 1001 lwz r11,_CTR(r1) 1002 mtspr SPRN_XER,r10 1003 mtctr r11 1004 1005BEGIN_FTR_SECTION 1006 lwarx r11,0,r1 1007END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) 1008 stwcx. r0,0,r1 /* to clear the reservation */ 1009 1010#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) 1011 andi. r10,r9,MSR_RI /* check if this exception occurred */ 1012 beql nonrecoverable /* at a bad place (MSR:RI = 0) */ 1013 1014 lwz r10,_CCR(r1) 1015 lwz r11,_LINK(r1) 1016 mtcrf 0xFF,r10 1017 mtlr r11 1018 1019 /* Clear the exception_marker on the stack to avoid confusing stacktrace */ 1020 li r10, 0 1021 stw r10, 8(r1) 1022 /* 1023 * Once we put values in SRR0 and SRR1, we are in a state 1024 * where exceptions are not recoverable, since taking an 1025 * exception will trash SRR0 and SRR1. Therefore we clear the 1026 * MSR:RI bit to indicate this. If we do take an exception, 1027 * we can't return to the point of the exception but we 1028 * can restart the exception exit path at the label 1029 * exc_exit_restart below. -- paulus 1030 */ 1031 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL & ~MSR_RI) 1032 SYNC 1033 mtmsr r10 /* clear the RI bit */ 1034 .globl exc_exit_restart 1035exc_exit_restart: 1036 lwz r12,_NIP(r1) 1037 mtspr SPRN_SRR0,r12 1038 mtspr SPRN_SRR1,r9 1039 REST_4GPRS(9, r1) 1040 lwz r1,GPR1(r1) 1041 .globl exc_exit_restart_end 1042exc_exit_restart_end: 1043 SYNC 1044 RFI 1045_ASM_NOKPROBE_SYMBOL(exc_exit_restart) 1046_ASM_NOKPROBE_SYMBOL(exc_exit_restart_end) 1047 1048#else /* !(CONFIG_4xx || CONFIG_BOOKE) */ 1049 /* 1050 * This is a bit different on 4xx/Book-E because it doesn't have 1051 * the RI bit in the MSR. 1052 * The TLB miss handler checks if we have interrupted 1053 * the exception exit path and restarts it if so 1054 * (well maybe one day it will... :). 1055 */ 1056 lwz r11,_LINK(r1) 1057 mtlr r11 1058 lwz r10,_CCR(r1) 1059 mtcrf 0xff,r10 1060 /* Clear the exception_marker on the stack to avoid confusing stacktrace */ 1061 li r10, 0 1062 stw r10, 8(r1) 1063 REST_2GPRS(9, r1) 1064 .globl exc_exit_restart 1065exc_exit_restart: 1066 lwz r11,_NIP(r1) 1067 lwz r12,_MSR(r1) 1068 mtspr SPRN_SRR0,r11 1069 mtspr SPRN_SRR1,r12 1070 REST_2GPRS(11, r1) 1071 lwz r1,GPR1(r1) 1072 .globl exc_exit_restart_end 1073exc_exit_restart_end: 1074 rfi 1075 b . /* prevent prefetch past rfi */ 1076_ASM_NOKPROBE_SYMBOL(exc_exit_restart) 1077 1078/* 1079 * Returning from a critical interrupt in user mode doesn't need 1080 * to be any different from a normal exception. For a critical 1081 * interrupt in the kernel, we just return (without checking for 1082 * preemption) since the interrupt may have happened at some crucial 1083 * place (e.g. inside the TLB miss handler), and because we will be 1084 * running with r1 pointing into critical_stack, not the current 1085 * process's kernel stack (and therefore current_thread_info() will 1086 * give the wrong answer). 1087 * We have to restore various SPRs that may have been in use at the 1088 * time of the critical interrupt. 1089 * 1090 */ 1091#ifdef CONFIG_40x 1092#define PPC_40x_TURN_OFF_MSR_DR \ 1093 /* avoid any possible TLB misses here by turning off MSR.DR, we \ 1094 * assume the instructions here are mapped by a pinned TLB entry */ \ 1095 li r10,MSR_IR; \ 1096 mtmsr r10; \ 1097 isync; \ 1098 tophys(r1, r1); 1099#else 1100#define PPC_40x_TURN_OFF_MSR_DR 1101#endif 1102 1103#define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \ 1104 REST_NVGPRS(r1); \ 1105 lwz r3,_MSR(r1); \ 1106 andi. r3,r3,MSR_PR; \ 1107 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL); \ 1108 bne user_exc_return; \ 1109 lwz r0,GPR0(r1); \ 1110 lwz r2,GPR2(r1); \ 1111 REST_4GPRS(3, r1); \ 1112 REST_2GPRS(7, r1); \ 1113 lwz r10,_XER(r1); \ 1114 lwz r11,_CTR(r1); \ 1115 mtspr SPRN_XER,r10; \ 1116 mtctr r11; \ 1117 stwcx. r0,0,r1; /* to clear the reservation */ \ 1118 lwz r11,_LINK(r1); \ 1119 mtlr r11; \ 1120 lwz r10,_CCR(r1); \ 1121 mtcrf 0xff,r10; \ 1122 PPC_40x_TURN_OFF_MSR_DR; \ 1123 lwz r9,_DEAR(r1); \ 1124 lwz r10,_ESR(r1); \ 1125 mtspr SPRN_DEAR,r9; \ 1126 mtspr SPRN_ESR,r10; \ 1127 lwz r11,_NIP(r1); \ 1128 lwz r12,_MSR(r1); \ 1129 mtspr exc_lvl_srr0,r11; \ 1130 mtspr exc_lvl_srr1,r12; \ 1131 lwz r9,GPR9(r1); \ 1132 lwz r12,GPR12(r1); \ 1133 lwz r10,GPR10(r1); \ 1134 lwz r11,GPR11(r1); \ 1135 lwz r1,GPR1(r1); \ 1136 exc_lvl_rfi; \ 1137 b .; /* prevent prefetch past exc_lvl_rfi */ 1138 1139#define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \ 1140 lwz r9,_##exc_lvl_srr0(r1); \ 1141 lwz r10,_##exc_lvl_srr1(r1); \ 1142 mtspr SPRN_##exc_lvl_srr0,r9; \ 1143 mtspr SPRN_##exc_lvl_srr1,r10; 1144 1145#if defined(CONFIG_PPC_BOOK3E_MMU) 1146#ifdef CONFIG_PHYS_64BIT 1147#define RESTORE_MAS7 \ 1148 lwz r11,MAS7(r1); \ 1149 mtspr SPRN_MAS7,r11; 1150#else 1151#define RESTORE_MAS7 1152#endif /* CONFIG_PHYS_64BIT */ 1153#define RESTORE_MMU_REGS \ 1154 lwz r9,MAS0(r1); \ 1155 lwz r10,MAS1(r1); \ 1156 lwz r11,MAS2(r1); \ 1157 mtspr SPRN_MAS0,r9; \ 1158 lwz r9,MAS3(r1); \ 1159 mtspr SPRN_MAS1,r10; \ 1160 lwz r10,MAS6(r1); \ 1161 mtspr SPRN_MAS2,r11; \ 1162 mtspr SPRN_MAS3,r9; \ 1163 mtspr SPRN_MAS6,r10; \ 1164 RESTORE_MAS7; 1165#elif defined(CONFIG_44x) 1166#define RESTORE_MMU_REGS \ 1167 lwz r9,MMUCR(r1); \ 1168 mtspr SPRN_MMUCR,r9; 1169#else 1170#define RESTORE_MMU_REGS 1171#endif 1172 1173#ifdef CONFIG_40x 1174 .globl ret_from_crit_exc 1175ret_from_crit_exc: 1176 mfspr r9,SPRN_SPRG_THREAD 1177 lis r10,saved_ksp_limit@ha; 1178 lwz r10,saved_ksp_limit@l(r10); 1179 tovirt(r9,r9); 1180 stw r10,KSP_LIMIT(r9) 1181 lis r9,crit_srr0@ha; 1182 lwz r9,crit_srr0@l(r9); 1183 lis r10,crit_srr1@ha; 1184 lwz r10,crit_srr1@l(r10); 1185 mtspr SPRN_SRR0,r9; 1186 mtspr SPRN_SRR1,r10; 1187 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI) 1188_ASM_NOKPROBE_SYMBOL(ret_from_crit_exc) 1189#endif /* CONFIG_40x */ 1190 1191#ifdef CONFIG_BOOKE 1192 .globl ret_from_crit_exc 1193ret_from_crit_exc: 1194 mfspr r9,SPRN_SPRG_THREAD 1195 lwz r10,SAVED_KSP_LIMIT(r1) 1196 stw r10,KSP_LIMIT(r9) 1197 RESTORE_xSRR(SRR0,SRR1); 1198 RESTORE_MMU_REGS; 1199 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI) 1200_ASM_NOKPROBE_SYMBOL(ret_from_crit_exc) 1201 1202 .globl ret_from_debug_exc 1203ret_from_debug_exc: 1204 mfspr r9,SPRN_SPRG_THREAD 1205 lwz r10,SAVED_KSP_LIMIT(r1) 1206 stw r10,KSP_LIMIT(r9) 1207 RESTORE_xSRR(SRR0,SRR1); 1208 RESTORE_xSRR(CSRR0,CSRR1); 1209 RESTORE_MMU_REGS; 1210 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI) 1211_ASM_NOKPROBE_SYMBOL(ret_from_debug_exc) 1212 1213 .globl ret_from_mcheck_exc 1214ret_from_mcheck_exc: 1215 mfspr r9,SPRN_SPRG_THREAD 1216 lwz r10,SAVED_KSP_LIMIT(r1) 1217 stw r10,KSP_LIMIT(r9) 1218 RESTORE_xSRR(SRR0,SRR1); 1219 RESTORE_xSRR(CSRR0,CSRR1); 1220 RESTORE_xSRR(DSRR0,DSRR1); 1221 RESTORE_MMU_REGS; 1222 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI) 1223_ASM_NOKPROBE_SYMBOL(ret_from_mcheck_exc) 1224#endif /* CONFIG_BOOKE */ 1225 1226/* 1227 * Load the DBCR0 value for a task that is being ptraced, 1228 * having first saved away the global DBCR0. Note that r0 1229 * has the dbcr0 value to set upon entry to this. 1230 */ 1231load_dbcr0: 1232 mfmsr r10 /* first disable debug exceptions */ 1233 rlwinm r10,r10,0,~MSR_DE 1234 mtmsr r10 1235 isync 1236 mfspr r10,SPRN_DBCR0 1237 lis r11,global_dbcr0@ha 1238 addi r11,r11,global_dbcr0@l 1239#ifdef CONFIG_SMP 1240 lwz r9,TASK_CPU(r2) 1241 slwi r9,r9,3 1242 add r11,r11,r9 1243#endif 1244 stw r10,0(r11) 1245 mtspr SPRN_DBCR0,r0 1246 lwz r10,4(r11) 1247 addi r10,r10,1 1248 stw r10,4(r11) 1249 li r11,-1 1250 mtspr SPRN_DBSR,r11 /* clear all pending debug events */ 1251 blr 1252 1253 .section .bss 1254 .align 4 1255 .global global_dbcr0 1256global_dbcr0: 1257 .space 8*NR_CPUS 1258 .previous 1259#endif /* !(CONFIG_4xx || CONFIG_BOOKE) */ 1260 1261do_work: /* r10 contains MSR_KERNEL here */ 1262 andi. r0,r9,_TIF_NEED_RESCHED 1263 beq do_user_signal 1264 1265do_resched: /* r10 contains MSR_KERNEL here */ 1266#ifdef CONFIG_TRACE_IRQFLAGS 1267 bl trace_hardirqs_on 1268 mfmsr r10 1269#endif 1270 ori r10,r10,MSR_EE 1271 SYNC 1272 mtmsr r10 /* hard-enable interrupts */ 1273 bl schedule 1274recheck: 1275 /* Note: And we don't tell it we are disabling them again 1276 * neither. Those disable/enable cycles used to peek at 1277 * TI_FLAGS aren't advertised. 1278 */ 1279 LOAD_REG_IMMEDIATE(r10,MSR_KERNEL) 1280 SYNC 1281 mtmsr r10 /* disable interrupts */ 1282 lwz r9,TI_FLAGS(r2) 1283 andi. r0,r9,_TIF_NEED_RESCHED 1284 bne- do_resched 1285 andi. r0,r9,_TIF_USER_WORK_MASK 1286 beq restore_user 1287do_user_signal: /* r10 contains MSR_KERNEL here */ 1288 ori r10,r10,MSR_EE 1289 SYNC 1290 mtmsr r10 /* hard-enable interrupts */ 1291 /* save r13-r31 in the exception frame, if not already done */ 1292 lwz r3,_TRAP(r1) 1293 andi. r0,r3,1 1294 beq 2f 1295 SAVE_NVGPRS(r1) 1296 rlwinm r3,r3,0,0,30 1297 stw r3,_TRAP(r1) 12982: addi r3,r1,STACK_FRAME_OVERHEAD 1299 mr r4,r9 1300 bl do_notify_resume 1301 REST_NVGPRS(r1) 1302 b recheck 1303 1304/* 1305 * We come here when we are at the end of handling an exception 1306 * that occurred at a place where taking an exception will lose 1307 * state information, such as the contents of SRR0 and SRR1. 1308 */ 1309nonrecoverable: 1310 lis r10,exc_exit_restart_end@ha 1311 addi r10,r10,exc_exit_restart_end@l 1312 cmplw r12,r10 1313#ifdef CONFIG_PPC_BOOK3S_601 1314 bgelr 1315#else 1316 bge 3f 1317#endif 1318 lis r11,exc_exit_restart@ha 1319 addi r11,r11,exc_exit_restart@l 1320 cmplw r12,r11 1321#ifdef CONFIG_PPC_BOOK3S_601 1322 bltlr 1323#else 1324 blt 3f 1325#endif 1326 lis r10,ee_restarts@ha 1327 lwz r12,ee_restarts@l(r10) 1328 addi r12,r12,1 1329 stw r12,ee_restarts@l(r10) 1330 mr r12,r11 /* restart at exc_exit_restart */ 1331 blr 13323: /* OK, we can't recover, kill this process */ 1333 /* but the 601 doesn't implement the RI bit, so assume it's OK */ 1334 lwz r3,_TRAP(r1) 1335 andi. r0,r3,1 1336 beq 5f 1337 SAVE_NVGPRS(r1) 1338 rlwinm r3,r3,0,0,30 1339 stw r3,_TRAP(r1) 13405: mfspr r2,SPRN_SPRG_THREAD 1341 addi r2,r2,-THREAD 1342 tovirt(r2,r2) /* set back r2 to current */ 13434: addi r3,r1,STACK_FRAME_OVERHEAD 1344 bl unrecoverable_exception 1345 /* shouldn't return */ 1346 b 4b 1347_ASM_NOKPROBE_SYMBOL(nonrecoverable) 1348 1349 .section .bss 1350 .align 2 1351ee_restarts: 1352 .space 4 1353 .previous 1354 1355/* 1356 * PROM code for specific machines follows. Put it 1357 * here so it's easy to add arch-specific sections later. 1358 * -- Cort 1359 */ 1360#ifdef CONFIG_PPC_RTAS 1361/* 1362 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be 1363 * called with the MMU off. 1364 */ 1365_GLOBAL(enter_rtas) 1366 stwu r1,-INT_FRAME_SIZE(r1) 1367 mflr r0 1368 stw r0,INT_FRAME_SIZE+4(r1) 1369 LOAD_REG_ADDR(r4, rtas) 1370 lis r6,1f@ha /* physical return address for rtas */ 1371 addi r6,r6,1f@l 1372 tophys(r6,r6) 1373 tophys_novmstack r7, r1 1374 lwz r8,RTASENTRY(r4) 1375 lwz r4,RTASBASE(r4) 1376 mfmsr r9 1377 stw r9,8(r1) 1378 LOAD_REG_IMMEDIATE(r0,MSR_KERNEL) 1379 SYNC /* disable interrupts so SRR0/1 */ 1380 mtmsr r0 /* don't get trashed */ 1381 li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR) 1382 mtlr r6 1383 stw r7, THREAD + RTAS_SP(r2) 1384 mtspr SPRN_SRR0,r8 1385 mtspr SPRN_SRR1,r9 1386 RFI 13871: tophys_novmstack r9, r1 1388#ifdef CONFIG_VMAP_STACK 1389 li r0, MSR_KERNEL & ~MSR_IR /* can take DTLB miss */ 1390 mtmsr r0 1391 isync 1392#endif 1393 lwz r8,INT_FRAME_SIZE+4(r9) /* get return address */ 1394 lwz r9,8(r9) /* original msr value */ 1395 addi r1,r1,INT_FRAME_SIZE 1396 li r0,0 1397 tophys_novmstack r7, r2 1398 stw r0, THREAD + RTAS_SP(r7) 1399 mtspr SPRN_SRR0,r8 1400 mtspr SPRN_SRR1,r9 1401 RFI /* return to caller */ 1402_ASM_NOKPROBE_SYMBOL(enter_rtas) 1403#endif /* CONFIG_PPC_RTAS */ 1404