1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MPC52xx PSC in SPI mode driver. 4 * 5 * Maintainer: Dragos Carp 6 * 7 * Copyright (C) 2006 TOPTICA Photonics AG. 8 */ 9 10 #include <linux/module.h> 11 #include <linux/types.h> 12 #include <linux/errno.h> 13 #include <linux/interrupt.h> 14 #include <linux/of_address.h> 15 #include <linux/of_platform.h> 16 #include <linux/workqueue.h> 17 #include <linux/completion.h> 18 #include <linux/io.h> 19 #include <linux/delay.h> 20 #include <linux/spi/spi.h> 21 #include <linux/fsl_devices.h> 22 #include <linux/slab.h> 23 24 #include <asm/mpc52xx.h> 25 #include <asm/mpc52xx_psc.h> 26 27 #define MCLK 20000000 /* PSC port MClk in hz */ 28 29 struct mpc52xx_psc_spi { 30 /* fsl_spi_platform data */ 31 void (*cs_control)(struct spi_device *spi, bool on); 32 u32 sysclk; 33 34 /* driver internal data */ 35 struct mpc52xx_psc __iomem *psc; 36 struct mpc52xx_psc_fifo __iomem *fifo; 37 unsigned int irq; 38 u8 bits_per_word; 39 u8 busy; 40 41 struct work_struct work; 42 43 struct list_head queue; 44 spinlock_t lock; 45 46 struct completion done; 47 }; 48 49 /* controller state */ 50 struct mpc52xx_psc_spi_cs { 51 int bits_per_word; 52 int speed_hz; 53 }; 54 55 /* set clock freq, clock ramp, bits per work 56 * if t is NULL then reset the values to the default values 57 */ 58 static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi, 59 struct spi_transfer *t) 60 { 61 struct mpc52xx_psc_spi_cs *cs = spi->controller_state; 62 63 cs->speed_hz = (t && t->speed_hz) 64 ? t->speed_hz : spi->max_speed_hz; 65 cs->bits_per_word = (t && t->bits_per_word) 66 ? t->bits_per_word : spi->bits_per_word; 67 cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8; 68 return 0; 69 } 70 71 static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi) 72 { 73 struct mpc52xx_psc_spi_cs *cs = spi->controller_state; 74 struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); 75 struct mpc52xx_psc __iomem *psc = mps->psc; 76 u32 sicr; 77 u16 ccr; 78 79 sicr = in_be32(&psc->sicr); 80 81 /* Set clock phase and polarity */ 82 if (spi->mode & SPI_CPHA) 83 sicr |= 0x00001000; 84 else 85 sicr &= ~0x00001000; 86 if (spi->mode & SPI_CPOL) 87 sicr |= 0x00002000; 88 else 89 sicr &= ~0x00002000; 90 91 if (spi->mode & SPI_LSB_FIRST) 92 sicr |= 0x10000000; 93 else 94 sicr &= ~0x10000000; 95 out_be32(&psc->sicr, sicr); 96 97 /* Set clock frequency and bits per word 98 * Because psc->ccr is defined as 16bit register instead of 32bit 99 * just set the lower byte of BitClkDiv 100 */ 101 ccr = in_be16((u16 __iomem *)&psc->ccr); 102 ccr &= 0xFF00; 103 if (cs->speed_hz) 104 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF; 105 else /* by default SPI Clk 1MHz */ 106 ccr |= (MCLK / 1000000 - 1) & 0xFF; 107 out_be16((u16 __iomem *)&psc->ccr, ccr); 108 mps->bits_per_word = cs->bits_per_word; 109 110 if (mps->cs_control) 111 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0); 112 } 113 114 static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi) 115 { 116 struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); 117 118 if (mps->cs_control) 119 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1); 120 } 121 122 #define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1) 123 /* wake up when 80% fifo full */ 124 #define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100) 125 126 static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi, 127 struct spi_transfer *t) 128 { 129 struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); 130 struct mpc52xx_psc __iomem *psc = mps->psc; 131 struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo; 132 unsigned rb = 0; /* number of bytes receieved */ 133 unsigned sb = 0; /* number of bytes sent */ 134 unsigned char *rx_buf = (unsigned char *)t->rx_buf; 135 unsigned char *tx_buf = (unsigned char *)t->tx_buf; 136 unsigned rfalarm; 137 unsigned send_at_once = MPC52xx_PSC_BUFSIZE; 138 unsigned recv_at_once; 139 int last_block = 0; 140 141 if (!t->tx_buf && !t->rx_buf && t->len) 142 return -EINVAL; 143 144 /* enable transmiter/receiver */ 145 out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE); 146 while (rb < t->len) { 147 if (t->len - rb > MPC52xx_PSC_BUFSIZE) { 148 rfalarm = MPC52xx_PSC_RFALARM; 149 last_block = 0; 150 } else { 151 send_at_once = t->len - sb; 152 rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb); 153 last_block = 1; 154 } 155 156 dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once); 157 for (; send_at_once; sb++, send_at_once--) { 158 /* set EOF flag before the last word is sent */ 159 if (send_at_once == 1 && last_block) 160 out_8(&psc->ircr2, 0x01); 161 162 if (tx_buf) 163 out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]); 164 else 165 out_8(&psc->mpc52xx_psc_buffer_8, 0); 166 } 167 168 169 /* enable interrupts and wait for wake up 170 * if just one byte is expected the Rx FIFO genererates no 171 * FFULL interrupt, so activate the RxRDY interrupt 172 */ 173 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); 174 if (t->len - rb == 1) { 175 out_8(&psc->mode, 0); 176 } else { 177 out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL); 178 out_be16(&fifo->rfalarm, rfalarm); 179 } 180 out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY); 181 wait_for_completion(&mps->done); 182 recv_at_once = in_be16(&fifo->rfnum); 183 dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once); 184 185 send_at_once = recv_at_once; 186 if (rx_buf) { 187 for (; recv_at_once; rb++, recv_at_once--) 188 rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8); 189 } else { 190 for (; recv_at_once; rb++, recv_at_once--) 191 in_8(&psc->mpc52xx_psc_buffer_8); 192 } 193 } 194 /* disable transmiter/receiver */ 195 out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); 196 197 return 0; 198 } 199 200 static void mpc52xx_psc_spi_work(struct work_struct *work) 201 { 202 struct mpc52xx_psc_spi *mps = 203 container_of(work, struct mpc52xx_psc_spi, work); 204 205 spin_lock_irq(&mps->lock); 206 mps->busy = 1; 207 while (!list_empty(&mps->queue)) { 208 struct spi_message *m; 209 struct spi_device *spi; 210 struct spi_transfer *t = NULL; 211 unsigned cs_change; 212 int status; 213 214 m = container_of(mps->queue.next, struct spi_message, queue); 215 list_del_init(&m->queue); 216 spin_unlock_irq(&mps->lock); 217 218 spi = m->spi; 219 cs_change = 1; 220 status = 0; 221 list_for_each_entry (t, &m->transfers, transfer_list) { 222 if (t->bits_per_word || t->speed_hz) { 223 status = mpc52xx_psc_spi_transfer_setup(spi, t); 224 if (status < 0) 225 break; 226 } 227 228 if (cs_change) 229 mpc52xx_psc_spi_activate_cs(spi); 230 cs_change = t->cs_change; 231 232 status = mpc52xx_psc_spi_transfer_rxtx(spi, t); 233 if (status) 234 break; 235 m->actual_length += t->len; 236 237 spi_transfer_delay_exec(t); 238 239 if (cs_change) 240 mpc52xx_psc_spi_deactivate_cs(spi); 241 } 242 243 m->status = status; 244 if (m->complete) 245 m->complete(m->context); 246 247 if (status || !cs_change) 248 mpc52xx_psc_spi_deactivate_cs(spi); 249 250 mpc52xx_psc_spi_transfer_setup(spi, NULL); 251 252 spin_lock_irq(&mps->lock); 253 } 254 mps->busy = 0; 255 spin_unlock_irq(&mps->lock); 256 } 257 258 static int mpc52xx_psc_spi_setup(struct spi_device *spi) 259 { 260 struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); 261 struct mpc52xx_psc_spi_cs *cs = spi->controller_state; 262 unsigned long flags; 263 264 if (spi->bits_per_word%8) 265 return -EINVAL; 266 267 if (!cs) { 268 cs = kzalloc(sizeof *cs, GFP_KERNEL); 269 if (!cs) 270 return -ENOMEM; 271 spi->controller_state = cs; 272 } 273 274 cs->bits_per_word = spi->bits_per_word; 275 cs->speed_hz = spi->max_speed_hz; 276 277 spin_lock_irqsave(&mps->lock, flags); 278 if (!mps->busy) 279 mpc52xx_psc_spi_deactivate_cs(spi); 280 spin_unlock_irqrestore(&mps->lock, flags); 281 282 return 0; 283 } 284 285 static int mpc52xx_psc_spi_transfer(struct spi_device *spi, 286 struct spi_message *m) 287 { 288 struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master); 289 unsigned long flags; 290 291 m->actual_length = 0; 292 m->status = -EINPROGRESS; 293 294 spin_lock_irqsave(&mps->lock, flags); 295 list_add_tail(&m->queue, &mps->queue); 296 schedule_work(&mps->work); 297 spin_unlock_irqrestore(&mps->lock, flags); 298 299 return 0; 300 } 301 302 static void mpc52xx_psc_spi_cleanup(struct spi_device *spi) 303 { 304 kfree(spi->controller_state); 305 } 306 307 static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps) 308 { 309 struct mpc52xx_psc __iomem *psc = mps->psc; 310 struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo; 311 u32 mclken_div; 312 int ret; 313 314 /* default sysclk is 512MHz */ 315 mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK; 316 ret = mpc52xx_set_psc_clkdiv(psc_id, mclken_div); 317 if (ret) 318 return ret; 319 320 /* Reset the PSC into a known state */ 321 out_8(&psc->command, MPC52xx_PSC_RST_RX); 322 out_8(&psc->command, MPC52xx_PSC_RST_TX); 323 out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE); 324 325 /* Disable interrupts, interrupts are based on alarm level */ 326 out_be16(&psc->mpc52xx_psc_imr, 0); 327 out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); 328 out_8(&fifo->rfcntl, 0); 329 out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL); 330 331 /* Configure 8bit codec mode as a SPI master and use EOF flags */ 332 /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */ 333 out_be32(&psc->sicr, 0x0180C800); 334 out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */ 335 336 /* Set 2ms DTL delay */ 337 out_8(&psc->ctur, 0x00); 338 out_8(&psc->ctlr, 0x84); 339 340 mps->bits_per_word = 8; 341 342 return 0; 343 } 344 345 static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id) 346 { 347 struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id; 348 struct mpc52xx_psc __iomem *psc = mps->psc; 349 350 /* disable interrupt and wake up the work queue */ 351 if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) { 352 out_be16(&psc->mpc52xx_psc_imr, 0); 353 complete(&mps->done); 354 return IRQ_HANDLED; 355 } 356 return IRQ_NONE; 357 } 358 359 /* bus_num is used only for the case dev->platform_data == NULL */ 360 static int mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr, 361 u32 size, unsigned int irq, s16 bus_num) 362 { 363 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev); 364 struct mpc52xx_psc_spi *mps; 365 struct spi_master *master; 366 int ret; 367 368 master = spi_alloc_master(dev, sizeof *mps); 369 if (master == NULL) 370 return -ENOMEM; 371 372 dev_set_drvdata(dev, master); 373 mps = spi_master_get_devdata(master); 374 375 /* the spi->mode bits understood by this driver: */ 376 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; 377 378 mps->irq = irq; 379 if (pdata == NULL) { 380 dev_warn(dev, 381 "probe called without platform data, no cs_control function will be called\n"); 382 mps->cs_control = NULL; 383 mps->sysclk = 0; 384 master->bus_num = bus_num; 385 master->num_chipselect = 255; 386 } else { 387 mps->cs_control = pdata->cs_control; 388 mps->sysclk = pdata->sysclk; 389 master->bus_num = pdata->bus_num; 390 master->num_chipselect = pdata->max_chipselect; 391 } 392 master->setup = mpc52xx_psc_spi_setup; 393 master->transfer = mpc52xx_psc_spi_transfer; 394 master->cleanup = mpc52xx_psc_spi_cleanup; 395 master->dev.of_node = dev->of_node; 396 397 mps->psc = ioremap(regaddr, size); 398 if (!mps->psc) { 399 dev_err(dev, "could not ioremap I/O port range\n"); 400 ret = -EFAULT; 401 goto free_master; 402 } 403 /* On the 5200, fifo regs are immediately ajacent to the psc regs */ 404 mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc); 405 406 ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi", 407 mps); 408 if (ret) 409 goto free_master; 410 411 ret = mpc52xx_psc_spi_port_config(master->bus_num, mps); 412 if (ret < 0) { 413 dev_err(dev, "can't configure PSC! Is it capable of SPI?\n"); 414 goto free_irq; 415 } 416 417 spin_lock_init(&mps->lock); 418 init_completion(&mps->done); 419 INIT_WORK(&mps->work, mpc52xx_psc_spi_work); 420 INIT_LIST_HEAD(&mps->queue); 421 422 ret = spi_register_master(master); 423 if (ret < 0) 424 goto free_irq; 425 426 return ret; 427 428 free_irq: 429 free_irq(mps->irq, mps); 430 free_master: 431 if (mps->psc) 432 iounmap(mps->psc); 433 spi_master_put(master); 434 435 return ret; 436 } 437 438 static int mpc52xx_psc_spi_of_probe(struct platform_device *op) 439 { 440 const u32 *regaddr_p; 441 u64 regaddr64, size64; 442 s16 id = -1; 443 444 regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL); 445 if (!regaddr_p) { 446 dev_err(&op->dev, "Invalid PSC address\n"); 447 return -EINVAL; 448 } 449 regaddr64 = of_translate_address(op->dev.of_node, regaddr_p); 450 451 /* get PSC id (1..6, used by port_config) */ 452 if (op->dev.platform_data == NULL) { 453 const u32 *psc_nump; 454 455 psc_nump = of_get_property(op->dev.of_node, "cell-index", NULL); 456 if (!psc_nump || *psc_nump > 5) { 457 dev_err(&op->dev, "Invalid cell-index property\n"); 458 return -EINVAL; 459 } 460 id = *psc_nump + 1; 461 } 462 463 return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64, 464 irq_of_parse_and_map(op->dev.of_node, 0), id); 465 } 466 467 static int mpc52xx_psc_spi_of_remove(struct platform_device *op) 468 { 469 struct spi_master *master = spi_master_get(platform_get_drvdata(op)); 470 struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master); 471 472 flush_work(&mps->work); 473 spi_unregister_master(master); 474 free_irq(mps->irq, mps); 475 if (mps->psc) 476 iounmap(mps->psc); 477 spi_master_put(master); 478 479 return 0; 480 } 481 482 static const struct of_device_id mpc52xx_psc_spi_of_match[] = { 483 { .compatible = "fsl,mpc5200-psc-spi", }, 484 { .compatible = "mpc5200-psc-spi", }, /* old */ 485 {} 486 }; 487 488 MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match); 489 490 static struct platform_driver mpc52xx_psc_spi_of_driver = { 491 .probe = mpc52xx_psc_spi_of_probe, 492 .remove = mpc52xx_psc_spi_of_remove, 493 .driver = { 494 .name = "mpc52xx-psc-spi", 495 .of_match_table = mpc52xx_psc_spi_of_match, 496 }, 497 }; 498 module_platform_driver(mpc52xx_psc_spi_of_driver); 499 500 MODULE_AUTHOR("Dragos Carp"); 501 MODULE_DESCRIPTION("MPC52xx PSC SPI Driver"); 502 MODULE_LICENSE("GPL"); 503