1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/soc/qcom,rpmh-rsc.h> 9 10/ { 11 interrupt-parent = <&intc>; 12 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 chosen { }; 17 18 clocks { 19 xo_board: xo-board { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 clock-frequency = <38400000>; 23 clock-output-names = "xo_board"; 24 }; 25 26 sleep_clk: sleep-clk { 27 compatible = "fixed-clock"; 28 clock-frequency = <32000>; 29 #clock-cells = <0>; 30 }; 31 }; 32 33 cpus { 34 #address-cells = <2>; 35 #size-cells = <0>; 36 37 CPU0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "qcom,kryo485"; 40 reg = <0x0 0x0>; 41 enable-method = "psci"; 42 next-level-cache = <&L2_0>; 43 L2_0: l2-cache { 44 compatible = "cache"; 45 next-level-cache = <&L3_0>; 46 L3_0: l3-cache { 47 compatible = "cache"; 48 }; 49 }; 50 }; 51 52 CPU1: cpu@100 { 53 device_type = "cpu"; 54 compatible = "qcom,kryo485"; 55 reg = <0x0 0x100>; 56 enable-method = "psci"; 57 next-level-cache = <&L2_100>; 58 L2_100: l2-cache { 59 compatible = "cache"; 60 next-level-cache = <&L3_0>; 61 }; 62 }; 63 64 CPU2: cpu@200 { 65 device_type = "cpu"; 66 compatible = "qcom,kryo485"; 67 reg = <0x0 0x200>; 68 enable-method = "psci"; 69 next-level-cache = <&L2_200>; 70 L2_200: l2-cache { 71 compatible = "cache"; 72 next-level-cache = <&L3_0>; 73 }; 74 }; 75 76 CPU3: cpu@300 { 77 device_type = "cpu"; 78 compatible = "qcom,kryo485"; 79 reg = <0x0 0x300>; 80 enable-method = "psci"; 81 next-level-cache = <&L2_300>; 82 L2_300: l2-cache { 83 compatible = "cache"; 84 next-level-cache = <&L3_0>; 85 }; 86 }; 87 88 CPU4: cpu@400 { 89 device_type = "cpu"; 90 compatible = "qcom,kryo485"; 91 reg = <0x0 0x400>; 92 enable-method = "psci"; 93 next-level-cache = <&L2_400>; 94 L2_400: l2-cache { 95 compatible = "cache"; 96 next-level-cache = <&L3_0>; 97 }; 98 }; 99 100 CPU5: cpu@500 { 101 device_type = "cpu"; 102 compatible = "qcom,kryo485"; 103 reg = <0x0 0x500>; 104 enable-method = "psci"; 105 next-level-cache = <&L2_500>; 106 L2_500: l2-cache { 107 compatible = "cache"; 108 next-level-cache = <&L3_0>; 109 }; 110 111 }; 112 113 CPU6: cpu@600 { 114 device_type = "cpu"; 115 compatible = "qcom,kryo485"; 116 reg = <0x0 0x600>; 117 enable-method = "psci"; 118 next-level-cache = <&L2_600>; 119 L2_600: l2-cache { 120 compatible = "cache"; 121 next-level-cache = <&L3_0>; 122 }; 123 }; 124 125 CPU7: cpu@700 { 126 device_type = "cpu"; 127 compatible = "qcom,kryo485"; 128 reg = <0x0 0x700>; 129 enable-method = "psci"; 130 next-level-cache = <&L2_700>; 131 L2_700: l2-cache { 132 compatible = "cache"; 133 next-level-cache = <&L3_0>; 134 }; 135 }; 136 }; 137 138 firmware { 139 scm: scm { 140 compatible = "qcom,scm"; 141 #reset-cells = <1>; 142 }; 143 }; 144 145 tcsr_mutex: hwlock { 146 compatible = "qcom,tcsr-mutex"; 147 syscon = <&tcsr_mutex_regs 0 0x1000>; 148 #hwlock-cells = <1>; 149 }; 150 151 memory@80000000 { 152 device_type = "memory"; 153 /* We expect the bootloader to fill in the size */ 154 reg = <0x0 0x80000000 0x0 0x0>; 155 }; 156 157 pmu { 158 compatible = "arm,armv8-pmuv3"; 159 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 160 }; 161 162 psci { 163 compatible = "arm,psci-1.0"; 164 method = "smc"; 165 }; 166 167 reserved-memory { 168 #address-cells = <2>; 169 #size-cells = <2>; 170 ranges; 171 172 hyp_mem: memory@80000000 { 173 reg = <0x0 0x80000000 0x0 0x600000>; 174 no-map; 175 }; 176 177 xbl_aop_mem: memory@80700000 { 178 reg = <0x0 0x80700000 0x0 0x160000>; 179 no-map; 180 }; 181 182 cmd_db: memory@80860000 { 183 compatible = "qcom,cmd-db"; 184 reg = <0x0 0x80860000 0x0 0x20000>; 185 no-map; 186 }; 187 188 smem_mem: memory@80900000 { 189 reg = <0x0 0x80900000 0x0 0x200000>; 190 no-map; 191 }; 192 193 removed_mem: memory@80b00000 { 194 reg = <0x0 0x80b00000 0x0 0x5300000>; 195 no-map; 196 }; 197 198 camera_mem: memory@86200000 { 199 reg = <0x0 0x86200000 0x0 0x500000>; 200 no-map; 201 }; 202 203 wlan_mem: memory@86700000 { 204 reg = <0x0 0x86700000 0x0 0x100000>; 205 no-map; 206 }; 207 208 ipa_fw_mem: memory@86800000 { 209 reg = <0x0 0x86800000 0x0 0x10000>; 210 no-map; 211 }; 212 213 ipa_gsi_mem: memory@86810000 { 214 reg = <0x0 0x86810000 0x0 0xa000>; 215 no-map; 216 }; 217 218 gpu_mem: memory@8681a000 { 219 reg = <0x0 0x8681a000 0x0 0x2000>; 220 no-map; 221 }; 222 223 npu_mem: memory@86900000 { 224 reg = <0x0 0x86900000 0x0 0x500000>; 225 no-map; 226 }; 227 228 video_mem: memory@86e00000 { 229 reg = <0x0 0x86e00000 0x0 0x500000>; 230 no-map; 231 }; 232 233 cvp_mem: memory@87300000 { 234 reg = <0x0 0x87300000 0x0 0x500000>; 235 no-map; 236 }; 237 238 cdsp_mem: memory@87800000 { 239 reg = <0x0 0x87800000 0x0 0x1400000>; 240 no-map; 241 }; 242 243 slpi_mem: memory@88c00000 { 244 reg = <0x0 0x88c00000 0x0 0x1500000>; 245 no-map; 246 }; 247 248 adsp_mem: memory@8a100000 { 249 reg = <0x0 0x8a100000 0x0 0x1d00000>; 250 no-map; 251 }; 252 253 spss_mem: memory@8be00000 { 254 reg = <0x0 0x8be00000 0x0 0x100000>; 255 no-map; 256 }; 257 258 cdsp_secure_heap: memory@8bf00000 { 259 reg = <0x0 0x8bf00000 0x0 0x4600000>; 260 no-map; 261 }; 262 }; 263 264 smem: qcom,smem { 265 compatible = "qcom,smem"; 266 memory-region = <&smem_mem>; 267 hwlocks = <&tcsr_mutex 3>; 268 }; 269 270 soc: soc@0 { 271 #address-cells = <2>; 272 #size-cells = <2>; 273 ranges = <0 0 0 0 0x10 0>; 274 dma-ranges = <0 0 0 0 0x10 0>; 275 compatible = "simple-bus"; 276 277 gcc: clock-controller@100000 { 278 compatible = "qcom,gcc-sm8250"; 279 reg = <0x0 0x00100000 0x0 0x1f0000>; 280 #clock-cells = <1>; 281 #reset-cells = <1>; 282 #power-domain-cells = <1>; 283 clock-names = "bi_tcxo", "sleep_clk"; 284 clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; 285 }; 286 287 qupv3_id_1: geniqup@ac0000 { 288 compatible = "qcom,geni-se-qup"; 289 reg = <0x0 0x00ac0000 0x0 0x6000>; 290 clock-names = "m-ahb", "s-ahb"; 291 clocks = <&gcc 133>, <&gcc 134>; 292 #address-cells = <2>; 293 #size-cells = <2>; 294 ranges; 295 status = "disabled"; 296 297 uart2: serial@a90000 { 298 compatible = "qcom,geni-debug-uart"; 299 reg = <0x0 0x00a90000 0x0 0x4000>; 300 clock-names = "se"; 301 clocks = <&gcc 113>; 302 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 303 status = "disabled"; 304 }; 305 }; 306 307 intc: interrupt-controller@17a00000 { 308 compatible = "arm,gic-v3"; 309 #interrupt-cells = <3>; 310 interrupt-controller; 311 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 312 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 313 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 314 }; 315 316 pdc: interrupt-controller@b220000 { 317 compatible = "qcom,sm8250-pdc"; 318 reg = <0x0b220000 0x30000>, <0x17c000f0 0x60>; 319 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 320 <125 63 1>, <126 716 12>; 321 #interrupt-cells = <2>; 322 interrupt-parent = <&intc>; 323 interrupt-controller; 324 }; 325 326 spmi: qcom,spmi@c440000 { 327 compatible = "qcom,spmi-pmic-arb"; 328 reg = <0x0 0x0c440000 0x0 0x0001100>, 329 <0x0 0x0c600000 0x0 0x2000000>, 330 <0x0 0x0e600000 0x0 0x0100000>, 331 <0x0 0x0e700000 0x0 0x00a0000>, 332 <0x0 0x0c40a000 0x0 0x0026000>; 333 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 334 interrupt-names = "periph_irq"; 335 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 336 qcom,ee = <0>; 337 qcom,channel = <0>; 338 #address-cells = <2>; 339 #size-cells = <0>; 340 interrupt-controller; 341 #interrupt-cells = <4>; 342 }; 343 344 apps_rsc: rsc@18200000 { 345 label = "apps_rsc"; 346 compatible = "qcom,rpmh-rsc"; 347 reg = <0x0 0x18200000 0x0 0x10000>, 348 <0x0 0x18210000 0x0 0x10000>, 349 <0x0 0x18220000 0x0 0x10000>; 350 reg-names = "drv-0", "drv-1", "drv-2"; 351 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 354 qcom,tcs-offset = <0xd00>; 355 qcom,drv-id = <2>; 356 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 357 <WAKE_TCS 3>, <CONTROL_TCS 1>; 358 359 rpmhcc: clock-controller { 360 compatible = "qcom,sm8250-rpmh-clk"; 361 #clock-cells = <1>; 362 clock-names = "xo"; 363 clocks = <&xo_board>; 364 }; 365 }; 366 367 tcsr_mutex_regs: syscon@1f40000 { 368 compatible = "syscon"; 369 reg = <0x0 0x01f40000 0x0 0x40000>; 370 }; 371 372 timer@17c20000 { 373 #address-cells = <2>; 374 #size-cells = <2>; 375 ranges; 376 compatible = "arm,armv7-timer-mem"; 377 reg = <0x0 0x17c20000 0x0 0x1000>; 378 clock-frequency = <19200000>; 379 380 frame@17c21000 { 381 frame-number = <0>; 382 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 384 reg = <0x0 0x17c21000 0x0 0x1000>, 385 <0x0 0x17c22000 0x0 0x1000>; 386 }; 387 388 frame@17c23000 { 389 frame-number = <1>; 390 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 391 reg = <0x0 0x17c23000 0x0 0x1000>; 392 status = "disabled"; 393 }; 394 395 frame@17c25000 { 396 frame-number = <2>; 397 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 398 reg = <0x0 0x17c25000 0x0 0x1000>; 399 status = "disabled"; 400 }; 401 402 frame@17c27000 { 403 frame-number = <3>; 404 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 405 reg = <0x0 0x17c27000 0x0 0x1000>; 406 status = "disabled"; 407 }; 408 409 frame@17c29000 { 410 frame-number = <4>; 411 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 412 reg = <0x0 0x17c29000 0x0 0x1000>; 413 status = "disabled"; 414 }; 415 416 frame@17c2b000 { 417 frame-number = <5>; 418 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 419 reg = <0x0 0x17c2b000 0x0 0x1000>; 420 status = "disabled"; 421 }; 422 423 frame@17c2d000 { 424 frame-number = <6>; 425 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 426 reg = <0x0 0x17c2d000 0x0 0x1000>; 427 status = "disabled"; 428 }; 429 }; 430 431 }; 432 433 timer { 434 compatible = "arm,armv8-timer"; 435 interrupts = <GIC_PPI 13 436 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 437 <GIC_PPI 14 438 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 439 <GIC_PPI 11 440 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 441 <GIC_PPI 12 442 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 443 }; 444}; 445