1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  *
6  * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
7  */
8 
9 #ifndef __ADRENO_GPU_H__
10 #define __ADRENO_GPU_H__
11 
12 #include <linux/firmware.h>
13 #include <linux/iopoll.h>
14 
15 #include "msm_gpu.h"
16 
17 #include "adreno_common.xml.h"
18 #include "adreno_pm4.xml.h"
19 
20 #define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
21 #define REG_SKIP ~0
22 #define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP
23 
24 /**
25  * adreno_regs: List of registers that are used in across all
26  * 3D devices. Each device type has different offset value for the same
27  * register, so an array of register offsets are declared for every device
28  * and are indexed by the enumeration values defined in this enum
29  */
30 enum adreno_regs {
31 	REG_ADRENO_CP_RB_BASE,
32 	REG_ADRENO_CP_RB_BASE_HI,
33 	REG_ADRENO_CP_RB_RPTR_ADDR,
34 	REG_ADRENO_CP_RB_RPTR_ADDR_HI,
35 	REG_ADRENO_CP_RB_RPTR,
36 	REG_ADRENO_CP_RB_WPTR,
37 	REG_ADRENO_CP_RB_CNTL,
38 	REG_ADRENO_REGISTER_MAX,
39 };
40 
41 enum {
42 	ADRENO_FW_PM4 = 0,
43 	ADRENO_FW_SQE = 0, /* a6xx */
44 	ADRENO_FW_PFP = 1,
45 	ADRENO_FW_GMU = 1, /* a6xx */
46 	ADRENO_FW_GPMU = 2,
47 	ADRENO_FW_MAX,
48 };
49 
50 enum adreno_quirks {
51 	ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
52 	ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
53 	ADRENO_QUIRK_LMLOADKILL_DISABLE = 3,
54 };
55 
56 struct adreno_rev {
57 	uint8_t  core;
58 	uint8_t  major;
59 	uint8_t  minor;
60 	uint8_t  patchid;
61 };
62 
63 #define ADRENO_REV(core, major, minor, patchid) \
64 	((struct adreno_rev){ core, major, minor, patchid })
65 
66 struct adreno_gpu_funcs {
67 	struct msm_gpu_funcs base;
68 	int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
69 };
70 
71 struct adreno_reglist {
72 	u32 offset;
73 	u32 value;
74 };
75 
76 extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[];
77 
78 struct adreno_info {
79 	struct adreno_rev rev;
80 	uint32_t revn;
81 	const char *name;
82 	const char *fw[ADRENO_FW_MAX];
83 	uint32_t gmem;
84 	enum adreno_quirks quirks;
85 	struct msm_gpu *(*init)(struct drm_device *dev);
86 	const char *zapfw;
87 	u32 inactive_period;
88 	const struct adreno_reglist *hwcg;
89 };
90 
91 const struct adreno_info *adreno_info(struct adreno_rev rev);
92 
93 struct adreno_gpu {
94 	struct msm_gpu base;
95 	struct adreno_rev rev;
96 	const struct adreno_info *info;
97 	uint32_t gmem;  /* actual gmem size */
98 	uint32_t revn;  /* numeric revision name */
99 	const struct adreno_gpu_funcs *funcs;
100 
101 	/* interesting register offsets to dump: */
102 	const unsigned int *registers;
103 
104 	/*
105 	 * Are we loading fw from legacy path?  Prior to addition
106 	 * of gpu firmware to linux-firmware, the fw files were
107 	 * placed in toplevel firmware directory, following qcom's
108 	 * android kernel.  But linux-firmware preferred they be
109 	 * placed in a 'qcom' subdirectory.
110 	 *
111 	 * For backwards compatibility, we try first to load from
112 	 * the new path, using request_firmware_direct() to avoid
113 	 * any potential timeout waiting for usermode helper, then
114 	 * fall back to the old path (with direct load).  And
115 	 * finally fall back to request_firmware() with the new
116 	 * path to allow the usermode helper.
117 	 */
118 	enum {
119 		FW_LOCATION_UNKNOWN = 0,
120 		FW_LOCATION_NEW,       /* /lib/firmware/qcom/$fwfile */
121 		FW_LOCATION_LEGACY,    /* /lib/firmware/$fwfile */
122 		FW_LOCATION_HELPER,
123 	} fwloc;
124 
125 	/* firmware: */
126 	const struct firmware *fw[ADRENO_FW_MAX];
127 
128 	/*
129 	 * Register offsets are different between some GPUs.
130 	 * GPU specific offsets will be exported by GPU specific
131 	 * code (a3xx_gpu.c) and stored in this common location.
132 	 */
133 	const unsigned int *reg_offsets;
134 };
135 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
136 
137 struct adreno_ocmem {
138 	struct ocmem *ocmem;
139 	unsigned long base;
140 	void *hdl;
141 };
142 
143 /* platform config data (ie. from DT, or pdata) */
144 struct adreno_platform_config {
145 	struct adreno_rev rev;
146 };
147 
148 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
149 
150 #define spin_until(X) ({                                   \
151 	int __ret = -ETIMEDOUT;                            \
152 	unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
153 	do {                                               \
154 		if (X) {                                   \
155 			__ret = 0;                         \
156 			break;                             \
157 		}                                          \
158 	} while (time_before(jiffies, __t));               \
159 	__ret;                                             \
160 })
161 
162 static inline bool adreno_is_a2xx(struct adreno_gpu *gpu)
163 {
164 	return (gpu->revn < 300);
165 }
166 
167 static inline bool adreno_is_a20x(struct adreno_gpu *gpu)
168 {
169 	return (gpu->revn < 210);
170 }
171 
172 static inline bool adreno_is_a225(struct adreno_gpu *gpu)
173 {
174 	return gpu->revn == 225;
175 }
176 
177 static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
178 {
179 	return (gpu->revn >= 300) && (gpu->revn < 400);
180 }
181 
182 static inline bool adreno_is_a305(struct adreno_gpu *gpu)
183 {
184 	return gpu->revn == 305;
185 }
186 
187 static inline bool adreno_is_a306(struct adreno_gpu *gpu)
188 {
189 	/* yes, 307, because a305c is 306 */
190 	return gpu->revn == 307;
191 }
192 
193 static inline bool adreno_is_a320(struct adreno_gpu *gpu)
194 {
195 	return gpu->revn == 320;
196 }
197 
198 static inline bool adreno_is_a330(struct adreno_gpu *gpu)
199 {
200 	return gpu->revn == 330;
201 }
202 
203 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
204 {
205 	return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
206 }
207 
208 static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
209 {
210 	return (gpu->revn >= 400) && (gpu->revn < 500);
211 }
212 
213 static inline int adreno_is_a405(struct adreno_gpu *gpu)
214 {
215 	return gpu->revn == 405;
216 }
217 
218 static inline int adreno_is_a420(struct adreno_gpu *gpu)
219 {
220 	return gpu->revn == 420;
221 }
222 
223 static inline int adreno_is_a430(struct adreno_gpu *gpu)
224 {
225        return gpu->revn == 430;
226 }
227 
228 static inline int adreno_is_a510(struct adreno_gpu *gpu)
229 {
230 	return gpu->revn == 510;
231 }
232 
233 static inline int adreno_is_a530(struct adreno_gpu *gpu)
234 {
235 	return gpu->revn == 530;
236 }
237 
238 static inline int adreno_is_a540(struct adreno_gpu *gpu)
239 {
240 	return gpu->revn == 540;
241 }
242 
243 static inline int adreno_is_a618(struct adreno_gpu *gpu)
244 {
245        return gpu->revn == 618;
246 }
247 
248 static inline int adreno_is_a630(struct adreno_gpu *gpu)
249 {
250        return gpu->revn == 630;
251 }
252 
253 static inline int adreno_is_a640(struct adreno_gpu *gpu)
254 {
255        return gpu->revn == 640;
256 }
257 
258 static inline int adreno_is_a650(struct adreno_gpu *gpu)
259 {
260        return gpu->revn == 650;
261 }
262 
263 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
264 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
265 		const char *fwname);
266 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
267 		const struct firmware *fw, u64 *iova);
268 int adreno_hw_init(struct msm_gpu *gpu);
269 void adreno_recover(struct msm_gpu *gpu);
270 void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
271 		struct msm_file_private *ctx);
272 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
273 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
274 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
275 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
276 		struct drm_printer *p);
277 #endif
278 void adreno_dump_info(struct msm_gpu *gpu);
279 void adreno_dump(struct msm_gpu *gpu);
280 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
281 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
282 
283 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
284 			  struct adreno_ocmem *ocmem);
285 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem);
286 
287 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
288 		struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
289 		int nr_rings);
290 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
291 int adreno_load_fw(struct adreno_gpu *adreno_gpu);
292 
293 void adreno_gpu_state_destroy(struct msm_gpu_state *state);
294 
295 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
296 int adreno_gpu_state_put(struct msm_gpu_state *state);
297 
298 /*
299  * Common helper function to initialize the default address space for arm-smmu
300  * attached targets
301  */
302 struct msm_gem_address_space *
303 adreno_iommu_create_address_space(struct msm_gpu *gpu,
304 		struct platform_device *pdev);
305 
306 /*
307  * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
308  * out of secure mode
309  */
310 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
311 
312 /* ringbuffer helpers (the parts that are adreno specific) */
313 
314 static inline void
315 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
316 {
317 	adreno_wait_ring(ring, cnt+1);
318 	OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
319 }
320 
321 /* no-op packet: */
322 static inline void
323 OUT_PKT2(struct msm_ringbuffer *ring)
324 {
325 	adreno_wait_ring(ring, 1);
326 	OUT_RING(ring, CP_TYPE2_PKT);
327 }
328 
329 static inline void
330 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
331 {
332 	adreno_wait_ring(ring, cnt+1);
333 	OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
334 }
335 
336 static inline u32 PM4_PARITY(u32 val)
337 {
338 	return (0x9669 >> (0xF & (val ^
339 		(val >> 4) ^ (val >> 8) ^ (val >> 12) ^
340 		(val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
341 		(val >> 28)))) & 1;
342 }
343 
344 /* Maximum number of values that can be executed for one opcode */
345 #define TYPE4_MAX_PAYLOAD 127
346 
347 #define PKT4(_reg, _cnt) \
348 	(CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
349 	 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
350 
351 static inline void
352 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
353 {
354 	adreno_wait_ring(ring, cnt + 1);
355 	OUT_RING(ring, PKT4(regindx, cnt));
356 }
357 
358 static inline void
359 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
360 {
361 	adreno_wait_ring(ring, cnt + 1);
362 	OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
363 		((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
364 }
365 
366 /*
367  * adreno_reg_check() - Checks the validity of a register enum
368  * @gpu:		Pointer to struct adreno_gpu
369  * @offset_name:	The register enum that is checked
370  */
371 static inline bool adreno_reg_check(struct adreno_gpu *gpu,
372 		enum adreno_regs offset_name)
373 {
374 	BUG_ON(offset_name >= REG_ADRENO_REGISTER_MAX || !gpu->reg_offsets[offset_name]);
375 
376 	/*
377 	 * REG_SKIP is a special value that tell us that the register in
378 	 * question isn't implemented on target but don't trigger a BUG(). This
379 	 * is used to cleanly implement adreno_gpu_write64() and
380 	 * adreno_gpu_read64() in a generic fashion
381 	 */
382 	if (gpu->reg_offsets[offset_name] == REG_SKIP)
383 		return false;
384 
385 	return true;
386 }
387 
388 static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
389 		enum adreno_regs offset_name)
390 {
391 	u32 reg = gpu->reg_offsets[offset_name];
392 	u32 val = 0;
393 	if(adreno_reg_check(gpu,offset_name))
394 		val = gpu_read(&gpu->base, reg - 1);
395 	return val;
396 }
397 
398 static inline void adreno_gpu_write(struct adreno_gpu *gpu,
399 		enum adreno_regs offset_name, u32 data)
400 {
401 	u32 reg = gpu->reg_offsets[offset_name];
402 	if(adreno_reg_check(gpu, offset_name))
403 		gpu_write(&gpu->base, reg - 1, data);
404 }
405 
406 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
407 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
408 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
409 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
410 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
411 
412 static inline void adreno_gpu_write64(struct adreno_gpu *gpu,
413 		enum adreno_regs lo, enum adreno_regs hi, u64 data)
414 {
415 	adreno_gpu_write(gpu, lo, lower_32_bits(data));
416 	adreno_gpu_write(gpu, hi, upper_32_bits(data));
417 }
418 
419 static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
420 {
421 	return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
422 }
423 
424 /*
425  * Given a register and a count, return a value to program into
426  * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
427  * registers starting at _reg.
428  *
429  * The register base needs to be a multiple of the length. If it is not, the
430  * hardware will quietly mask off the bits for you and shift the size. For
431  * example, if you intend the protection to start at 0x07 for a length of 4
432  * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
433  * expose registers you intended to protect!
434  */
435 #define ADRENO_PROTECT_RW(_reg, _len) \
436 	((1 << 30) | (1 << 29) | \
437 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
438 
439 /*
440  * Same as above, but allow reads over the range. For areas of mixed use (such
441  * as performance counters) this allows us to protect a much larger range with a
442  * single register
443  */
444 #define ADRENO_PROTECT_RDONLY(_reg, _len) \
445 	((1 << 29) \
446 	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
447 
448 
449 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
450 	readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
451 		interval, timeout)
452 
453 #endif /* __ADRENO_GPU_H__ */
454