1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/interconnect.h> 10 #include <linux/of_irq.h> 11 12 #include <drm/drm_debugfs.h> 13 #include <drm/drm_drv.h> 14 #include <drm/drm_file.h> 15 #include <drm/drm_vblank.h> 16 17 #include "msm_drv.h" 18 #include "msm_gem.h" 19 #include "msm_mmu.h" 20 #include "mdp5_kms.h" 21 22 static int mdp5_hw_init(struct msm_kms *kms) 23 { 24 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 25 struct device *dev = &mdp5_kms->pdev->dev; 26 unsigned long flags; 27 28 pm_runtime_get_sync(dev); 29 30 /* Magic unknown register writes: 31 * 32 * W VBIF:0x004 00000001 (mdss_mdp.c:839) 33 * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839) 34 * W MDP5:0x2e4 0x55 (mdss_mdp.c:839) 35 * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839) 36 * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839) 37 * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839) 38 * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839) 39 * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839) 40 * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839) 41 * 42 * Downstream fbdev driver gets these register offsets/values 43 * from DT.. not really sure what these registers are or if 44 * different values for different boards/SoC's, etc. I guess 45 * they are the golden registers. 46 * 47 * Not setting these does not seem to cause any problem. But 48 * we may be getting lucky with the bootloader initializing 49 * them for us. OTOH, if we can always count on the bootloader 50 * setting the golden registers, then perhaps we don't need to 51 * care. 52 */ 53 54 spin_lock_irqsave(&mdp5_kms->resource_lock, flags); 55 mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0); 56 spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags); 57 58 mdp5_ctlm_hw_reset(mdp5_kms->ctlm); 59 60 pm_runtime_put_sync(dev); 61 62 return 0; 63 } 64 65 /* Global/shared object state funcs */ 66 67 /* 68 * This is a helper that returns the private state currently in operation. 69 * Note that this would return the "old_state" if called in the atomic check 70 * path, and the "new_state" after the atomic swap has been done. 71 */ 72 struct mdp5_global_state * 73 mdp5_get_existing_global_state(struct mdp5_kms *mdp5_kms) 74 { 75 return to_mdp5_global_state(mdp5_kms->glob_state.state); 76 } 77 78 /* 79 * This acquires the modeset lock set aside for global state, creates 80 * a new duplicated private object state. 81 */ 82 struct mdp5_global_state *mdp5_get_global_state(struct drm_atomic_state *s) 83 { 84 struct msm_drm_private *priv = s->dev->dev_private; 85 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 86 struct drm_private_state *priv_state; 87 int ret; 88 89 ret = drm_modeset_lock(&mdp5_kms->glob_state_lock, s->acquire_ctx); 90 if (ret) 91 return ERR_PTR(ret); 92 93 priv_state = drm_atomic_get_private_obj_state(s, &mdp5_kms->glob_state); 94 if (IS_ERR(priv_state)) 95 return ERR_CAST(priv_state); 96 97 return to_mdp5_global_state(priv_state); 98 } 99 100 static struct drm_private_state * 101 mdp5_global_duplicate_state(struct drm_private_obj *obj) 102 { 103 struct mdp5_global_state *state; 104 105 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 106 if (!state) 107 return NULL; 108 109 __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 110 111 return &state->base; 112 } 113 114 static void mdp5_global_destroy_state(struct drm_private_obj *obj, 115 struct drm_private_state *state) 116 { 117 struct mdp5_global_state *mdp5_state = to_mdp5_global_state(state); 118 119 kfree(mdp5_state); 120 } 121 122 static const struct drm_private_state_funcs mdp5_global_state_funcs = { 123 .atomic_duplicate_state = mdp5_global_duplicate_state, 124 .atomic_destroy_state = mdp5_global_destroy_state, 125 }; 126 127 static int mdp5_global_obj_init(struct mdp5_kms *mdp5_kms) 128 { 129 struct mdp5_global_state *state; 130 131 drm_modeset_lock_init(&mdp5_kms->glob_state_lock); 132 133 state = kzalloc(sizeof(*state), GFP_KERNEL); 134 if (!state) 135 return -ENOMEM; 136 137 state->mdp5_kms = mdp5_kms; 138 139 drm_atomic_private_obj_init(mdp5_kms->dev, &mdp5_kms->glob_state, 140 &state->base, 141 &mdp5_global_state_funcs); 142 return 0; 143 } 144 145 static void mdp5_enable_commit(struct msm_kms *kms) 146 { 147 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 148 pm_runtime_get_sync(&mdp5_kms->pdev->dev); 149 } 150 151 static void mdp5_disable_commit(struct msm_kms *kms) 152 { 153 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 154 pm_runtime_put_sync(&mdp5_kms->pdev->dev); 155 } 156 157 static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) 158 { 159 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 160 struct mdp5_global_state *global_state; 161 162 global_state = mdp5_get_existing_global_state(mdp5_kms); 163 164 if (mdp5_kms->smp) 165 mdp5_smp_prepare_commit(mdp5_kms->smp, &global_state->smp); 166 } 167 168 static void mdp5_flush_commit(struct msm_kms *kms, unsigned crtc_mask) 169 { 170 /* TODO */ 171 } 172 173 static void mdp5_wait_flush(struct msm_kms *kms, unsigned crtc_mask) 174 { 175 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 176 struct drm_crtc *crtc; 177 178 for_each_crtc_mask(mdp5_kms->dev, crtc, crtc_mask) 179 mdp5_crtc_wait_for_commit_done(crtc); 180 } 181 182 static void mdp5_complete_commit(struct msm_kms *kms, unsigned crtc_mask) 183 { 184 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 185 struct mdp5_global_state *global_state; 186 187 global_state = mdp5_get_existing_global_state(mdp5_kms); 188 189 if (mdp5_kms->smp) 190 mdp5_smp_complete_commit(mdp5_kms->smp, &global_state->smp); 191 } 192 193 static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate, 194 struct drm_encoder *encoder) 195 { 196 return rate; 197 } 198 199 static int mdp5_set_split_display(struct msm_kms *kms, 200 struct drm_encoder *encoder, 201 struct drm_encoder *slave_encoder, 202 bool is_cmd_mode) 203 { 204 if (is_cmd_mode) 205 return mdp5_cmd_encoder_set_split_display(encoder, 206 slave_encoder); 207 else 208 return mdp5_vid_encoder_set_split_display(encoder, 209 slave_encoder); 210 } 211 212 static void mdp5_set_encoder_mode(struct msm_kms *kms, 213 struct drm_encoder *encoder, 214 bool cmd_mode) 215 { 216 mdp5_encoder_set_intf_mode(encoder, cmd_mode); 217 } 218 219 static void mdp5_kms_destroy(struct msm_kms *kms) 220 { 221 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 222 struct msm_gem_address_space *aspace = kms->aspace; 223 int i; 224 225 for (i = 0; i < mdp5_kms->num_hwmixers; i++) 226 mdp5_mixer_destroy(mdp5_kms->hwmixers[i]); 227 228 for (i = 0; i < mdp5_kms->num_hwpipes; i++) 229 mdp5_pipe_destroy(mdp5_kms->hwpipes[i]); 230 231 if (aspace) { 232 aspace->mmu->funcs->detach(aspace->mmu); 233 msm_gem_address_space_put(aspace); 234 } 235 } 236 237 #ifdef CONFIG_DEBUG_FS 238 static int smp_show(struct seq_file *m, void *arg) 239 { 240 struct drm_info_node *node = (struct drm_info_node *) m->private; 241 struct drm_device *dev = node->minor->dev; 242 struct msm_drm_private *priv = dev->dev_private; 243 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); 244 struct drm_printer p = drm_seq_file_printer(m); 245 246 if (!mdp5_kms->smp) { 247 drm_printf(&p, "no SMP pool\n"); 248 return 0; 249 } 250 251 mdp5_smp_dump(mdp5_kms->smp, &p); 252 253 return 0; 254 } 255 256 static struct drm_info_list mdp5_debugfs_list[] = { 257 {"smp", smp_show }, 258 }; 259 260 static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) 261 { 262 struct drm_device *dev = minor->dev; 263 int ret; 264 265 ret = drm_debugfs_create_files(mdp5_debugfs_list, 266 ARRAY_SIZE(mdp5_debugfs_list), 267 minor->debugfs_root, minor); 268 269 if (ret) { 270 DRM_DEV_ERROR(dev->dev, "could not install mdp5_debugfs_list\n"); 271 return ret; 272 } 273 274 return 0; 275 } 276 #endif 277 278 static const struct mdp_kms_funcs kms_funcs = { 279 .base = { 280 .hw_init = mdp5_hw_init, 281 .irq_preinstall = mdp5_irq_preinstall, 282 .irq_postinstall = mdp5_irq_postinstall, 283 .irq_uninstall = mdp5_irq_uninstall, 284 .irq = mdp5_irq, 285 .enable_vblank = mdp5_enable_vblank, 286 .disable_vblank = mdp5_disable_vblank, 287 .flush_commit = mdp5_flush_commit, 288 .enable_commit = mdp5_enable_commit, 289 .disable_commit = mdp5_disable_commit, 290 .prepare_commit = mdp5_prepare_commit, 291 .wait_flush = mdp5_wait_flush, 292 .complete_commit = mdp5_complete_commit, 293 .get_format = mdp_get_format, 294 .round_pixclk = mdp5_round_pixclk, 295 .set_split_display = mdp5_set_split_display, 296 .set_encoder_mode = mdp5_set_encoder_mode, 297 .destroy = mdp5_kms_destroy, 298 #ifdef CONFIG_DEBUG_FS 299 .debugfs_init = mdp5_kms_debugfs_init, 300 #endif 301 }, 302 .set_irqmask = mdp5_set_irqmask, 303 }; 304 305 int mdp5_disable(struct mdp5_kms *mdp5_kms) 306 { 307 DBG(""); 308 309 mdp5_kms->enable_count--; 310 WARN_ON(mdp5_kms->enable_count < 0); 311 312 if (mdp5_kms->tbu_rt_clk) 313 clk_disable_unprepare(mdp5_kms->tbu_rt_clk); 314 if (mdp5_kms->tbu_clk) 315 clk_disable_unprepare(mdp5_kms->tbu_clk); 316 clk_disable_unprepare(mdp5_kms->ahb_clk); 317 clk_disable_unprepare(mdp5_kms->axi_clk); 318 clk_disable_unprepare(mdp5_kms->core_clk); 319 if (mdp5_kms->lut_clk) 320 clk_disable_unprepare(mdp5_kms->lut_clk); 321 322 return 0; 323 } 324 325 int mdp5_enable(struct mdp5_kms *mdp5_kms) 326 { 327 DBG(""); 328 329 mdp5_kms->enable_count++; 330 331 clk_prepare_enable(mdp5_kms->ahb_clk); 332 clk_prepare_enable(mdp5_kms->axi_clk); 333 clk_prepare_enable(mdp5_kms->core_clk); 334 if (mdp5_kms->lut_clk) 335 clk_prepare_enable(mdp5_kms->lut_clk); 336 if (mdp5_kms->tbu_clk) 337 clk_prepare_enable(mdp5_kms->tbu_clk); 338 if (mdp5_kms->tbu_rt_clk) 339 clk_prepare_enable(mdp5_kms->tbu_rt_clk); 340 341 return 0; 342 } 343 344 static struct drm_encoder *construct_encoder(struct mdp5_kms *mdp5_kms, 345 struct mdp5_interface *intf, 346 struct mdp5_ctl *ctl) 347 { 348 struct drm_device *dev = mdp5_kms->dev; 349 struct msm_drm_private *priv = dev->dev_private; 350 struct drm_encoder *encoder; 351 352 encoder = mdp5_encoder_init(dev, intf, ctl); 353 if (IS_ERR(encoder)) { 354 DRM_DEV_ERROR(dev->dev, "failed to construct encoder\n"); 355 return encoder; 356 } 357 358 priv->encoders[priv->num_encoders++] = encoder; 359 360 return encoder; 361 } 362 363 static int get_dsi_id_from_intf(const struct mdp5_cfg_hw *hw_cfg, int intf_num) 364 { 365 const enum mdp5_intf_type *intfs = hw_cfg->intf.connect; 366 const int intf_cnt = ARRAY_SIZE(hw_cfg->intf.connect); 367 int id = 0, i; 368 369 for (i = 0; i < intf_cnt; i++) { 370 if (intfs[i] == INTF_DSI) { 371 if (intf_num == i) 372 return id; 373 374 id++; 375 } 376 } 377 378 return -EINVAL; 379 } 380 381 static int modeset_init_intf(struct mdp5_kms *mdp5_kms, 382 struct mdp5_interface *intf) 383 { 384 struct drm_device *dev = mdp5_kms->dev; 385 struct msm_drm_private *priv = dev->dev_private; 386 struct mdp5_ctl_manager *ctlm = mdp5_kms->ctlm; 387 struct mdp5_ctl *ctl; 388 struct drm_encoder *encoder; 389 int ret = 0; 390 391 switch (intf->type) { 392 case INTF_eDP: 393 if (!priv->edp) 394 break; 395 396 ctl = mdp5_ctlm_request(ctlm, intf->num); 397 if (!ctl) { 398 ret = -EINVAL; 399 break; 400 } 401 402 encoder = construct_encoder(mdp5_kms, intf, ctl); 403 if (IS_ERR(encoder)) { 404 ret = PTR_ERR(encoder); 405 break; 406 } 407 408 ret = msm_edp_modeset_init(priv->edp, dev, encoder); 409 break; 410 case INTF_HDMI: 411 if (!priv->hdmi) 412 break; 413 414 ctl = mdp5_ctlm_request(ctlm, intf->num); 415 if (!ctl) { 416 ret = -EINVAL; 417 break; 418 } 419 420 encoder = construct_encoder(mdp5_kms, intf, ctl); 421 if (IS_ERR(encoder)) { 422 ret = PTR_ERR(encoder); 423 break; 424 } 425 426 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder); 427 break; 428 case INTF_DSI: 429 { 430 const struct mdp5_cfg_hw *hw_cfg = 431 mdp5_cfg_get_hw_config(mdp5_kms->cfg); 432 int dsi_id = get_dsi_id_from_intf(hw_cfg, intf->num); 433 434 if ((dsi_id >= ARRAY_SIZE(priv->dsi)) || (dsi_id < 0)) { 435 DRM_DEV_ERROR(dev->dev, "failed to find dsi from intf %d\n", 436 intf->num); 437 ret = -EINVAL; 438 break; 439 } 440 441 if (!priv->dsi[dsi_id]) 442 break; 443 444 ctl = mdp5_ctlm_request(ctlm, intf->num); 445 if (!ctl) { 446 ret = -EINVAL; 447 break; 448 } 449 450 encoder = construct_encoder(mdp5_kms, intf, ctl); 451 if (IS_ERR(encoder)) { 452 ret = PTR_ERR(encoder); 453 break; 454 } 455 456 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder); 457 break; 458 } 459 default: 460 DRM_DEV_ERROR(dev->dev, "unknown intf: %d\n", intf->type); 461 ret = -EINVAL; 462 break; 463 } 464 465 return ret; 466 } 467 468 static int modeset_init(struct mdp5_kms *mdp5_kms) 469 { 470 struct drm_device *dev = mdp5_kms->dev; 471 struct msm_drm_private *priv = dev->dev_private; 472 unsigned int num_crtcs; 473 int i, ret, pi = 0, ci = 0; 474 struct drm_plane *primary[MAX_BASES] = { NULL }; 475 struct drm_plane *cursor[MAX_BASES] = { NULL }; 476 477 /* 478 * Construct encoders and modeset initialize connector devices 479 * for each external display interface. 480 */ 481 for (i = 0; i < mdp5_kms->num_intfs; i++) { 482 ret = modeset_init_intf(mdp5_kms, mdp5_kms->intfs[i]); 483 if (ret) 484 goto fail; 485 } 486 487 /* 488 * We should ideally have less number of encoders (set up by parsing 489 * the MDP5 interfaces) than the number of layer mixers present in HW, 490 * but let's be safe here anyway 491 */ 492 num_crtcs = min(priv->num_encoders, mdp5_kms->num_hwmixers); 493 494 /* 495 * Construct planes equaling the number of hw pipes, and CRTCs for the 496 * N encoders set up by the driver. The first N planes become primary 497 * planes for the CRTCs, with the remainder as overlay planes: 498 */ 499 for (i = 0; i < mdp5_kms->num_hwpipes; i++) { 500 struct mdp5_hw_pipe *hwpipe = mdp5_kms->hwpipes[i]; 501 struct drm_plane *plane; 502 enum drm_plane_type type; 503 504 if (i < num_crtcs) 505 type = DRM_PLANE_TYPE_PRIMARY; 506 else if (hwpipe->caps & MDP_PIPE_CAP_CURSOR) 507 type = DRM_PLANE_TYPE_CURSOR; 508 else 509 type = DRM_PLANE_TYPE_OVERLAY; 510 511 plane = mdp5_plane_init(dev, type); 512 if (IS_ERR(plane)) { 513 ret = PTR_ERR(plane); 514 DRM_DEV_ERROR(dev->dev, "failed to construct plane %d (%d)\n", i, ret); 515 goto fail; 516 } 517 priv->planes[priv->num_planes++] = plane; 518 519 if (type == DRM_PLANE_TYPE_PRIMARY) 520 primary[pi++] = plane; 521 if (type == DRM_PLANE_TYPE_CURSOR) 522 cursor[ci++] = plane; 523 } 524 525 for (i = 0; i < num_crtcs; i++) { 526 struct drm_crtc *crtc; 527 528 crtc = mdp5_crtc_init(dev, primary[i], cursor[i], i); 529 if (IS_ERR(crtc)) { 530 ret = PTR_ERR(crtc); 531 DRM_DEV_ERROR(dev->dev, "failed to construct crtc %d (%d)\n", i, ret); 532 goto fail; 533 } 534 priv->crtcs[priv->num_crtcs++] = crtc; 535 } 536 537 /* 538 * Now that we know the number of crtcs we've created, set the possible 539 * crtcs for the encoders 540 */ 541 for (i = 0; i < priv->num_encoders; i++) { 542 struct drm_encoder *encoder = priv->encoders[i]; 543 544 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1; 545 } 546 547 return 0; 548 549 fail: 550 return ret; 551 } 552 553 static void read_mdp_hw_revision(struct mdp5_kms *mdp5_kms, 554 u32 *major, u32 *minor) 555 { 556 struct device *dev = &mdp5_kms->pdev->dev; 557 u32 version; 558 559 pm_runtime_get_sync(dev); 560 version = mdp5_read(mdp5_kms, REG_MDP5_HW_VERSION); 561 pm_runtime_put_sync(dev); 562 563 *major = FIELD(version, MDP5_HW_VERSION_MAJOR); 564 *minor = FIELD(version, MDP5_HW_VERSION_MINOR); 565 566 DRM_DEV_INFO(dev, "MDP5 version v%d.%d", *major, *minor); 567 } 568 569 static int get_clk(struct platform_device *pdev, struct clk **clkp, 570 const char *name, bool mandatory) 571 { 572 struct device *dev = &pdev->dev; 573 struct clk *clk = msm_clk_get(pdev, name); 574 if (IS_ERR(clk) && mandatory) { 575 DRM_DEV_ERROR(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); 576 return PTR_ERR(clk); 577 } 578 if (IS_ERR(clk)) 579 DBG("skipping %s", name); 580 else 581 *clkp = clk; 582 583 return 0; 584 } 585 586 struct msm_kms *mdp5_kms_init(struct drm_device *dev) 587 { 588 struct msm_drm_private *priv = dev->dev_private; 589 struct platform_device *pdev; 590 struct mdp5_kms *mdp5_kms; 591 struct mdp5_cfg *config; 592 struct msm_kms *kms; 593 struct msm_gem_address_space *aspace; 594 int irq, i, ret; 595 struct device *iommu_dev; 596 597 /* priv->kms would have been populated by the MDP5 driver */ 598 kms = priv->kms; 599 if (!kms) 600 return NULL; 601 602 mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); 603 604 mdp_kms_init(&mdp5_kms->base, &kms_funcs); 605 606 pdev = mdp5_kms->pdev; 607 608 irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 609 if (irq < 0) { 610 ret = irq; 611 DRM_DEV_ERROR(&pdev->dev, "failed to get irq: %d\n", ret); 612 goto fail; 613 } 614 615 kms->irq = irq; 616 617 config = mdp5_cfg_get_config(mdp5_kms->cfg); 618 619 /* make sure things are off before attaching iommu (bootloader could 620 * have left things on, in which case we'll start getting faults if 621 * we don't disable): 622 */ 623 pm_runtime_get_sync(&pdev->dev); 624 for (i = 0; i < MDP5_INTF_NUM_MAX; i++) { 625 if (mdp5_cfg_intf_is_virtual(config->hw->intf.connect[i]) || 626 !config->hw->intf.base[i]) 627 continue; 628 mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0); 629 630 mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(i), 0x3); 631 } 632 mdelay(16); 633 634 if (config->platform.iommu) { 635 iommu_dev = &pdev->dev; 636 if (!dev_iommu_fwspec_get(iommu_dev)) 637 iommu_dev = iommu_dev->parent; 638 639 aspace = msm_gem_address_space_create(iommu_dev, 640 config->platform.iommu, "mdp5"); 641 if (IS_ERR(aspace)) { 642 ret = PTR_ERR(aspace); 643 goto fail; 644 } 645 646 kms->aspace = aspace; 647 648 ret = aspace->mmu->funcs->attach(aspace->mmu); 649 if (ret) { 650 DRM_DEV_ERROR(&pdev->dev, "failed to attach iommu: %d\n", 651 ret); 652 goto fail; 653 } 654 } else { 655 DRM_DEV_INFO(&pdev->dev, 656 "no iommu, fallback to phys contig buffers for scanout\n"); 657 aspace = NULL; 658 } 659 660 pm_runtime_put_sync(&pdev->dev); 661 662 ret = modeset_init(mdp5_kms); 663 if (ret) { 664 DRM_DEV_ERROR(&pdev->dev, "modeset_init failed: %d\n", ret); 665 goto fail; 666 } 667 668 dev->mode_config.min_width = 0; 669 dev->mode_config.min_height = 0; 670 dev->mode_config.max_width = 0xffff; 671 dev->mode_config.max_height = 0xffff; 672 673 dev->max_vblank_count = 0; /* max_vblank_count is set on each CRTC */ 674 dev->vblank_disable_immediate = true; 675 676 return kms; 677 fail: 678 if (kms) 679 mdp5_kms_destroy(kms); 680 return ERR_PTR(ret); 681 } 682 683 static void mdp5_destroy(struct platform_device *pdev) 684 { 685 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); 686 int i; 687 688 if (mdp5_kms->ctlm) 689 mdp5_ctlm_destroy(mdp5_kms->ctlm); 690 if (mdp5_kms->smp) 691 mdp5_smp_destroy(mdp5_kms->smp); 692 if (mdp5_kms->cfg) 693 mdp5_cfg_destroy(mdp5_kms->cfg); 694 695 for (i = 0; i < mdp5_kms->num_intfs; i++) 696 kfree(mdp5_kms->intfs[i]); 697 698 if (mdp5_kms->rpm_enabled) 699 pm_runtime_disable(&pdev->dev); 700 701 drm_atomic_private_obj_fini(&mdp5_kms->glob_state); 702 drm_modeset_lock_fini(&mdp5_kms->glob_state_lock); 703 } 704 705 static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt, 706 const enum mdp5_pipe *pipes, const uint32_t *offsets, 707 uint32_t caps) 708 { 709 struct drm_device *dev = mdp5_kms->dev; 710 int i, ret; 711 712 for (i = 0; i < cnt; i++) { 713 struct mdp5_hw_pipe *hwpipe; 714 715 hwpipe = mdp5_pipe_init(pipes[i], offsets[i], caps); 716 if (IS_ERR(hwpipe)) { 717 ret = PTR_ERR(hwpipe); 718 DRM_DEV_ERROR(dev->dev, "failed to construct pipe for %s (%d)\n", 719 pipe2name(pipes[i]), ret); 720 return ret; 721 } 722 hwpipe->idx = mdp5_kms->num_hwpipes; 723 mdp5_kms->hwpipes[mdp5_kms->num_hwpipes++] = hwpipe; 724 } 725 726 return 0; 727 } 728 729 static int hwpipe_init(struct mdp5_kms *mdp5_kms) 730 { 731 static const enum mdp5_pipe rgb_planes[] = { 732 SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3, 733 }; 734 static const enum mdp5_pipe vig_planes[] = { 735 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, 736 }; 737 static const enum mdp5_pipe dma_planes[] = { 738 SSPP_DMA0, SSPP_DMA1, 739 }; 740 static const enum mdp5_pipe cursor_planes[] = { 741 SSPP_CURSOR0, SSPP_CURSOR1, 742 }; 743 const struct mdp5_cfg_hw *hw_cfg; 744 int ret; 745 746 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 747 748 /* Construct RGB pipes: */ 749 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_rgb.count, rgb_planes, 750 hw_cfg->pipe_rgb.base, hw_cfg->pipe_rgb.caps); 751 if (ret) 752 return ret; 753 754 /* Construct video (VIG) pipes: */ 755 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes, 756 hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps); 757 if (ret) 758 return ret; 759 760 /* Construct DMA pipes: */ 761 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_dma.count, dma_planes, 762 hw_cfg->pipe_dma.base, hw_cfg->pipe_dma.caps); 763 if (ret) 764 return ret; 765 766 /* Construct cursor pipes: */ 767 ret = construct_pipes(mdp5_kms, hw_cfg->pipe_cursor.count, 768 cursor_planes, hw_cfg->pipe_cursor.base, 769 hw_cfg->pipe_cursor.caps); 770 if (ret) 771 return ret; 772 773 return 0; 774 } 775 776 static int hwmixer_init(struct mdp5_kms *mdp5_kms) 777 { 778 struct drm_device *dev = mdp5_kms->dev; 779 const struct mdp5_cfg_hw *hw_cfg; 780 int i, ret; 781 782 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 783 784 for (i = 0; i < hw_cfg->lm.count; i++) { 785 struct mdp5_hw_mixer *mixer; 786 787 mixer = mdp5_mixer_init(&hw_cfg->lm.instances[i]); 788 if (IS_ERR(mixer)) { 789 ret = PTR_ERR(mixer); 790 DRM_DEV_ERROR(dev->dev, "failed to construct LM%d (%d)\n", 791 i, ret); 792 return ret; 793 } 794 795 mixer->idx = mdp5_kms->num_hwmixers; 796 mdp5_kms->hwmixers[mdp5_kms->num_hwmixers++] = mixer; 797 } 798 799 return 0; 800 } 801 802 static int interface_init(struct mdp5_kms *mdp5_kms) 803 { 804 struct drm_device *dev = mdp5_kms->dev; 805 const struct mdp5_cfg_hw *hw_cfg; 806 const enum mdp5_intf_type *intf_types; 807 int i; 808 809 hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); 810 intf_types = hw_cfg->intf.connect; 811 812 for (i = 0; i < ARRAY_SIZE(hw_cfg->intf.connect); i++) { 813 struct mdp5_interface *intf; 814 815 if (intf_types[i] == INTF_DISABLED) 816 continue; 817 818 intf = kzalloc(sizeof(*intf), GFP_KERNEL); 819 if (!intf) { 820 DRM_DEV_ERROR(dev->dev, "failed to construct INTF%d\n", i); 821 return -ENOMEM; 822 } 823 824 intf->num = i; 825 intf->type = intf_types[i]; 826 intf->mode = MDP5_INTF_MODE_NONE; 827 intf->idx = mdp5_kms->num_intfs; 828 mdp5_kms->intfs[mdp5_kms->num_intfs++] = intf; 829 } 830 831 return 0; 832 } 833 834 static int mdp5_init(struct platform_device *pdev, struct drm_device *dev) 835 { 836 struct msm_drm_private *priv = dev->dev_private; 837 struct mdp5_kms *mdp5_kms; 838 struct mdp5_cfg *config; 839 u32 major, minor; 840 int ret; 841 842 mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL); 843 if (!mdp5_kms) { 844 ret = -ENOMEM; 845 goto fail; 846 } 847 848 platform_set_drvdata(pdev, mdp5_kms); 849 850 spin_lock_init(&mdp5_kms->resource_lock); 851 852 mdp5_kms->dev = dev; 853 mdp5_kms->pdev = pdev; 854 855 ret = mdp5_global_obj_init(mdp5_kms); 856 if (ret) 857 goto fail; 858 859 mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5"); 860 if (IS_ERR(mdp5_kms->mmio)) { 861 ret = PTR_ERR(mdp5_kms->mmio); 862 goto fail; 863 } 864 865 /* mandatory clocks: */ 866 ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus", true); 867 if (ret) 868 goto fail; 869 ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface", true); 870 if (ret) 871 goto fail; 872 ret = get_clk(pdev, &mdp5_kms->core_clk, "core", true); 873 if (ret) 874 goto fail; 875 ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync", true); 876 if (ret) 877 goto fail; 878 879 /* optional clocks: */ 880 get_clk(pdev, &mdp5_kms->lut_clk, "lut", false); 881 get_clk(pdev, &mdp5_kms->tbu_clk, "tbu", false); 882 get_clk(pdev, &mdp5_kms->tbu_rt_clk, "tbu_rt", false); 883 884 /* we need to set a default rate before enabling. Set a safe 885 * rate first, then figure out hw revision, and then set a 886 * more optimal rate: 887 */ 888 clk_set_rate(mdp5_kms->core_clk, 200000000); 889 890 pm_runtime_enable(&pdev->dev); 891 mdp5_kms->rpm_enabled = true; 892 893 read_mdp_hw_revision(mdp5_kms, &major, &minor); 894 895 mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor); 896 if (IS_ERR(mdp5_kms->cfg)) { 897 ret = PTR_ERR(mdp5_kms->cfg); 898 mdp5_kms->cfg = NULL; 899 goto fail; 900 } 901 902 config = mdp5_cfg_get_config(mdp5_kms->cfg); 903 mdp5_kms->caps = config->hw->mdp.caps; 904 905 /* TODO: compute core clock rate at runtime */ 906 clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk); 907 908 /* 909 * Some chipsets have a Shared Memory Pool (SMP), while others 910 * have dedicated latency buffering per source pipe instead; 911 * this section initializes the SMP: 912 */ 913 if (mdp5_kms->caps & MDP_CAP_SMP) { 914 mdp5_kms->smp = mdp5_smp_init(mdp5_kms, &config->hw->smp); 915 if (IS_ERR(mdp5_kms->smp)) { 916 ret = PTR_ERR(mdp5_kms->smp); 917 mdp5_kms->smp = NULL; 918 goto fail; 919 } 920 } 921 922 mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg); 923 if (IS_ERR(mdp5_kms->ctlm)) { 924 ret = PTR_ERR(mdp5_kms->ctlm); 925 mdp5_kms->ctlm = NULL; 926 goto fail; 927 } 928 929 ret = hwpipe_init(mdp5_kms); 930 if (ret) 931 goto fail; 932 933 ret = hwmixer_init(mdp5_kms); 934 if (ret) 935 goto fail; 936 937 ret = interface_init(mdp5_kms); 938 if (ret) 939 goto fail; 940 941 /* set uninit-ed kms */ 942 priv->kms = &mdp5_kms->base.base; 943 944 return 0; 945 fail: 946 mdp5_destroy(pdev); 947 return ret; 948 } 949 950 static int mdp5_bind(struct device *dev, struct device *master, void *data) 951 { 952 struct drm_device *ddev = dev_get_drvdata(master); 953 struct platform_device *pdev = to_platform_device(dev); 954 955 DBG(""); 956 957 return mdp5_init(pdev, ddev); 958 } 959 960 static void mdp5_unbind(struct device *dev, struct device *master, 961 void *data) 962 { 963 struct platform_device *pdev = to_platform_device(dev); 964 965 mdp5_destroy(pdev); 966 } 967 968 static const struct component_ops mdp5_ops = { 969 .bind = mdp5_bind, 970 .unbind = mdp5_unbind, 971 }; 972 973 static int mdp5_setup_interconnect(struct platform_device *pdev) 974 { 975 struct icc_path *path0 = of_icc_get(&pdev->dev, "mdp0-mem"); 976 struct icc_path *path1 = of_icc_get(&pdev->dev, "mdp1-mem"); 977 struct icc_path *path_rot = of_icc_get(&pdev->dev, "rotator-mem"); 978 979 if (IS_ERR(path0)) 980 return PTR_ERR(path0); 981 982 if (!path0) { 983 /* no interconnect support is not necessarily a fatal 984 * condition, the platform may simply not have an 985 * interconnect driver yet. But warn about it in case 986 * bootloader didn't setup bus clocks high enough for 987 * scanout. 988 */ 989 dev_warn(&pdev->dev, "No interconnect support may cause display underflows!\n"); 990 return 0; 991 } 992 993 icc_set_bw(path0, 0, MBps_to_icc(6400)); 994 995 if (!IS_ERR_OR_NULL(path1)) 996 icc_set_bw(path1, 0, MBps_to_icc(6400)); 997 if (!IS_ERR_OR_NULL(path_rot)) 998 icc_set_bw(path_rot, 0, MBps_to_icc(6400)); 999 1000 return 0; 1001 } 1002 1003 static int mdp5_dev_probe(struct platform_device *pdev) 1004 { 1005 int ret; 1006 1007 DBG(""); 1008 1009 ret = mdp5_setup_interconnect(pdev); 1010 if (ret) 1011 return ret; 1012 1013 return component_add(&pdev->dev, &mdp5_ops); 1014 } 1015 1016 static int mdp5_dev_remove(struct platform_device *pdev) 1017 { 1018 DBG(""); 1019 component_del(&pdev->dev, &mdp5_ops); 1020 return 0; 1021 } 1022 1023 static __maybe_unused int mdp5_runtime_suspend(struct device *dev) 1024 { 1025 struct platform_device *pdev = to_platform_device(dev); 1026 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); 1027 1028 DBG(""); 1029 1030 return mdp5_disable(mdp5_kms); 1031 } 1032 1033 static __maybe_unused int mdp5_runtime_resume(struct device *dev) 1034 { 1035 struct platform_device *pdev = to_platform_device(dev); 1036 struct mdp5_kms *mdp5_kms = platform_get_drvdata(pdev); 1037 1038 DBG(""); 1039 1040 return mdp5_enable(mdp5_kms); 1041 } 1042 1043 static const struct dev_pm_ops mdp5_pm_ops = { 1044 SET_RUNTIME_PM_OPS(mdp5_runtime_suspend, mdp5_runtime_resume, NULL) 1045 }; 1046 1047 static const struct of_device_id mdp5_dt_match[] = { 1048 { .compatible = "qcom,mdp5", }, 1049 /* to support downstream DT files */ 1050 { .compatible = "qcom,mdss_mdp", }, 1051 {} 1052 }; 1053 MODULE_DEVICE_TABLE(of, mdp5_dt_match); 1054 1055 static struct platform_driver mdp5_driver = { 1056 .probe = mdp5_dev_probe, 1057 .remove = mdp5_dev_remove, 1058 .driver = { 1059 .name = "msm_mdp", 1060 .of_match_table = mdp5_dt_match, 1061 .pm = &mdp5_pm_ops, 1062 }, 1063 }; 1064 1065 void __init msm_mdp_register(void) 1066 { 1067 DBG(""); 1068 platform_driver_register(&mdp5_driver); 1069 } 1070 1071 void __exit msm_mdp_unregister(void) 1072 { 1073 DBG(""); 1074 platform_driver_unregister(&mdp5_driver); 1075 } 1076