1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas SDHI 4 * 5 * Copyright (C) 2015-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 8 * Copyright (C) 2009 Magnus Damm 9 * 10 * Based on "Compaq ASIC3 support": 11 * 12 * Copyright 2001 Compaq Computer Corporation. 13 * Copyright 2004-2005 Phil Blundell 14 * Copyright 2007-2008 OpenedHand Ltd. 15 * 16 * Authors: Phil Blundell <pb@handhelds.org>, 17 * Samuel Ortiz <sameo@openedhand.com> 18 * 19 */ 20 21 #include <linux/kernel.h> 22 #include <linux/clk.h> 23 #include <linux/slab.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_device.h> 27 #include <linux/mmc/host.h> 28 #include <linux/mmc/slot-gpio.h> 29 #include <linux/mfd/tmio.h> 30 #include <linux/sh_dma.h> 31 #include <linux/delay.h> 32 #include <linux/pinctrl/consumer.h> 33 #include <linux/pinctrl/pinctrl-state.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/sys_soc.h> 36 37 #include "renesas_sdhi.h" 38 #include "tmio_mmc.h" 39 40 #define HOST_MODE 0xe4 41 42 #define SDHI_VER_GEN2_SDR50 0x490c 43 #define SDHI_VER_RZ_A1 0x820b 44 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 45 #define SDHI_VER_GEN2_SDR104 0xcb0d 46 #define SDHI_VER_GEN3_SD 0xcc10 47 #define SDHI_VER_GEN3_SDMMC 0xcd10 48 49 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 50 { 51 u32 val; 52 53 /* 54 * see also 55 * renesas_sdhi_of_data :: dma_buswidth 56 */ 57 switch (sd_ctrl_read16(host, CTL_VERSION)) { 58 case SDHI_VER_GEN2_SDR50: 59 val = (width == 32) ? 0x0001 : 0x0000; 60 break; 61 case SDHI_VER_GEN2_SDR104: 62 val = (width == 32) ? 0x0000 : 0x0001; 63 break; 64 case SDHI_VER_GEN3_SD: 65 case SDHI_VER_GEN3_SDMMC: 66 if (width == 64) 67 val = 0x0000; 68 else if (width == 32) 69 val = 0x0101; 70 else 71 val = 0x0001; 72 break; 73 default: 74 /* nothing to do */ 75 return; 76 } 77 78 sd_ctrl_write16(host, HOST_MODE, val); 79 } 80 81 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 82 { 83 struct mmc_host *mmc = host->mmc; 84 struct renesas_sdhi *priv = host_to_priv(host); 85 int ret = clk_prepare_enable(priv->clk); 86 87 if (ret < 0) 88 return ret; 89 90 ret = clk_prepare_enable(priv->clk_cd); 91 if (ret < 0) { 92 clk_disable_unprepare(priv->clk); 93 return ret; 94 } 95 96 /* 97 * The clock driver may not know what maximum frequency 98 * actually works, so it should be set with the max-frequency 99 * property which will already have been read to f_max. If it 100 * was missing, assume the current frequency is the maximum. 101 */ 102 if (!mmc->f_max) 103 mmc->f_max = clk_get_rate(priv->clk); 104 105 /* 106 * Minimum frequency is the minimum input clock frequency 107 * divided by our maximum divider. 108 */ 109 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 110 111 /* enable 16bit data access on SDBUF as default */ 112 renesas_sdhi_sdbuf_width(host, 16); 113 114 return 0; 115 } 116 117 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 118 unsigned int new_clock) 119 { 120 struct renesas_sdhi *priv = host_to_priv(host); 121 unsigned int freq, diff, best_freq = 0, diff_min = ~0; 122 int i; 123 124 /* tested only on R-Car Gen2+ currently; may work for others */ 125 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 126 return clk_get_rate(priv->clk); 127 128 /* 129 * We want the bus clock to be as close as possible to, but no 130 * greater than, new_clock. As we can divide by 1 << i for 131 * any i in [0, 9] we want the input clock to be as close as 132 * possible, but no greater than, new_clock << i. 133 */ 134 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 135 freq = clk_round_rate(priv->clk, new_clock << i); 136 if (freq > (new_clock << i)) { 137 /* Too fast; look for a slightly slower option */ 138 freq = clk_round_rate(priv->clk, 139 (new_clock << i) / 4 * 3); 140 if (freq > (new_clock << i)) 141 continue; 142 } 143 144 diff = new_clock - (freq >> i); 145 if (diff <= diff_min) { 146 best_freq = freq; 147 diff_min = diff; 148 } 149 } 150 151 clk_set_rate(priv->clk, best_freq); 152 153 return clk_get_rate(priv->clk); 154 } 155 156 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 157 unsigned int new_clock) 158 { 159 u32 clk = 0, clock; 160 161 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 162 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 163 164 if (new_clock == 0) { 165 host->mmc->actual_clock = 0; 166 goto out; 167 } 168 169 host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock); 170 clock = host->mmc->actual_clock / 512; 171 172 for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) 173 clock <<= 1; 174 175 /* 1/1 clock is option */ 176 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { 177 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) 178 clk |= 0xff; 179 else 180 clk &= ~0xff; 181 } 182 183 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); 184 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 185 usleep_range(10000, 11000); 186 187 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 188 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 189 190 out: 191 /* HW engineers overrode docs: no sleep needed on R-Car2+ */ 192 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 193 usleep_range(10000, 11000); 194 } 195 196 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 197 { 198 struct renesas_sdhi *priv = host_to_priv(host); 199 200 clk_disable_unprepare(priv->clk); 201 clk_disable_unprepare(priv->clk_cd); 202 } 203 204 static int renesas_sdhi_card_busy(struct mmc_host *mmc) 205 { 206 struct tmio_mmc_host *host = mmc_priv(mmc); 207 208 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 209 TMIO_STAT_DAT0); 210 } 211 212 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 213 struct mmc_ios *ios) 214 { 215 struct tmio_mmc_host *host = mmc_priv(mmc); 216 struct renesas_sdhi *priv = host_to_priv(host); 217 struct pinctrl_state *pin_state; 218 int ret; 219 220 switch (ios->signal_voltage) { 221 case MMC_SIGNAL_VOLTAGE_330: 222 pin_state = priv->pins_default; 223 break; 224 case MMC_SIGNAL_VOLTAGE_180: 225 pin_state = priv->pins_uhs; 226 break; 227 default: 228 return -EINVAL; 229 } 230 231 /* 232 * If anything is missing, assume signal voltage is fixed at 233 * 3.3V and succeed/fail accordingly. 234 */ 235 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 236 return ios->signal_voltage == 237 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 238 239 ret = mmc_regulator_set_vqmmc(host->mmc, ios); 240 if (ret) 241 return ret; 242 243 return pinctrl_select_state(priv->pinctrl, pin_state); 244 } 245 246 /* SCC registers */ 247 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 248 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 249 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 250 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 251 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 252 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 253 #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C 254 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 255 256 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 257 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 258 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 259 260 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 261 262 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 263 264 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) 265 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) 266 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 267 268 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) 269 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) 270 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) 271 272 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 273 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 274 275 static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 276 struct renesas_sdhi *priv, int addr) 277 { 278 return readl(priv->scc_ctl + (addr << host->bus_shift)); 279 } 280 281 static inline void sd_scc_write32(struct tmio_mmc_host *host, 282 struct renesas_sdhi *priv, 283 int addr, u32 val) 284 { 285 writel(val, priv->scc_ctl + (addr << host->bus_shift)); 286 } 287 288 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 289 { 290 struct renesas_sdhi *priv; 291 292 priv = host_to_priv(host); 293 294 /* Initialize SCC */ 295 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 296 297 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 298 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 299 300 /* set sampling clock selection range */ 301 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 302 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 303 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 304 305 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 306 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 307 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 308 309 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 310 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 311 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 312 313 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 314 315 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 316 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 317 318 /* Read TAPNUM */ 319 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 320 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 321 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 322 } 323 324 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc) 325 { 326 struct tmio_mmc_host *host = mmc_priv(mmc); 327 struct renesas_sdhi *priv = host_to_priv(host); 328 329 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 330 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 331 332 /* Set HS400 mode */ 333 sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 | 334 sd_ctrl_read16(host, CTL_SDIF_MODE)); 335 336 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, 337 priv->scc_tappos_hs400); 338 339 /* Gen3 can't do automatic tap correction with HS400, so disable it */ 340 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC) 341 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 342 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 343 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 344 345 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 346 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 347 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 348 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 349 350 /* Set the sampling clock selection range of HS400 mode */ 351 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 352 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 353 0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 354 355 356 if (priv->quirks && priv->quirks->hs400_4taps) 357 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 358 priv->tap_set / 2); 359 360 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 361 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 362 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 363 364 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 365 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 366 } 367 368 static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host, 369 struct renesas_sdhi *priv) 370 { 371 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 372 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 373 374 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 375 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 376 sd_scc_read32(host, priv, 377 SH_MOBILE_SDHI_SCC_CKSEL)); 378 } 379 380 static void renesas_sdhi_disable_scc(struct mmc_host *mmc) 381 { 382 struct tmio_mmc_host *host = mmc_priv(mmc); 383 struct renesas_sdhi *priv = host_to_priv(host); 384 385 renesas_sdhi_reset_scc(host, priv); 386 387 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 388 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 389 sd_scc_read32(host, priv, 390 SH_MOBILE_SDHI_SCC_DTCNTL)); 391 392 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 393 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 394 } 395 396 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 397 struct renesas_sdhi *priv) 398 { 399 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 400 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 401 402 /* Reset HS400 mode */ 403 sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 & 404 sd_ctrl_read16(host, CTL_SDIF_MODE)); 405 406 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 407 408 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 409 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 410 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 411 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 412 413 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 414 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 415 } 416 417 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 418 { 419 struct tmio_mmc_host *host = mmc_priv(mmc); 420 421 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 422 return 0; 423 } 424 425 #define SH_MOBILE_SDHI_MAX_TAP 3 426 427 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 428 { 429 struct renesas_sdhi *priv = host_to_priv(host); 430 unsigned long tap_cnt; /* counter of tuning success */ 431 unsigned long tap_start;/* start position of tuning success */ 432 unsigned long tap_end; /* end position of tuning success */ 433 unsigned long ntap; /* temporary counter of tuning success */ 434 unsigned long i; 435 436 priv->doing_tune = false; 437 438 /* Clear SCC_RVSREQ */ 439 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 440 441 /* 442 * When tuning CMD19 is issued twice for each tap, merge the 443 * result requiring the tap to be good in both runs before 444 * considering it for tuning selection. 445 */ 446 for (i = 0; i < priv->tap_num * 2; i++) { 447 int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1); 448 449 if (!test_bit(i, priv->taps)) 450 clear_bit(i + offset, priv->taps); 451 } 452 453 /* 454 * Find the longest consecutive run of successful probes. If that 455 * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the 456 * center index as the tap. 457 */ 458 tap_cnt = 0; 459 ntap = 0; 460 tap_start = 0; 461 tap_end = 0; 462 for (i = 0; i < priv->tap_num * 2; i++) { 463 if (test_bit(i, priv->taps)) { 464 ntap++; 465 } else { 466 if (ntap > tap_cnt) { 467 tap_start = i - ntap; 468 tap_end = i - 1; 469 tap_cnt = ntap; 470 } 471 ntap = 0; 472 } 473 } 474 475 if (ntap > tap_cnt) { 476 tap_start = i - ntap; 477 tap_end = i - 1; 478 tap_cnt = ntap; 479 } 480 481 if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP) 482 priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num; 483 else 484 return -EIO; 485 486 /* Set SCC */ 487 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set); 488 489 /* Enable auto re-tuning */ 490 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 491 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | 492 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 493 494 return 0; 495 } 496 497 static int renesas_sdhi_execute_tuning(struct tmio_mmc_host *host, u32 opcode) 498 { 499 struct renesas_sdhi *priv = host_to_priv(host); 500 int i; 501 502 priv->tap_num = renesas_sdhi_init_tuning(host); 503 if (!priv->tap_num) 504 return 0; /* Tuning is not supported */ 505 506 if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) { 507 dev_err(&host->pdev->dev, 508 "Too many taps, please update 'taps' in tmio_mmc_host!\n"); 509 return -EINVAL; 510 } 511 512 priv->doing_tune = true; 513 bitmap_zero(priv->taps, priv->tap_num * 2); 514 515 /* Issue CMD19 twice for each tap */ 516 for (i = 0; i < 2 * priv->tap_num; i++) { 517 /* Set sampling clock position */ 518 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num); 519 520 if (mmc_send_tuning(host->mmc, opcode, NULL) == 0) 521 set_bit(i, priv->taps); 522 } 523 524 return renesas_sdhi_select_tuning(host); 525 } 526 527 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap) 528 { 529 struct renesas_sdhi *priv = host_to_priv(host); 530 unsigned long new_tap = priv->tap_set; 531 u32 val; 532 533 val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ); 534 if (!val) 535 return false; 536 537 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 538 539 /* Change TAP position according to correction status */ 540 if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC && 541 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 542 /* 543 * With HS400, the DAT signal is based on DS, not CLK. 544 * Therefore, use only CMD status. 545 */ 546 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) & 547 SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR; 548 if (!smpcmp) 549 return false; /* no error in CMD signal */ 550 else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) 551 new_tap++; 552 else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) 553 new_tap--; 554 else 555 return true; /* need retune */ 556 } else { 557 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) 558 return true; /* need retune */ 559 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP) 560 new_tap++; 561 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN) 562 new_tap--; 563 else 564 return false; 565 } 566 567 priv->tap_set = (new_tap % priv->tap_num); 568 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 569 priv->tap_set / (use_4tap ? 2 : 1)); 570 571 return false; 572 } 573 574 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host) 575 { 576 struct renesas_sdhi *priv = host_to_priv(host); 577 578 /* Check SCC error */ 579 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 580 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 581 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 582 return true; 583 } 584 585 return false; 586 } 587 588 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host) 589 { 590 struct renesas_sdhi *priv = host_to_priv(host); 591 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 592 593 /* 594 * Skip checking SCC errors when running on 4 taps in HS400 mode as 595 * any retuning would still result in the same 4 taps being used. 596 */ 597 if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && 598 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && 599 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) 600 return false; 601 602 if (mmc_doing_retune(host->mmc) || priv->doing_tune) 603 return false; 604 605 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 606 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) 607 return renesas_sdhi_auto_correction(host); 608 609 return renesas_sdhi_manual_correction(host, use_4tap); 610 } 611 612 static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host) 613 { 614 struct renesas_sdhi *priv; 615 616 priv = host_to_priv(host); 617 618 renesas_sdhi_reset_scc(host, priv); 619 renesas_sdhi_reset_hs400_mode(host, priv); 620 621 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 622 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 623 624 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 625 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 626 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 627 628 if (host->pdata->flags & TMIO_MMC_MIN_RCAR2) 629 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, 630 TMIO_MASK_INIT_RCAR2); 631 } 632 633 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 634 { 635 int timeout = 1000; 636 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 637 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 638 639 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 640 & bit) == wait_state) 641 udelay(1); 642 643 if (!timeout) { 644 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 645 return -EBUSY; 646 } 647 648 return 0; 649 } 650 651 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 652 { 653 u32 bit = TMIO_STAT_SCLKDIVEN; 654 655 switch (addr) { 656 case CTL_SD_CMD: 657 case CTL_STOP_INTERNAL_ACTION: 658 case CTL_XFER_BLK_COUNT: 659 case CTL_SD_XFER_LEN: 660 case CTL_SD_MEM_CARD_OPT: 661 case CTL_TRANSACTION_CTL: 662 case CTL_DMA_ENABLE: 663 case HOST_MODE: 664 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 665 bit = TMIO_STAT_CMD_BUSY; 666 /* fallthrough */ 667 case CTL_SD_CARD_CLK_CTL: 668 return renesas_sdhi_wait_idle(host, bit); 669 } 670 671 return 0; 672 } 673 674 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 675 unsigned int direction, int blk_size) 676 { 677 /* 678 * In Renesas controllers, when performing a 679 * multiple block read of one or two blocks, 680 * depending on the timing with which the 681 * response register is read, the response 682 * value may not be read properly. 683 * Use single block read for this HW bug 684 */ 685 if ((direction == MMC_DATA_READ) && 686 blk_size == 2) 687 return 1; 688 689 return blk_size; 690 } 691 692 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 693 { 694 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 695 int width = (host->bus_shift == 2) ? 64 : 32; 696 697 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 698 renesas_sdhi_sdbuf_width(host, enable ? width : 16); 699 } 700 701 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = { 702 .hs400_disabled = true, 703 .hs400_4taps = true, 704 }; 705 706 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = { 707 .hs400_4taps = true, 708 }; 709 710 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = { 711 .hs400_disabled = true, 712 }; 713 714 static const struct soc_device_attribute sdhi_quirks_match[] = { 715 { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 716 { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 }, 717 { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap }, 718 { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 719 { .soc_id = "r8a77980", .data = &sdhi_quirks_nohs400 }, 720 { /* Sentinel. */ }, 721 }; 722 723 int renesas_sdhi_probe(struct platform_device *pdev, 724 const struct tmio_mmc_dma_ops *dma_ops) 725 { 726 struct tmio_mmc_data *mmd = pdev->dev.platform_data; 727 const struct renesas_sdhi_quirks *quirks = NULL; 728 const struct renesas_sdhi_of_data *of_data; 729 const struct soc_device_attribute *attr; 730 struct tmio_mmc_data *mmc_data; 731 struct tmio_mmc_dma *dma_priv; 732 struct tmio_mmc_host *host; 733 struct renesas_sdhi *priv; 734 int num_irqs, irq, ret, i; 735 struct resource *res; 736 u16 ver; 737 738 of_data = of_device_get_match_data(&pdev->dev); 739 740 attr = soc_device_match(sdhi_quirks_match); 741 if (attr) 742 quirks = attr->data; 743 744 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 745 if (!res) 746 return -EINVAL; 747 748 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 749 GFP_KERNEL); 750 if (!priv) 751 return -ENOMEM; 752 753 priv->quirks = quirks; 754 mmc_data = &priv->mmc_data; 755 dma_priv = &priv->dma_priv; 756 757 priv->clk = devm_clk_get(&pdev->dev, NULL); 758 if (IS_ERR(priv->clk)) { 759 ret = PTR_ERR(priv->clk); 760 dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 761 return ret; 762 } 763 764 /* 765 * Some controllers provide a 2nd clock just to run the internal card 766 * detection logic. Unfortunately, the existing driver architecture does 767 * not support a separation of clocks for runtime PM usage. When 768 * native hotplug is used, the tmio driver assumes that the core 769 * must continue to run for card detect to stay active, so we cannot 770 * disable it. 771 * Additionally, it is prohibited to supply a clock to the core but not 772 * to the card detect circuit. That leaves us with if separate clocks 773 * are presented, we must treat them both as virtually 1 clock. 774 */ 775 priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); 776 if (IS_ERR(priv->clk_cd)) 777 priv->clk_cd = NULL; 778 779 priv->pinctrl = devm_pinctrl_get(&pdev->dev); 780 if (!IS_ERR(priv->pinctrl)) { 781 priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 782 PINCTRL_STATE_DEFAULT); 783 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 784 "state_uhs"); 785 } 786 787 host = tmio_mmc_host_alloc(pdev, mmc_data); 788 if (IS_ERR(host)) 789 return PTR_ERR(host); 790 791 if (of_data) { 792 mmc_data->flags |= of_data->tmio_flags; 793 mmc_data->ocr_mask = of_data->tmio_ocr_mask; 794 mmc_data->capabilities |= of_data->capabilities; 795 mmc_data->capabilities2 |= of_data->capabilities2; 796 mmc_data->dma_rx_offset = of_data->dma_rx_offset; 797 mmc_data->max_blk_count = of_data->max_blk_count; 798 mmc_data->max_segs = of_data->max_segs; 799 dma_priv->dma_buswidth = of_data->dma_buswidth; 800 host->bus_shift = of_data->bus_shift; 801 } 802 803 host->write16_hook = renesas_sdhi_write16_hook; 804 host->clk_enable = renesas_sdhi_clk_enable; 805 host->clk_disable = renesas_sdhi_clk_disable; 806 host->set_clock = renesas_sdhi_set_clock; 807 host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 808 host->dma_ops = dma_ops; 809 810 if (quirks && quirks->hs400_disabled) 811 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 812 813 /* For some SoC, we disable internal WP. GPIO may override this */ 814 if (mmc_can_gpio_ro(host->mmc)) 815 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 816 817 /* SDR speeds are only available on Gen2+ */ 818 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 819 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 820 host->ops.card_busy = renesas_sdhi_card_busy; 821 host->ops.start_signal_voltage_switch = 822 renesas_sdhi_start_signal_voltage_switch; 823 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; 824 825 /* SDR and HS200/400 registers requires HW reset */ 826 if (of_data && of_data->scc_offset) { 827 priv->scc_ctl = host->ctl + of_data->scc_offset; 828 host->mmc->caps |= MMC_CAP_HW_RESET; 829 host->hw_reset = renesas_sdhi_hw_reset; 830 } 831 } 832 833 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 834 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 835 host->bus_shift = 1; 836 837 if (mmd) 838 *mmc_data = *mmd; 839 840 dma_priv->filter = shdma_chan_filter; 841 dma_priv->enable = renesas_sdhi_enable_dma; 842 843 mmc_data->alignment_shift = 1; /* 2-byte alignment */ 844 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 845 846 /* 847 * All SDHI blocks support 2-byte and larger block sizes in 4-bit 848 * bus width mode. 849 */ 850 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 851 852 /* 853 * All SDHI blocks support SDIO IRQ signalling. 854 */ 855 mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 856 857 /* All SDHI have CMD12 control bit */ 858 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 859 860 /* All SDHI have SDIO status bits which must be 1 */ 861 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 862 863 ret = renesas_sdhi_clk_enable(host); 864 if (ret) 865 goto efree; 866 867 ver = sd_ctrl_read16(host, CTL_VERSION); 868 /* GEN2_SDR104 is first known SDHI to use 32bit block count */ 869 if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) 870 mmc_data->max_blk_count = U16_MAX; 871 872 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 873 if (ver == SDHI_VER_GEN2_SDR50) 874 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 875 876 ret = tmio_mmc_host_probe(host); 877 if (ret < 0) 878 goto edisclk; 879 880 /* Enable tuning iff we have an SCC and a supported mode */ 881 if (of_data && of_data->scc_offset && 882 (host->mmc->caps & MMC_CAP_UHS_SDR104 || 883 host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | 884 MMC_CAP2_HS400_1_8V))) { 885 const struct renesas_sdhi_scc *taps = of_data->taps; 886 bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; 887 bool hit = false; 888 889 for (i = 0; i < of_data->taps_num; i++) { 890 if (taps[i].clk_rate == 0 || 891 taps[i].clk_rate == host->mmc->f_max) { 892 priv->scc_tappos = taps->tap; 893 priv->scc_tappos_hs400 = use_4tap ? 894 taps->tap_hs400_4tap : 895 taps->tap; 896 hit = true; 897 break; 898 } 899 } 900 901 if (!hit) 902 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); 903 904 host->execute_tuning = renesas_sdhi_execute_tuning; 905 host->check_retune = renesas_sdhi_check_scc_error; 906 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning; 907 host->ops.hs400_downgrade = renesas_sdhi_disable_scc; 908 host->ops.hs400_complete = renesas_sdhi_hs400_complete; 909 } 910 911 num_irqs = platform_irq_count(pdev); 912 if (num_irqs < 0) { 913 ret = num_irqs; 914 goto eirq; 915 } 916 917 /* There must be at least one IRQ source */ 918 if (!num_irqs) { 919 ret = -ENXIO; 920 goto eirq; 921 } 922 923 for (i = 0; i < num_irqs; i++) { 924 irq = platform_get_irq(pdev, i); 925 if (irq < 0) { 926 ret = irq; 927 goto eirq; 928 } 929 930 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 931 dev_name(&pdev->dev), host); 932 if (ret) 933 goto eirq; 934 } 935 936 dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n", 937 mmc_hostname(host->mmc), (unsigned long) 938 (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start), 939 host->mmc->f_max / 1000000); 940 941 return ret; 942 943 eirq: 944 tmio_mmc_host_remove(host); 945 edisclk: 946 renesas_sdhi_clk_disable(host); 947 efree: 948 tmio_mmc_host_free(host); 949 950 return ret; 951 } 952 EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 953 954 int renesas_sdhi_remove(struct platform_device *pdev) 955 { 956 struct tmio_mmc_host *host = platform_get_drvdata(pdev); 957 958 tmio_mmc_host_remove(host); 959 renesas_sdhi_clk_disable(host); 960 961 return 0; 962 } 963 EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 964 965 MODULE_LICENSE("GPL v2"); 966