1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _M68K_PGTABLE_H 3 #define _M68K_PGTABLE_H 4 5 6 #if defined(CONFIG_SUN3) || defined(CONFIG_COLDFIRE) 7 #include <asm-generic/pgtable-nopmd.h> 8 #else 9 #include <asm-generic/pgtable-nopud.h> 10 #endif 11 12 #include <asm/setup.h> 13 14 #ifndef __ASSEMBLY__ 15 #include <asm/processor.h> 16 #include <linux/sched.h> 17 #include <linux/threads.h> 18 19 /* 20 * This file contains the functions and defines necessary to modify and use 21 * the m68k page table tree. 22 */ 23 24 #include <asm/virtconvert.h> 25 26 /* Certain architectures need to do special things when pte's 27 * within a page table are directly modified. Thus, the following 28 * hook is made available. 29 */ 30 #define set_pte(pteptr, pteval) \ 31 do{ \ 32 *(pteptr) = (pteval); \ 33 } while(0) 34 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) 35 36 37 /* PMD_SHIFT determines the size of the area a second-level page table can map */ 38 #if CONFIG_PGTABLE_LEVELS == 3 39 #define PMD_SHIFT 18 40 #endif 41 #define PMD_SIZE (1UL << PMD_SHIFT) 42 #define PMD_MASK (~(PMD_SIZE-1)) 43 44 /* PGDIR_SHIFT determines what a third-level page table entry can map */ 45 #ifdef CONFIG_SUN3 46 #define PGDIR_SHIFT 17 47 #elif defined(CONFIG_COLDFIRE) 48 #define PGDIR_SHIFT 22 49 #else 50 #define PGDIR_SHIFT 25 51 #endif 52 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 53 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 54 55 /* 56 * entries per page directory level: the m68k is configured as three-level, 57 * so we do have PMD level physically. 58 */ 59 #ifdef CONFIG_SUN3 60 #define PTRS_PER_PTE 16 61 #define __PAGETABLE_PMD_FOLDED 1 62 #define PTRS_PER_PMD 1 63 #define PTRS_PER_PGD 2048 64 #elif defined(CONFIG_COLDFIRE) 65 #define PTRS_PER_PTE 512 66 #define __PAGETABLE_PMD_FOLDED 1 67 #define PTRS_PER_PMD 1 68 #define PTRS_PER_PGD 1024 69 #else 70 #define PTRS_PER_PTE 64 71 #define PTRS_PER_PMD 128 72 #define PTRS_PER_PGD 128 73 #endif 74 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) 75 #define FIRST_USER_ADDRESS 0UL 76 77 /* Virtual address region for use by kernel_map() */ 78 #ifdef CONFIG_SUN3 79 #define KMAP_START 0x0dc00000 80 #define KMAP_END 0x0e000000 81 #elif defined(CONFIG_COLDFIRE) 82 #define KMAP_START 0xe0000000 83 #define KMAP_END 0xf0000000 84 #else 85 #define KMAP_START 0xd0000000 86 #define KMAP_END 0xf0000000 87 #endif 88 89 #ifdef CONFIG_SUN3 90 extern unsigned long m68k_vmalloc_end; 91 #define VMALLOC_START 0x0f800000 92 #define VMALLOC_END m68k_vmalloc_end 93 #elif defined(CONFIG_COLDFIRE) 94 #define VMALLOC_START 0xd0000000 95 #define VMALLOC_END 0xe0000000 96 #else 97 /* Just any arbitrary offset to the start of the vmalloc VM area: the 98 * current 8MB value just means that there will be a 8MB "hole" after the 99 * physical memory until the kernel virtual memory starts. That means that 100 * any out-of-bounds memory accesses will hopefully be caught. 101 * The vmalloc() routines leaves a hole of 4kB between each vmalloced 102 * area for the same reason. ;) 103 */ 104 #define VMALLOC_OFFSET (8*1024*1024) 105 #define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) 106 #define VMALLOC_END KMAP_START 107 #endif 108 109 /* zero page used for uninitialized stuff */ 110 extern void *empty_zero_page; 111 112 /* 113 * ZERO_PAGE is a global shared page that is always zero: used 114 * for zero-mapped memory areas etc.. 115 */ 116 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 117 118 /* number of bits that fit into a memory pointer */ 119 #define BITS_PER_PTR (8*sizeof(unsigned long)) 120 121 /* to align the pointer to a pointer address */ 122 #define PTR_MASK (~(sizeof(void*)-1)) 123 124 /* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */ 125 /* 64-bit machines, beware! SRB. */ 126 #define SIZEOF_PTR_LOG2 2 127 128 extern void kernel_set_cachemode(void *addr, unsigned long size, int cmode); 129 130 /* 131 * The m68k doesn't have any external MMU info: the kernel page 132 * tables contain all the necessary information. The Sun3 does, but 133 * they are updated on demand. 134 */ 135 static inline void update_mmu_cache(struct vm_area_struct *vma, 136 unsigned long address, pte_t *ptep) 137 { 138 } 139 140 #endif /* !__ASSEMBLY__ */ 141 142 #define kern_addr_valid(addr) (1) 143 144 /* MMU-specific headers */ 145 146 #ifdef CONFIG_SUN3 147 #include <asm/sun3_pgtable.h> 148 #elif defined(CONFIG_COLDFIRE) 149 #include <asm/mcf_pgtable.h> 150 #else 151 #include <asm/motorola_pgtable.h> 152 #endif 153 154 #ifndef __ASSEMBLY__ 155 /* 156 * Macro to mark a page protection value as "uncacheable". 157 */ 158 #ifdef CONFIG_COLDFIRE 159 # define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | CF_PAGE_NOCACHE)) 160 #else 161 #ifdef SUN3_PAGE_NOCACHE 162 # define __SUN3_PAGE_NOCACHE SUN3_PAGE_NOCACHE 163 #else 164 # define __SUN3_PAGE_NOCACHE 0 165 #endif 166 #define pgprot_noncached(prot) \ 167 (MMU_IS_SUN3 \ 168 ? (__pgprot(pgprot_val(prot) | __SUN3_PAGE_NOCACHE)) \ 169 : ((MMU_IS_851 || MMU_IS_030) \ 170 ? (__pgprot(pgprot_val(prot) | _PAGE_NOCACHE030)) \ 171 : (MMU_IS_040 || MMU_IS_060) \ 172 ? (__pgprot((pgprot_val(prot) & _CACHEMASK040) | _PAGE_NOCACHE_S)) \ 173 : (prot))) 174 175 pgprot_t pgprot_dmacoherent(pgprot_t prot); 176 #define pgprot_dmacoherent(prot) pgprot_dmacoherent(prot) 177 178 #endif /* CONFIG_COLDFIRE */ 179 #endif /* !__ASSEMBLY__ */ 180 181 #endif /* _M68K_PGTABLE_H */ 182