1 /* 2 * Copyright 2018 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "head.h" 23 #include "base.h" 24 #include "core.h" 25 #include "curs.h" 26 #include "ovly.h" 27 28 #include <nvif/class.h> 29 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_crtc_helper.h> 32 #include "nouveau_connector.h" 33 void 34 nv50_head_flush_clr(struct nv50_head *head, 35 struct nv50_head_atom *asyh, bool flush) 36 { 37 union nv50_head_atom_mask clr = { 38 .mask = asyh->clr.mask & ~(flush ? 0 : asyh->set.mask), 39 }; 40 if (clr.olut) head->func->olut_clr(head); 41 if (clr.core) head->func->core_clr(head); 42 if (clr.curs) head->func->curs_clr(head); 43 } 44 45 void 46 nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh) 47 { 48 if (asyh->set.view ) head->func->view (head, asyh); 49 if (asyh->set.mode ) head->func->mode (head, asyh); 50 if (asyh->set.core ) head->func->core_set(head, asyh); 51 if (asyh->set.olut ) { 52 asyh->olut.offset = nv50_lut_load(&head->olut, 53 asyh->olut.buffer, 54 asyh->state.gamma_lut, 55 asyh->olut.load); 56 head->func->olut_set(head, asyh); 57 } 58 if (asyh->set.curs ) head->func->curs_set(head, asyh); 59 if (asyh->set.base ) head->func->base (head, asyh); 60 if (asyh->set.ovly ) head->func->ovly (head, asyh); 61 if (asyh->set.dither ) head->func->dither (head, asyh); 62 if (asyh->set.procamp) head->func->procamp (head, asyh); 63 if (asyh->set.or ) head->func->or (head, asyh); 64 } 65 66 static void 67 nv50_head_atomic_check_procamp(struct nv50_head_atom *armh, 68 struct nv50_head_atom *asyh, 69 struct nouveau_conn_atom *asyc) 70 { 71 const int vib = asyc->procamp.color_vibrance - 100; 72 const int hue = asyc->procamp.vibrant_hue - 90; 73 const int adj = (vib > 0) ? 50 : 0; 74 asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff; 75 asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff; 76 asyh->set.procamp = true; 77 } 78 79 static void 80 nv50_head_atomic_check_dither(struct nv50_head_atom *armh, 81 struct nv50_head_atom *asyh, 82 struct nouveau_conn_atom *asyc) 83 { 84 u32 mode = 0x00; 85 86 if (asyc->dither.mode == DITHERING_MODE_AUTO) { 87 if (asyh->base.depth > asyh->or.bpc * 3) 88 mode = DITHERING_MODE_DYNAMIC2X2; 89 } else { 90 mode = asyc->dither.mode; 91 } 92 93 if (asyc->dither.depth == DITHERING_DEPTH_AUTO) { 94 if (asyh->or.bpc >= 8) 95 mode |= DITHERING_DEPTH_8BPC; 96 } else { 97 mode |= asyc->dither.depth; 98 } 99 100 asyh->dither.enable = mode; 101 asyh->dither.bits = mode >> 1; 102 asyh->dither.mode = mode >> 3; 103 asyh->set.dither = true; 104 } 105 106 static void 107 nv50_head_atomic_check_view(struct nv50_head_atom *armh, 108 struct nv50_head_atom *asyh, 109 struct nouveau_conn_atom *asyc) 110 { 111 struct drm_connector *connector = asyc->state.connector; 112 struct drm_display_mode *omode = &asyh->state.adjusted_mode; 113 struct drm_display_mode *umode = &asyh->state.mode; 114 int mode = asyc->scaler.mode; 115 struct edid *edid; 116 int umode_vdisplay, omode_hdisplay, omode_vdisplay; 117 118 if (connector->edid_blob_ptr) 119 edid = (struct edid *)connector->edid_blob_ptr->data; 120 else 121 edid = NULL; 122 123 if (!asyc->scaler.full) { 124 if (mode == DRM_MODE_SCALE_NONE) 125 omode = umode; 126 } else { 127 /* Non-EDID LVDS/eDP mode. */ 128 mode = DRM_MODE_SCALE_FULLSCREEN; 129 } 130 131 /* For the user-specified mode, we must ignore doublescan and 132 * the like, but honor frame packing. 133 */ 134 umode_vdisplay = umode->vdisplay; 135 if ((umode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 136 umode_vdisplay += umode->vtotal; 137 asyh->view.iW = umode->hdisplay; 138 asyh->view.iH = umode_vdisplay; 139 /* For the output mode, we can just use the stock helper. */ 140 drm_mode_get_hv_timing(omode, &omode_hdisplay, &omode_vdisplay); 141 asyh->view.oW = omode_hdisplay; 142 asyh->view.oH = omode_vdisplay; 143 144 /* Add overscan compensation if necessary, will keep the aspect 145 * ratio the same as the backend mode unless overridden by the 146 * user setting both hborder and vborder properties. 147 */ 148 if ((asyc->scaler.underscan.mode == UNDERSCAN_ON || 149 (asyc->scaler.underscan.mode == UNDERSCAN_AUTO && 150 drm_detect_hdmi_monitor(edid)))) { 151 u32 bX = asyc->scaler.underscan.hborder; 152 u32 bY = asyc->scaler.underscan.vborder; 153 u32 r = (asyh->view.oH << 19) / asyh->view.oW; 154 155 if (bX) { 156 asyh->view.oW -= (bX * 2); 157 if (bY) asyh->view.oH -= (bY * 2); 158 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; 159 } else { 160 asyh->view.oW -= (asyh->view.oW >> 4) + 32; 161 if (bY) asyh->view.oH -= (bY * 2); 162 else asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; 163 } 164 } 165 166 /* Handle CENTER/ASPECT scaling, taking into account the areas 167 * removed already for overscan compensation. 168 */ 169 switch (mode) { 170 case DRM_MODE_SCALE_CENTER: 171 /* NOTE: This will cause scaling when the input is 172 * larger than the output. 173 */ 174 asyh->view.oW = min(asyh->view.iW, asyh->view.oW); 175 asyh->view.oH = min(asyh->view.iH, asyh->view.oH); 176 break; 177 case DRM_MODE_SCALE_ASPECT: 178 /* Determine whether the scaling should be on width or on 179 * height. This is done by comparing the aspect ratios of the 180 * sizes. If the output AR is larger than input AR, that means 181 * we want to change the width (letterboxed on the 182 * left/right), otherwise on the height (letterboxed on the 183 * top/bottom). 184 * 185 * E.g. 4:3 (1.333) AR image displayed on a 16:10 (1.6) AR 186 * screen will have letterboxes on the left/right. However a 187 * 16:9 (1.777) AR image on that same screen will have 188 * letterboxes on the top/bottom. 189 * 190 * inputAR = iW / iH; outputAR = oW / oH 191 * outputAR > inputAR is equivalent to oW * iH > iW * oH 192 */ 193 if (asyh->view.oW * asyh->view.iH > asyh->view.iW * asyh->view.oH) { 194 /* Recompute output width, i.e. left/right letterbox */ 195 u32 r = (asyh->view.iW << 19) / asyh->view.iH; 196 asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19; 197 } else { 198 /* Recompute output height, i.e. top/bottom letterbox */ 199 u32 r = (asyh->view.iH << 19) / asyh->view.iW; 200 asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19; 201 } 202 break; 203 default: 204 break; 205 } 206 207 asyh->set.view = true; 208 } 209 210 static int 211 nv50_head_atomic_check_lut(struct nv50_head *head, 212 struct nv50_head_atom *asyh) 213 { 214 struct nv50_disp *disp = nv50_disp(head->base.base.dev); 215 struct drm_property_blob *olut = asyh->state.gamma_lut; 216 int size; 217 218 /* Determine whether core output LUT should be enabled. */ 219 if (olut) { 220 /* Check if any window(s) have stolen the core output LUT 221 * to as an input LUT for legacy gamma + I8 colour format. 222 */ 223 if (asyh->wndw.olut) { 224 /* If any window has stolen the core output LUT, 225 * all of them must. 226 */ 227 if (asyh->wndw.olut != asyh->wndw.mask) 228 return -EINVAL; 229 olut = NULL; 230 } 231 } 232 233 if (!olut) { 234 if (!head->func->olut_identity) { 235 asyh->olut.handle = 0; 236 return 0; 237 } 238 size = 0; 239 } else { 240 size = drm_color_lut_size(olut); 241 } 242 243 if (!head->func->olut(head, asyh, size)) { 244 DRM_DEBUG_KMS("Invalid olut\n"); 245 return -EINVAL; 246 } 247 asyh->olut.handle = disp->core->chan.vram.handle; 248 asyh->olut.buffer = !asyh->olut.buffer; 249 250 return 0; 251 } 252 253 static void 254 nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh) 255 { 256 struct drm_display_mode *mode = &asyh->state.adjusted_mode; 257 struct nv50_head_mode *m = &asyh->mode; 258 u32 blankus; 259 260 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE); 261 262 /* 263 * DRM modes are defined in terms of a repeating interval 264 * starting with the active display area. The hardware modes 265 * are defined in terms of a repeating interval starting one 266 * unit (pixel or line) into the sync pulse. So, add bias. 267 */ 268 269 m->h.active = mode->crtc_htotal; 270 m->h.synce = mode->crtc_hsync_end - mode->crtc_hsync_start - 1; 271 m->h.blanke = mode->crtc_hblank_end - mode->crtc_hsync_start - 1; 272 m->h.blanks = m->h.blanke + mode->crtc_hdisplay; 273 274 m->v.active = mode->crtc_vtotal; 275 m->v.synce = mode->crtc_vsync_end - mode->crtc_vsync_start - 1; 276 m->v.blanke = mode->crtc_vblank_end - mode->crtc_vsync_start - 1; 277 m->v.blanks = m->v.blanke + mode->crtc_vdisplay; 278 279 /*XXX: Safe underestimate, even "0" works */ 280 blankus = (m->v.active - mode->crtc_vdisplay - 2) * m->h.active; 281 blankus *= 1000; 282 blankus /= mode->crtc_clock; 283 m->v.blankus = blankus; 284 285 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 286 m->v.blank2e = m->v.active + m->v.blanke; 287 m->v.blank2s = m->v.blank2e + mode->crtc_vdisplay; 288 m->v.active = (m->v.active * 2) + 1; 289 m->interlace = true; 290 } else { 291 m->v.blank2e = 0; 292 m->v.blank2s = 1; 293 m->interlace = false; 294 } 295 m->clock = mode->crtc_clock; 296 297 asyh->or.nhsync = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); 298 asyh->or.nvsync = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); 299 asyh->set.or = head->func->or != NULL; 300 asyh->set.mode = true; 301 } 302 303 static int 304 nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) 305 { 306 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 307 struct nv50_head *head = nv50_head(crtc); 308 struct nv50_head_atom *armh = nv50_head_atom(crtc->state); 309 struct nv50_head_atom *asyh = nv50_head_atom(state); 310 struct nouveau_conn_atom *asyc = NULL; 311 struct drm_connector_state *conns; 312 struct drm_connector *conn; 313 int i; 314 315 NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active); 316 if (asyh->state.active) { 317 for_each_new_connector_in_state(asyh->state.state, conn, conns, i) { 318 if (conns->crtc == crtc) { 319 asyc = nouveau_conn_atom(conns); 320 break; 321 } 322 } 323 324 if (armh->state.active) { 325 if (asyc) { 326 if (asyh->state.mode_changed) 327 asyc->set.scaler = true; 328 if (armh->base.depth != asyh->base.depth) 329 asyc->set.dither = true; 330 } 331 } else { 332 if (asyc) 333 asyc->set.mask = ~0; 334 asyh->set.mask = ~0; 335 asyh->set.or = head->func->or != NULL; 336 } 337 338 if (asyh->state.mode_changed || asyh->state.connectors_changed) 339 nv50_head_atomic_check_mode(head, asyh); 340 341 if (asyh->state.color_mgmt_changed || 342 memcmp(&armh->wndw, &asyh->wndw, sizeof(asyh->wndw))) { 343 int ret = nv50_head_atomic_check_lut(head, asyh); 344 if (ret) 345 return ret; 346 347 asyh->olut.visible = asyh->olut.handle != 0; 348 } 349 350 if (asyc) { 351 if (asyc->set.scaler) 352 nv50_head_atomic_check_view(armh, asyh, asyc); 353 if (asyc->set.dither) 354 nv50_head_atomic_check_dither(armh, asyh, asyc); 355 if (asyc->set.procamp) 356 nv50_head_atomic_check_procamp(armh, asyh, asyc); 357 } 358 359 if (head->func->core_calc) { 360 head->func->core_calc(head, asyh); 361 if (!asyh->core.visible) 362 asyh->olut.visible = false; 363 } 364 365 asyh->set.base = armh->base.cpp != asyh->base.cpp; 366 asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp; 367 } else { 368 asyh->olut.visible = false; 369 asyh->core.visible = false; 370 asyh->curs.visible = false; 371 asyh->base.cpp = 0; 372 asyh->ovly.cpp = 0; 373 } 374 375 if (!drm_atomic_crtc_needs_modeset(&asyh->state)) { 376 if (asyh->core.visible) { 377 if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core))) 378 asyh->set.core = true; 379 } else 380 if (armh->core.visible) { 381 asyh->clr.core = true; 382 } 383 384 if (asyh->curs.visible) { 385 if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs))) 386 asyh->set.curs = true; 387 } else 388 if (armh->curs.visible) { 389 asyh->clr.curs = true; 390 } 391 392 if (asyh->olut.visible) { 393 if (memcmp(&armh->olut, &asyh->olut, sizeof(asyh->olut))) 394 asyh->set.olut = true; 395 } else 396 if (armh->olut.visible) { 397 asyh->clr.olut = true; 398 } 399 } else { 400 asyh->clr.olut = armh->olut.visible; 401 asyh->clr.core = armh->core.visible; 402 asyh->clr.curs = armh->curs.visible; 403 asyh->set.olut = asyh->olut.visible; 404 asyh->set.core = asyh->core.visible; 405 asyh->set.curs = asyh->curs.visible; 406 } 407 408 if (asyh->clr.mask || asyh->set.mask) 409 nv50_atom(asyh->state.state)->lock_core = true; 410 return 0; 411 } 412 413 static const struct drm_crtc_helper_funcs 414 nv50_head_help = { 415 .atomic_check = nv50_head_atomic_check, 416 }; 417 418 static void 419 nv50_head_atomic_destroy_state(struct drm_crtc *crtc, 420 struct drm_crtc_state *state) 421 { 422 struct nv50_head_atom *asyh = nv50_head_atom(state); 423 __drm_atomic_helper_crtc_destroy_state(&asyh->state); 424 kfree(asyh); 425 } 426 427 static struct drm_crtc_state * 428 nv50_head_atomic_duplicate_state(struct drm_crtc *crtc) 429 { 430 struct nv50_head_atom *armh = nv50_head_atom(crtc->state); 431 struct nv50_head_atom *asyh; 432 if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL))) 433 return NULL; 434 __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state); 435 asyh->wndw = armh->wndw; 436 asyh->view = armh->view; 437 asyh->mode = armh->mode; 438 asyh->olut = armh->olut; 439 asyh->core = armh->core; 440 asyh->curs = armh->curs; 441 asyh->base = armh->base; 442 asyh->ovly = armh->ovly; 443 asyh->dither = armh->dither; 444 asyh->procamp = armh->procamp; 445 asyh->or = armh->or; 446 asyh->dp = armh->dp; 447 asyh->clr.mask = 0; 448 asyh->set.mask = 0; 449 return &asyh->state; 450 } 451 452 static void 453 nv50_head_reset(struct drm_crtc *crtc) 454 { 455 struct nv50_head_atom *asyh; 456 457 if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL)))) 458 return; 459 460 if (crtc->state) 461 nv50_head_atomic_destroy_state(crtc, crtc->state); 462 463 __drm_atomic_helper_crtc_reset(crtc, &asyh->state); 464 } 465 466 static void 467 nv50_head_destroy(struct drm_crtc *crtc) 468 { 469 struct nv50_head *head = nv50_head(crtc); 470 nv50_lut_fini(&head->olut); 471 drm_crtc_cleanup(crtc); 472 kfree(head); 473 } 474 475 static const struct drm_crtc_funcs 476 nv50_head_func = { 477 .reset = nv50_head_reset, 478 .gamma_set = drm_atomic_helper_legacy_gamma_set, 479 .destroy = nv50_head_destroy, 480 .set_config = drm_atomic_helper_set_config, 481 .page_flip = drm_atomic_helper_page_flip, 482 .atomic_duplicate_state = nv50_head_atomic_duplicate_state, 483 .atomic_destroy_state = nv50_head_atomic_destroy_state, 484 }; 485 486 struct nv50_head * 487 nv50_head_create(struct drm_device *dev, int index) 488 { 489 struct nouveau_drm *drm = nouveau_drm(dev); 490 struct nv50_disp *disp = nv50_disp(dev); 491 struct nv50_head *head; 492 struct nv50_wndw *base, *ovly, *curs; 493 struct drm_crtc *crtc; 494 int ret; 495 496 head = kzalloc(sizeof(*head), GFP_KERNEL); 497 if (!head) 498 return ERR_PTR(-ENOMEM); 499 500 head->func = disp->core->func->head; 501 head->base.index = index; 502 503 if (disp->disp->object.oclass < GV100_DISP) { 504 ret = nv50_base_new(drm, head->base.index, &base); 505 ret = nv50_ovly_new(drm, head->base.index, &ovly); 506 } else { 507 ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_PRIMARY, 508 head->base.index * 2 + 0, &base); 509 ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_OVERLAY, 510 head->base.index * 2 + 1, &ovly); 511 } 512 if (ret == 0) 513 ret = nv50_curs_new(drm, head->base.index, &curs); 514 if (ret) { 515 kfree(head); 516 return ERR_PTR(ret); 517 } 518 519 crtc = &head->base.base; 520 drm_crtc_init_with_planes(dev, crtc, &base->plane, &curs->plane, 521 &nv50_head_func, "head-%d", head->base.index); 522 drm_crtc_helper_add(crtc, &nv50_head_help); 523 /* Keep the legacy gamma size at 256 to avoid compatibility issues */ 524 drm_mode_crtc_set_gamma_size(crtc, 256); 525 drm_crtc_enable_color_mgmt(crtc, base->func->ilut_size, 526 disp->disp->object.oclass >= GF110_DISP, 527 head->func->olut_size); 528 529 if (head->func->olut_set) { 530 ret = nv50_lut_init(disp, &drm->client.mmu, &head->olut); 531 if (ret) { 532 nv50_head_destroy(crtc); 533 return ERR_PTR(ret); 534 } 535 } 536 537 return head; 538 } 539