1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Driver for the MMC / SD / SDIO cell found in: 4 * 5 * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3 6 * 7 * Copyright (C) 2015-19 Renesas Electronics Corporation 8 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 9 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 10 * Copyright (C) 2007 Ian Molton 11 * Copyright (C) 2004 Ian Molton 12 */ 13 14 #ifndef TMIO_MMC_H 15 #define TMIO_MMC_H 16 17 #include <linux/dmaengine.h> 18 #include <linux/highmem.h> 19 #include <linux/mutex.h> 20 #include <linux/pagemap.h> 21 #include <linux/scatterlist.h> 22 #include <linux/spinlock.h> 23 #include <linux/interrupt.h> 24 25 #define CTL_SD_CMD 0x00 26 #define CTL_ARG_REG 0x04 27 #define CTL_STOP_INTERNAL_ACTION 0x08 28 #define CTL_XFER_BLK_COUNT 0xa 29 #define CTL_RESPONSE 0x0c 30 /* driver merges STATUS and following STATUS2 */ 31 #define CTL_STATUS 0x1c 32 /* driver merges IRQ_MASK and following IRQ_MASK2 */ 33 #define CTL_IRQ_MASK 0x20 34 #define CTL_SD_CARD_CLK_CTL 0x24 35 #define CTL_SD_XFER_LEN 0x26 36 #define CTL_SD_MEM_CARD_OPT 0x28 37 #define CTL_SD_ERROR_DETAIL_STATUS 0x2c 38 #define CTL_SD_DATA_PORT 0x30 39 #define CTL_TRANSACTION_CTL 0x34 40 #define CTL_SDIO_STATUS 0x36 41 #define CTL_SDIO_IRQ_MASK 0x38 42 #define CTL_DMA_ENABLE 0xd8 43 #define CTL_RESET_SD 0xe0 44 #define CTL_VERSION 0xe2 45 #define CTL_SDIF_MODE 0xe6 46 47 /* Definitions for values the CTL_STOP_INTERNAL_ACTION register can take */ 48 #define TMIO_STOP_STP BIT(0) 49 #define TMIO_STOP_SEC BIT(8) 50 51 /* Definitions for values the CTL_STATUS register can take */ 52 #define TMIO_STAT_CMDRESPEND BIT(0) 53 #define TMIO_STAT_DATAEND BIT(2) 54 #define TMIO_STAT_CARD_REMOVE BIT(3) 55 #define TMIO_STAT_CARD_INSERT BIT(4) 56 #define TMIO_STAT_SIGSTATE BIT(5) 57 #define TMIO_STAT_WRPROTECT BIT(7) 58 #define TMIO_STAT_CARD_REMOVE_A BIT(8) 59 #define TMIO_STAT_CARD_INSERT_A BIT(9) 60 #define TMIO_STAT_SIGSTATE_A BIT(10) 61 62 /* These belong technically to CTL_STATUS2, but the driver merges them */ 63 #define TMIO_STAT_CMD_IDX_ERR BIT(16) 64 #define TMIO_STAT_CRCFAIL BIT(17) 65 #define TMIO_STAT_STOPBIT_ERR BIT(18) 66 #define TMIO_STAT_DATATIMEOUT BIT(19) 67 #define TMIO_STAT_RXOVERFLOW BIT(20) 68 #define TMIO_STAT_TXUNDERRUN BIT(21) 69 #define TMIO_STAT_CMDTIMEOUT BIT(22) 70 #define TMIO_STAT_DAT0 BIT(23) /* only known on R-Car so far */ 71 #define TMIO_STAT_RXRDY BIT(24) 72 #define TMIO_STAT_TXRQ BIT(25) 73 #define TMIO_STAT_ALWAYS_SET_27 BIT(27) /* only known on R-Car 2+ so far */ 74 #define TMIO_STAT_ILL_FUNC BIT(29) /* only when !TMIO_MMC_HAS_IDLE_WAIT */ 75 #define TMIO_STAT_SCLKDIVEN BIT(29) /* only when TMIO_MMC_HAS_IDLE_WAIT */ 76 #define TMIO_STAT_CMD_BUSY BIT(30) 77 #define TMIO_STAT_ILL_ACCESS BIT(31) 78 79 /* Definitions for values the CTL_SD_CARD_CLK_CTL register can take */ 80 #define CLK_CTL_DIV_MASK 0xff 81 #define CLK_CTL_SCLKEN BIT(8) 82 83 /* Definitions for values the CTL_SD_MEM_CARD_OPT register can take */ 84 #define CARD_OPT_WIDTH8 BIT(13) 85 #define CARD_OPT_WIDTH BIT(15) 86 87 /* Definitions for values the CTL_SDIO_STATUS register can take */ 88 #define TMIO_SDIO_STAT_IOIRQ 0x0001 89 #define TMIO_SDIO_STAT_EXPUB52 0x4000 90 #define TMIO_SDIO_STAT_EXWT 0x8000 91 #define TMIO_SDIO_MASK_ALL 0xc007 92 93 #define TMIO_SDIO_SETBITS_MASK 0x0006 94 95 /* Definitions for values the CTL_DMA_ENABLE register can take */ 96 #define DMA_ENABLE_DMASDRW BIT(1) 97 98 /* Define some IRQ masks */ 99 /* This is the mask used at reset by the chip */ 100 #define TMIO_MASK_INIT_RCAR2 0x8b7f031d /* Initial value for R-Car Gen2+ */ 101 #define TMIO_MASK_ALL 0x837f031d 102 #define TMIO_MASK_READOP (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND) 103 #define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND) 104 #define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \ 105 TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT) 106 #define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD) 107 108 #define TMIO_MAX_BLK_SIZE 512 109 110 struct tmio_mmc_data; 111 struct tmio_mmc_host; 112 113 struct tmio_mmc_dma_ops { 114 void (*start)(struct tmio_mmc_host *host, struct mmc_data *data); 115 void (*enable)(struct tmio_mmc_host *host, bool enable); 116 void (*request)(struct tmio_mmc_host *host, 117 struct tmio_mmc_data *pdata); 118 void (*release)(struct tmio_mmc_host *host); 119 void (*abort)(struct tmio_mmc_host *host); 120 void (*dataend)(struct tmio_mmc_host *host); 121 122 /* optional */ 123 void (*end)(struct tmio_mmc_host *host); /* held host->lock */ 124 }; 125 126 struct tmio_mmc_host { 127 void __iomem *ctl; 128 struct mmc_command *cmd; 129 struct mmc_request *mrq; 130 struct mmc_data *data; 131 struct mmc_host *mmc; 132 struct mmc_host_ops ops; 133 134 /* Callbacks for clock / power control */ 135 void (*set_pwr)(struct platform_device *host, int state); 136 137 /* pio related stuff */ 138 struct scatterlist *sg_ptr; 139 struct scatterlist *sg_orig; 140 unsigned int sg_len; 141 unsigned int sg_off; 142 unsigned int bus_shift; 143 144 struct platform_device *pdev; 145 struct tmio_mmc_data *pdata; 146 147 /* DMA support */ 148 bool dma_on; 149 struct dma_chan *chan_rx; 150 struct dma_chan *chan_tx; 151 struct tasklet_struct dma_issue; 152 struct scatterlist bounce_sg; 153 u8 *bounce_buf; 154 155 /* Track lost interrupts */ 156 struct delayed_work delayed_reset_work; 157 struct work_struct done; 158 159 /* Cache */ 160 u32 sdcard_irq_mask; 161 u32 sdio_irq_mask; 162 unsigned int clk_cache; 163 u32 sdcard_irq_setbit_mask; 164 165 spinlock_t lock; /* protect host private data */ 166 unsigned long last_req_ts; 167 struct mutex ios_lock; /* protect set_ios() context */ 168 bool native_hotplug; 169 bool sdio_irq_enabled; 170 171 /* Mandatory callback */ 172 int (*clk_enable)(struct tmio_mmc_host *host); 173 void (*set_clock)(struct tmio_mmc_host *host, unsigned int clock); 174 175 /* Optional callbacks */ 176 void (*clk_disable)(struct tmio_mmc_host *host); 177 int (*multi_io_quirk)(struct mmc_card *card, 178 unsigned int direction, int blk_size); 179 int (*write16_hook)(struct tmio_mmc_host *host, int addr); 180 void (*reset)(struct tmio_mmc_host *host); 181 void (*hw_reset)(struct tmio_mmc_host *host); 182 bool (*check_retune)(struct tmio_mmc_host *host); 183 184 /* 185 * Mandatory callback for tuning to occur which is optional for SDR50 186 * and mandatory for SDR104. 187 */ 188 int (*execute_tuning)(struct tmio_mmc_host *host, u32 opcode); 189 190 void (*prepare_hs400_tuning)(struct tmio_mmc_host *host); 191 void (*hs400_downgrade)(struct tmio_mmc_host *host); 192 void (*hs400_complete)(struct tmio_mmc_host *host); 193 194 const struct tmio_mmc_dma_ops *dma_ops; 195 }; 196 197 struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev, 198 struct tmio_mmc_data *pdata); 199 void tmio_mmc_host_free(struct tmio_mmc_host *host); 200 int tmio_mmc_host_probe(struct tmio_mmc_host *host); 201 void tmio_mmc_host_remove(struct tmio_mmc_host *host); 202 void tmio_mmc_do_data_irq(struct tmio_mmc_host *host); 203 204 void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i); 205 void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i); 206 irqreturn_t tmio_mmc_irq(int irq, void *devid); 207 208 static inline char *tmio_mmc_kmap_atomic(struct scatterlist *sg, 209 unsigned long *flags) 210 { 211 local_irq_save(*flags); 212 return kmap_atomic(sg_page(sg)) + sg->offset; 213 } 214 215 static inline void tmio_mmc_kunmap_atomic(struct scatterlist *sg, 216 unsigned long *flags, void *virt) 217 { 218 kunmap_atomic(virt - sg->offset); 219 local_irq_restore(*flags); 220 } 221 222 #ifdef CONFIG_PM 223 int tmio_mmc_host_runtime_suspend(struct device *dev); 224 int tmio_mmc_host_runtime_resume(struct device *dev); 225 #endif 226 227 static inline u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr) 228 { 229 return ioread16(host->ctl + (addr << host->bus_shift)); 230 } 231 232 static inline void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr, 233 u16 *buf, int count) 234 { 235 ioread16_rep(host->ctl + (addr << host->bus_shift), buf, count); 236 } 237 238 static inline u32 sd_ctrl_read16_and_16_as_32(struct tmio_mmc_host *host, 239 int addr) 240 { 241 return ioread16(host->ctl + (addr << host->bus_shift)) | 242 ioread16(host->ctl + ((addr + 2) << host->bus_shift)) << 16; 243 } 244 245 static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr, 246 u32 *buf, int count) 247 { 248 ioread32_rep(host->ctl + (addr << host->bus_shift), buf, count); 249 } 250 251 static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr, 252 u16 val) 253 { 254 /* If there is a hook and it returns non-zero then there 255 * is an error and the write should be skipped 256 */ 257 if (host->write16_hook && host->write16_hook(host, addr)) 258 return; 259 iowrite16(val, host->ctl + (addr << host->bus_shift)); 260 } 261 262 static inline void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr, 263 u16 *buf, int count) 264 { 265 iowrite16_rep(host->ctl + (addr << host->bus_shift), buf, count); 266 } 267 268 static inline void sd_ctrl_write32_as_16_and_16(struct tmio_mmc_host *host, 269 int addr, u32 val) 270 { 271 if (addr == CTL_IRQ_MASK || addr == CTL_STATUS) 272 val |= host->sdcard_irq_setbit_mask; 273 274 iowrite16(val & 0xffff, host->ctl + (addr << host->bus_shift)); 275 iowrite16(val >> 16, host->ctl + ((addr + 2) << host->bus_shift)); 276 } 277 278 static inline void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val) 279 { 280 iowrite32(val, host->ctl + (addr << host->bus_shift)); 281 } 282 283 static inline void sd_ctrl_write32_rep(struct tmio_mmc_host *host, int addr, 284 const u32 *buf, int count) 285 { 286 iowrite32_rep(host->ctl + (addr << host->bus_shift), buf, count); 287 } 288 289 #endif 290