1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/bridge/renesas,lvds.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas R-Car LVDS Encoder
8
9maintainers:
10  - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
11
12description: |
13  These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
14  Gen2, R-Car Gen3, RZ/G1 and RZ/G2 SoCs.
15
16properties:
17  compatible:
18    enum:
19      - renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders
20      - renesas,r8a7744-lvds # for RZ/G1N compatible LVDS encoders
21      - renesas,r8a774a1-lvds # for RZ/G2M compatible LVDS encoders
22      - renesas,r8a774b1-lvds # for RZ/G2N compatible LVDS encoders
23      - renesas,r8a774c0-lvds # for RZ/G2E compatible LVDS encoders
24      - renesas,r8a7790-lvds # for R-Car H2 compatible LVDS encoders
25      - renesas,r8a7791-lvds # for R-Car M2-W compatible LVDS encoders
26      - renesas,r8a7793-lvds # for R-Car M2-N compatible LVDS encoders
27      - renesas,r8a7795-lvds # for R-Car H3 compatible LVDS encoders
28      - renesas,r8a7796-lvds # for R-Car M3-W compatible LVDS encoders
29      - renesas,r8a77965-lvds # for R-Car M3-N compatible LVDS encoders
30      - renesas,r8a77970-lvds # for R-Car V3M compatible LVDS encoders
31      - renesas,r8a77980-lvds # for R-Car V3H compatible LVDS encoders
32      - renesas,r8a77990-lvds # for R-Car E3 compatible LVDS encoders
33      - renesas,r8a77995-lvds # for R-Car D3 compatible LVDS encoders
34
35  reg:
36    maxItems: 1
37
38  clocks:
39    minItems: 1
40    maxItems: 4
41
42  clock-names:
43    minItems: 1
44    maxItems: 4
45
46  resets:
47    maxItems: 1
48
49  ports:
50    type: object
51    description: |
52      This device has two video ports. Their connections are modelled using the
53      OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
54      Each port shall have a single endpoint.
55
56    properties:
57      '#address-cells':
58        const: 1
59
60      '#size-cells':
61        const: 0
62
63      port@0:
64        type: object
65        description: Parallel RGB input port
66
67      port@1:
68        type: object
69        description: LVDS output port
70
71    required:
72      - port@0
73      - port@1
74
75    additionalProperties: false
76
77  power-domains:
78    maxItems: 1
79
80  renesas,companion:
81    $ref: /schemas/types.yaml#/definitions/phandle
82    description:
83      phandle to the companion LVDS encoder. This property is mandatory
84      for the first LVDS encoder on D3 and E3 SoCs, and shall point to
85      the second encoder to be used as a companion in dual-link mode. It
86      shall not be set for any other LVDS encoder.
87
88required:
89  - compatible
90  - reg
91  - clocks
92  - power-domains
93  - resets
94  - ports
95
96if:
97  properties:
98    compatible:
99      enum:
100        - renesas,r8a774c0-lvds
101        - renesas,r8a77990-lvds
102        - renesas,r8a77995-lvds
103then:
104  properties:
105    clocks:
106      minItems: 1
107      maxItems: 4
108      items:
109        - description: Functional clock
110        - description: EXTAL input clock
111        - description: DU_DOTCLKIN0 input clock
112        - description: DU_DOTCLKIN1 input clock
113
114    clock-names:
115      minItems: 1
116      maxItems: 4
117      items:
118        - const: fck
119        # The LVDS encoder can use the EXTAL or DU_DOTCLKINx clocks.
120        # These clocks are optional.
121        - enum:
122            - extal
123            - dclkin.0
124            - dclkin.1
125        - enum:
126            - extal
127            - dclkin.0
128            - dclkin.1
129        - enum:
130            - extal
131            - dclkin.0
132            - dclkin.1
133
134  required:
135    - clock-names
136
137else:
138  properties:
139    clocks:
140      maxItems: 1
141      items:
142        - description: Functional clock
143
144    clock-names:
145      maxItems: 1
146      items:
147        - const: fck
148
149    renesas,companion: false
150
151additionalProperties: false
152
153examples:
154  - |
155    #include <dt-bindings/clock/renesas-cpg-mssr.h>
156    #include <dt-bindings/power/r8a7795-sysc.h>
157
158    lvds@feb90000 {
159        compatible = "renesas,r8a7795-lvds";
160        reg = <0xfeb90000 0x14>;
161        clocks = <&cpg CPG_MOD 727>;
162        power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
163        resets = <&cpg 727>;
164
165        ports {
166            #address-cells = <1>;
167            #size-cells = <0>;
168
169            port@0 {
170                reg = <0>;
171                lvds_in: endpoint {
172                    remote-endpoint = <&du_out_lvds0>;
173                };
174            };
175            port@1 {
176                reg = <1>;
177                lvds_out: endpoint {
178                    remote-endpoint = <&panel_in>;
179                };
180            };
181        };
182    };
183
184  - |
185    #include <dt-bindings/clock/renesas-cpg-mssr.h>
186    #include <dt-bindings/power/r8a77990-sysc.h>
187
188    lvds0: lvds@feb90000 {
189        compatible = "renesas,r8a77990-lvds";
190        reg = <0xfeb90000 0x20>;
191        clocks = <&cpg CPG_MOD 727>,
192                 <&x13_clk>,
193                 <&extal_clk>;
194        clock-names = "fck", "dclkin.0", "extal";
195        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
196        resets = <&cpg 727>;
197
198        renesas,companion = <&lvds1>;
199
200        ports {
201            #address-cells = <1>;
202            #size-cells = <0>;
203
204            port@0 {
205                reg = <0>;
206                lvds0_in: endpoint {
207                    remote-endpoint = <&du_out_lvds0>;
208                };
209            };
210            port@1 {
211                reg = <1>;
212                lvds0_out: endpoint {
213                    remote-endpoint = <&panel_in1>;
214                };
215            };
216        };
217    };
218
219    lvds1: lvds@feb90100 {
220        compatible = "renesas,r8a77990-lvds";
221        reg = <0xfeb90100 0x20>;
222        clocks = <&cpg CPG_MOD 727>,
223                 <&x13_clk>,
224                 <&extal_clk>;
225        clock-names = "fck", "dclkin.0", "extal";
226        power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
227        resets = <&cpg 726>;
228
229        ports {
230            #address-cells = <1>;
231            #size-cells = <0>;
232
233            port@0 {
234                reg = <0>;
235                lvds1_in: endpoint {
236                    remote-endpoint = <&du_out_lvds1>;
237                };
238            };
239            port@1 {
240                reg = <1>;
241                lvds1_out: endpoint {
242                    remote-endpoint = <&panel_in2>;
243                };
244            };
245        };
246    };
247
248...
249