1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Atlantic Network Driver 3 * 4 * Copyright (C) 2014-2019 aQuantia Corporation 5 * Copyright (C) 2019-2020 Marvell International Ltd. 6 */ 7 8 /* File aq_hw.h: Declaration of abstract interface for NIC hardware specific 9 * functions. 10 */ 11 12 #ifndef AQ_HW_H 13 #define AQ_HW_H 14 15 #include "aq_common.h" 16 #include "aq_rss.h" 17 #include "hw_atl/hw_atl_utils.h" 18 19 #define AQ_HW_MAC_COUNTER_HZ 312500000ll 20 #define AQ_HW_PHY_COUNTER_HZ 160000000ll 21 22 enum aq_tc_mode { 23 AQ_TC_MODE_INVALID = -1, 24 AQ_TC_MODE_8TCS, 25 AQ_TC_MODE_4TCS, 26 }; 27 28 #define AQ_RX_FIRST_LOC_FVLANID 0U 29 #define AQ_RX_LAST_LOC_FVLANID 15U 30 #define AQ_RX_FIRST_LOC_FETHERT 16U 31 #define AQ_RX_LAST_LOC_FETHERT 31U 32 #define AQ_RX_FIRST_LOC_FL3L4 32U 33 #define AQ_RX_LAST_LOC_FL3L4 39U 34 #define AQ_RX_MAX_RXNFC_LOC AQ_RX_LAST_LOC_FL3L4 35 #define AQ_VLAN_MAX_FILTERS \ 36 (AQ_RX_LAST_LOC_FVLANID - AQ_RX_FIRST_LOC_FVLANID + 1U) 37 #define AQ_RX_QUEUE_NOT_ASSIGNED 0xFFU 38 39 #define AQ_FRAC_PER_NS 0x100000000LL 40 41 /* Used for rate to Mbps conversion */ 42 #define AQ_MBPS_DIVISOR 125000 /* 1000000 / 8 */ 43 44 /* NIC H/W capabilities */ 45 struct aq_hw_caps_s { 46 u64 hw_features; 47 u64 link_speed_msk; 48 unsigned int hw_priv_flags; 49 u32 media_type; 50 u32 rxds_max; 51 u32 txds_max; 52 u32 rxds_min; 53 u32 txds_min; 54 u32 txhwb_alignment; 55 u32 irq_mask; 56 u32 vecs; 57 u32 mtu; 58 u32 mac_regs_count; 59 u32 hw_alive_check_addr; 60 u8 msix_irqs; 61 u8 tcs_max; 62 u8 rxd_alignment; 63 u8 rxd_size; 64 u8 txd_alignment; 65 u8 txd_size; 66 u8 tx_rings; 67 u8 rx_rings; 68 bool flow_control; 69 bool is_64_dma; 70 bool op64bit; 71 u32 quirks; 72 u32 priv_data_len; 73 }; 74 75 struct aq_hw_link_status_s { 76 unsigned int mbps; 77 bool full_duplex; 78 u32 lp_link_speed_msk; 79 u32 lp_flow_control; 80 }; 81 82 struct aq_stats_s { 83 u64 uprc; 84 u64 mprc; 85 u64 bprc; 86 u64 erpt; 87 u64 uptc; 88 u64 mptc; 89 u64 bptc; 90 u64 erpr; 91 u64 mbtc; 92 u64 bbtc; 93 u64 mbrc; 94 u64 bbrc; 95 u64 ubrc; 96 u64 ubtc; 97 u64 dpc; 98 u64 dma_pkt_rc; 99 u64 dma_pkt_tc; 100 u64 dma_oct_rc; 101 u64 dma_oct_tc; 102 }; 103 104 #define AQ_HW_IRQ_INVALID 0U 105 #define AQ_HW_IRQ_LEGACY 1U 106 #define AQ_HW_IRQ_MSI 2U 107 #define AQ_HW_IRQ_MSIX 3U 108 109 #define AQ_HW_SERVICE_IRQS 1U 110 111 #define AQ_HW_POWER_STATE_D0 0U 112 #define AQ_HW_POWER_STATE_D3 3U 113 114 #define AQ_HW_FLAG_STARTED 0x00000004U 115 #define AQ_HW_FLAG_STOPPING 0x00000008U 116 #define AQ_HW_FLAG_RESETTING 0x00000010U 117 #define AQ_HW_FLAG_CLOSING 0x00000020U 118 #define AQ_HW_PTP_AVAILABLE 0x01000000U 119 #define AQ_HW_LINK_DOWN 0x04000000U 120 #define AQ_HW_FLAG_ERR_UNPLUG 0x40000000U 121 #define AQ_HW_FLAG_ERR_HW 0x80000000U 122 123 #define AQ_HW_FLAG_ERRORS (AQ_HW_FLAG_ERR_HW | AQ_HW_FLAG_ERR_UNPLUG) 124 125 #define AQ_NIC_FLAGS_IS_NOT_READY (AQ_NIC_FLAG_STOPPING | \ 126 AQ_NIC_FLAG_RESETTING | AQ_NIC_FLAG_CLOSING | \ 127 AQ_NIC_FLAG_ERR_UNPLUG | AQ_NIC_FLAG_ERR_HW) 128 129 #define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \ 130 AQ_NIC_LINK_DOWN) 131 132 #define AQ_HW_MEDIA_TYPE_TP 1U 133 #define AQ_HW_MEDIA_TYPE_FIBRE 2U 134 135 #define AQ_HW_TXD_MULTIPLE 8U 136 #define AQ_HW_RXD_MULTIPLE 8U 137 138 #define AQ_HW_QUEUES_MAX 32U 139 #define AQ_HW_MULTICAST_ADDRESS_MAX 32U 140 141 #define AQ_HW_PTP_TC 2U 142 143 #define AQ_HW_LED_BLINK 0x2U 144 #define AQ_HW_LED_DEFAULT 0x0U 145 146 enum aq_priv_flags { 147 AQ_HW_LOOPBACK_DMA_SYS, 148 AQ_HW_LOOPBACK_PKT_SYS, 149 AQ_HW_LOOPBACK_DMA_NET, 150 AQ_HW_LOOPBACK_PHYINT_SYS, 151 AQ_HW_LOOPBACK_PHYEXT_SYS, 152 }; 153 154 #define AQ_HW_LOOPBACK_MASK (BIT(AQ_HW_LOOPBACK_DMA_SYS) |\ 155 BIT(AQ_HW_LOOPBACK_PKT_SYS) |\ 156 BIT(AQ_HW_LOOPBACK_DMA_NET) |\ 157 BIT(AQ_HW_LOOPBACK_PHYINT_SYS) |\ 158 BIT(AQ_HW_LOOPBACK_PHYEXT_SYS)) 159 160 #define ATL_HW_CHIP_MIPS 0x00000001U 161 #define ATL_HW_CHIP_TPO2 0x00000002U 162 #define ATL_HW_CHIP_RPF2 0x00000004U 163 #define ATL_HW_CHIP_MPI_AQ 0x00000010U 164 #define ATL_HW_CHIP_ATLANTIC 0x00800000U 165 #define ATL_HW_CHIP_REVISION_A0 0x01000000U 166 #define ATL_HW_CHIP_REVISION_B0 0x02000000U 167 #define ATL_HW_CHIP_REVISION_B1 0x04000000U 168 #define ATL_HW_CHIP_ANTIGUA 0x08000000U 169 170 #define ATL_HW_IS_CHIP_FEATURE(_HW_, _F_) (!!(ATL_HW_CHIP_##_F_ & \ 171 (_HW_)->chip_features)) 172 173 struct aq_hw_s { 174 atomic_t flags; 175 u8 rbl_enabled:1; 176 struct aq_nic_cfg_s *aq_nic_cfg; 177 const struct aq_fw_ops *aq_fw_ops; 178 void __iomem *mmio; 179 struct aq_hw_link_status_s aq_link_status; 180 struct hw_atl_utils_mbox mbox; 181 struct hw_atl_stats_s last_stats; 182 struct aq_stats_s curr_stats; 183 u64 speed; 184 u32 itr_tx; 185 u32 itr_rx; 186 unsigned int chip_features; 187 u32 fw_ver_actual; 188 atomic_t dpc; 189 u32 mbox_addr; 190 u32 rpc_addr; 191 u32 settings_addr; 192 u32 rpc_tid; 193 struct hw_atl_utils_fw_rpc rpc; 194 s64 ptp_clk_offset; 195 u16 phy_id; 196 void *priv; 197 }; 198 199 struct aq_ring_s; 200 struct aq_ring_param_s; 201 struct sk_buff; 202 struct aq_rx_filter_l3l4; 203 204 struct aq_hw_ops { 205 206 int (*hw_ring_tx_xmit)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 207 unsigned int frags); 208 209 int (*hw_ring_rx_receive)(struct aq_hw_s *self, 210 struct aq_ring_s *aq_ring); 211 212 int (*hw_ring_rx_fill)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 213 unsigned int sw_tail_old); 214 215 int (*hw_ring_tx_head_update)(struct aq_hw_s *self, 216 struct aq_ring_s *aq_ring); 217 218 int (*hw_set_mac_address)(struct aq_hw_s *self, u8 *mac_addr); 219 220 int (*hw_soft_reset)(struct aq_hw_s *self); 221 222 int (*hw_prepare)(struct aq_hw_s *self, 223 const struct aq_fw_ops **fw_ops); 224 225 int (*hw_reset)(struct aq_hw_s *self); 226 227 int (*hw_init)(struct aq_hw_s *self, u8 *mac_addr); 228 229 int (*hw_start)(struct aq_hw_s *self); 230 231 int (*hw_stop)(struct aq_hw_s *self); 232 233 int (*hw_ring_tx_init)(struct aq_hw_s *self, struct aq_ring_s *aq_ring, 234 struct aq_ring_param_s *aq_ring_param); 235 236 int (*hw_ring_tx_start)(struct aq_hw_s *self, 237 struct aq_ring_s *aq_ring); 238 239 int (*hw_ring_tx_stop)(struct aq_hw_s *self, 240 struct aq_ring_s *aq_ring); 241 242 int (*hw_ring_rx_init)(struct aq_hw_s *self, 243 struct aq_ring_s *aq_ring, 244 struct aq_ring_param_s *aq_ring_param); 245 246 int (*hw_ring_rx_start)(struct aq_hw_s *self, 247 struct aq_ring_s *aq_ring); 248 249 int (*hw_ring_rx_stop)(struct aq_hw_s *self, 250 struct aq_ring_s *aq_ring); 251 252 int (*hw_irq_enable)(struct aq_hw_s *self, u64 mask); 253 254 int (*hw_irq_disable)(struct aq_hw_s *self, u64 mask); 255 256 int (*hw_irq_read)(struct aq_hw_s *self, u64 *mask); 257 258 int (*hw_packet_filter_set)(struct aq_hw_s *self, 259 unsigned int packet_filter); 260 261 int (*hw_filter_l3l4_set)(struct aq_hw_s *self, 262 struct aq_rx_filter_l3l4 *data); 263 264 int (*hw_filter_l3l4_clear)(struct aq_hw_s *self, 265 struct aq_rx_filter_l3l4 *data); 266 267 int (*hw_filter_l2_set)(struct aq_hw_s *self, 268 struct aq_rx_filter_l2 *data); 269 270 int (*hw_filter_l2_clear)(struct aq_hw_s *self, 271 struct aq_rx_filter_l2 *data); 272 273 int (*hw_filter_vlan_set)(struct aq_hw_s *self, 274 struct aq_rx_filter_vlan *aq_vlans); 275 276 int (*hw_filter_vlan_ctrl)(struct aq_hw_s *self, bool enable); 277 278 int (*hw_multicast_list_set)(struct aq_hw_s *self, 279 u8 ar_mac[AQ_HW_MULTICAST_ADDRESS_MAX] 280 [ETH_ALEN], 281 u32 count); 282 283 int (*hw_interrupt_moderation_set)(struct aq_hw_s *self); 284 285 int (*hw_rss_set)(struct aq_hw_s *self, 286 struct aq_rss_parameters *rss_params); 287 288 int (*hw_rss_hash_set)(struct aq_hw_s *self, 289 struct aq_rss_parameters *rss_params); 290 291 int (*hw_tc_rate_limit_set)(struct aq_hw_s *self); 292 293 int (*hw_get_regs)(struct aq_hw_s *self, 294 const struct aq_hw_caps_s *aq_hw_caps, 295 u32 *regs_buff); 296 297 struct aq_stats_s *(*hw_get_hw_stats)(struct aq_hw_s *self); 298 299 u32 (*hw_get_fw_version)(struct aq_hw_s *self); 300 301 int (*hw_set_offload)(struct aq_hw_s *self, 302 struct aq_nic_cfg_s *aq_nic_cfg); 303 304 int (*hw_ring_hwts_rx_fill)(struct aq_hw_s *self, 305 struct aq_ring_s *aq_ring); 306 307 int (*hw_ring_hwts_rx_receive)(struct aq_hw_s *self, 308 struct aq_ring_s *ring); 309 310 void (*hw_get_ptp_ts)(struct aq_hw_s *self, u64 *stamp); 311 312 int (*hw_adj_clock_freq)(struct aq_hw_s *self, s32 delta); 313 314 int (*hw_adj_sys_clock)(struct aq_hw_s *self, s64 delta); 315 316 int (*hw_set_sys_clock)(struct aq_hw_s *self, u64 time, u64 ts); 317 318 int (*hw_ts_to_sys_clock)(struct aq_hw_s *self, u64 ts, u64 *time); 319 320 int (*hw_gpio_pulse)(struct aq_hw_s *self, u32 index, u64 start, 321 u32 period); 322 323 int (*hw_extts_gpio_enable)(struct aq_hw_s *self, u32 index, 324 u32 enable); 325 326 int (*hw_get_sync_ts)(struct aq_hw_s *self, u64 *ts); 327 328 u16 (*rx_extract_ts)(struct aq_hw_s *self, u8 *p, unsigned int len, 329 u64 *timestamp); 330 331 int (*extract_hwts)(struct aq_hw_s *self, u8 *p, unsigned int len, 332 u64 *timestamp); 333 334 int (*hw_set_fc)(struct aq_hw_s *self, u32 fc, u32 tc); 335 336 int (*hw_set_loopback)(struct aq_hw_s *self, u32 mode, bool enable); 337 338 int (*hw_get_mac_temp)(struct aq_hw_s *self, u32 *temp); 339 }; 340 341 struct aq_fw_ops { 342 int (*init)(struct aq_hw_s *self); 343 344 int (*deinit)(struct aq_hw_s *self); 345 346 int (*reset)(struct aq_hw_s *self); 347 348 int (*renegotiate)(struct aq_hw_s *self); 349 350 int (*get_mac_permanent)(struct aq_hw_s *self, u8 *mac); 351 352 int (*set_link_speed)(struct aq_hw_s *self, u32 speed); 353 354 int (*set_state)(struct aq_hw_s *self, 355 enum hal_atl_utils_fw_state_e state); 356 357 int (*update_link_status)(struct aq_hw_s *self); 358 359 int (*update_stats)(struct aq_hw_s *self); 360 361 int (*get_mac_temp)(struct aq_hw_s *self, int *temp); 362 363 int (*get_phy_temp)(struct aq_hw_s *self, int *temp); 364 365 u32 (*get_flow_control)(struct aq_hw_s *self, u32 *fcmode); 366 367 int (*set_flow_control)(struct aq_hw_s *self); 368 369 int (*led_control)(struct aq_hw_s *self, u32 mode); 370 371 int (*set_phyloopback)(struct aq_hw_s *self, u32 mode, bool enable); 372 373 int (*set_power)(struct aq_hw_s *self, unsigned int power_state, 374 u8 *mac); 375 376 int (*send_fw_request)(struct aq_hw_s *self, 377 const struct hw_fw_request_iface *fw_req, 378 size_t size); 379 380 void (*enable_ptp)(struct aq_hw_s *self, int enable); 381 382 void (*adjust_ptp)(struct aq_hw_s *self, uint64_t adj); 383 384 int (*set_eee_rate)(struct aq_hw_s *self, u32 speed); 385 386 int (*get_eee_rate)(struct aq_hw_s *self, u32 *rate, 387 u32 *supported_rates); 388 389 u32 (*get_link_capabilities)(struct aq_hw_s *self); 390 391 int (*send_macsec_req)(struct aq_hw_s *self, 392 struct macsec_msg_fw_request *msg, 393 struct macsec_msg_fw_response *resp); 394 }; 395 396 #endif /* AQ_HW_H */ 397