1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2019 MediaTek Inc. */ 3 4 #ifndef __MT7615_MCU_H 5 #define __MT7615_MCU_H 6 7 struct mt7615_mcu_txd { 8 __le32 txd[8]; 9 10 __le16 len; 11 __le16 pq_id; 12 13 u8 cid; 14 u8 pkt_type; 15 u8 set_query; /* FW don't care */ 16 u8 seq; 17 18 u8 uc_d2b0_rev; 19 u8 ext_cid; 20 u8 s2d_index; 21 u8 ext_cid_ack; 22 23 u32 reserved[5]; 24 } __packed __aligned(4); 25 26 /** 27 * struct mt7615_uni_txd - mcu command descriptor for firmware v3 28 * @txd: hardware descriptor 29 * @len: total length not including txd 30 * @cid: command identifier 31 * @pkt_type: must be 0xa0 (cmd packet by long format) 32 * @frag_n: fragment number 33 * @seq: sequence number 34 * @checksum: 0 mean there is no checksum 35 * @s2d_index: index for command source and destination 36 * Definition | value | note 37 * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM 38 * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM 39 * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA 40 * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM 41 * 42 * @option: command option 43 * BIT[0]: UNI_CMD_OPT_BIT_ACK 44 * set to 1 to request a fw reply 45 * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY 46 * is set, mcu firmware will send response event EID = 0x01 47 * (UNI_EVENT_ID_CMD_RESULT) to the host. 48 * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD 49 * 0: original command 50 * 1: unified command 51 * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY 52 * 0: QUERY command 53 * 1: SET command 54 */ 55 struct mt7615_uni_txd { 56 __le32 txd[8]; 57 58 /* DW1 */ 59 __le16 len; 60 __le16 cid; 61 62 /* DW2 */ 63 u8 reserved; 64 u8 pkt_type; 65 u8 frag_n; 66 u8 seq; 67 68 /* DW3 */ 69 __le16 checksum; 70 u8 s2d_index; 71 u8 option; 72 73 /* DW4 */ 74 u8 reserved2[4]; 75 } __packed __aligned(4); 76 77 /* event table */ 78 enum { 79 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 80 MCU_EVENT_FW_START = 0x01, 81 MCU_EVENT_GENERIC = 0x01, 82 MCU_EVENT_ACCESS_REG = 0x02, 83 MCU_EVENT_MT_PATCH_SEM = 0x04, 84 MCU_EVENT_SCAN_DONE = 0x0d, 85 MCU_EVENT_ROC = 0x10, 86 MCU_EVENT_BSS_ABSENCE = 0x11, 87 MCU_EVENT_BSS_BEACON_LOSS = 0x13, 88 MCU_EVENT_CH_PRIVILEGE = 0x18, 89 MCU_EVENT_SCHED_SCAN_DONE = 0x23, 90 MCU_EVENT_EXT = 0xed, 91 MCU_EVENT_RESTART_DL = 0xef, 92 }; 93 94 /* ext event table */ 95 enum { 96 MCU_EXT_EVENT_PS_SYNC = 0x5, 97 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 98 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 99 MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 100 MCU_EXT_EVENT_RDD_REPORT = 0x3a, 101 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 102 }; 103 104 enum { 105 MT_SKU_CCK_1_2 = 0, 106 MT_SKU_CCK_55_11, 107 MT_SKU_OFDM_6_9, 108 MT_SKU_OFDM_12_18, 109 MT_SKU_OFDM_24_36, 110 MT_SKU_OFDM_48, 111 MT_SKU_OFDM_54, 112 MT_SKU_HT20_0_8, 113 MT_SKU_HT20_32, 114 MT_SKU_HT20_1_2_9_10, 115 MT_SKU_HT20_3_4_11_12, 116 MT_SKU_HT20_5_13, 117 MT_SKU_HT20_6_14, 118 MT_SKU_HT20_7_15, 119 MT_SKU_HT40_0_8, 120 MT_SKU_HT40_32, 121 MT_SKU_HT40_1_2_9_10, 122 MT_SKU_HT40_3_4_11_12, 123 MT_SKU_HT40_5_13, 124 MT_SKU_HT40_6_14, 125 MT_SKU_HT40_7_15, 126 MT_SKU_VHT20_0, 127 MT_SKU_VHT20_1_2, 128 MT_SKU_VHT20_3_4, 129 MT_SKU_VHT20_5_6, 130 MT_SKU_VHT20_7, 131 MT_SKU_VHT20_8, 132 MT_SKU_VHT20_9, 133 MT_SKU_VHT40_0, 134 MT_SKU_VHT40_1_2, 135 MT_SKU_VHT40_3_4, 136 MT_SKU_VHT40_5_6, 137 MT_SKU_VHT40_7, 138 MT_SKU_VHT40_8, 139 MT_SKU_VHT40_9, 140 MT_SKU_VHT80_0, 141 MT_SKU_VHT80_1_2, 142 MT_SKU_VHT80_3_4, 143 MT_SKU_VHT80_5_6, 144 MT_SKU_VHT80_7, 145 MT_SKU_VHT80_8, 146 MT_SKU_VHT80_9, 147 MT_SKU_VHT160_0, 148 MT_SKU_VHT160_1_2, 149 MT_SKU_VHT160_3_4, 150 MT_SKU_VHT160_5_6, 151 MT_SKU_VHT160_7, 152 MT_SKU_VHT160_8, 153 MT_SKU_VHT160_9, 154 MT_SKU_1SS_DELTA, 155 MT_SKU_2SS_DELTA, 156 MT_SKU_3SS_DELTA, 157 MT_SKU_4SS_DELTA, 158 }; 159 160 struct mt7615_mcu_rxd { 161 __le32 rxd[4]; 162 163 __le16 len; 164 __le16 pkt_type_id; 165 166 u8 eid; 167 u8 seq; 168 __le16 __rsv; 169 170 u8 ext_eid; 171 u8 __rsv1[2]; 172 u8 s2d_index; 173 }; 174 175 struct mt7615_mcu_rdd_report { 176 struct mt7615_mcu_rxd rxd; 177 178 u8 idx; 179 u8 long_detected; 180 u8 constant_prf_detected; 181 u8 staggered_prf_detected; 182 u8 radar_type_idx; 183 u8 periodic_pulse_num; 184 u8 long_pulse_num; 185 u8 hw_pulse_num; 186 187 u8 out_lpn; 188 u8 out_spn; 189 u8 out_crpn; 190 u8 out_crpw; 191 u8 out_crbn; 192 u8 out_stgpn; 193 u8 out_stgpw; 194 195 u8 _rsv[2]; 196 197 __le32 out_pri_const; 198 __le32 out_pri_stg[3]; 199 200 struct { 201 __le32 start; 202 __le16 pulse_width; 203 __le16 pulse_power; 204 } long_pulse[32]; 205 206 struct { 207 __le32 start; 208 __le16 pulse_width; 209 __le16 pulse_power; 210 } periodic_pulse[32]; 211 212 struct { 213 __le32 start; 214 __le16 pulse_width; 215 __le16 pulse_power; 216 u8 sc_pass; 217 u8 sw_reset; 218 } hw_pulse[32]; 219 }; 220 221 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 222 #define MCU_PKT_ID 0xa0 223 224 enum { 225 MCU_Q_QUERY, 226 MCU_Q_SET, 227 MCU_Q_RESERVED, 228 MCU_Q_NA 229 }; 230 231 enum { 232 MCU_S2D_H2N, 233 MCU_S2D_C2N, 234 MCU_S2D_H2C, 235 MCU_S2D_H2CN 236 }; 237 238 #define MCU_FW_PREFIX BIT(31) 239 #define MCU_UNI_PREFIX BIT(30) 240 #define MCU_CE_PREFIX BIT(29) 241 #define MCU_CMD_MASK ~(MCU_FW_PREFIX | MCU_UNI_PREFIX | \ 242 MCU_CE_PREFIX) 243 244 enum { 245 MCU_CMD_TARGET_ADDRESS_LEN_REQ = MCU_FW_PREFIX | 0x01, 246 MCU_CMD_FW_START_REQ = MCU_FW_PREFIX | 0x02, 247 MCU_CMD_INIT_ACCESS_REG = 0x3, 248 MCU_CMD_PATCH_START_REQ = 0x05, 249 MCU_CMD_PATCH_FINISH_REQ = MCU_FW_PREFIX | 0x07, 250 MCU_CMD_PATCH_SEM_CONTROL = MCU_FW_PREFIX | 0x10, 251 MCU_CMD_EXT_CID = 0xED, 252 MCU_CMD_FW_SCATTER = MCU_FW_PREFIX | 0xEE, 253 MCU_CMD_RESTART_DL_REQ = MCU_FW_PREFIX | 0xEF, 254 }; 255 256 enum { 257 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 258 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 259 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11, 260 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 261 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 262 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 263 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 264 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 265 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 266 MCU_EXT_CMD_GET_TEMP = 0x2c, 267 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 268 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 269 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 270 MCU_EXT_CMD_DBDC_CTRL = 0x45, 271 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 272 MCU_EXT_CMD_BCN_OFFLOAD = 0x49, 273 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 274 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 275 MCU_EXT_CMD_RXDCOC_CAL = 0x59, 276 MCU_EXT_CMD_TXDPD_CAL = 0x60, 277 MCU_EXT_CMD_SET_RDD_TH = 0x7c, 278 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d, 279 }; 280 281 enum { 282 MCU_UNI_CMD_DEV_INFO_UPDATE = MCU_UNI_PREFIX | 0x01, 283 MCU_UNI_CMD_BSS_INFO_UPDATE = MCU_UNI_PREFIX | 0x02, 284 MCU_UNI_CMD_STA_REC_UPDATE = MCU_UNI_PREFIX | 0x03, 285 MCU_UNI_CMD_SUSPEND = MCU_UNI_PREFIX | 0x05, 286 MCU_UNI_CMD_OFFLOAD = MCU_UNI_PREFIX | 0x06, 287 MCU_UNI_CMD_HIF_CTRL = MCU_UNI_PREFIX | 0x07, 288 }; 289 290 struct mt7615_mcu_uni_event { 291 u8 cid; 292 u8 pad[3]; 293 __le32 status; /* 0: success, others: fail */ 294 } __packed; 295 296 struct mt7615_beacon_loss_event { 297 u8 bss_idx; 298 u8 reason; 299 u8 pad[2]; 300 } __packed; 301 302 struct mt7615_mcu_scan_ssid { 303 __le32 ssid_len; 304 u8 ssid[IEEE80211_MAX_SSID_LEN]; 305 } __packed; 306 307 struct mt7615_mcu_scan_channel { 308 u8 band; /* 1: 2.4GHz 309 * 2: 5.0GHz 310 * Others: Reserved 311 */ 312 u8 channel_num; 313 } __packed; 314 315 struct mt7615_mcu_scan_match { 316 __le32 rssi_th; 317 u8 ssid[IEEE80211_MAX_SSID_LEN]; 318 u8 ssid_len; 319 u8 rsv[3]; 320 } __packed; 321 322 struct mt7615_hw_scan_req { 323 u8 seq_num; 324 u8 bss_idx; 325 u8 scan_type; /* 0: PASSIVE SCAN 326 * 1: ACTIVE SCAN 327 */ 328 u8 ssid_type; /* BIT(0) wildcard SSID 329 * BIT(1) P2P wildcard SSID 330 * BIT(2) specified SSID + wildcard SSID 331 * BIT(2) + ssid_type_ext BIT(0) specified SSID only 332 */ 333 u8 ssids_num; 334 u8 probe_req_num; /* Number of probe request for each SSID */ 335 u8 scan_func; /* BIT(0) Enable random MAC scan 336 * BIT(1) Disable DBDC scan type 1~3. 337 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan). 338 */ 339 u8 version; /* 0: Not support fields after ies. 340 * 1: Support fields after ies. 341 */ 342 struct mt7615_mcu_scan_ssid ssids[4]; 343 __le16 probe_delay_time; 344 __le16 channel_dwell_time; /* channel Dwell interval */ 345 __le16 timeout_value; 346 u8 channel_type; /* 0: Full channels 347 * 1: Only 2.4GHz channels 348 * 2: Only 5GHz channels 349 * 3: P2P social channel only (channel #1, #6 and #11) 350 * 4: Specified channels 351 * Others: Reserved 352 */ 353 u8 channels_num; /* valid when channel_type is 4 */ 354 /* valid when channels_num is set */ 355 struct mt7615_mcu_scan_channel channels[32]; 356 __le16 ies_len; 357 u8 ies[MT7615_SCAN_IE_LEN]; 358 /* following fields are valid if version > 0 */ 359 u8 ext_channels_num; 360 u8 ext_ssids_num; 361 __le16 channel_min_dwell_time; 362 struct mt7615_mcu_scan_channel ext_channels[32]; 363 struct mt7615_mcu_scan_ssid ext_ssids[6]; 364 u8 bssid[ETH_ALEN]; 365 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */ 366 u8 pad[63]; 367 u8 ssid_type_ext; 368 } __packed; 369 370 #define SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64 371 struct mt7615_hw_scan_done { 372 u8 seq_num; 373 u8 sparse_channel_num; 374 struct mt7615_mcu_scan_channel sparse_channel; 375 u8 complete_channel_num; 376 u8 current_state; 377 u8 version; 378 u8 pad; 379 __le32 beacon_scan_num; 380 u8 pno_enabled; 381 u8 pad2[3]; 382 u8 sparse_channel_valid_num; 383 u8 pad3[3]; 384 u8 channel_num[SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 385 /* idle format for channel_idle_time 386 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms) 387 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms) 388 * 2: dwell time (16us) 389 */ 390 __le16 channel_idle_time[SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 391 /* beacon and probe response count */ 392 u8 beacon_probe_num[SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 393 u8 mdrdy_count[SCAN_DONE_EVENT_MAX_CHANNEL_NUM]; 394 __le32 beacon_2g_num; 395 __le32 beacon_5g_num; 396 } __packed; 397 398 struct mt7615_sched_scan_req { 399 u8 version; 400 u8 seq_num; 401 u8 stop_on_match; 402 u8 ssids_num; 403 u8 match_num; 404 u8 pad; 405 __le16 ie_len; 406 struct mt7615_mcu_scan_ssid ssids[MT7615_MAX_SCHED_SCAN_SSID]; 407 struct mt7615_mcu_scan_match match[MT7615_MAX_SCAN_MATCH]; 408 u8 channel_type; 409 u8 channels_num; 410 u8 intervals_num; 411 u8 scan_func; /* BIT(0) eable random mac address */ 412 struct mt7615_mcu_scan_channel channels[64]; 413 __le16 intervals[MT7615_MAX_SCHED_SCAN_INTERVAL]; 414 u8 random_mac[ETH_ALEN]; /* valid when BIT(0) in scan_func is set */ 415 u8 pad2[58]; 416 } __packed; 417 418 struct nt7615_sched_scan_done { 419 u8 seq_num; 420 u8 status; /* 0: ssid found */ 421 __le16 pad; 422 } __packed; 423 424 struct mt7615_mcu_bss_event { 425 u8 bss_idx; 426 u8 is_absent; 427 u8 free_quota; 428 u8 pad; 429 } __packed; 430 431 struct mt7615_bss_basic_tlv { 432 __le16 tag; 433 __le16 len; 434 u8 active; 435 u8 omac_idx; 436 u8 hw_bss_idx; 437 u8 band_idx; 438 __le32 conn_type; 439 u8 conn_state; 440 u8 wmm_idx; 441 u8 bssid[ETH_ALEN]; 442 __le16 bmc_tx_wlan_idx; 443 __le16 bcn_interval; 444 u8 dtim_period; 445 u8 phymode; /* bit(0): A 446 * bit(1): B 447 * bit(2): G 448 * bit(3): GN 449 * bit(4): AN 450 * bit(5): AC 451 */ 452 __le16 sta_idx; 453 u8 nonht_basic_phy; 454 u8 pad[3]; 455 } __packed; 456 457 struct mt7615_wow_ctrl_tlv { 458 __le16 tag; 459 __le16 len; 460 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START 461 * 0x2: PM_WOWLAN_REQ_STOP 462 * 0x3: PM_WOWLAN_PARAM_CLEAR 463 */ 464 u8 trigger; /* 0: NONE 465 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT 466 * BIT(1): NL80211_WOWLAN_TRIG_ANY 467 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT 468 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE 469 * BIT(4): BEACON_LOST 470 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT 471 */ 472 u8 wakeup_hif; /* 0x0: HIF_SDIO 473 * 0x1: HIF_USB 474 * 0x2: HIF_PCIE 475 * 0x3: HIF_GPIO 476 */ 477 u8 pad; 478 u8 rsv[4]; 479 } __packed; 480 481 #define MT7615_WOW_MASK_MAX_LEN 16 482 #define MT7615_WOW_PATTEN_MAX_LEN 128 483 struct mt7615_wow_pattern_tlv { 484 __le16 tag; 485 __le16 len; 486 u8 index; /* pattern index */ 487 u8 enable; /* 0: disable 488 * 1: enable 489 */ 490 u8 data_len; /* pattern length */ 491 u8 pad; 492 u8 mask[MT7615_WOW_MASK_MAX_LEN]; 493 u8 pattern[MT7615_WOW_PATTEN_MAX_LEN]; 494 u8 rsv[4]; 495 } __packed; 496 497 struct mt7615_suspend_tlv { 498 __le16 tag; 499 __le16 len; 500 u8 enable; /* 0: suspend mode disabled 501 * 1: suspend mode enabled 502 */ 503 u8 mdtim; /* LP parameter */ 504 u8 wow_suspend; /* 0: update by origin policy 505 * 1: update by wow dtim 506 */ 507 u8 pad[5]; 508 } __packed; 509 510 struct mt7615_gtk_rekey_tlv { 511 __le16 tag; 512 __le16 len; 513 u8 kek[NL80211_KEK_LEN]; 514 u8 kck[NL80211_KCK_LEN]; 515 u8 replay_ctr[NL80211_REPLAY_CTR_LEN]; 516 u8 rekey_mode; /* 0: rekey offload enable 517 * 1: rekey offload disable 518 * 2: rekey update 519 */ 520 u8 keyid; 521 u8 pad[2]; 522 __le32 proto; /* WPA-RSN-WAPI-OPSN */ 523 __le32 pairwise_cipher; 524 __le32 group_cipher; 525 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */ 526 __le32 mgmt_group_cipher; 527 u8 option; /* 1: rekey data update without enabling offload */ 528 u8 reserverd[3]; 529 } __packed; 530 531 struct mt7615_roc_tlv { 532 u8 bss_idx; 533 u8 token; 534 u8 active; 535 u8 primary_chan; 536 u8 sco; 537 u8 band; 538 u8 width; /* To support 80/160MHz bandwidth */ 539 u8 freq_seg1; /* To support 80/160MHz bandwidth */ 540 u8 freq_seg2; /* To support 80/160MHz bandwidth */ 541 u8 req_type; 542 u8 dbdc_band; 543 u8 rsv0; 544 __le32 max_interval; /* ms */ 545 u8 rsv1[8]; 546 } __packed; 547 548 /* offload mcu commands */ 549 enum { 550 MCU_CMD_START_HW_SCAN = MCU_CE_PREFIX | 0x03, 551 MCU_CMD_SET_PS_PROFILE = MCU_CE_PREFIX | 0x05, 552 MCU_CMD_SET_CHAN_DOMAIN = MCU_CE_PREFIX | 0x0f, 553 MCU_CMD_SET_BSS_CONNECTED = MCU_CE_PREFIX | 0x16, 554 MCU_CMD_SET_BSS_ABORT = MCU_CE_PREFIX | 0x17, 555 MCU_CMD_CANCEL_HW_SCAN = MCU_CE_PREFIX | 0x1b, 556 MCU_CMD_SET_ROC = MCU_CE_PREFIX | 0x1c, 557 MCU_CMD_SET_P2P_OPPPS = MCU_CE_PREFIX | 0x33, 558 MCU_CMD_SCHED_SCAN_ENABLE = MCU_CE_PREFIX | 0x61, 559 MCU_CMD_SCHED_SCAN_REQ = MCU_CE_PREFIX | 0x62, 560 }; 561 562 #define MCU_CMD_ACK BIT(0) 563 #define MCU_CMD_UNI BIT(1) 564 #define MCU_CMD_QUERY BIT(2) 565 566 #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | MCU_CMD_QUERY) 567 568 enum { 569 UNI_BSS_INFO_BASIC = 0, 570 UNI_BSS_INFO_RLM = 2, 571 UNI_BSS_INFO_BCN_CONTENT = 7, 572 }; 573 574 enum { 575 UNI_SUSPEND_MODE_SETTING, 576 UNI_SUSPEND_WOW_CTRL, 577 UNI_SUSPEND_WOW_GPIO_PARAM, 578 UNI_SUSPEND_WOW_WAKEUP_PORT, 579 UNI_SUSPEND_WOW_PATTERN, 580 }; 581 582 enum { 583 UNI_OFFLOAD_OFFLOAD_ARPNS_IPV4, 584 UNI_OFFLOAD_OFFLOAD_ARPNS_IPV6, 585 UNI_OFFLOAD_OFFLOAD_GTK_REKEY, 586 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT, 587 }; 588 589 enum { 590 PATCH_SEM_RELEASE = 0x0, 591 PATCH_SEM_GET = 0x1 592 }; 593 594 enum { 595 PATCH_NOT_DL_SEM_FAIL = 0x0, 596 PATCH_IS_DL = 0x1, 597 PATCH_NOT_DL_SEM_SUCCESS = 0x2, 598 PATCH_REL_SEM_SUCCESS = 0x3 599 }; 600 601 enum { 602 FW_STATE_INITIAL = 0, 603 FW_STATE_FW_DOWNLOAD = 1, 604 FW_STATE_NORMAL_OPERATION = 2, 605 FW_STATE_NORMAL_TRX = 3, 606 FW_STATE_CR4_RDY = 7 607 }; 608 609 enum { 610 FW_STATE_PWR_ON = 1, 611 FW_STATE_N9_RDY = 2, 612 }; 613 614 #define STA_TYPE_STA BIT(0) 615 #define STA_TYPE_AP BIT(1) 616 #define STA_TYPE_ADHOC BIT(2) 617 #define STA_TYPE_WDS BIT(4) 618 #define STA_TYPE_BC BIT(5) 619 620 #define NETWORK_INFRA BIT(16) 621 #define NETWORK_P2P BIT(17) 622 #define NETWORK_IBSS BIT(18) 623 #define NETWORK_WDS BIT(21) 624 625 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 626 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 627 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 628 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 629 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 630 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 631 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 632 633 #define CONN_STATE_DISCONNECT 0 634 #define CONN_STATE_CONNECT 1 635 #define CONN_STATE_PORT_SECURE 2 636 637 enum { 638 DEV_INFO_ACTIVE, 639 DEV_INFO_MAX_NUM 640 }; 641 642 enum { 643 DBDC_TYPE_WMM, 644 DBDC_TYPE_MGMT, 645 DBDC_TYPE_BSS, 646 DBDC_TYPE_MBSS, 647 DBDC_TYPE_REPEATER, 648 DBDC_TYPE_MU, 649 DBDC_TYPE_BF, 650 DBDC_TYPE_PTA, 651 __DBDC_TYPE_MAX, 652 }; 653 654 struct tlv { 655 __le16 tag; 656 __le16 len; 657 } __packed; 658 659 struct bss_info_omac { 660 __le16 tag; 661 __le16 len; 662 u8 hw_bss_idx; 663 u8 omac_idx; 664 u8 band_idx; 665 u8 rsv0; 666 __le32 conn_type; 667 u32 rsv1; 668 } __packed; 669 670 struct bss_info_basic { 671 __le16 tag; 672 __le16 len; 673 __le32 network_type; 674 u8 active; 675 u8 rsv0; 676 __le16 bcn_interval; 677 u8 bssid[ETH_ALEN]; 678 u8 wmm_idx; 679 u8 dtim_period; 680 u8 bmc_tx_wlan_idx; 681 u8 cipher; /* not used */ 682 u8 phymode; /* not used */ 683 u8 rsv1[5]; 684 } __packed; 685 686 struct bss_info_rf_ch { 687 __le16 tag; 688 __le16 len; 689 u8 pri_ch; 690 u8 central_ch0; 691 u8 central_ch1; 692 u8 bw; 693 } __packed; 694 695 struct bss_info_ext_bss { 696 __le16 tag; 697 __le16 len; 698 __le32 mbss_tsf_offset; /* in unit of us */ 699 u8 rsv[8]; 700 } __packed; 701 702 enum { 703 BSS_INFO_OMAC, 704 BSS_INFO_BASIC, 705 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 706 BSS_INFO_PM, /* sta only */ 707 BSS_INFO_UAPSD, /* sta only */ 708 BSS_INFO_ROAM_DETECTION, /* obsoleted */ 709 BSS_INFO_LQ_RM, /* obsoleted */ 710 BSS_INFO_EXT_BSS, 711 BSS_INFO_BMC_INFO, /* for bmc rate control in CR4 */ 712 BSS_INFO_SYNC_MODE, /* obsoleted */ 713 BSS_INFO_RA, 714 BSS_INFO_MAX_NUM 715 }; 716 717 enum { 718 WTBL_RESET_AND_SET = 1, 719 WTBL_SET, 720 WTBL_QUERY, 721 WTBL_RESET_ALL 722 }; 723 724 struct wtbl_req_hdr { 725 u8 wlan_idx; 726 u8 operation; 727 __le16 tlv_num; 728 u8 rsv[4]; 729 } __packed; 730 731 struct wtbl_generic { 732 __le16 tag; 733 __le16 len; 734 u8 peer_addr[ETH_ALEN]; 735 u8 muar_idx; 736 u8 skip_tx; 737 u8 cf_ack; 738 u8 qos; 739 u8 mesh; 740 u8 adm; 741 __le16 partial_aid; 742 u8 baf_en; 743 u8 aad_om; 744 } __packed; 745 746 struct wtbl_rx { 747 __le16 tag; 748 __le16 len; 749 u8 rcid; 750 u8 rca1; 751 u8 rca2; 752 u8 rv; 753 u8 rsv[4]; 754 } __packed; 755 756 struct wtbl_ht { 757 __le16 tag; 758 __le16 len; 759 u8 ht; 760 u8 ldpc; 761 u8 af; 762 u8 mm; 763 u8 rsv[4]; 764 } __packed; 765 766 struct wtbl_vht { 767 __le16 tag; 768 __le16 len; 769 u8 ldpc; 770 u8 dyn_bw; 771 u8 vht; 772 u8 txop_ps; 773 u8 rsv[4]; 774 } __packed; 775 776 struct wtbl_tx_ps { 777 __le16 tag; 778 __le16 len; 779 u8 txps; 780 u8 rsv[3]; 781 } __packed; 782 783 struct wtbl_hdr_trans { 784 __le16 tag; 785 __le16 len; 786 u8 to_ds; 787 u8 from_ds; 788 u8 disable_rx_trans; 789 u8 rsv; 790 } __packed; 791 792 enum { 793 MT_BA_TYPE_INVALID, 794 MT_BA_TYPE_ORIGINATOR, 795 MT_BA_TYPE_RECIPIENT 796 }; 797 798 enum { 799 RST_BA_MAC_TID_MATCH, 800 RST_BA_MAC_MATCH, 801 RST_BA_NO_MATCH 802 }; 803 804 struct wtbl_ba { 805 __le16 tag; 806 __le16 len; 807 /* common */ 808 u8 tid; 809 u8 ba_type; 810 u8 rsv0[2]; 811 /* originator only */ 812 __le16 sn; 813 u8 ba_en; 814 u8 ba_winsize_idx; 815 __le16 ba_winsize; 816 /* recipient only */ 817 u8 peer_addr[ETH_ALEN]; 818 u8 rst_ba_tid; 819 u8 rst_ba_sel; 820 u8 rst_ba_sb; 821 u8 band_idx; 822 u8 rsv1[4]; 823 } __packed; 824 825 struct wtbl_bf { 826 __le16 tag; 827 __le16 len; 828 u8 ibf; 829 u8 ebf; 830 u8 ibf_vht; 831 u8 ebf_vht; 832 u8 gid; 833 u8 pfmu_idx; 834 u8 rsv[2]; 835 } __packed; 836 837 struct wtbl_smps { 838 __le16 tag; 839 __le16 len; 840 u8 smps; 841 u8 rsv[3]; 842 } __packed; 843 844 struct wtbl_pn { 845 __le16 tag; 846 __le16 len; 847 u8 pn[6]; 848 u8 rsv[2]; 849 } __packed; 850 851 struct wtbl_spe { 852 __le16 tag; 853 __le16 len; 854 u8 spe_idx; 855 u8 rsv[3]; 856 } __packed; 857 858 struct wtbl_raw { 859 __le16 tag; 860 __le16 len; 861 u8 wtbl_idx; 862 u8 dw; 863 u8 rsv[2]; 864 __le32 msk; 865 __le32 val; 866 } __packed; 867 868 #define MT7615_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 869 sizeof(struct wtbl_generic) + \ 870 sizeof(struct wtbl_rx) + \ 871 sizeof(struct wtbl_ht) + \ 872 sizeof(struct wtbl_vht) + \ 873 sizeof(struct wtbl_tx_ps) + \ 874 sizeof(struct wtbl_hdr_trans) +\ 875 sizeof(struct wtbl_ba) + \ 876 sizeof(struct wtbl_bf) + \ 877 sizeof(struct wtbl_smps) + \ 878 sizeof(struct wtbl_pn) + \ 879 sizeof(struct wtbl_spe)) 880 881 #define MT7615_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 882 sizeof(struct sta_rec_basic) + \ 883 sizeof(struct sta_rec_ht) + \ 884 sizeof(struct sta_rec_vht) + \ 885 sizeof(struct tlv) + \ 886 MT7615_WTBL_UPDATE_MAX_SIZE) 887 888 #define MT7615_WTBL_UPDATE_BA_SIZE (sizeof(struct wtbl_req_hdr) + \ 889 sizeof(struct wtbl_ba)) 890 891 enum { 892 WTBL_GENERIC, 893 WTBL_RX, 894 WTBL_HT, 895 WTBL_VHT, 896 WTBL_PEER_PS, /* not used */ 897 WTBL_TX_PS, 898 WTBL_HDR_TRANS, 899 WTBL_SEC_KEY, 900 WTBL_BA, 901 WTBL_RDG, /* obsoleted */ 902 WTBL_PROTECT, /* not used */ 903 WTBL_CLEAR, /* not used */ 904 WTBL_BF, 905 WTBL_SMPS, 906 WTBL_RAW_DATA, /* debug only */ 907 WTBL_PN, 908 WTBL_SPE, 909 WTBL_MAX_NUM 910 }; 911 912 struct sta_ntlv_hdr { 913 u8 rsv[2]; 914 __le16 tlv_num; 915 } __packed; 916 917 struct sta_req_hdr { 918 u8 bss_idx; 919 u8 wlan_idx; 920 __le16 tlv_num; 921 u8 is_tlv_append; 922 u8 muar_idx; 923 u8 rsv[2]; 924 } __packed; 925 926 struct sta_rec_state { 927 __le16 tag; 928 __le16 len; 929 u8 state; 930 __le32 flags; 931 u8 vhtop; 932 u8 pad[2]; 933 } __packed; 934 935 struct sta_rec_basic { 936 __le16 tag; 937 __le16 len; 938 __le32 conn_type; 939 u8 conn_state; 940 u8 qos; 941 __le16 aid; 942 u8 peer_addr[ETH_ALEN]; 943 #define EXTRA_INFO_VER BIT(0) 944 #define EXTRA_INFO_NEW BIT(1) 945 __le16 extra_info; 946 } __packed; 947 948 struct sta_rec_ht { 949 __le16 tag; 950 __le16 len; 951 __le16 ht_cap; 952 u16 rsv; 953 } __packed; 954 955 struct sta_rec_vht { 956 __le16 tag; 957 __le16 len; 958 __le32 vht_cap; 959 __le16 vht_rx_mcs_map; 960 __le16 vht_tx_mcs_map; 961 } __packed; 962 963 struct sta_rec_ba { 964 __le16 tag; 965 __le16 len; 966 u8 tid; 967 u8 ba_type; 968 u8 amsdu; 969 u8 ba_en; 970 __le16 ssn; 971 __le16 winsize; 972 } __packed; 973 974 enum { 975 STA_REC_BASIC, 976 STA_REC_RA, 977 STA_REC_RA_CMM_INFO, 978 STA_REC_RA_UPDATE, 979 STA_REC_BF, 980 STA_REC_AMSDU, /* for CR4 */ 981 STA_REC_BA, 982 STA_REC_STATE, 983 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 984 STA_REC_HT, 985 STA_REC_VHT, 986 STA_REC_APPS, 987 STA_REC_WTBL = 13, 988 STA_REC_MAX_NUM 989 }; 990 991 enum { 992 CMD_CBW_20MHZ, 993 CMD_CBW_40MHZ, 994 CMD_CBW_80MHZ, 995 CMD_CBW_160MHZ, 996 CMD_CBW_10MHZ, 997 CMD_CBW_5MHZ, 998 CMD_CBW_8080MHZ 999 }; 1000 1001 enum { 1002 CH_SWITCH_NORMAL = 0, 1003 CH_SWITCH_SCAN = 3, 1004 CH_SWITCH_MCC = 4, 1005 CH_SWITCH_DFS = 5, 1006 CH_SWITCH_BACKGROUND_SCAN_START = 6, 1007 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 1008 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 1009 CH_SWITCH_SCAN_BYPASS_DPD = 9 1010 }; 1011 1012 #endif 1013