1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Huawei HiNIC PCI Express Linux driver 4 * Copyright(c) 2017 Huawei Technologies Co., Ltd 5 */ 6 7 #ifndef HINIC_HW_DEV_H 8 #define HINIC_HW_DEV_H 9 10 #include <linux/pci.h> 11 #include <linux/types.h> 12 #include <linux/bitops.h> 13 14 #include "hinic_hw_if.h" 15 #include "hinic_hw_eqs.h" 16 #include "hinic_hw_mgmt.h" 17 #include "hinic_hw_qp.h" 18 #include "hinic_hw_io.h" 19 #include "hinic_hw_mbox.h" 20 21 #define HINIC_MAX_QPS 32 22 23 #define HINIC_MGMT_NUM_MSG_CMD (HINIC_MGMT_MSG_CMD_MAX - \ 24 HINIC_MGMT_MSG_CMD_BASE) 25 26 #define HINIC_PF_SET_VF_ALREADY 0x4 27 #define HINIC_MGMT_STATUS_EXIST 0x6 28 #define HINIC_MGMT_CMD_UNSUPPORTED 0xFF 29 30 struct hinic_cap { 31 u16 max_qps; 32 u16 num_qps; 33 u8 max_vf; 34 u16 max_vf_qps; 35 }; 36 37 enum hw_ioctxt_set_cmdq_depth { 38 HW_IOCTXT_SET_CMDQ_DEPTH_DEFAULT, 39 HW_IOCTXT_SET_CMDQ_DEPTH_ENABLE, 40 }; 41 42 enum hinic_port_cmd { 43 HINIC_PORT_CMD_VF_REGISTER = 0x0, 44 HINIC_PORT_CMD_VF_UNREGISTER = 0x1, 45 46 HINIC_PORT_CMD_CHANGE_MTU = 2, 47 48 HINIC_PORT_CMD_ADD_VLAN = 3, 49 HINIC_PORT_CMD_DEL_VLAN = 4, 50 51 HINIC_PORT_CMD_SET_MAC = 9, 52 HINIC_PORT_CMD_GET_MAC = 10, 53 HINIC_PORT_CMD_DEL_MAC = 11, 54 55 HINIC_PORT_CMD_SET_RX_MODE = 12, 56 57 HINIC_PORT_CMD_GET_PAUSE_INFO = 20, 58 HINIC_PORT_CMD_SET_PAUSE_INFO = 21, 59 60 HINIC_PORT_CMD_GET_LINK_STATE = 24, 61 62 HINIC_PORT_CMD_SET_LRO = 25, 63 64 HINIC_PORT_CMD_SET_RX_CSUM = 26, 65 66 HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD = 27, 67 68 HINIC_PORT_CMD_GET_PORT_STATISTICS = 28, 69 70 HINIC_PORT_CMD_CLEAR_PORT_STATISTICS = 29, 71 72 HINIC_PORT_CMD_GET_VPORT_STAT = 30, 73 74 HINIC_PORT_CMD_CLEAN_VPORT_STAT = 31, 75 76 HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 37, 77 78 HINIC_PORT_CMD_SET_PORT_STATE = 41, 79 80 HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL = 43, 81 82 HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL = 44, 83 84 HINIC_PORT_CMD_SET_RSS_HASH_ENGINE = 45, 85 86 HINIC_PORT_CMD_GET_RSS_HASH_ENGINE = 46, 87 88 HINIC_PORT_CMD_GET_RSS_CTX_TBL = 47, 89 90 HINIC_PORT_CMD_SET_RSS_CTX_TBL = 48, 91 92 HINIC_PORT_CMD_RSS_TEMP_MGR = 49, 93 94 HINIC_PORT_CMD_RSS_CFG = 66, 95 96 HINIC_PORT_CMD_FWCTXT_INIT = 69, 97 98 HINIC_PORT_CMD_ENABLE_SPOOFCHK = 78, 99 100 HINIC_PORT_CMD_GET_MGMT_VERSION = 88, 101 102 HINIC_PORT_CMD_SET_FUNC_STATE = 93, 103 104 HINIC_PORT_CMD_GET_GLOBAL_QPN = 102, 105 106 HINIC_PORT_CMD_SET_VF_RATE = 105, 107 108 HINIC_PORT_CMD_SET_VF_VLAN = 106, 109 110 HINIC_PORT_CMD_CLR_VF_VLAN, 111 112 HINIC_PORT_CMD_SET_TSO = 112, 113 114 HINIC_PORT_CMD_SET_RQ_IQ_MAP = 115, 115 116 HINIC_PORT_CMD_LINK_STATUS_REPORT = 160, 117 118 HINIC_PORT_CMD_UPDATE_MAC = 164, 119 120 HINIC_PORT_CMD_GET_CAP = 170, 121 122 HINIC_PORT_CMD_GET_LINK_MODE = 217, 123 124 HINIC_PORT_CMD_SET_SPEED = 218, 125 126 HINIC_PORT_CMD_SET_AUTONEG = 219, 127 128 HINIC_PORT_CMD_SET_LRO_TIMER = 244, 129 130 HINIC_PORT_CMD_SET_VF_MAX_MIN_RATE = 249, 131 }; 132 133 /* cmd of mgmt CPU message for HILINK module */ 134 enum hinic_hilink_cmd { 135 HINIC_HILINK_CMD_GET_LINK_INFO = 0x3, 136 HINIC_HILINK_CMD_SET_LINK_SETTINGS = 0x8, 137 }; 138 139 enum hinic_ucode_cmd { 140 HINIC_UCODE_CMD_MODIFY_QUEUE_CONTEXT = 0, 141 HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT, 142 HINIC_UCODE_CMD_ARM_SQ, 143 HINIC_UCODE_CMD_ARM_RQ, 144 HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE, 145 HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE, 146 HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE, 147 HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE, 148 HINIC_UCODE_CMD_SET_IQ_ENABLE, 149 HINIC_UCODE_CMD_SET_RQ_FLUSH = 10 150 }; 151 152 #define NIC_RSS_CMD_TEMP_ALLOC 0x01 153 #define NIC_RSS_CMD_TEMP_FREE 0x02 154 155 enum hinic_mgmt_msg_cmd { 156 HINIC_MGMT_MSG_CMD_BASE = 160, 157 158 HINIC_MGMT_MSG_CMD_LINK_STATUS = 160, 159 160 HINIC_MGMT_MSG_CMD_MAX, 161 }; 162 163 enum hinic_cb_state { 164 HINIC_CB_ENABLED = BIT(0), 165 HINIC_CB_RUNNING = BIT(1), 166 }; 167 168 enum hinic_res_state { 169 HINIC_RES_CLEAN = 0, 170 HINIC_RES_ACTIVE = 1, 171 }; 172 173 struct hinic_cmd_fw_ctxt { 174 u8 status; 175 u8 version; 176 u8 rsvd0[6]; 177 178 u16 func_idx; 179 u16 rx_buf_sz; 180 181 u32 rsvd1; 182 }; 183 184 struct hinic_cmd_hw_ioctxt { 185 u8 status; 186 u8 version; 187 u8 rsvd0[6]; 188 189 u16 func_idx; 190 191 u16 rsvd1; 192 193 u8 set_cmdq_depth; 194 u8 cmdq_depth; 195 196 u8 lro_en; 197 u8 rsvd3; 198 u8 ppf_idx; 199 u8 rsvd4; 200 201 u16 rq_depth; 202 u16 rx_buf_sz_idx; 203 u16 sq_depth; 204 }; 205 206 struct hinic_cmd_io_status { 207 u8 status; 208 u8 version; 209 u8 rsvd0[6]; 210 211 u16 func_idx; 212 u8 rsvd1; 213 u8 rsvd2; 214 u32 io_status; 215 }; 216 217 struct hinic_cmd_clear_io_res { 218 u8 status; 219 u8 version; 220 u8 rsvd0[6]; 221 222 u16 func_idx; 223 u8 rsvd1; 224 u8 rsvd2; 225 }; 226 227 struct hinic_cmd_set_res_state { 228 u8 status; 229 u8 version; 230 u8 rsvd0[6]; 231 232 u16 func_idx; 233 u8 state; 234 u8 rsvd1; 235 u32 rsvd2; 236 }; 237 238 struct hinic_ceq_ctrl_reg { 239 u8 status; 240 u8 version; 241 u8 rsvd0[6]; 242 243 u16 func_id; 244 u16 q_id; 245 u32 ctrl0; 246 u32 ctrl1; 247 }; 248 249 struct hinic_cmd_base_qpn { 250 u8 status; 251 u8 version; 252 u8 rsvd0[6]; 253 254 u16 func_idx; 255 u16 qpn; 256 }; 257 258 struct hinic_cmd_hw_ci { 259 u8 status; 260 u8 version; 261 u8 rsvd0[6]; 262 263 u16 func_idx; 264 265 u8 dma_attr_off; 266 u8 pending_limit; 267 u8 coalesc_timer; 268 269 u8 msix_en; 270 u16 msix_entry_idx; 271 272 u32 sq_id; 273 u32 rsvd1; 274 u64 ci_addr; 275 }; 276 277 struct hinic_cmd_l2nic_reset { 278 u8 status; 279 u8 version; 280 u8 rsvd0[6]; 281 282 u16 func_id; 283 u16 reset_flag; 284 }; 285 286 struct hinic_hwdev { 287 struct hinic_hwif *hwif; 288 struct msix_entry *msix_entries; 289 290 struct hinic_aeqs aeqs; 291 struct hinic_func_to_io func_to_io; 292 struct hinic_mbox_func_to_func *func_to_func; 293 294 struct hinic_cap nic_cap; 295 }; 296 297 struct hinic_nic_cb { 298 void (*handler)(void *handle, void *buf_in, 299 u16 in_size, void *buf_out, 300 u16 *out_size); 301 302 void *handle; 303 unsigned long cb_state; 304 }; 305 306 struct hinic_pfhwdev { 307 struct hinic_hwdev hwdev; 308 309 struct hinic_pf_to_mgmt pf_to_mgmt; 310 311 struct hinic_nic_cb nic_cb[HINIC_MGMT_NUM_MSG_CMD]; 312 }; 313 314 struct hinic_dev_cap { 315 u8 status; 316 u8 version; 317 u8 rsvd0[6]; 318 319 u8 rsvd1[5]; 320 u8 intr_type; 321 u8 max_cos_id; 322 u8 er_id; 323 u8 port_id; 324 u8 max_vf; 325 u8 rsvd2[62]; 326 u16 max_sqs; 327 u16 max_rqs; 328 u16 max_vf_sqs; 329 u16 max_vf_rqs; 330 u8 rsvd3[204]; 331 }; 332 333 void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev, 334 enum hinic_mgmt_msg_cmd cmd, void *handle, 335 void (*handler)(void *handle, void *buf_in, 336 u16 in_size, void *buf_out, 337 u16 *out_size)); 338 339 void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev, 340 enum hinic_mgmt_msg_cmd cmd); 341 342 int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd, 343 void *buf_in, u16 in_size, void *buf_out, 344 u16 *out_size); 345 346 int hinic_hilink_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_hilink_cmd cmd, 347 void *buf_in, u16 in_size, void *buf_out, 348 u16 *out_size); 349 350 int hinic_hwdev_ifup(struct hinic_hwdev *hwdev, u16 sq_depth, u16 rq_depth); 351 352 void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev); 353 354 struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev); 355 356 void hinic_free_hwdev(struct hinic_hwdev *hwdev); 357 358 int hinic_hwdev_max_num_qps(struct hinic_hwdev *hwdev); 359 360 int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev); 361 362 struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i); 363 364 struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i); 365 366 int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index); 367 368 int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index, 369 u8 pending_limit, u8 coalesc_timer, 370 u8 lli_timer_cfg, u8 lli_credit_limit, 371 u8 resend_timer); 372 373 int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq, 374 u8 pending_limit, u8 coalesc_timer); 375 376 void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index, 377 enum hinic_msix_state flag); 378 379 #endif 380