1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/hdmi.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_hdcp.h> 38 #include <drm/drm_scdc_helper.h> 39 #include <drm/intel_lpe_audio.h> 40 41 #include "i915_debugfs.h" 42 #include "i915_drv.h" 43 #include "intel_atomic.h" 44 #include "intel_audio.h" 45 #include "intel_connector.h" 46 #include "intel_ddi.h" 47 #include "intel_display_debugfs.h" 48 #include "intel_display_types.h" 49 #include "intel_dp.h" 50 #include "intel_dpio_phy.h" 51 #include "intel_fifo_underrun.h" 52 #include "intel_gmbus.h" 53 #include "intel_hdcp.h" 54 #include "intel_hdmi.h" 55 #include "intel_hotplug.h" 56 #include "intel_lspcon.h" 57 #include "intel_panel.h" 58 #include "intel_sdvo.h" 59 #include "intel_sideband.h" 60 61 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 62 { 63 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 64 } 65 66 static void 67 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 68 { 69 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 70 struct drm_i915_private *dev_priv = to_i915(dev); 71 u32 enabled_bits; 72 73 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 74 75 drm_WARN(dev, 76 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, 77 "HDMI port enabled, expecting disabled\n"); 78 } 79 80 static void 81 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, 82 enum transcoder cpu_transcoder) 83 { 84 drm_WARN(&dev_priv->drm, 85 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & 86 TRANS_DDI_FUNC_ENABLE, 87 "HDMI transcoder function enabled, expecting disabled\n"); 88 } 89 90 struct intel_hdmi *enc_to_intel_hdmi(struct intel_encoder *encoder) 91 { 92 struct intel_digital_port *intel_dig_port = 93 container_of(&encoder->base, struct intel_digital_port, 94 base.base); 95 return &intel_dig_port->hdmi; 96 } 97 98 static struct intel_hdmi *intel_attached_hdmi(struct intel_connector *connector) 99 { 100 return enc_to_intel_hdmi(intel_attached_encoder(connector)); 101 } 102 103 static u32 g4x_infoframe_index(unsigned int type) 104 { 105 switch (type) { 106 case HDMI_PACKET_TYPE_GAMUT_METADATA: 107 return VIDEO_DIP_SELECT_GAMUT; 108 case HDMI_INFOFRAME_TYPE_AVI: 109 return VIDEO_DIP_SELECT_AVI; 110 case HDMI_INFOFRAME_TYPE_SPD: 111 return VIDEO_DIP_SELECT_SPD; 112 case HDMI_INFOFRAME_TYPE_VENDOR: 113 return VIDEO_DIP_SELECT_VENDOR; 114 default: 115 MISSING_CASE(type); 116 return 0; 117 } 118 } 119 120 static u32 g4x_infoframe_enable(unsigned int type) 121 { 122 switch (type) { 123 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 124 return VIDEO_DIP_ENABLE_GCP; 125 case HDMI_PACKET_TYPE_GAMUT_METADATA: 126 return VIDEO_DIP_ENABLE_GAMUT; 127 case DP_SDP_VSC: 128 return 0; 129 case HDMI_INFOFRAME_TYPE_AVI: 130 return VIDEO_DIP_ENABLE_AVI; 131 case HDMI_INFOFRAME_TYPE_SPD: 132 return VIDEO_DIP_ENABLE_SPD; 133 case HDMI_INFOFRAME_TYPE_VENDOR: 134 return VIDEO_DIP_ENABLE_VENDOR; 135 case HDMI_INFOFRAME_TYPE_DRM: 136 return 0; 137 default: 138 MISSING_CASE(type); 139 return 0; 140 } 141 } 142 143 static u32 hsw_infoframe_enable(unsigned int type) 144 { 145 switch (type) { 146 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 147 return VIDEO_DIP_ENABLE_GCP_HSW; 148 case HDMI_PACKET_TYPE_GAMUT_METADATA: 149 return VIDEO_DIP_ENABLE_GMP_HSW; 150 case DP_SDP_VSC: 151 return VIDEO_DIP_ENABLE_VSC_HSW; 152 case DP_SDP_PPS: 153 return VDIP_ENABLE_PPS; 154 case HDMI_INFOFRAME_TYPE_AVI: 155 return VIDEO_DIP_ENABLE_AVI_HSW; 156 case HDMI_INFOFRAME_TYPE_SPD: 157 return VIDEO_DIP_ENABLE_SPD_HSW; 158 case HDMI_INFOFRAME_TYPE_VENDOR: 159 return VIDEO_DIP_ENABLE_VS_HSW; 160 case HDMI_INFOFRAME_TYPE_DRM: 161 return VIDEO_DIP_ENABLE_DRM_GLK; 162 default: 163 MISSING_CASE(type); 164 return 0; 165 } 166 } 167 168 static i915_reg_t 169 hsw_dip_data_reg(struct drm_i915_private *dev_priv, 170 enum transcoder cpu_transcoder, 171 unsigned int type, 172 int i) 173 { 174 switch (type) { 175 case HDMI_PACKET_TYPE_GAMUT_METADATA: 176 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); 177 case DP_SDP_VSC: 178 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); 179 case DP_SDP_PPS: 180 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); 181 case HDMI_INFOFRAME_TYPE_AVI: 182 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); 183 case HDMI_INFOFRAME_TYPE_SPD: 184 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); 185 case HDMI_INFOFRAME_TYPE_VENDOR: 186 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); 187 case HDMI_INFOFRAME_TYPE_DRM: 188 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i); 189 default: 190 MISSING_CASE(type); 191 return INVALID_MMIO_REG; 192 } 193 } 194 195 static int hsw_dip_data_size(struct drm_i915_private *dev_priv, 196 unsigned int type) 197 { 198 switch (type) { 199 case DP_SDP_VSC: 200 return VIDEO_DIP_VSC_DATA_SIZE; 201 case DP_SDP_PPS: 202 return VIDEO_DIP_PPS_DATA_SIZE; 203 case HDMI_PACKET_TYPE_GAMUT_METADATA: 204 if (INTEL_GEN(dev_priv) >= 11) 205 return VIDEO_DIP_GMP_DATA_SIZE; 206 else 207 return VIDEO_DIP_DATA_SIZE; 208 default: 209 return VIDEO_DIP_DATA_SIZE; 210 } 211 } 212 213 static void g4x_write_infoframe(struct intel_encoder *encoder, 214 const struct intel_crtc_state *crtc_state, 215 unsigned int type, 216 const void *frame, ssize_t len) 217 { 218 const u32 *data = frame; 219 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 220 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 221 int i; 222 223 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 224 "Writing DIP with CTL reg disabled\n"); 225 226 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 227 val |= g4x_infoframe_index(type); 228 229 val &= ~g4x_infoframe_enable(type); 230 231 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 232 233 for (i = 0; i < len; i += 4) { 234 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data); 235 data++; 236 } 237 /* Write every possible data byte to force correct ECC calculation. */ 238 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 239 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0); 240 241 val |= g4x_infoframe_enable(type); 242 val &= ~VIDEO_DIP_FREQ_MASK; 243 val |= VIDEO_DIP_FREQ_VSYNC; 244 245 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 246 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL); 247 } 248 249 static void g4x_read_infoframe(struct intel_encoder *encoder, 250 const struct intel_crtc_state *crtc_state, 251 unsigned int type, 252 void *frame, ssize_t len) 253 { 254 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 255 u32 val, *data = frame; 256 int i; 257 258 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 259 260 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 261 val |= g4x_infoframe_index(type); 262 263 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 264 265 for (i = 0; i < len; i += 4) 266 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); 267 } 268 269 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 270 const struct intel_crtc_state *pipe_config) 271 { 272 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 273 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 274 275 if ((val & VIDEO_DIP_ENABLE) == 0) 276 return 0; 277 278 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 279 return 0; 280 281 return val & (VIDEO_DIP_ENABLE_AVI | 282 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 283 } 284 285 static void ibx_write_infoframe(struct intel_encoder *encoder, 286 const struct intel_crtc_state *crtc_state, 287 unsigned int type, 288 const void *frame, ssize_t len) 289 { 290 const u32 *data = frame; 291 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 293 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 294 u32 val = intel_de_read(dev_priv, reg); 295 int i; 296 297 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 298 "Writing DIP with CTL reg disabled\n"); 299 300 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 301 val |= g4x_infoframe_index(type); 302 303 val &= ~g4x_infoframe_enable(type); 304 305 intel_de_write(dev_priv, reg, val); 306 307 for (i = 0; i < len; i += 4) { 308 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 309 *data); 310 data++; 311 } 312 /* Write every possible data byte to force correct ECC calculation. */ 313 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 314 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 315 316 val |= g4x_infoframe_enable(type); 317 val &= ~VIDEO_DIP_FREQ_MASK; 318 val |= VIDEO_DIP_FREQ_VSYNC; 319 320 intel_de_write(dev_priv, reg, val); 321 intel_de_posting_read(dev_priv, reg); 322 } 323 324 static void ibx_read_infoframe(struct intel_encoder *encoder, 325 const struct intel_crtc_state *crtc_state, 326 unsigned int type, 327 void *frame, ssize_t len) 328 { 329 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 330 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 331 u32 val, *data = frame; 332 int i; 333 334 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); 335 336 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 337 val |= g4x_infoframe_index(type); 338 339 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); 340 341 for (i = 0; i < len; i += 4) 342 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 343 } 344 345 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 346 const struct intel_crtc_state *pipe_config) 347 { 348 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 349 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 350 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 351 u32 val = intel_de_read(dev_priv, reg); 352 353 if ((val & VIDEO_DIP_ENABLE) == 0) 354 return 0; 355 356 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 357 return 0; 358 359 return val & (VIDEO_DIP_ENABLE_AVI | 360 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 361 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 362 } 363 364 static void cpt_write_infoframe(struct intel_encoder *encoder, 365 const struct intel_crtc_state *crtc_state, 366 unsigned int type, 367 const void *frame, ssize_t len) 368 { 369 const u32 *data = frame; 370 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 372 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 373 u32 val = intel_de_read(dev_priv, reg); 374 int i; 375 376 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 377 "Writing DIP with CTL reg disabled\n"); 378 379 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 380 val |= g4x_infoframe_index(type); 381 382 /* The DIP control register spec says that we need to update the AVI 383 * infoframe without clearing its enable bit */ 384 if (type != HDMI_INFOFRAME_TYPE_AVI) 385 val &= ~g4x_infoframe_enable(type); 386 387 intel_de_write(dev_priv, reg, val); 388 389 for (i = 0; i < len; i += 4) { 390 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 391 *data); 392 data++; 393 } 394 /* Write every possible data byte to force correct ECC calculation. */ 395 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 396 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 397 398 val |= g4x_infoframe_enable(type); 399 val &= ~VIDEO_DIP_FREQ_MASK; 400 val |= VIDEO_DIP_FREQ_VSYNC; 401 402 intel_de_write(dev_priv, reg, val); 403 intel_de_posting_read(dev_priv, reg); 404 } 405 406 static void cpt_read_infoframe(struct intel_encoder *encoder, 407 const struct intel_crtc_state *crtc_state, 408 unsigned int type, 409 void *frame, ssize_t len) 410 { 411 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 412 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 413 u32 val, *data = frame; 414 int i; 415 416 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); 417 418 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 419 val |= g4x_infoframe_index(type); 420 421 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); 422 423 for (i = 0; i < len; i += 4) 424 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 425 } 426 427 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 428 const struct intel_crtc_state *pipe_config) 429 { 430 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 431 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 432 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe)); 433 434 if ((val & VIDEO_DIP_ENABLE) == 0) 435 return 0; 436 437 return val & (VIDEO_DIP_ENABLE_AVI | 438 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 439 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 440 } 441 442 static void vlv_write_infoframe(struct intel_encoder *encoder, 443 const struct intel_crtc_state *crtc_state, 444 unsigned int type, 445 const void *frame, ssize_t len) 446 { 447 const u32 *data = frame; 448 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 450 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 451 u32 val = intel_de_read(dev_priv, reg); 452 int i; 453 454 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 455 "Writing DIP with CTL reg disabled\n"); 456 457 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 458 val |= g4x_infoframe_index(type); 459 460 val &= ~g4x_infoframe_enable(type); 461 462 intel_de_write(dev_priv, reg, val); 463 464 for (i = 0; i < len; i += 4) { 465 intel_de_write(dev_priv, 466 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 467 data++; 468 } 469 /* Write every possible data byte to force correct ECC calculation. */ 470 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 471 intel_de_write(dev_priv, 472 VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); 473 474 val |= g4x_infoframe_enable(type); 475 val &= ~VIDEO_DIP_FREQ_MASK; 476 val |= VIDEO_DIP_FREQ_VSYNC; 477 478 intel_de_write(dev_priv, reg, val); 479 intel_de_posting_read(dev_priv, reg); 480 } 481 482 static void vlv_read_infoframe(struct intel_encoder *encoder, 483 const struct intel_crtc_state *crtc_state, 484 unsigned int type, 485 void *frame, ssize_t len) 486 { 487 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 488 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 489 u32 val, *data = frame; 490 int i; 491 492 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe)); 493 494 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 495 val |= g4x_infoframe_index(type); 496 497 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val); 498 499 for (i = 0; i < len; i += 4) 500 *data++ = intel_de_read(dev_priv, 501 VLV_TVIDEO_DIP_DATA(crtc->pipe)); 502 } 503 504 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 505 const struct intel_crtc_state *pipe_config) 506 { 507 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 508 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 509 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe)); 510 511 if ((val & VIDEO_DIP_ENABLE) == 0) 512 return 0; 513 514 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 515 return 0; 516 517 return val & (VIDEO_DIP_ENABLE_AVI | 518 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 519 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 520 } 521 522 static void hsw_write_infoframe(struct intel_encoder *encoder, 523 const struct intel_crtc_state *crtc_state, 524 unsigned int type, 525 const void *frame, ssize_t len) 526 { 527 const u32 *data = frame; 528 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 529 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 530 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 531 int data_size; 532 int i; 533 u32 val = intel_de_read(dev_priv, ctl_reg); 534 535 data_size = hsw_dip_data_size(dev_priv, type); 536 537 drm_WARN_ON(&dev_priv->drm, len > data_size); 538 539 val &= ~hsw_infoframe_enable(type); 540 intel_de_write(dev_priv, ctl_reg, val); 541 542 for (i = 0; i < len; i += 4) { 543 intel_de_write(dev_priv, 544 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 545 *data); 546 data++; 547 } 548 /* Write every possible data byte to force correct ECC calculation. */ 549 for (; i < data_size; i += 4) 550 intel_de_write(dev_priv, 551 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 552 0); 553 554 val |= hsw_infoframe_enable(type); 555 intel_de_write(dev_priv, ctl_reg, val); 556 intel_de_posting_read(dev_priv, ctl_reg); 557 } 558 559 static void hsw_read_infoframe(struct intel_encoder *encoder, 560 const struct intel_crtc_state *crtc_state, 561 unsigned int type, 562 void *frame, ssize_t len) 563 { 564 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 565 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 566 u32 val, *data = frame; 567 int i; 568 569 val = intel_de_read(dev_priv, HSW_TVIDEO_DIP_CTL(cpu_transcoder)); 570 571 for (i = 0; i < len; i += 4) 572 *data++ = intel_de_read(dev_priv, 573 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2)); 574 } 575 576 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 577 const struct intel_crtc_state *pipe_config) 578 { 579 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 580 u32 val = intel_de_read(dev_priv, 581 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 582 u32 mask; 583 584 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 585 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 586 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 587 588 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 589 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 590 591 return val & mask; 592 } 593 594 static const u8 infoframe_type_to_idx[] = { 595 HDMI_PACKET_TYPE_GENERAL_CONTROL, 596 HDMI_PACKET_TYPE_GAMUT_METADATA, 597 DP_SDP_VSC, 598 HDMI_INFOFRAME_TYPE_AVI, 599 HDMI_INFOFRAME_TYPE_SPD, 600 HDMI_INFOFRAME_TYPE_VENDOR, 601 HDMI_INFOFRAME_TYPE_DRM, 602 }; 603 604 u32 intel_hdmi_infoframe_enable(unsigned int type) 605 { 606 int i; 607 608 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 609 if (infoframe_type_to_idx[i] == type) 610 return BIT(i); 611 } 612 613 return 0; 614 } 615 616 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 617 const struct intel_crtc_state *crtc_state) 618 { 619 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 620 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 621 u32 val, ret = 0; 622 int i; 623 624 val = dig_port->infoframes_enabled(encoder, crtc_state); 625 626 /* map from hardware bits to dip idx */ 627 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 628 unsigned int type = infoframe_type_to_idx[i]; 629 630 if (HAS_DDI(dev_priv)) { 631 if (val & hsw_infoframe_enable(type)) 632 ret |= BIT(i); 633 } else { 634 if (val & g4x_infoframe_enable(type)) 635 ret |= BIT(i); 636 } 637 } 638 639 return ret; 640 } 641 642 /* 643 * The data we write to the DIP data buffer registers is 1 byte bigger than the 644 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 645 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 646 * used for both technologies. 647 * 648 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 649 * DW1: DB3 | DB2 | DB1 | DB0 650 * DW2: DB7 | DB6 | DB5 | DB4 651 * DW3: ... 652 * 653 * (HB is Header Byte, DB is Data Byte) 654 * 655 * The hdmi pack() functions don't know about that hardware specific hole so we 656 * trick them by giving an offset into the buffer and moving back the header 657 * bytes by one. 658 */ 659 static void intel_write_infoframe(struct intel_encoder *encoder, 660 const struct intel_crtc_state *crtc_state, 661 enum hdmi_infoframe_type type, 662 const union hdmi_infoframe *frame) 663 { 664 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 665 u8 buffer[VIDEO_DIP_DATA_SIZE]; 666 ssize_t len; 667 668 if ((crtc_state->infoframes.enable & 669 intel_hdmi_infoframe_enable(type)) == 0) 670 return; 671 672 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) 673 return; 674 675 /* see comment above for the reason for this offset */ 676 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 677 if (drm_WARN_ON(encoder->base.dev, len < 0)) 678 return; 679 680 /* Insert the 'hole' (see big comment above) at position 3 */ 681 memmove(&buffer[0], &buffer[1], 3); 682 buffer[3] = 0; 683 len++; 684 685 intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 686 } 687 688 void intel_read_infoframe(struct intel_encoder *encoder, 689 const struct intel_crtc_state *crtc_state, 690 enum hdmi_infoframe_type type, 691 union hdmi_infoframe *frame) 692 { 693 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 694 u8 buffer[VIDEO_DIP_DATA_SIZE]; 695 int ret; 696 697 if ((crtc_state->infoframes.enable & 698 intel_hdmi_infoframe_enable(type)) == 0) 699 return; 700 701 intel_dig_port->read_infoframe(encoder, crtc_state, 702 type, buffer, sizeof(buffer)); 703 704 /* Fill the 'hole' (see big comment above) at position 3 */ 705 memmove(&buffer[1], &buffer[0], 3); 706 707 /* see comment above for the reason for this offset */ 708 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 709 if (ret) { 710 DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type); 711 return; 712 } 713 714 if (frame->any.type != type) 715 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 716 frame->any.type, type); 717 } 718 719 static bool 720 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 721 struct intel_crtc_state *crtc_state, 722 struct drm_connector_state *conn_state) 723 { 724 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 725 const struct drm_display_mode *adjusted_mode = 726 &crtc_state->hw.adjusted_mode; 727 struct drm_connector *connector = conn_state->connector; 728 int ret; 729 730 if (!crtc_state->has_infoframe) 731 return true; 732 733 crtc_state->infoframes.enable |= 734 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 735 736 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, 737 adjusted_mode); 738 if (ret) 739 return false; 740 741 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 742 frame->colorspace = HDMI_COLORSPACE_YUV420; 743 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 744 frame->colorspace = HDMI_COLORSPACE_YUV444; 745 else 746 frame->colorspace = HDMI_COLORSPACE_RGB; 747 748 drm_hdmi_avi_infoframe_colorspace(frame, conn_state); 749 750 /* nonsense combination */ 751 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 752 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 753 754 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 755 drm_hdmi_avi_infoframe_quant_range(frame, connector, 756 adjusted_mode, 757 crtc_state->limited_color_range ? 758 HDMI_QUANTIZATION_RANGE_LIMITED : 759 HDMI_QUANTIZATION_RANGE_FULL); 760 } else { 761 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 762 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 763 } 764 765 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 766 767 /* TODO: handle pixel repetition for YCBCR420 outputs */ 768 769 ret = hdmi_avi_infoframe_check(frame); 770 if (drm_WARN_ON(encoder->base.dev, ret)) 771 return false; 772 773 return true; 774 } 775 776 static bool 777 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 778 struct intel_crtc_state *crtc_state, 779 struct drm_connector_state *conn_state) 780 { 781 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 782 int ret; 783 784 if (!crtc_state->has_infoframe) 785 return true; 786 787 crtc_state->infoframes.enable |= 788 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 789 790 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 791 if (drm_WARN_ON(encoder->base.dev, ret)) 792 return false; 793 794 frame->sdi = HDMI_SPD_SDI_PC; 795 796 ret = hdmi_spd_infoframe_check(frame); 797 if (drm_WARN_ON(encoder->base.dev, ret)) 798 return false; 799 800 return true; 801 } 802 803 static bool 804 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 805 struct intel_crtc_state *crtc_state, 806 struct drm_connector_state *conn_state) 807 { 808 struct hdmi_vendor_infoframe *frame = 809 &crtc_state->infoframes.hdmi.vendor.hdmi; 810 const struct drm_display_info *info = 811 &conn_state->connector->display_info; 812 int ret; 813 814 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 815 return true; 816 817 crtc_state->infoframes.enable |= 818 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 819 820 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 821 conn_state->connector, 822 &crtc_state->hw.adjusted_mode); 823 if (drm_WARN_ON(encoder->base.dev, ret)) 824 return false; 825 826 ret = hdmi_vendor_infoframe_check(frame); 827 if (drm_WARN_ON(encoder->base.dev, ret)) 828 return false; 829 830 return true; 831 } 832 833 static bool 834 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 835 struct intel_crtc_state *crtc_state, 836 struct drm_connector_state *conn_state) 837 { 838 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 839 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 840 int ret; 841 842 if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))) 843 return true; 844 845 if (!crtc_state->has_infoframe) 846 return true; 847 848 if (!conn_state->hdr_output_metadata) 849 return true; 850 851 crtc_state->infoframes.enable |= 852 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 853 854 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 855 if (ret < 0) { 856 DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n"); 857 return false; 858 } 859 860 ret = hdmi_drm_infoframe_check(frame); 861 if (drm_WARN_ON(&dev_priv->drm, ret)) 862 return false; 863 864 return true; 865 } 866 867 static void g4x_set_infoframes(struct intel_encoder *encoder, 868 bool enable, 869 const struct intel_crtc_state *crtc_state, 870 const struct drm_connector_state *conn_state) 871 { 872 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 873 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 874 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 875 i915_reg_t reg = VIDEO_DIP_CTL; 876 u32 val = intel_de_read(dev_priv, reg); 877 u32 port = VIDEO_DIP_PORT(encoder->port); 878 879 assert_hdmi_port_disabled(intel_hdmi); 880 881 /* If the registers were not initialized yet, they might be zeroes, 882 * which means we're selecting the AVI DIP and we're setting its 883 * frequency to once. This seems to really confuse the HW and make 884 * things stop working (the register spec says the AVI always needs to 885 * be sent every VSync). So here we avoid writing to the register more 886 * than we need and also explicitly select the AVI DIP and explicitly 887 * set its frequency to every VSync. Avoiding to write it twice seems to 888 * be enough to solve the problem, but being defensive shouldn't hurt us 889 * either. */ 890 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 891 892 if (!enable) { 893 if (!(val & VIDEO_DIP_ENABLE)) 894 return; 895 if (port != (val & VIDEO_DIP_PORT_MASK)) { 896 DRM_DEBUG_KMS("video DIP still enabled on port %c\n", 897 (val & VIDEO_DIP_PORT_MASK) >> 29); 898 return; 899 } 900 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 901 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 902 intel_de_write(dev_priv, reg, val); 903 intel_de_posting_read(dev_priv, reg); 904 return; 905 } 906 907 if (port != (val & VIDEO_DIP_PORT_MASK)) { 908 if (val & VIDEO_DIP_ENABLE) { 909 DRM_DEBUG_KMS("video DIP already enabled on port %c\n", 910 (val & VIDEO_DIP_PORT_MASK) >> 29); 911 return; 912 } 913 val &= ~VIDEO_DIP_PORT_MASK; 914 val |= port; 915 } 916 917 val |= VIDEO_DIP_ENABLE; 918 val &= ~(VIDEO_DIP_ENABLE_AVI | 919 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 920 921 intel_de_write(dev_priv, reg, val); 922 intel_de_posting_read(dev_priv, reg); 923 924 intel_write_infoframe(encoder, crtc_state, 925 HDMI_INFOFRAME_TYPE_AVI, 926 &crtc_state->infoframes.avi); 927 intel_write_infoframe(encoder, crtc_state, 928 HDMI_INFOFRAME_TYPE_SPD, 929 &crtc_state->infoframes.spd); 930 intel_write_infoframe(encoder, crtc_state, 931 HDMI_INFOFRAME_TYPE_VENDOR, 932 &crtc_state->infoframes.hdmi); 933 } 934 935 /* 936 * Determine if default_phase=1 can be indicated in the GCP infoframe. 937 * 938 * From HDMI specification 1.4a: 939 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 940 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 941 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 942 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 943 * phase of 0 944 */ 945 static bool gcp_default_phase_possible(int pipe_bpp, 946 const struct drm_display_mode *mode) 947 { 948 unsigned int pixels_per_group; 949 950 switch (pipe_bpp) { 951 case 30: 952 /* 4 pixels in 5 clocks */ 953 pixels_per_group = 4; 954 break; 955 case 36: 956 /* 2 pixels in 3 clocks */ 957 pixels_per_group = 2; 958 break; 959 case 48: 960 /* 1 pixel in 2 clocks */ 961 pixels_per_group = 1; 962 break; 963 default: 964 /* phase information not relevant for 8bpc */ 965 return false; 966 } 967 968 return mode->crtc_hdisplay % pixels_per_group == 0 && 969 mode->crtc_htotal % pixels_per_group == 0 && 970 mode->crtc_hblank_start % pixels_per_group == 0 && 971 mode->crtc_hblank_end % pixels_per_group == 0 && 972 mode->crtc_hsync_start % pixels_per_group == 0 && 973 mode->crtc_hsync_end % pixels_per_group == 0 && 974 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 975 mode->crtc_htotal/2 % pixels_per_group == 0); 976 } 977 978 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 979 const struct intel_crtc_state *crtc_state, 980 const struct drm_connector_state *conn_state) 981 { 982 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 983 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 984 i915_reg_t reg; 985 986 if ((crtc_state->infoframes.enable & 987 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 988 return false; 989 990 if (HAS_DDI(dev_priv)) 991 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 992 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 993 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 994 else if (HAS_PCH_SPLIT(dev_priv)) 995 reg = TVIDEO_DIP_GCP(crtc->pipe); 996 else 997 return false; 998 999 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp); 1000 1001 return true; 1002 } 1003 1004 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 1005 struct intel_crtc_state *crtc_state) 1006 { 1007 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1008 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1009 i915_reg_t reg; 1010 1011 if ((crtc_state->infoframes.enable & 1012 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1013 return; 1014 1015 if (HAS_DDI(dev_priv)) 1016 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 1017 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1018 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1019 else if (HAS_PCH_SPLIT(dev_priv)) 1020 reg = TVIDEO_DIP_GCP(crtc->pipe); 1021 else 1022 return; 1023 1024 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg); 1025 } 1026 1027 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1028 struct intel_crtc_state *crtc_state, 1029 struct drm_connector_state *conn_state) 1030 { 1031 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1032 1033 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) 1034 return; 1035 1036 crtc_state->infoframes.enable |= 1037 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1038 1039 /* Indicate color indication for deep color mode */ 1040 if (crtc_state->pipe_bpp > 24) 1041 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1042 1043 /* Enable default_phase whenever the display mode is suitably aligned */ 1044 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1045 &crtc_state->hw.adjusted_mode)) 1046 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1047 } 1048 1049 static void ibx_set_infoframes(struct intel_encoder *encoder, 1050 bool enable, 1051 const struct intel_crtc_state *crtc_state, 1052 const struct drm_connector_state *conn_state) 1053 { 1054 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1056 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 1057 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 1058 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 1059 u32 val = intel_de_read(dev_priv, reg); 1060 u32 port = VIDEO_DIP_PORT(encoder->port); 1061 1062 assert_hdmi_port_disabled(intel_hdmi); 1063 1064 /* See the big comment in g4x_set_infoframes() */ 1065 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1066 1067 if (!enable) { 1068 if (!(val & VIDEO_DIP_ENABLE)) 1069 return; 1070 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1071 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1072 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1073 intel_de_write(dev_priv, reg, val); 1074 intel_de_posting_read(dev_priv, reg); 1075 return; 1076 } 1077 1078 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1079 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1080 "DIP already enabled on port %c\n", 1081 (val & VIDEO_DIP_PORT_MASK) >> 29); 1082 val &= ~VIDEO_DIP_PORT_MASK; 1083 val |= port; 1084 } 1085 1086 val |= VIDEO_DIP_ENABLE; 1087 val &= ~(VIDEO_DIP_ENABLE_AVI | 1088 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1089 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1090 1091 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1092 val |= VIDEO_DIP_ENABLE_GCP; 1093 1094 intel_de_write(dev_priv, reg, val); 1095 intel_de_posting_read(dev_priv, reg); 1096 1097 intel_write_infoframe(encoder, crtc_state, 1098 HDMI_INFOFRAME_TYPE_AVI, 1099 &crtc_state->infoframes.avi); 1100 intel_write_infoframe(encoder, crtc_state, 1101 HDMI_INFOFRAME_TYPE_SPD, 1102 &crtc_state->infoframes.spd); 1103 intel_write_infoframe(encoder, crtc_state, 1104 HDMI_INFOFRAME_TYPE_VENDOR, 1105 &crtc_state->infoframes.hdmi); 1106 } 1107 1108 static void cpt_set_infoframes(struct intel_encoder *encoder, 1109 bool enable, 1110 const struct intel_crtc_state *crtc_state, 1111 const struct drm_connector_state *conn_state) 1112 { 1113 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1115 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1116 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 1117 u32 val = intel_de_read(dev_priv, reg); 1118 1119 assert_hdmi_port_disabled(intel_hdmi); 1120 1121 /* See the big comment in g4x_set_infoframes() */ 1122 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1123 1124 if (!enable) { 1125 if (!(val & VIDEO_DIP_ENABLE)) 1126 return; 1127 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1128 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1129 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1130 intel_de_write(dev_priv, reg, val); 1131 intel_de_posting_read(dev_priv, reg); 1132 return; 1133 } 1134 1135 /* Set both together, unset both together: see the spec. */ 1136 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1137 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1138 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1139 1140 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1141 val |= VIDEO_DIP_ENABLE_GCP; 1142 1143 intel_de_write(dev_priv, reg, val); 1144 intel_de_posting_read(dev_priv, reg); 1145 1146 intel_write_infoframe(encoder, crtc_state, 1147 HDMI_INFOFRAME_TYPE_AVI, 1148 &crtc_state->infoframes.avi); 1149 intel_write_infoframe(encoder, crtc_state, 1150 HDMI_INFOFRAME_TYPE_SPD, 1151 &crtc_state->infoframes.spd); 1152 intel_write_infoframe(encoder, crtc_state, 1153 HDMI_INFOFRAME_TYPE_VENDOR, 1154 &crtc_state->infoframes.hdmi); 1155 } 1156 1157 static void vlv_set_infoframes(struct intel_encoder *encoder, 1158 bool enable, 1159 const struct intel_crtc_state *crtc_state, 1160 const struct drm_connector_state *conn_state) 1161 { 1162 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); 1164 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1165 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); 1166 u32 val = intel_de_read(dev_priv, reg); 1167 u32 port = VIDEO_DIP_PORT(encoder->port); 1168 1169 assert_hdmi_port_disabled(intel_hdmi); 1170 1171 /* See the big comment in g4x_set_infoframes() */ 1172 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1173 1174 if (!enable) { 1175 if (!(val & VIDEO_DIP_ENABLE)) 1176 return; 1177 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1178 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1179 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1180 intel_de_write(dev_priv, reg, val); 1181 intel_de_posting_read(dev_priv, reg); 1182 return; 1183 } 1184 1185 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1186 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1187 "DIP already enabled on port %c\n", 1188 (val & VIDEO_DIP_PORT_MASK) >> 29); 1189 val &= ~VIDEO_DIP_PORT_MASK; 1190 val |= port; 1191 } 1192 1193 val |= VIDEO_DIP_ENABLE; 1194 val &= ~(VIDEO_DIP_ENABLE_AVI | 1195 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1196 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1197 1198 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1199 val |= VIDEO_DIP_ENABLE_GCP; 1200 1201 intel_de_write(dev_priv, reg, val); 1202 intel_de_posting_read(dev_priv, reg); 1203 1204 intel_write_infoframe(encoder, crtc_state, 1205 HDMI_INFOFRAME_TYPE_AVI, 1206 &crtc_state->infoframes.avi); 1207 intel_write_infoframe(encoder, crtc_state, 1208 HDMI_INFOFRAME_TYPE_SPD, 1209 &crtc_state->infoframes.spd); 1210 intel_write_infoframe(encoder, crtc_state, 1211 HDMI_INFOFRAME_TYPE_VENDOR, 1212 &crtc_state->infoframes.hdmi); 1213 } 1214 1215 static void hsw_set_infoframes(struct intel_encoder *encoder, 1216 bool enable, 1217 const struct intel_crtc_state *crtc_state, 1218 const struct drm_connector_state *conn_state) 1219 { 1220 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1221 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); 1222 u32 val = intel_de_read(dev_priv, reg); 1223 1224 assert_hdmi_transcoder_func_disabled(dev_priv, 1225 crtc_state->cpu_transcoder); 1226 1227 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1228 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1229 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1230 VIDEO_DIP_ENABLE_DRM_GLK); 1231 1232 if (!enable) { 1233 intel_de_write(dev_priv, reg, val); 1234 intel_de_posting_read(dev_priv, reg); 1235 return; 1236 } 1237 1238 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1239 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1240 1241 intel_de_write(dev_priv, reg, val); 1242 intel_de_posting_read(dev_priv, reg); 1243 1244 intel_write_infoframe(encoder, crtc_state, 1245 HDMI_INFOFRAME_TYPE_AVI, 1246 &crtc_state->infoframes.avi); 1247 intel_write_infoframe(encoder, crtc_state, 1248 HDMI_INFOFRAME_TYPE_SPD, 1249 &crtc_state->infoframes.spd); 1250 intel_write_infoframe(encoder, crtc_state, 1251 HDMI_INFOFRAME_TYPE_VENDOR, 1252 &crtc_state->infoframes.hdmi); 1253 intel_write_infoframe(encoder, crtc_state, 1254 HDMI_INFOFRAME_TYPE_DRM, 1255 &crtc_state->infoframes.drm); 1256 } 1257 1258 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1259 { 1260 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 1261 struct i2c_adapter *adapter = 1262 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 1263 1264 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1265 return; 1266 1267 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", 1268 enable ? "Enabling" : "Disabling"); 1269 1270 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, 1271 adapter, enable); 1272 } 1273 1274 static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, 1275 unsigned int offset, void *buffer, size_t size) 1276 { 1277 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); 1278 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1279 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1280 hdmi->ddc_bus); 1281 int ret; 1282 u8 start = offset & 0xff; 1283 struct i2c_msg msgs[] = { 1284 { 1285 .addr = DRM_HDCP_DDC_ADDR, 1286 .flags = 0, 1287 .len = 1, 1288 .buf = &start, 1289 }, 1290 { 1291 .addr = DRM_HDCP_DDC_ADDR, 1292 .flags = I2C_M_RD, 1293 .len = size, 1294 .buf = buffer 1295 } 1296 }; 1297 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); 1298 if (ret == ARRAY_SIZE(msgs)) 1299 return 0; 1300 return ret >= 0 ? -EIO : ret; 1301 } 1302 1303 static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port, 1304 unsigned int offset, void *buffer, size_t size) 1305 { 1306 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); 1307 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1308 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1309 hdmi->ddc_bus); 1310 int ret; 1311 u8 *write_buf; 1312 struct i2c_msg msg; 1313 1314 write_buf = kzalloc(size + 1, GFP_KERNEL); 1315 if (!write_buf) 1316 return -ENOMEM; 1317 1318 write_buf[0] = offset & 0xff; 1319 memcpy(&write_buf[1], buffer, size); 1320 1321 msg.addr = DRM_HDCP_DDC_ADDR; 1322 msg.flags = 0, 1323 msg.len = size + 1, 1324 msg.buf = write_buf; 1325 1326 ret = i2c_transfer(adapter, &msg, 1); 1327 if (ret == 1) 1328 ret = 0; 1329 else if (ret >= 0) 1330 ret = -EIO; 1331 1332 kfree(write_buf); 1333 return ret; 1334 } 1335 1336 static 1337 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, 1338 u8 *an) 1339 { 1340 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); 1341 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1342 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1343 hdmi->ddc_bus); 1344 int ret; 1345 1346 ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an, 1347 DRM_HDCP_AN_LEN); 1348 if (ret) { 1349 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret); 1350 return ret; 1351 } 1352 1353 ret = intel_gmbus_output_aksv(adapter); 1354 if (ret < 0) { 1355 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret); 1356 return ret; 1357 } 1358 return 0; 1359 } 1360 1361 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, 1362 u8 *bksv) 1363 { 1364 int ret; 1365 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv, 1366 DRM_HDCP_KSV_LEN); 1367 if (ret) 1368 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret); 1369 return ret; 1370 } 1371 1372 static 1373 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, 1374 u8 *bstatus) 1375 { 1376 int ret; 1377 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS, 1378 bstatus, DRM_HDCP_BSTATUS_LEN); 1379 if (ret) 1380 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret); 1381 return ret; 1382 } 1383 1384 static 1385 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, 1386 bool *repeater_present) 1387 { 1388 int ret; 1389 u8 val; 1390 1391 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1392 if (ret) { 1393 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); 1394 return ret; 1395 } 1396 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1397 return 0; 1398 } 1399 1400 static 1401 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, 1402 u8 *ri_prime) 1403 { 1404 int ret; 1405 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME, 1406 ri_prime, DRM_HDCP_RI_LEN); 1407 if (ret) 1408 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret); 1409 return ret; 1410 } 1411 1412 static 1413 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, 1414 bool *ksv_ready) 1415 { 1416 int ret; 1417 u8 val; 1418 1419 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1420 if (ret) { 1421 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); 1422 return ret; 1423 } 1424 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1425 return 0; 1426 } 1427 1428 static 1429 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, 1430 int num_downstream, u8 *ksv_fifo) 1431 { 1432 int ret; 1433 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO, 1434 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1435 if (ret) { 1436 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret); 1437 return ret; 1438 } 1439 return 0; 1440 } 1441 1442 static 1443 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, 1444 int i, u32 *part) 1445 { 1446 int ret; 1447 1448 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1449 return -EINVAL; 1450 1451 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i), 1452 part, DRM_HDCP_V_PRIME_PART_LEN); 1453 if (ret) 1454 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret); 1455 return ret; 1456 } 1457 1458 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) 1459 { 1460 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1461 struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); 1462 struct drm_crtc *crtc = connector->base.state->crtc; 1463 struct intel_crtc *intel_crtc = container_of(crtc, 1464 struct intel_crtc, base); 1465 u32 scanline; 1466 int ret; 1467 1468 for (;;) { 1469 scanline = intel_de_read(dev_priv, PIPEDSL(intel_crtc->pipe)); 1470 if (scanline > 100 && scanline < 200) 1471 break; 1472 usleep_range(25, 50); 1473 } 1474 1475 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false); 1476 if (ret) { 1477 DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret); 1478 return ret; 1479 } 1480 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true); 1481 if (ret) { 1482 DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret); 1483 return ret; 1484 } 1485 1486 return 0; 1487 } 1488 1489 static 1490 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, 1491 bool enable) 1492 { 1493 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1494 struct intel_connector *connector = hdmi->attached_connector; 1495 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1496 int ret; 1497 1498 if (!enable) 1499 usleep_range(6, 60); /* Bspec says >= 6us */ 1500 1501 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable); 1502 if (ret) { 1503 DRM_ERROR("%s HDCP signalling failed (%d)\n", 1504 enable ? "Enable" : "Disable", ret); 1505 return ret; 1506 } 1507 1508 /* 1509 * WA: To fix incorrect positioning of the window of 1510 * opportunity and enc_en signalling in KABYLAKE. 1511 */ 1512 if (IS_KABYLAKE(dev_priv) && enable) 1513 return kbl_repositioning_enc_en_signal(connector); 1514 1515 return 0; 1516 } 1517 1518 static 1519 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) 1520 { 1521 struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); 1522 struct intel_connector *connector = 1523 intel_dig_port->hdmi.attached_connector; 1524 enum port port = intel_dig_port->base.port; 1525 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1526 int ret; 1527 union { 1528 u32 reg; 1529 u8 shim[DRM_HDCP_RI_LEN]; 1530 } ri; 1531 1532 ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim); 1533 if (ret) 1534 return false; 1535 1536 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg); 1537 1538 /* Wait for Ri prime match */ 1539 if (wait_for(intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & 1540 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { 1541 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n", 1542 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port))); 1543 return false; 1544 } 1545 return true; 1546 } 1547 1548 struct hdcp2_hdmi_msg_timeout { 1549 u8 msg_id; 1550 u16 timeout; 1551 }; 1552 1553 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1554 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1555 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1556 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1557 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1558 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1559 }; 1560 1561 static 1562 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, 1563 u8 *rx_status) 1564 { 1565 return intel_hdmi_hdcp_read(intel_dig_port, 1566 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1567 rx_status, 1568 HDCP_2_2_HDMI_RXSTATUS_LEN); 1569 } 1570 1571 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1572 { 1573 int i; 1574 1575 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1576 if (is_paired) 1577 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1578 else 1579 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1580 } 1581 1582 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1583 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1584 return hdcp2_msg_timeout[i].timeout; 1585 } 1586 1587 return -EINVAL; 1588 } 1589 1590 static inline 1591 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port, 1592 u8 msg_id, bool *msg_ready, 1593 ssize_t *msg_sz) 1594 { 1595 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1596 int ret; 1597 1598 ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status); 1599 if (ret < 0) { 1600 DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret); 1601 return ret; 1602 } 1603 1604 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1605 rx_status[0]); 1606 1607 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1608 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1609 *msg_sz); 1610 else 1611 *msg_ready = *msg_sz; 1612 1613 return 0; 1614 } 1615 1616 static ssize_t 1617 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, 1618 u8 msg_id, bool paired) 1619 { 1620 bool msg_ready = false; 1621 int timeout, ret; 1622 ssize_t msg_sz = 0; 1623 1624 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1625 if (timeout < 0) 1626 return timeout; 1627 1628 ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port, 1629 msg_id, &msg_ready, 1630 &msg_sz), 1631 !ret && msg_ready && msg_sz, timeout * 1000, 1632 1000, 5 * 1000); 1633 if (ret) 1634 DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n", 1635 msg_id, ret, timeout); 1636 1637 return ret ? ret : msg_sz; 1638 } 1639 1640 static 1641 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, 1642 void *buf, size_t size) 1643 { 1644 unsigned int offset; 1645 1646 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1647 return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size); 1648 } 1649 1650 static 1651 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, 1652 u8 msg_id, void *buf, size_t size) 1653 { 1654 struct intel_hdmi *hdmi = &intel_dig_port->hdmi; 1655 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1656 unsigned int offset; 1657 ssize_t ret; 1658 1659 ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id, 1660 hdcp->is_paired); 1661 if (ret < 0) 1662 return ret; 1663 1664 /* 1665 * Available msg size should be equal to or lesser than the 1666 * available buffer. 1667 */ 1668 if (ret > size) { 1669 DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n", 1670 ret, size); 1671 return -1; 1672 } 1673 1674 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1675 ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret); 1676 if (ret) 1677 DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret); 1678 1679 return ret; 1680 } 1681 1682 static 1683 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port) 1684 { 1685 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1686 int ret; 1687 1688 ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status); 1689 if (ret) 1690 return ret; 1691 1692 /* 1693 * Re-auth request and Link Integrity Failures are represented by 1694 * same bit. i.e reauth_req. 1695 */ 1696 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1697 ret = HDCP_REAUTH_REQUEST; 1698 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1699 ret = HDCP_TOPOLOGY_CHANGE; 1700 1701 return ret; 1702 } 1703 1704 static 1705 int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port, 1706 bool *capable) 1707 { 1708 u8 hdcp2_version; 1709 int ret; 1710 1711 *capable = false; 1712 ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1713 &hdcp2_version, sizeof(hdcp2_version)); 1714 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1715 *capable = true; 1716 1717 return ret; 1718 } 1719 1720 static inline 1721 enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void) 1722 { 1723 return HDCP_PROTOCOL_HDMI; 1724 } 1725 1726 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1727 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1728 .read_bksv = intel_hdmi_hdcp_read_bksv, 1729 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1730 .repeater_present = intel_hdmi_hdcp_repeater_present, 1731 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1732 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1733 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1734 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1735 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1736 .check_link = intel_hdmi_hdcp_check_link, 1737 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1738 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1739 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1740 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable, 1741 .protocol = HDCP_PROTOCOL_HDMI, 1742 }; 1743 1744 static void intel_hdmi_prepare(struct intel_encoder *encoder, 1745 const struct intel_crtc_state *crtc_state) 1746 { 1747 struct drm_device *dev = encoder->base.dev; 1748 struct drm_i915_private *dev_priv = to_i915(dev); 1749 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1750 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1751 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 1752 u32 hdmi_val; 1753 1754 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 1755 1756 hdmi_val = SDVO_ENCODING_HDMI; 1757 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) 1758 hdmi_val |= HDMI_COLOR_RANGE_16_235; 1759 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 1760 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; 1761 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 1762 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; 1763 1764 if (crtc_state->pipe_bpp > 24) 1765 hdmi_val |= HDMI_COLOR_FORMAT_12bpc; 1766 else 1767 hdmi_val |= SDVO_COLOR_FORMAT_8bpc; 1768 1769 if (crtc_state->has_hdmi_sink) 1770 hdmi_val |= HDMI_MODE_SELECT_HDMI; 1771 1772 if (HAS_PCH_CPT(dev_priv)) 1773 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); 1774 else if (IS_CHERRYVIEW(dev_priv)) 1775 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); 1776 else 1777 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); 1778 1779 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val); 1780 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1781 } 1782 1783 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, 1784 enum pipe *pipe) 1785 { 1786 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1787 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1788 intel_wakeref_t wakeref; 1789 bool ret; 1790 1791 wakeref = intel_display_power_get_if_enabled(dev_priv, 1792 encoder->power_domain); 1793 if (!wakeref) 1794 return false; 1795 1796 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); 1797 1798 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1799 1800 return ret; 1801 } 1802 1803 static void intel_hdmi_get_config(struct intel_encoder *encoder, 1804 struct intel_crtc_state *pipe_config) 1805 { 1806 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1807 struct drm_device *dev = encoder->base.dev; 1808 struct drm_i915_private *dev_priv = to_i915(dev); 1809 u32 tmp, flags = 0; 1810 int dotclock; 1811 1812 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); 1813 1814 tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 1815 1816 if (tmp & SDVO_HSYNC_ACTIVE_HIGH) 1817 flags |= DRM_MODE_FLAG_PHSYNC; 1818 else 1819 flags |= DRM_MODE_FLAG_NHSYNC; 1820 1821 if (tmp & SDVO_VSYNC_ACTIVE_HIGH) 1822 flags |= DRM_MODE_FLAG_PVSYNC; 1823 else 1824 flags |= DRM_MODE_FLAG_NVSYNC; 1825 1826 if (tmp & HDMI_MODE_SELECT_HDMI) 1827 pipe_config->has_hdmi_sink = true; 1828 1829 pipe_config->infoframes.enable |= 1830 intel_hdmi_infoframes_enabled(encoder, pipe_config); 1831 1832 if (pipe_config->infoframes.enable) 1833 pipe_config->has_infoframe = true; 1834 1835 if (tmp & HDMI_AUDIO_ENABLE) 1836 pipe_config->has_audio = true; 1837 1838 if (!HAS_PCH_SPLIT(dev_priv) && 1839 tmp & HDMI_COLOR_RANGE_16_235) 1840 pipe_config->limited_color_range = true; 1841 1842 pipe_config->hw.adjusted_mode.flags |= flags; 1843 1844 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) 1845 dotclock = pipe_config->port_clock * 2 / 3; 1846 else 1847 dotclock = pipe_config->port_clock; 1848 1849 if (pipe_config->pixel_multiplier) 1850 dotclock /= pipe_config->pixel_multiplier; 1851 1852 pipe_config->hw.adjusted_mode.crtc_clock = dotclock; 1853 1854 pipe_config->lane_count = 4; 1855 1856 intel_hdmi_read_gcp_infoframe(encoder, pipe_config); 1857 1858 intel_read_infoframe(encoder, pipe_config, 1859 HDMI_INFOFRAME_TYPE_AVI, 1860 &pipe_config->infoframes.avi); 1861 intel_read_infoframe(encoder, pipe_config, 1862 HDMI_INFOFRAME_TYPE_SPD, 1863 &pipe_config->infoframes.spd); 1864 intel_read_infoframe(encoder, pipe_config, 1865 HDMI_INFOFRAME_TYPE_VENDOR, 1866 &pipe_config->infoframes.hdmi); 1867 } 1868 1869 static void intel_enable_hdmi_audio(struct intel_encoder *encoder, 1870 const struct intel_crtc_state *pipe_config, 1871 const struct drm_connector_state *conn_state) 1872 { 1873 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1874 1875 drm_WARN_ON(encoder->base.dev, !pipe_config->has_hdmi_sink); 1876 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", 1877 pipe_name(crtc->pipe)); 1878 intel_audio_codec_enable(encoder, pipe_config, conn_state); 1879 } 1880 1881 static void g4x_enable_hdmi(struct intel_encoder *encoder, 1882 const struct intel_crtc_state *pipe_config, 1883 const struct drm_connector_state *conn_state) 1884 { 1885 struct drm_device *dev = encoder->base.dev; 1886 struct drm_i915_private *dev_priv = to_i915(dev); 1887 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1888 u32 temp; 1889 1890 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 1891 1892 temp |= SDVO_ENABLE; 1893 if (pipe_config->has_audio) 1894 temp |= HDMI_AUDIO_ENABLE; 1895 1896 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1897 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1898 1899 if (pipe_config->has_audio) 1900 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 1901 } 1902 1903 static void ibx_enable_hdmi(struct intel_encoder *encoder, 1904 const struct intel_crtc_state *pipe_config, 1905 const struct drm_connector_state *conn_state) 1906 { 1907 struct drm_device *dev = encoder->base.dev; 1908 struct drm_i915_private *dev_priv = to_i915(dev); 1909 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1910 u32 temp; 1911 1912 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 1913 1914 temp |= SDVO_ENABLE; 1915 if (pipe_config->has_audio) 1916 temp |= HDMI_AUDIO_ENABLE; 1917 1918 /* 1919 * HW workaround, need to write this twice for issue 1920 * that may result in first write getting masked. 1921 */ 1922 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1923 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1924 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1925 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1926 1927 /* 1928 * HW workaround, need to toggle enable bit off and on 1929 * for 12bpc with pixel repeat. 1930 * 1931 * FIXME: BSpec says this should be done at the end of 1932 * of the modeset sequence, so not sure if this isn't too soon. 1933 */ 1934 if (pipe_config->pipe_bpp > 24 && 1935 pipe_config->pixel_multiplier > 1) { 1936 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, 1937 temp & ~SDVO_ENABLE); 1938 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1939 1940 /* 1941 * HW workaround, need to write this twice for issue 1942 * that may result in first write getting masked. 1943 */ 1944 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1945 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1946 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1947 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1948 } 1949 1950 if (pipe_config->has_audio) 1951 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 1952 } 1953 1954 static void cpt_enable_hdmi(struct intel_encoder *encoder, 1955 const struct intel_crtc_state *pipe_config, 1956 const struct drm_connector_state *conn_state) 1957 { 1958 struct drm_device *dev = encoder->base.dev; 1959 struct drm_i915_private *dev_priv = to_i915(dev); 1960 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1961 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1962 enum pipe pipe = crtc->pipe; 1963 u32 temp; 1964 1965 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 1966 1967 temp |= SDVO_ENABLE; 1968 if (pipe_config->has_audio) 1969 temp |= HDMI_AUDIO_ENABLE; 1970 1971 /* 1972 * WaEnableHDMI8bpcBefore12bpc:snb,ivb 1973 * 1974 * The procedure for 12bpc is as follows: 1975 * 1. disable HDMI clock gating 1976 * 2. enable HDMI with 8bpc 1977 * 3. enable HDMI with 12bpc 1978 * 4. enable HDMI clock gating 1979 */ 1980 1981 if (pipe_config->pipe_bpp > 24) { 1982 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), 1983 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 1984 1985 temp &= ~SDVO_COLOR_FORMAT_MASK; 1986 temp |= SDVO_COLOR_FORMAT_8bpc; 1987 } 1988 1989 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1990 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1991 1992 if (pipe_config->pipe_bpp > 24) { 1993 temp &= ~SDVO_COLOR_FORMAT_MASK; 1994 temp |= HDMI_COLOR_FORMAT_12bpc; 1995 1996 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 1997 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 1998 1999 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), 2000 intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); 2001 } 2002 2003 if (pipe_config->has_audio) 2004 intel_enable_hdmi_audio(encoder, pipe_config, conn_state); 2005 } 2006 2007 static void vlv_enable_hdmi(struct intel_encoder *encoder, 2008 const struct intel_crtc_state *pipe_config, 2009 const struct drm_connector_state *conn_state) 2010 { 2011 } 2012 2013 static void intel_disable_hdmi(struct intel_encoder *encoder, 2014 const struct intel_crtc_state *old_crtc_state, 2015 const struct drm_connector_state *old_conn_state) 2016 { 2017 struct drm_device *dev = encoder->base.dev; 2018 struct drm_i915_private *dev_priv = to_i915(dev); 2019 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2020 struct intel_digital_port *intel_dig_port = 2021 hdmi_to_dig_port(intel_hdmi); 2022 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 2023 u32 temp; 2024 2025 temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); 2026 2027 temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE); 2028 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2029 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2030 2031 /* 2032 * HW workaround for IBX, we need to move the port 2033 * to transcoder A after disabling it to allow the 2034 * matching DP port to be enabled on transcoder A. 2035 */ 2036 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { 2037 /* 2038 * We get CPU/PCH FIFO underruns on the other pipe when 2039 * doing the workaround. Sweep them under the rug. 2040 */ 2041 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 2042 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 2043 2044 temp &= ~SDVO_PIPE_SEL_MASK; 2045 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); 2046 /* 2047 * HW workaround, need to write this twice for issue 2048 * that may result in first write getting masked. 2049 */ 2050 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2051 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2052 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2053 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2054 2055 temp &= ~SDVO_ENABLE; 2056 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); 2057 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); 2058 2059 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 2060 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 2061 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 2062 } 2063 2064 intel_dig_port->set_infoframes(encoder, 2065 false, 2066 old_crtc_state, old_conn_state); 2067 2068 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); 2069 } 2070 2071 static void g4x_disable_hdmi(struct intel_encoder *encoder, 2072 const struct intel_crtc_state *old_crtc_state, 2073 const struct drm_connector_state *old_conn_state) 2074 { 2075 if (old_crtc_state->has_audio) 2076 intel_audio_codec_disable(encoder, 2077 old_crtc_state, old_conn_state); 2078 2079 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); 2080 } 2081 2082 static void pch_disable_hdmi(struct intel_encoder *encoder, 2083 const struct intel_crtc_state *old_crtc_state, 2084 const struct drm_connector_state *old_conn_state) 2085 { 2086 if (old_crtc_state->has_audio) 2087 intel_audio_codec_disable(encoder, 2088 old_crtc_state, old_conn_state); 2089 } 2090 2091 static void pch_post_disable_hdmi(struct intel_encoder *encoder, 2092 const struct intel_crtc_state *old_crtc_state, 2093 const struct drm_connector_state *old_conn_state) 2094 { 2095 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); 2096 } 2097 2098 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 2099 { 2100 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2101 int max_tmds_clock, vbt_max_tmds_clock; 2102 2103 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2104 max_tmds_clock = 594000; 2105 else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) 2106 max_tmds_clock = 300000; 2107 else if (INTEL_GEN(dev_priv) >= 5) 2108 max_tmds_clock = 225000; 2109 else 2110 max_tmds_clock = 165000; 2111 2112 vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder); 2113 if (vbt_max_tmds_clock) 2114 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); 2115 2116 return max_tmds_clock; 2117 } 2118 2119 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, 2120 const struct drm_connector_state *conn_state) 2121 { 2122 return hdmi->has_hdmi_sink && 2123 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 2124 } 2125 2126 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 2127 bool respect_downstream_limits, 2128 bool has_hdmi_sink) 2129 { 2130 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 2131 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 2132 2133 if (respect_downstream_limits) { 2134 struct intel_connector *connector = hdmi->attached_connector; 2135 const struct drm_display_info *info = &connector->base.display_info; 2136 2137 if (hdmi->dp_dual_mode.max_tmds_clock) 2138 max_tmds_clock = min(max_tmds_clock, 2139 hdmi->dp_dual_mode.max_tmds_clock); 2140 2141 if (info->max_tmds_clock) 2142 max_tmds_clock = min(max_tmds_clock, 2143 info->max_tmds_clock); 2144 else if (!has_hdmi_sink) 2145 max_tmds_clock = min(max_tmds_clock, 165000); 2146 } 2147 2148 return max_tmds_clock; 2149 } 2150 2151 static enum drm_mode_status 2152 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 2153 int clock, bool respect_downstream_limits, 2154 bool has_hdmi_sink) 2155 { 2156 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 2157 2158 if (clock < 25000) 2159 return MODE_CLOCK_LOW; 2160 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, 2161 has_hdmi_sink)) 2162 return MODE_CLOCK_HIGH; 2163 2164 /* BXT DPLL can't generate 223-240 MHz */ 2165 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) 2166 return MODE_CLOCK_RANGE; 2167 2168 /* CHV DPLL can't generate 216-240 MHz */ 2169 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) 2170 return MODE_CLOCK_RANGE; 2171 2172 return MODE_OK; 2173 } 2174 2175 static enum drm_mode_status 2176 intel_hdmi_mode_valid(struct drm_connector *connector, 2177 struct drm_display_mode *mode) 2178 { 2179 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2180 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 2181 struct drm_i915_private *dev_priv = to_i915(dev); 2182 enum drm_mode_status status; 2183 int clock = mode->clock; 2184 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 2185 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); 2186 2187 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 2188 return MODE_NO_DBLESCAN; 2189 2190 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 2191 clock *= 2; 2192 2193 if (clock > max_dotclk) 2194 return MODE_CLOCK_HIGH; 2195 2196 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2197 clock *= 2; 2198 2199 if (drm_mode_is_420_only(&connector->display_info, mode)) 2200 clock /= 2; 2201 2202 /* check if we can do 8bpc */ 2203 status = hdmi_port_clock_valid(hdmi, clock, true, has_hdmi_sink); 2204 2205 if (has_hdmi_sink) { 2206 /* if we can't do 8bpc we may still be able to do 12bpc */ 2207 if (status != MODE_OK && !HAS_GMCH(dev_priv)) 2208 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, 2209 true, has_hdmi_sink); 2210 2211 /* if we can't do 8,12bpc we may still be able to do 10bpc */ 2212 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11) 2213 status = hdmi_port_clock_valid(hdmi, clock * 5 / 4, 2214 true, has_hdmi_sink); 2215 } 2216 if (status != MODE_OK) 2217 return status; 2218 2219 return intel_mode_valid_max_plane_size(dev_priv, mode); 2220 } 2221 2222 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, 2223 int bpc) 2224 { 2225 struct drm_i915_private *dev_priv = 2226 to_i915(crtc_state->uapi.crtc->dev); 2227 struct drm_atomic_state *state = crtc_state->uapi.state; 2228 struct drm_connector_state *connector_state; 2229 struct drm_connector *connector; 2230 const struct drm_display_mode *adjusted_mode = 2231 &crtc_state->hw.adjusted_mode; 2232 int i; 2233 2234 if (HAS_GMCH(dev_priv)) 2235 return false; 2236 2237 if (bpc == 10 && INTEL_GEN(dev_priv) < 11) 2238 return false; 2239 2240 if (crtc_state->pipe_bpp < bpc * 3) 2241 return false; 2242 2243 if (!crtc_state->has_hdmi_sink) 2244 return false; 2245 2246 /* 2247 * HDMI deep color affects the clocks, so it's only possible 2248 * when not cloning with other encoder types. 2249 */ 2250 if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI) 2251 return false; 2252 2253 for_each_new_connector_in_state(state, connector, connector_state, i) { 2254 const struct drm_display_info *info = &connector->display_info; 2255 2256 if (connector_state->crtc != crtc_state->uapi.crtc) 2257 continue; 2258 2259 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 2260 const struct drm_hdmi_info *hdmi = &info->hdmi; 2261 2262 if (bpc == 12 && !(hdmi->y420_dc_modes & 2263 DRM_EDID_YCBCR420_DC_36)) 2264 return false; 2265 else if (bpc == 10 && !(hdmi->y420_dc_modes & 2266 DRM_EDID_YCBCR420_DC_30)) 2267 return false; 2268 } else { 2269 if (bpc == 12 && !(info->edid_hdmi_dc_modes & 2270 DRM_EDID_HDMI_DC_36)) 2271 return false; 2272 else if (bpc == 10 && !(info->edid_hdmi_dc_modes & 2273 DRM_EDID_HDMI_DC_30)) 2274 return false; 2275 } 2276 } 2277 2278 /* Display Wa_1405510057:icl,ehl */ 2279 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 2280 bpc == 10 && IS_GEN(dev_priv, 11) && 2281 (adjusted_mode->crtc_hblank_end - 2282 adjusted_mode->crtc_hblank_start) % 8 == 2) 2283 return false; 2284 2285 return true; 2286 } 2287 2288 static bool 2289 intel_hdmi_ycbcr420_config(struct drm_connector *connector, 2290 struct intel_crtc_state *config) 2291 { 2292 struct intel_crtc *intel_crtc = to_intel_crtc(config->uapi.crtc); 2293 2294 if (!connector->ycbcr_420_allowed) { 2295 DRM_ERROR("Platform doesn't support YCBCR420 output\n"); 2296 return false; 2297 } 2298 2299 config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2300 2301 /* YCBCR 420 output conversion needs a scaler */ 2302 if (skl_update_scaler_crtc(config)) { 2303 DRM_DEBUG_KMS("Scaler allocation for output failed\n"); 2304 return false; 2305 } 2306 2307 intel_pch_panel_fitting(intel_crtc, config, 2308 DRM_MODE_SCALE_FULLSCREEN); 2309 2310 return true; 2311 } 2312 2313 static int intel_hdmi_port_clock(int clock, int bpc) 2314 { 2315 /* 2316 * Need to adjust the port link by: 2317 * 1.5x for 12bpc 2318 * 1.25x for 10bpc 2319 */ 2320 return clock * bpc / 8; 2321 } 2322 2323 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2324 struct intel_crtc_state *crtc_state, 2325 int clock) 2326 { 2327 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2328 int bpc; 2329 2330 for (bpc = 12; bpc >= 10; bpc -= 2) { 2331 if (hdmi_deep_color_possible(crtc_state, bpc) && 2332 hdmi_port_clock_valid(intel_hdmi, 2333 intel_hdmi_port_clock(clock, bpc), 2334 true, crtc_state->has_hdmi_sink) == MODE_OK) 2335 return bpc; 2336 } 2337 2338 return 8; 2339 } 2340 2341 static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2342 struct intel_crtc_state *crtc_state) 2343 { 2344 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2345 const struct drm_display_mode *adjusted_mode = 2346 &crtc_state->hw.adjusted_mode; 2347 int bpc, clock = adjusted_mode->crtc_clock; 2348 2349 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2350 clock *= 2; 2351 2352 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 2353 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2354 clock /= 2; 2355 2356 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock); 2357 2358 crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc); 2359 2360 /* 2361 * pipe_bpp could already be below 8bpc due to 2362 * FDI bandwidth constraints. We shouldn't bump it 2363 * back up to 8bpc in that case. 2364 */ 2365 if (crtc_state->pipe_bpp > bpc * 3) 2366 crtc_state->pipe_bpp = bpc * 3; 2367 2368 DRM_DEBUG_KMS("picking %d bpc for HDMI output (pipe bpp: %d)\n", 2369 bpc, crtc_state->pipe_bpp); 2370 2371 if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock, 2372 false, crtc_state->has_hdmi_sink) != MODE_OK) { 2373 DRM_DEBUG_KMS("unsupported HDMI clock (%d kHz), rejecting mode\n", 2374 crtc_state->port_clock); 2375 return -EINVAL; 2376 } 2377 2378 return 0; 2379 } 2380 2381 static bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2382 const struct drm_connector_state *conn_state) 2383 { 2384 const struct intel_digital_connector_state *intel_conn_state = 2385 to_intel_digital_connector_state(conn_state); 2386 const struct drm_display_mode *adjusted_mode = 2387 &crtc_state->hw.adjusted_mode; 2388 2389 /* 2390 * Our YCbCr output is always limited range. 2391 * crtc_state->limited_color_range only applies to RGB, 2392 * and it must never be set for YCbCr or we risk setting 2393 * some conflicting bits in PIPECONF which will mess up 2394 * the colors on the monitor. 2395 */ 2396 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2397 return false; 2398 2399 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2400 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2401 return crtc_state->has_hdmi_sink && 2402 drm_default_rgb_quant_range(adjusted_mode) == 2403 HDMI_QUANTIZATION_RANGE_LIMITED; 2404 } else { 2405 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2406 } 2407 } 2408 2409 int intel_hdmi_compute_config(struct intel_encoder *encoder, 2410 struct intel_crtc_state *pipe_config, 2411 struct drm_connector_state *conn_state) 2412 { 2413 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2414 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2415 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2416 struct drm_connector *connector = conn_state->connector; 2417 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; 2418 struct intel_digital_connector_state *intel_conn_state = 2419 to_intel_digital_connector_state(conn_state); 2420 int ret; 2421 2422 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2423 return -EINVAL; 2424 2425 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2426 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi, 2427 conn_state); 2428 2429 if (pipe_config->has_hdmi_sink) 2430 pipe_config->has_infoframe = true; 2431 2432 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2433 pipe_config->pixel_multiplier = 2; 2434 2435 if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) { 2436 if (!intel_hdmi_ycbcr420_config(connector, pipe_config)) { 2437 DRM_ERROR("Can't support YCBCR420 output\n"); 2438 return -EINVAL; 2439 } 2440 } 2441 2442 pipe_config->limited_color_range = 2443 intel_hdmi_limited_color_range(pipe_config, conn_state); 2444 2445 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) 2446 pipe_config->has_pch_encoder = true; 2447 2448 if (pipe_config->has_hdmi_sink) { 2449 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2450 pipe_config->has_audio = intel_hdmi->has_audio; 2451 else 2452 pipe_config->has_audio = 2453 intel_conn_state->force_audio == HDMI_AUDIO_ON; 2454 } 2455 2456 ret = intel_hdmi_compute_clock(encoder, pipe_config); 2457 if (ret) 2458 return ret; 2459 2460 if (conn_state->picture_aspect_ratio) 2461 adjusted_mode->picture_aspect_ratio = 2462 conn_state->picture_aspect_ratio; 2463 2464 pipe_config->lane_count = 4; 2465 2466 if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 || 2467 IS_GEMINILAKE(dev_priv))) { 2468 if (scdc->scrambling.low_rates) 2469 pipe_config->hdmi_scrambling = true; 2470 2471 if (pipe_config->port_clock > 340000) { 2472 pipe_config->hdmi_scrambling = true; 2473 pipe_config->hdmi_high_tmds_clock_ratio = true; 2474 } 2475 } 2476 2477 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state); 2478 2479 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2480 DRM_DEBUG_KMS("bad AVI infoframe\n"); 2481 return -EINVAL; 2482 } 2483 2484 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2485 DRM_DEBUG_KMS("bad SPD infoframe\n"); 2486 return -EINVAL; 2487 } 2488 2489 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2490 DRM_DEBUG_KMS("bad HDMI infoframe\n"); 2491 return -EINVAL; 2492 } 2493 2494 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2495 DRM_DEBUG_KMS("bad DRM infoframe\n"); 2496 return -EINVAL; 2497 } 2498 2499 return 0; 2500 } 2501 2502 static void 2503 intel_hdmi_unset_edid(struct drm_connector *connector) 2504 { 2505 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2506 2507 intel_hdmi->has_hdmi_sink = false; 2508 intel_hdmi->has_audio = false; 2509 2510 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2511 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2512 2513 kfree(to_intel_connector(connector)->detect_edid); 2514 to_intel_connector(connector)->detect_edid = NULL; 2515 } 2516 2517 static void 2518 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) 2519 { 2520 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2521 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2522 enum port port = hdmi_to_dig_port(hdmi)->base.port; 2523 struct i2c_adapter *adapter = 2524 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 2525 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); 2526 2527 /* 2528 * Type 1 DVI adaptors are not required to implement any 2529 * registers, so we can't always detect their presence. 2530 * Ideally we should be able to check the state of the 2531 * CONFIG1 pin, but no such luck on our hardware. 2532 * 2533 * The only method left to us is to check the VBT to see 2534 * if the port is a dual mode capable DP port. But let's 2535 * only do that when we sucesfully read the EDID, to avoid 2536 * confusing log messages about DP dual mode adaptors when 2537 * there's nothing connected to the port. 2538 */ 2539 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2540 /* An overridden EDID imply that we want this port for testing. 2541 * Make sure not to set limits for that port. 2542 */ 2543 if (has_edid && !connector->override_edid && 2544 intel_bios_is_port_dp_dual_mode(dev_priv, port)) { 2545 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); 2546 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2547 } else { 2548 type = DRM_DP_DUAL_MODE_NONE; 2549 } 2550 } 2551 2552 if (type == DRM_DP_DUAL_MODE_NONE) 2553 return; 2554 2555 hdmi->dp_dual_mode.type = type; 2556 hdmi->dp_dual_mode.max_tmds_clock = 2557 drm_dp_dual_mode_max_tmds_clock(type, adapter); 2558 2559 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2560 drm_dp_get_dual_mode_type_name(type), 2561 hdmi->dp_dual_mode.max_tmds_clock); 2562 } 2563 2564 static bool 2565 intel_hdmi_set_edid(struct drm_connector *connector) 2566 { 2567 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2568 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2569 intel_wakeref_t wakeref; 2570 struct edid *edid; 2571 bool connected = false; 2572 struct i2c_adapter *i2c; 2573 2574 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2575 2576 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2577 2578 edid = drm_get_edid(connector, i2c); 2579 2580 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 2581 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2582 intel_gmbus_force_bit(i2c, true); 2583 edid = drm_get_edid(connector, i2c); 2584 intel_gmbus_force_bit(i2c, false); 2585 } 2586 2587 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); 2588 2589 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2590 2591 to_intel_connector(connector)->detect_edid = edid; 2592 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 2593 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 2594 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); 2595 2596 connected = true; 2597 } 2598 2599 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); 2600 2601 return connected; 2602 } 2603 2604 static enum drm_connector_status 2605 intel_hdmi_detect(struct drm_connector *connector, bool force) 2606 { 2607 enum drm_connector_status status = connector_status_disconnected; 2608 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2609 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2610 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2611 intel_wakeref_t wakeref; 2612 2613 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2614 connector->base.id, connector->name); 2615 2616 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2617 2618 if (INTEL_GEN(dev_priv) >= 11 && 2619 !intel_digital_port_connected(encoder)) 2620 goto out; 2621 2622 intel_hdmi_unset_edid(connector); 2623 2624 if (intel_hdmi_set_edid(connector)) 2625 status = connector_status_connected; 2626 2627 out: 2628 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2629 2630 if (status != connector_status_connected) 2631 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2632 2633 /* 2634 * Make sure the refs for power wells enabled during detect are 2635 * dropped to avoid a new detect cycle triggered by HPD polling. 2636 */ 2637 intel_display_power_flush_work(dev_priv); 2638 2639 return status; 2640 } 2641 2642 static void 2643 intel_hdmi_force(struct drm_connector *connector) 2644 { 2645 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 2646 connector->base.id, connector->name); 2647 2648 intel_hdmi_unset_edid(connector); 2649 2650 if (connector->status != connector_status_connected) 2651 return; 2652 2653 intel_hdmi_set_edid(connector); 2654 } 2655 2656 static int intel_hdmi_get_modes(struct drm_connector *connector) 2657 { 2658 struct edid *edid; 2659 2660 edid = to_intel_connector(connector)->detect_edid; 2661 if (edid == NULL) 2662 return 0; 2663 2664 return intel_connector_update_modes(connector, edid); 2665 } 2666 2667 static void intel_hdmi_pre_enable(struct intel_encoder *encoder, 2668 const struct intel_crtc_state *pipe_config, 2669 const struct drm_connector_state *conn_state) 2670 { 2671 struct intel_digital_port *intel_dig_port = 2672 enc_to_dig_port(encoder); 2673 2674 intel_hdmi_prepare(encoder, pipe_config); 2675 2676 intel_dig_port->set_infoframes(encoder, 2677 pipe_config->has_infoframe, 2678 pipe_config, conn_state); 2679 } 2680 2681 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, 2682 const struct intel_crtc_state *pipe_config, 2683 const struct drm_connector_state *conn_state) 2684 { 2685 struct intel_digital_port *dport = enc_to_dig_port(encoder); 2686 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2687 2688 vlv_phy_pre_encoder_enable(encoder, pipe_config); 2689 2690 /* HDMI 1.0V-2dB */ 2691 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, 2692 0x2b247878); 2693 2694 dport->set_infoframes(encoder, 2695 pipe_config->has_infoframe, 2696 pipe_config, conn_state); 2697 2698 g4x_enable_hdmi(encoder, pipe_config, conn_state); 2699 2700 vlv_wait_port_ready(dev_priv, dport, 0x0); 2701 } 2702 2703 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, 2704 const struct intel_crtc_state *pipe_config, 2705 const struct drm_connector_state *conn_state) 2706 { 2707 intel_hdmi_prepare(encoder, pipe_config); 2708 2709 vlv_phy_pre_pll_enable(encoder, pipe_config); 2710 } 2711 2712 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, 2713 const struct intel_crtc_state *pipe_config, 2714 const struct drm_connector_state *conn_state) 2715 { 2716 intel_hdmi_prepare(encoder, pipe_config); 2717 2718 chv_phy_pre_pll_enable(encoder, pipe_config); 2719 } 2720 2721 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, 2722 const struct intel_crtc_state *old_crtc_state, 2723 const struct drm_connector_state *old_conn_state) 2724 { 2725 chv_phy_post_pll_disable(encoder, old_crtc_state); 2726 } 2727 2728 static void vlv_hdmi_post_disable(struct intel_encoder *encoder, 2729 const struct intel_crtc_state *old_crtc_state, 2730 const struct drm_connector_state *old_conn_state) 2731 { 2732 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 2733 vlv_phy_reset_lanes(encoder, old_crtc_state); 2734 } 2735 2736 static void chv_hdmi_post_disable(struct intel_encoder *encoder, 2737 const struct intel_crtc_state *old_crtc_state, 2738 const struct drm_connector_state *old_conn_state) 2739 { 2740 struct drm_device *dev = encoder->base.dev; 2741 struct drm_i915_private *dev_priv = to_i915(dev); 2742 2743 vlv_dpio_get(dev_priv); 2744 2745 /* Assert data lane reset */ 2746 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 2747 2748 vlv_dpio_put(dev_priv); 2749 } 2750 2751 static void chv_hdmi_pre_enable(struct intel_encoder *encoder, 2752 const struct intel_crtc_state *pipe_config, 2753 const struct drm_connector_state *conn_state) 2754 { 2755 struct intel_digital_port *dport = enc_to_dig_port(encoder); 2756 struct drm_device *dev = encoder->base.dev; 2757 struct drm_i915_private *dev_priv = to_i915(dev); 2758 2759 chv_phy_pre_encoder_enable(encoder, pipe_config); 2760 2761 /* FIXME: Program the support xxx V-dB */ 2762 /* Use 800mV-0dB */ 2763 chv_set_phy_signal_level(encoder, 128, 102, false); 2764 2765 dport->set_infoframes(encoder, 2766 pipe_config->has_infoframe, 2767 pipe_config, conn_state); 2768 2769 g4x_enable_hdmi(encoder, pipe_config, conn_state); 2770 2771 vlv_wait_port_ready(dev_priv, dport, 0x0); 2772 2773 /* Second common lane will stay alive on its own now */ 2774 chv_phy_release_cl2_override(encoder); 2775 } 2776 2777 static struct i2c_adapter * 2778 intel_hdmi_get_i2c_adapter(struct drm_connector *connector) 2779 { 2780 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2781 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2782 2783 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2784 } 2785 2786 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector) 2787 { 2788 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2789 struct kobject *i2c_kobj = &adapter->dev.kobj; 2790 struct kobject *connector_kobj = &connector->kdev->kobj; 2791 int ret; 2792 2793 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name); 2794 if (ret) 2795 DRM_ERROR("Failed to create i2c symlink (%d)\n", ret); 2796 } 2797 2798 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector) 2799 { 2800 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2801 struct kobject *i2c_kobj = &adapter->dev.kobj; 2802 struct kobject *connector_kobj = &connector->kdev->kobj; 2803 2804 sysfs_remove_link(connector_kobj, i2c_kobj->name); 2805 } 2806 2807 static int 2808 intel_hdmi_connector_register(struct drm_connector *connector) 2809 { 2810 int ret; 2811 2812 ret = intel_connector_register(connector); 2813 if (ret) 2814 return ret; 2815 2816 intel_connector_debugfs_add(connector); 2817 2818 intel_hdmi_create_i2c_symlink(connector); 2819 2820 return ret; 2821 } 2822 2823 static void intel_hdmi_destroy(struct drm_connector *connector) 2824 { 2825 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; 2826 2827 cec_notifier_conn_unregister(n); 2828 2829 intel_connector_destroy(connector); 2830 } 2831 2832 static void intel_hdmi_connector_unregister(struct drm_connector *connector) 2833 { 2834 intel_hdmi_remove_i2c_symlink(connector); 2835 2836 intel_connector_unregister(connector); 2837 } 2838 2839 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2840 .detect = intel_hdmi_detect, 2841 .force = intel_hdmi_force, 2842 .fill_modes = drm_helper_probe_single_connector_modes, 2843 .atomic_get_property = intel_digital_connector_atomic_get_property, 2844 .atomic_set_property = intel_digital_connector_atomic_set_property, 2845 .late_register = intel_hdmi_connector_register, 2846 .early_unregister = intel_hdmi_connector_unregister, 2847 .destroy = intel_hdmi_destroy, 2848 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2849 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2850 }; 2851 2852 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2853 .get_modes = intel_hdmi_get_modes, 2854 .mode_valid = intel_hdmi_mode_valid, 2855 .atomic_check = intel_digital_connector_atomic_check, 2856 }; 2857 2858 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 2859 .destroy = intel_encoder_destroy, 2860 }; 2861 2862 static void 2863 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2864 { 2865 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2866 struct intel_digital_port *intel_dig_port = 2867 hdmi_to_dig_port(intel_hdmi); 2868 2869 intel_attach_force_audio_property(connector); 2870 intel_attach_broadcast_rgb_property(connector); 2871 intel_attach_aspect_ratio_property(connector); 2872 2873 /* 2874 * Attach Colorspace property for Non LSPCON based device 2875 * ToDo: This needs to be extended for LSPCON implementation 2876 * as well. Will be implemented separately. 2877 */ 2878 if (!intel_dig_port->lspcon.active) 2879 intel_attach_colorspace_property(connector); 2880 2881 drm_connector_attach_content_type_property(connector); 2882 2883 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2884 drm_object_attach_property(&connector->base, 2885 connector->dev->mode_config.hdr_output_metadata_property, 0); 2886 2887 if (!HAS_GMCH(dev_priv)) 2888 drm_connector_attach_max_bpc_property(connector, 8, 12); 2889 } 2890 2891 /* 2892 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2893 * @encoder: intel_encoder 2894 * @connector: drm_connector 2895 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2896 * or reset the high tmds clock ratio for scrambling 2897 * @scrambling: bool to Indicate if the function needs to set or reset 2898 * sink scrambling 2899 * 2900 * This function handles scrambling on HDMI 2.0 capable sinks. 2901 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2902 * it enables scrambling. This should be called before enabling the HDMI 2903 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2904 * detect a scrambled clock within 100 ms. 2905 * 2906 * Returns: 2907 * True on success, false on failure. 2908 */ 2909 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2910 struct drm_connector *connector, 2911 bool high_tmds_clock_ratio, 2912 bool scrambling) 2913 { 2914 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2915 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2916 struct drm_scrambling *sink_scrambling = 2917 &connector->display_info.hdmi.scdc.scrambling; 2918 struct i2c_adapter *adapter = 2919 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2920 2921 if (!sink_scrambling->supported) 2922 return true; 2923 2924 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 2925 connector->base.id, connector->name, 2926 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10); 2927 2928 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 2929 return drm_scdc_set_high_tmds_clock_ratio(adapter, 2930 high_tmds_clock_ratio) && 2931 drm_scdc_set_scrambling(adapter, scrambling); 2932 } 2933 2934 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2935 { 2936 u8 ddc_pin; 2937 2938 switch (port) { 2939 case PORT_B: 2940 ddc_pin = GMBUS_PIN_DPB; 2941 break; 2942 case PORT_C: 2943 ddc_pin = GMBUS_PIN_DPC; 2944 break; 2945 case PORT_D: 2946 ddc_pin = GMBUS_PIN_DPD_CHV; 2947 break; 2948 default: 2949 MISSING_CASE(port); 2950 ddc_pin = GMBUS_PIN_DPB; 2951 break; 2952 } 2953 return ddc_pin; 2954 } 2955 2956 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2957 { 2958 u8 ddc_pin; 2959 2960 switch (port) { 2961 case PORT_B: 2962 ddc_pin = GMBUS_PIN_1_BXT; 2963 break; 2964 case PORT_C: 2965 ddc_pin = GMBUS_PIN_2_BXT; 2966 break; 2967 default: 2968 MISSING_CASE(port); 2969 ddc_pin = GMBUS_PIN_1_BXT; 2970 break; 2971 } 2972 return ddc_pin; 2973 } 2974 2975 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, 2976 enum port port) 2977 { 2978 u8 ddc_pin; 2979 2980 switch (port) { 2981 case PORT_B: 2982 ddc_pin = GMBUS_PIN_1_BXT; 2983 break; 2984 case PORT_C: 2985 ddc_pin = GMBUS_PIN_2_BXT; 2986 break; 2987 case PORT_D: 2988 ddc_pin = GMBUS_PIN_4_CNP; 2989 break; 2990 case PORT_F: 2991 ddc_pin = GMBUS_PIN_3_BXT; 2992 break; 2993 default: 2994 MISSING_CASE(port); 2995 ddc_pin = GMBUS_PIN_1_BXT; 2996 break; 2997 } 2998 return ddc_pin; 2999 } 3000 3001 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 3002 { 3003 enum phy phy = intel_port_to_phy(dev_priv, port); 3004 3005 if (intel_phy_is_combo(dev_priv, phy)) 3006 return GMBUS_PIN_1_BXT + port; 3007 else if (intel_phy_is_tc(dev_priv, phy)) 3008 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port); 3009 3010 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port)); 3011 return GMBUS_PIN_2_BXT; 3012 } 3013 3014 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 3015 { 3016 enum phy phy = intel_port_to_phy(dev_priv, port); 3017 u8 ddc_pin; 3018 3019 switch (phy) { 3020 case PHY_A: 3021 ddc_pin = GMBUS_PIN_1_BXT; 3022 break; 3023 case PHY_B: 3024 ddc_pin = GMBUS_PIN_2_BXT; 3025 break; 3026 case PHY_C: 3027 ddc_pin = GMBUS_PIN_9_TC1_ICP; 3028 break; 3029 default: 3030 MISSING_CASE(phy); 3031 ddc_pin = GMBUS_PIN_1_BXT; 3032 break; 3033 } 3034 return ddc_pin; 3035 } 3036 3037 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, 3038 enum port port) 3039 { 3040 u8 ddc_pin; 3041 3042 switch (port) { 3043 case PORT_B: 3044 ddc_pin = GMBUS_PIN_DPB; 3045 break; 3046 case PORT_C: 3047 ddc_pin = GMBUS_PIN_DPC; 3048 break; 3049 case PORT_D: 3050 ddc_pin = GMBUS_PIN_DPD; 3051 break; 3052 default: 3053 MISSING_CASE(port); 3054 ddc_pin = GMBUS_PIN_DPB; 3055 break; 3056 } 3057 return ddc_pin; 3058 } 3059 3060 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 3061 { 3062 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3063 enum port port = encoder->port; 3064 u8 ddc_pin; 3065 3066 ddc_pin = intel_bios_alternate_ddc_pin(encoder); 3067 if (ddc_pin) { 3068 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", 3069 ddc_pin, port_name(port)); 3070 return ddc_pin; 3071 } 3072 3073 if (HAS_PCH_MCC(dev_priv)) 3074 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); 3075 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 3076 ddc_pin = icl_port_to_ddc_pin(dev_priv, port); 3077 else if (HAS_PCH_CNP(dev_priv)) 3078 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); 3079 else if (IS_GEN9_LP(dev_priv)) 3080 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); 3081 else if (IS_CHERRYVIEW(dev_priv)) 3082 ddc_pin = chv_port_to_ddc_pin(dev_priv, port); 3083 else 3084 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); 3085 3086 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", 3087 ddc_pin, port_name(port)); 3088 3089 return ddc_pin; 3090 } 3091 3092 void intel_infoframe_init(struct intel_digital_port *intel_dig_port) 3093 { 3094 struct drm_i915_private *dev_priv = 3095 to_i915(intel_dig_port->base.base.dev); 3096 3097 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 3098 intel_dig_port->write_infoframe = vlv_write_infoframe; 3099 intel_dig_port->read_infoframe = vlv_read_infoframe; 3100 intel_dig_port->set_infoframes = vlv_set_infoframes; 3101 intel_dig_port->infoframes_enabled = vlv_infoframes_enabled; 3102 } else if (IS_G4X(dev_priv)) { 3103 intel_dig_port->write_infoframe = g4x_write_infoframe; 3104 intel_dig_port->read_infoframe = g4x_read_infoframe; 3105 intel_dig_port->set_infoframes = g4x_set_infoframes; 3106 intel_dig_port->infoframes_enabled = g4x_infoframes_enabled; 3107 } else if (HAS_DDI(dev_priv)) { 3108 if (intel_dig_port->lspcon.active) { 3109 intel_dig_port->write_infoframe = lspcon_write_infoframe; 3110 intel_dig_port->read_infoframe = lspcon_read_infoframe; 3111 intel_dig_port->set_infoframes = lspcon_set_infoframes; 3112 intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled; 3113 } else { 3114 intel_dig_port->write_infoframe = hsw_write_infoframe; 3115 intel_dig_port->read_infoframe = hsw_read_infoframe; 3116 intel_dig_port->set_infoframes = hsw_set_infoframes; 3117 intel_dig_port->infoframes_enabled = hsw_infoframes_enabled; 3118 } 3119 } else if (HAS_PCH_IBX(dev_priv)) { 3120 intel_dig_port->write_infoframe = ibx_write_infoframe; 3121 intel_dig_port->read_infoframe = ibx_read_infoframe; 3122 intel_dig_port->set_infoframes = ibx_set_infoframes; 3123 intel_dig_port->infoframes_enabled = ibx_infoframes_enabled; 3124 } else { 3125 intel_dig_port->write_infoframe = cpt_write_infoframe; 3126 intel_dig_port->read_infoframe = cpt_read_infoframe; 3127 intel_dig_port->set_infoframes = cpt_set_infoframes; 3128 intel_dig_port->infoframes_enabled = cpt_infoframes_enabled; 3129 } 3130 } 3131 3132 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 3133 struct intel_connector *intel_connector) 3134 { 3135 struct drm_connector *connector = &intel_connector->base; 3136 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 3137 struct intel_encoder *intel_encoder = &intel_dig_port->base; 3138 struct drm_device *dev = intel_encoder->base.dev; 3139 struct drm_i915_private *dev_priv = to_i915(dev); 3140 struct i2c_adapter *ddc; 3141 enum port port = intel_encoder->port; 3142 struct cec_connector_info conn_info; 3143 3144 DRM_DEBUG_KMS("Adding HDMI connector on [ENCODER:%d:%s]\n", 3145 intel_encoder->base.base.id, intel_encoder->base.name); 3146 3147 if (INTEL_GEN(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A)) 3148 return; 3149 3150 if (drm_WARN(dev, intel_dig_port->max_lanes < 4, 3151 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 3152 intel_dig_port->max_lanes, intel_encoder->base.base.id, 3153 intel_encoder->base.name)) 3154 return; 3155 3156 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder); 3157 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 3158 3159 drm_connector_init_with_ddc(dev, connector, 3160 &intel_hdmi_connector_funcs, 3161 DRM_MODE_CONNECTOR_HDMIA, 3162 ddc); 3163 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 3164 3165 connector->interlace_allowed = 1; 3166 connector->doublescan_allowed = 0; 3167 connector->stereo_allowed = 1; 3168 3169 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 3170 connector->ycbcr_420_allowed = true; 3171 3172 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 3173 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 3174 3175 if (HAS_DDI(dev_priv)) 3176 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3177 else 3178 intel_connector->get_hw_state = intel_connector_get_hw_state; 3179 3180 intel_hdmi_add_properties(intel_hdmi, connector); 3181 3182 intel_connector_attach_encoder(intel_connector, intel_encoder); 3183 intel_hdmi->attached_connector = intel_connector; 3184 3185 if (is_hdcp_supported(dev_priv, port)) { 3186 int ret = intel_hdcp_init(intel_connector, 3187 &intel_hdmi_hdcp_shim); 3188 if (ret) 3189 DRM_DEBUG_KMS("HDCP init failed, skipping.\n"); 3190 } 3191 3192 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 3193 * 0xd. Failure to do so will result in spurious interrupts being 3194 * generated on the port when a cable is not attached. 3195 */ 3196 if (IS_G45(dev_priv)) { 3197 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA); 3198 intel_de_write(dev_priv, PEG_BAND_GAP_DATA, 3199 (temp & ~0xf) | 0xd); 3200 } 3201 3202 cec_fill_conn_info_from_drm(&conn_info, connector); 3203 3204 intel_hdmi->cec_notifier = 3205 cec_notifier_conn_register(dev->dev, port_identifier(port), 3206 &conn_info); 3207 if (!intel_hdmi->cec_notifier) 3208 DRM_DEBUG_KMS("CEC notifier get failed\n"); 3209 } 3210 3211 static enum intel_hotplug_state 3212 intel_hdmi_hotplug(struct intel_encoder *encoder, 3213 struct intel_connector *connector, bool irq_received) 3214 { 3215 enum intel_hotplug_state state; 3216 3217 state = intel_encoder_hotplug(encoder, connector, irq_received); 3218 3219 /* 3220 * On many platforms the HDMI live state signal is known to be 3221 * unreliable, so we can't use it to detect if a sink is connected or 3222 * not. Instead we detect if it's connected based on whether we can 3223 * read the EDID or not. That in turn has a problem during disconnect, 3224 * since the HPD interrupt may be raised before the DDC lines get 3225 * disconnected (due to how the required length of DDC vs. HPD 3226 * connector pins are specified) and so we'll still be able to get a 3227 * valid EDID. To solve this schedule another detection cycle if this 3228 * time around we didn't detect any change in the sink's connection 3229 * status. 3230 */ 3231 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received) 3232 state = INTEL_HOTPLUG_RETRY; 3233 3234 return state; 3235 } 3236 3237 void intel_hdmi_init(struct drm_i915_private *dev_priv, 3238 i915_reg_t hdmi_reg, enum port port) 3239 { 3240 struct intel_digital_port *intel_dig_port; 3241 struct intel_encoder *intel_encoder; 3242 struct intel_connector *intel_connector; 3243 3244 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 3245 if (!intel_dig_port) 3246 return; 3247 3248 intel_connector = intel_connector_alloc(); 3249 if (!intel_connector) { 3250 kfree(intel_dig_port); 3251 return; 3252 } 3253 3254 intel_encoder = &intel_dig_port->base; 3255 3256 drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 3257 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, 3258 "HDMI %c", port_name(port)); 3259 3260 intel_encoder->hotplug = intel_hdmi_hotplug; 3261 intel_encoder->compute_config = intel_hdmi_compute_config; 3262 if (HAS_PCH_SPLIT(dev_priv)) { 3263 intel_encoder->disable = pch_disable_hdmi; 3264 intel_encoder->post_disable = pch_post_disable_hdmi; 3265 } else { 3266 intel_encoder->disable = g4x_disable_hdmi; 3267 } 3268 intel_encoder->get_hw_state = intel_hdmi_get_hw_state; 3269 intel_encoder->get_config = intel_hdmi_get_config; 3270 if (IS_CHERRYVIEW(dev_priv)) { 3271 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; 3272 intel_encoder->pre_enable = chv_hdmi_pre_enable; 3273 intel_encoder->enable = vlv_enable_hdmi; 3274 intel_encoder->post_disable = chv_hdmi_post_disable; 3275 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; 3276 } else if (IS_VALLEYVIEW(dev_priv)) { 3277 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; 3278 intel_encoder->pre_enable = vlv_hdmi_pre_enable; 3279 intel_encoder->enable = vlv_enable_hdmi; 3280 intel_encoder->post_disable = vlv_hdmi_post_disable; 3281 } else { 3282 intel_encoder->pre_enable = intel_hdmi_pre_enable; 3283 if (HAS_PCH_CPT(dev_priv)) 3284 intel_encoder->enable = cpt_enable_hdmi; 3285 else if (HAS_PCH_IBX(dev_priv)) 3286 intel_encoder->enable = ibx_enable_hdmi; 3287 else 3288 intel_encoder->enable = g4x_enable_hdmi; 3289 } 3290 3291 intel_encoder->type = INTEL_OUTPUT_HDMI; 3292 intel_encoder->power_domain = intel_port_to_power_domain(port); 3293 intel_encoder->port = port; 3294 if (IS_CHERRYVIEW(dev_priv)) { 3295 if (port == PORT_D) 3296 intel_encoder->pipe_mask = BIT(PIPE_C); 3297 else 3298 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); 3299 } else { 3300 intel_encoder->pipe_mask = ~0; 3301 } 3302 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; 3303 /* 3304 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems 3305 * to work on real hardware. And since g4x can send infoframes to 3306 * only one port anyway, nothing is lost by allowing it. 3307 */ 3308 if (IS_G4X(dev_priv)) 3309 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; 3310 3311 intel_dig_port->hdmi.hdmi_reg = hdmi_reg; 3312 intel_dig_port->dp.output_reg = INVALID_MMIO_REG; 3313 intel_dig_port->max_lanes = 4; 3314 3315 intel_infoframe_init(intel_dig_port); 3316 3317 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 3318 intel_hdmi_init_connector(intel_dig_port, intel_connector); 3319 } 3320