1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #include <linux/types.h> 33 #include <asm/byteorder.h> 34 #include <linux/bitops.h> 35 #include <linux/delay.h> 36 #include <linux/dma-mapping.h> 37 #include <linux/errno.h> 38 #include <linux/io.h> 39 #include <linux/kernel.h> 40 #include <linux/list.h> 41 #include <linux/module.h> 42 #include <linux/mutex.h> 43 #include <linux/pci.h> 44 #include <linux/slab.h> 45 #include <linux/spinlock.h> 46 #include <linux/string.h> 47 #include "qed.h" 48 #include "qed_cxt.h" 49 #include "qed_hsi.h" 50 #include "qed_hw.h" 51 #include "qed_init_ops.h" 52 #include "qed_int.h" 53 #include "qed_ll2.h" 54 #include "qed_mcp.h" 55 #include "qed_reg_addr.h" 56 #include <linux/qed/qed_rdma_if.h> 57 #include "qed_rdma.h" 58 #include "qed_roce.h" 59 #include "qed_sp.h" 60 61 62 int qed_rdma_bmap_alloc(struct qed_hwfn *p_hwfn, 63 struct qed_bmap *bmap, u32 max_count, char *name) 64 { 65 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "max_count = %08x\n", max_count); 66 67 bmap->max_count = max_count; 68 69 bmap->bitmap = kcalloc(BITS_TO_LONGS(max_count), sizeof(long), 70 GFP_KERNEL); 71 if (!bmap->bitmap) 72 return -ENOMEM; 73 74 snprintf(bmap->name, QED_RDMA_MAX_BMAP_NAME, "%s", name); 75 76 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "0\n"); 77 return 0; 78 } 79 80 int qed_rdma_bmap_alloc_id(struct qed_hwfn *p_hwfn, 81 struct qed_bmap *bmap, u32 *id_num) 82 { 83 *id_num = find_first_zero_bit(bmap->bitmap, bmap->max_count); 84 if (*id_num >= bmap->max_count) 85 return -EINVAL; 86 87 __set_bit(*id_num, bmap->bitmap); 88 89 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "%s bitmap: allocated id %d\n", 90 bmap->name, *id_num); 91 92 return 0; 93 } 94 95 void qed_bmap_set_id(struct qed_hwfn *p_hwfn, 96 struct qed_bmap *bmap, u32 id_num) 97 { 98 if (id_num >= bmap->max_count) 99 return; 100 101 __set_bit(id_num, bmap->bitmap); 102 } 103 104 void qed_bmap_release_id(struct qed_hwfn *p_hwfn, 105 struct qed_bmap *bmap, u32 id_num) 106 { 107 bool b_acquired; 108 109 if (id_num >= bmap->max_count) 110 return; 111 112 b_acquired = test_and_clear_bit(id_num, bmap->bitmap); 113 if (!b_acquired) { 114 DP_NOTICE(p_hwfn, "%s bitmap: id %d already released\n", 115 bmap->name, id_num); 116 return; 117 } 118 119 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "%s bitmap: released id %d\n", 120 bmap->name, id_num); 121 } 122 123 int qed_bmap_test_id(struct qed_hwfn *p_hwfn, 124 struct qed_bmap *bmap, u32 id_num) 125 { 126 if (id_num >= bmap->max_count) 127 return -1; 128 129 return test_bit(id_num, bmap->bitmap); 130 } 131 132 static bool qed_bmap_is_empty(struct qed_bmap *bmap) 133 { 134 return bmap->max_count == find_first_bit(bmap->bitmap, bmap->max_count); 135 } 136 137 static u32 qed_rdma_get_sb_id(void *p_hwfn, u32 rel_sb_id) 138 { 139 /* First sb id for RoCE is after all the l2 sb */ 140 return FEAT_NUM((struct qed_hwfn *)p_hwfn, QED_PF_L2_QUE) + rel_sb_id; 141 } 142 143 int qed_rdma_info_alloc(struct qed_hwfn *p_hwfn) 144 { 145 struct qed_rdma_info *p_rdma_info; 146 147 p_rdma_info = kzalloc(sizeof(*p_rdma_info), GFP_KERNEL); 148 if (!p_rdma_info) 149 return -ENOMEM; 150 151 spin_lock_init(&p_rdma_info->lock); 152 153 p_hwfn->p_rdma_info = p_rdma_info; 154 return 0; 155 } 156 157 void qed_rdma_info_free(struct qed_hwfn *p_hwfn) 158 { 159 kfree(p_hwfn->p_rdma_info); 160 p_hwfn->p_rdma_info = NULL; 161 } 162 163 static int qed_rdma_alloc(struct qed_hwfn *p_hwfn) 164 { 165 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 166 u32 num_cons, num_tasks; 167 int rc = -ENOMEM; 168 169 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocating RDMA\n"); 170 171 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 172 p_rdma_info->proto = PROTOCOLID_IWARP; 173 else 174 p_rdma_info->proto = PROTOCOLID_ROCE; 175 176 num_cons = qed_cxt_get_proto_cid_count(p_hwfn, p_rdma_info->proto, 177 NULL); 178 179 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 180 p_rdma_info->num_qps = num_cons; 181 else 182 p_rdma_info->num_qps = num_cons / 2; /* 2 cids per qp */ 183 184 num_tasks = qed_cxt_get_proto_tid_count(p_hwfn, PROTOCOLID_ROCE); 185 186 /* Each MR uses a single task */ 187 p_rdma_info->num_mrs = num_tasks; 188 189 /* Queue zone lines are shared between RoCE and L2 in such a way that 190 * they can be used by each without obstructing the other. 191 */ 192 p_rdma_info->queue_zone_base = (u16)RESC_START(p_hwfn, QED_L2_QUEUE); 193 p_rdma_info->max_queue_zones = (u16)RESC_NUM(p_hwfn, QED_L2_QUEUE); 194 195 /* Allocate a struct with device params and fill it */ 196 p_rdma_info->dev = kzalloc(sizeof(*p_rdma_info->dev), GFP_KERNEL); 197 if (!p_rdma_info->dev) 198 return rc; 199 200 /* Allocate a struct with port params and fill it */ 201 p_rdma_info->port = kzalloc(sizeof(*p_rdma_info->port), GFP_KERNEL); 202 if (!p_rdma_info->port) 203 goto free_rdma_dev; 204 205 /* Allocate bit map for pd's */ 206 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->pd_map, RDMA_MAX_PDS, 207 "PD"); 208 if (rc) { 209 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 210 "Failed to allocate pd_map, rc = %d\n", 211 rc); 212 goto free_rdma_port; 213 } 214 215 /* Allocate bit map for XRC Domains */ 216 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->xrcd_map, 217 QED_RDMA_MAX_XRCDS, "XRCD"); 218 if (rc) { 219 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 220 "Failed to allocate xrcd_map,rc = %d\n", rc); 221 goto free_pd_map; 222 } 223 224 /* Allocate DPI bitmap */ 225 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->dpi_map, 226 p_hwfn->dpi_count, "DPI"); 227 if (rc) { 228 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 229 "Failed to allocate DPI bitmap, rc = %d\n", rc); 230 goto free_xrcd_map; 231 } 232 233 /* Allocate bitmap for cq's. The maximum number of CQs is bound to 234 * the number of connections we support. (num_qps in iWARP or 235 * num_qps/2 in RoCE). 236 */ 237 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cq_map, num_cons, "CQ"); 238 if (rc) { 239 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 240 "Failed to allocate cq bitmap, rc = %d\n", rc); 241 goto free_dpi_map; 242 } 243 244 /* Allocate bitmap for toggle bit for cq icids 245 * We toggle the bit every time we create or resize cq for a given icid. 246 * Size needs to equal the size of the cq bmap. 247 */ 248 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->toggle_bits, 249 num_cons, "Toggle"); 250 if (rc) { 251 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 252 "Failed to allocate toggle bits, rc = %d\n", rc); 253 goto free_cq_map; 254 } 255 256 /* Allocate bitmap for itids */ 257 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->tid_map, 258 p_rdma_info->num_mrs, "MR"); 259 if (rc) { 260 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 261 "Failed to allocate itids bitmaps, rc = %d\n", rc); 262 goto free_toggle_map; 263 } 264 265 /* Allocate bitmap for cids used for qps. */ 266 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->cid_map, num_cons, 267 "CID"); 268 if (rc) { 269 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 270 "Failed to allocate cid bitmap, rc = %d\n", rc); 271 goto free_tid_map; 272 } 273 274 /* Allocate bitmap for cids used for responders/requesters. */ 275 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->real_cid_map, num_cons, 276 "REAL_CID"); 277 if (rc) { 278 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 279 "Failed to allocate real cid bitmap, rc = %d\n", rc); 280 goto free_cid_map; 281 } 282 283 /* The first SRQ follows the last XRC SRQ. This means that the 284 * SRQ IDs start from an offset equals to max_xrc_srqs. 285 */ 286 p_rdma_info->srq_id_offset = p_hwfn->p_cxt_mngr->xrc_srq_count; 287 rc = qed_rdma_bmap_alloc(p_hwfn, 288 &p_rdma_info->xrc_srq_map, 289 p_hwfn->p_cxt_mngr->xrc_srq_count, "XRC SRQ"); 290 if (rc) { 291 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 292 "Failed to allocate xrc srq bitmap, rc = %d\n", rc); 293 goto free_real_cid_map; 294 } 295 296 /* Allocate bitmap for srqs */ 297 p_rdma_info->num_srqs = p_hwfn->p_cxt_mngr->srq_count; 298 rc = qed_rdma_bmap_alloc(p_hwfn, &p_rdma_info->srq_map, 299 p_rdma_info->num_srqs, "SRQ"); 300 if (rc) { 301 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 302 "Failed to allocate srq bitmap, rc = %d\n", rc); 303 goto free_xrc_srq_map; 304 } 305 306 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 307 rc = qed_iwarp_alloc(p_hwfn); 308 309 if (rc) 310 goto free_srq_map; 311 312 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocation successful\n"); 313 return 0; 314 315 free_srq_map: 316 kfree(p_rdma_info->srq_map.bitmap); 317 free_xrc_srq_map: 318 kfree(p_rdma_info->xrc_srq_map.bitmap); 319 free_real_cid_map: 320 kfree(p_rdma_info->real_cid_map.bitmap); 321 free_cid_map: 322 kfree(p_rdma_info->cid_map.bitmap); 323 free_tid_map: 324 kfree(p_rdma_info->tid_map.bitmap); 325 free_toggle_map: 326 kfree(p_rdma_info->toggle_bits.bitmap); 327 free_cq_map: 328 kfree(p_rdma_info->cq_map.bitmap); 329 free_dpi_map: 330 kfree(p_rdma_info->dpi_map.bitmap); 331 free_xrcd_map: 332 kfree(p_rdma_info->xrcd_map.bitmap); 333 free_pd_map: 334 kfree(p_rdma_info->pd_map.bitmap); 335 free_rdma_port: 336 kfree(p_rdma_info->port); 337 free_rdma_dev: 338 kfree(p_rdma_info->dev); 339 340 return rc; 341 } 342 343 void qed_rdma_bmap_free(struct qed_hwfn *p_hwfn, 344 struct qed_bmap *bmap, bool check) 345 { 346 int weight = bitmap_weight(bmap->bitmap, bmap->max_count); 347 int last_line = bmap->max_count / (64 * 8); 348 int last_item = last_line * 8 + 349 DIV_ROUND_UP(bmap->max_count % (64 * 8), 64); 350 u64 *pmap = (u64 *)bmap->bitmap; 351 int line, item, offset; 352 u8 str_last_line[200] = { 0 }; 353 354 if (!weight || !check) 355 goto end; 356 357 DP_NOTICE(p_hwfn, 358 "%s bitmap not free - size=%d, weight=%d, 512 bits per line\n", 359 bmap->name, bmap->max_count, weight); 360 361 /* print aligned non-zero lines, if any */ 362 for (item = 0, line = 0; line < last_line; line++, item += 8) 363 if (bitmap_weight((unsigned long *)&pmap[item], 64 * 8)) 364 DP_NOTICE(p_hwfn, 365 "line 0x%04x: 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx\n", 366 line, 367 pmap[item], 368 pmap[item + 1], 369 pmap[item + 2], 370 pmap[item + 3], 371 pmap[item + 4], 372 pmap[item + 5], 373 pmap[item + 6], pmap[item + 7]); 374 375 /* print last unaligned non-zero line, if any */ 376 if ((bmap->max_count % (64 * 8)) && 377 (bitmap_weight((unsigned long *)&pmap[item], 378 bmap->max_count - item * 64))) { 379 offset = sprintf(str_last_line, "line 0x%04x: ", line); 380 for (; item < last_item; item++) 381 offset += sprintf(str_last_line + offset, 382 "0x%016llx ", pmap[item]); 383 DP_NOTICE(p_hwfn, "%s\n", str_last_line); 384 } 385 386 end: 387 kfree(bmap->bitmap); 388 bmap->bitmap = NULL; 389 } 390 391 static void qed_rdma_resc_free(struct qed_hwfn *p_hwfn) 392 { 393 struct qed_rdma_info *p_rdma_info = p_hwfn->p_rdma_info; 394 395 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 396 qed_iwarp_resc_free(p_hwfn); 397 398 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->cid_map, 1); 399 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->pd_map, 1); 400 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, 1); 401 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->cq_map, 1); 402 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->toggle_bits, 0); 403 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->tid_map, 1); 404 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->srq_map, 1); 405 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->real_cid_map, 1); 406 qed_rdma_bmap_free(p_hwfn, &p_hwfn->p_rdma_info->xrc_srq_map, 1); 407 408 kfree(p_rdma_info->port); 409 kfree(p_rdma_info->dev); 410 } 411 412 static void qed_rdma_free_tid(void *rdma_cxt, u32 itid) 413 { 414 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 415 416 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid); 417 418 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 419 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->tid_map, itid); 420 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 421 } 422 423 static void qed_rdma_free_reserved_lkey(struct qed_hwfn *p_hwfn) 424 { 425 qed_rdma_free_tid(p_hwfn, p_hwfn->p_rdma_info->dev->reserved_lkey); 426 } 427 428 static void qed_rdma_free(struct qed_hwfn *p_hwfn) 429 { 430 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Freeing RDMA\n"); 431 432 qed_rdma_free_reserved_lkey(p_hwfn); 433 qed_cxt_free_proto_ilt(p_hwfn, p_hwfn->p_rdma_info->proto); 434 qed_rdma_resc_free(p_hwfn); 435 } 436 437 static void qed_rdma_get_guid(struct qed_hwfn *p_hwfn, u8 *guid) 438 { 439 guid[0] = p_hwfn->hw_info.hw_mac_addr[0] ^ 2; 440 guid[1] = p_hwfn->hw_info.hw_mac_addr[1]; 441 guid[2] = p_hwfn->hw_info.hw_mac_addr[2]; 442 guid[3] = 0xff; 443 guid[4] = 0xfe; 444 guid[5] = p_hwfn->hw_info.hw_mac_addr[3]; 445 guid[6] = p_hwfn->hw_info.hw_mac_addr[4]; 446 guid[7] = p_hwfn->hw_info.hw_mac_addr[5]; 447 } 448 449 static void qed_rdma_init_events(struct qed_hwfn *p_hwfn, 450 struct qed_rdma_start_in_params *params) 451 { 452 struct qed_rdma_events *events; 453 454 events = &p_hwfn->p_rdma_info->events; 455 456 events->unaffiliated_event = params->events->unaffiliated_event; 457 events->affiliated_event = params->events->affiliated_event; 458 events->context = params->events->context; 459 } 460 461 static void qed_rdma_init_devinfo(struct qed_hwfn *p_hwfn, 462 struct qed_rdma_start_in_params *params) 463 { 464 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev; 465 struct qed_dev *cdev = p_hwfn->cdev; 466 u32 pci_status_control; 467 u32 num_qps; 468 469 /* Vendor specific information */ 470 dev->vendor_id = cdev->vendor_id; 471 dev->vendor_part_id = cdev->device_id; 472 dev->hw_ver = cdev->chip_rev; 473 dev->fw_ver = (FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | 474 (FW_REVISION_VERSION << 8) | (FW_ENGINEERING_VERSION); 475 476 qed_rdma_get_guid(p_hwfn, (u8 *)&dev->sys_image_guid); 477 dev->node_guid = dev->sys_image_guid; 478 479 dev->max_sge = min_t(u32, RDMA_MAX_SGE_PER_SQ_WQE, 480 RDMA_MAX_SGE_PER_RQ_WQE); 481 482 if (cdev->rdma_max_sge) 483 dev->max_sge = min_t(u32, cdev->rdma_max_sge, dev->max_sge); 484 485 dev->max_srq_sge = QED_RDMA_MAX_SGE_PER_SRQ_WQE; 486 if (p_hwfn->cdev->rdma_max_srq_sge) { 487 dev->max_srq_sge = min_t(u32, 488 p_hwfn->cdev->rdma_max_srq_sge, 489 dev->max_srq_sge); 490 } 491 dev->max_inline = ROCE_REQ_MAX_INLINE_DATA_SIZE; 492 493 dev->max_inline = (cdev->rdma_max_inline) ? 494 min_t(u32, cdev->rdma_max_inline, dev->max_inline) : 495 dev->max_inline; 496 497 dev->max_wqe = QED_RDMA_MAX_WQE; 498 dev->max_cnq = (u8)FEAT_NUM(p_hwfn, QED_RDMA_CNQ); 499 500 /* The number of QPs may be higher than QED_ROCE_MAX_QPS, because 501 * it is up-aligned to 16 and then to ILT page size within qed cxt. 502 * This is OK in terms of ILT but we don't want to configure the FW 503 * above its abilities 504 */ 505 num_qps = ROCE_MAX_QPS; 506 num_qps = min_t(u64, num_qps, p_hwfn->p_rdma_info->num_qps); 507 dev->max_qp = num_qps; 508 509 /* CQs uses the same icids that QPs use hence they are limited by the 510 * number of icids. There are two icids per QP. 511 */ 512 dev->max_cq = num_qps * 2; 513 514 /* The number of mrs is smaller by 1 since the first is reserved */ 515 dev->max_mr = p_hwfn->p_rdma_info->num_mrs - 1; 516 dev->max_mr_size = QED_RDMA_MAX_MR_SIZE; 517 518 /* The maximum CQE capacity per CQ supported. 519 * max number of cqes will be in two layer pbl, 520 * 8 is the pointer size in bytes 521 * 32 is the size of cq element in bytes 522 */ 523 if (params->cq_mode == QED_RDMA_CQ_MODE_32_BITS) 524 dev->max_cqe = QED_RDMA_MAX_CQE_32_BIT; 525 else 526 dev->max_cqe = QED_RDMA_MAX_CQE_16_BIT; 527 528 dev->max_mw = 0; 529 dev->max_mr_mw_fmr_pbl = (PAGE_SIZE / 8) * (PAGE_SIZE / 8); 530 dev->max_mr_mw_fmr_size = dev->max_mr_mw_fmr_pbl * PAGE_SIZE; 531 dev->max_pkey = QED_RDMA_MAX_P_KEY; 532 533 dev->max_srq = p_hwfn->p_rdma_info->num_srqs; 534 dev->max_srq_wr = QED_RDMA_MAX_SRQ_WQE_ELEM; 535 dev->max_qp_resp_rd_atomic_resc = RDMA_RING_PAGE_SIZE / 536 (RDMA_RESP_RD_ATOMIC_ELM_SIZE * 2); 537 dev->max_qp_req_rd_atomic_resc = RDMA_RING_PAGE_SIZE / 538 RDMA_REQ_RD_ATOMIC_ELM_SIZE; 539 dev->max_dev_resp_rd_atomic_resc = dev->max_qp_resp_rd_atomic_resc * 540 p_hwfn->p_rdma_info->num_qps; 541 dev->page_size_caps = QED_RDMA_PAGE_SIZE_CAPS; 542 dev->dev_ack_delay = QED_RDMA_ACK_DELAY; 543 dev->max_pd = RDMA_MAX_PDS; 544 dev->max_ah = p_hwfn->p_rdma_info->num_qps; 545 dev->max_stats_queues = (u8)RESC_NUM(p_hwfn, QED_RDMA_STATS_QUEUE); 546 547 /* Set capablities */ 548 dev->dev_caps = 0; 549 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RNR_NAK, 1); 550 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_ACTIVE_EVENT, 1); 551 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_PORT_CHANGE_EVENT, 1); 552 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_RESIZE_CQ, 1); 553 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_MEMORY_EXT, 1); 554 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_BASE_QUEUE_EXT, 1); 555 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ZBVA, 1); 556 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_LOCAL_INV_FENCE, 1); 557 558 /* Check atomic operations support in PCI configuration space. */ 559 pcie_capability_read_dword(cdev->pdev, PCI_EXP_DEVCTL2, 560 &pci_status_control); 561 562 if (pci_status_control & PCI_EXP_DEVCTL2_LTR_EN) 563 SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ATOMIC_OP, 1); 564 565 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 566 qed_iwarp_init_devinfo(p_hwfn); 567 } 568 569 static void qed_rdma_init_port(struct qed_hwfn *p_hwfn) 570 { 571 struct qed_rdma_port *port = p_hwfn->p_rdma_info->port; 572 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev; 573 574 port->port_state = p_hwfn->mcp_info->link_output.link_up ? 575 QED_RDMA_PORT_UP : QED_RDMA_PORT_DOWN; 576 577 port->max_msg_size = min_t(u64, 578 (dev->max_mr_mw_fmr_size * 579 p_hwfn->cdev->rdma_max_sge), 580 BIT(31)); 581 582 port->pkey_bad_counter = 0; 583 } 584 585 static int qed_rdma_init_hw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 586 { 587 int rc = 0; 588 589 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Initializing HW\n"); 590 p_hwfn->b_rdma_enabled_in_prs = false; 591 592 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 593 qed_iwarp_init_hw(p_hwfn, p_ptt); 594 else 595 rc = qed_roce_init_hw(p_hwfn, p_ptt); 596 597 return rc; 598 } 599 600 static int qed_rdma_start_fw(struct qed_hwfn *p_hwfn, 601 struct qed_rdma_start_in_params *params, 602 struct qed_ptt *p_ptt) 603 { 604 struct rdma_init_func_ramrod_data *p_ramrod; 605 struct qed_rdma_cnq_params *p_cnq_pbl_list; 606 struct rdma_init_func_hdr *p_params_header; 607 struct rdma_cnq_params *p_cnq_params; 608 struct qed_sp_init_data init_data; 609 struct qed_spq_entry *p_ent; 610 u32 cnq_id, sb_id; 611 u16 igu_sb_id; 612 int rc; 613 614 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Starting FW\n"); 615 616 /* Save the number of cnqs for the function close ramrod */ 617 p_hwfn->p_rdma_info->num_cnqs = params->desired_cnq; 618 619 /* Get SPQ entry */ 620 memset(&init_data, 0, sizeof(init_data)); 621 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 622 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 623 624 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_INIT, 625 p_hwfn->p_rdma_info->proto, &init_data); 626 if (rc) 627 return rc; 628 629 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) { 630 qed_iwarp_init_fw_ramrod(p_hwfn, 631 &p_ent->ramrod.iwarp_init_func); 632 p_ramrod = &p_ent->ramrod.iwarp_init_func.rdma; 633 } else { 634 p_ramrod = &p_ent->ramrod.roce_init_func.rdma; 635 } 636 637 p_params_header = &p_ramrod->params_header; 638 p_params_header->cnq_start_offset = (u8)RESC_START(p_hwfn, 639 QED_RDMA_CNQ_RAM); 640 p_params_header->num_cnqs = params->desired_cnq; 641 p_params_header->first_reg_srq_id = 642 cpu_to_le16(p_hwfn->p_rdma_info->srq_id_offset); 643 p_params_header->reg_srq_base_addr = 644 cpu_to_le32(qed_cxt_get_ilt_page_size(p_hwfn, ILT_CLI_TSDM)); 645 if (params->cq_mode == QED_RDMA_CQ_MODE_16_BITS) 646 p_params_header->cq_ring_mode = 1; 647 else 648 p_params_header->cq_ring_mode = 0; 649 650 for (cnq_id = 0; cnq_id < params->desired_cnq; cnq_id++) { 651 sb_id = qed_rdma_get_sb_id(p_hwfn, cnq_id); 652 igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id); 653 p_ramrod->cnq_params[cnq_id].sb_num = cpu_to_le16(igu_sb_id); 654 p_cnq_params = &p_ramrod->cnq_params[cnq_id]; 655 p_cnq_pbl_list = ¶ms->cnq_pbl_list[cnq_id]; 656 657 p_cnq_params->sb_index = p_hwfn->pf_params.rdma_pf_params.gl_pi; 658 p_cnq_params->num_pbl_pages = p_cnq_pbl_list->num_pbl_pages; 659 660 DMA_REGPAIR_LE(p_cnq_params->pbl_base_addr, 661 p_cnq_pbl_list->pbl_ptr); 662 663 /* we assume here that cnq_id and qz_offset are the same */ 664 p_cnq_params->queue_zone_num = 665 cpu_to_le16(p_hwfn->p_rdma_info->queue_zone_base + 666 cnq_id); 667 } 668 669 return qed_spq_post(p_hwfn, p_ent, NULL); 670 } 671 672 static int qed_rdma_alloc_tid(void *rdma_cxt, u32 *itid) 673 { 674 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 675 int rc; 676 677 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID\n"); 678 679 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 680 rc = qed_rdma_bmap_alloc_id(p_hwfn, 681 &p_hwfn->p_rdma_info->tid_map, itid); 682 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 683 if (rc) 684 goto out; 685 686 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_TASK, *itid); 687 out: 688 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Allocate TID - done, rc = %d\n", rc); 689 return rc; 690 } 691 692 static int qed_rdma_reserve_lkey(struct qed_hwfn *p_hwfn) 693 { 694 struct qed_rdma_device *dev = p_hwfn->p_rdma_info->dev; 695 696 /* Tid 0 will be used as the key for "reserved MR". 697 * The driver should allocate memory for it so it can be loaded but no 698 * ramrod should be passed on it. 699 */ 700 qed_rdma_alloc_tid(p_hwfn, &dev->reserved_lkey); 701 if (dev->reserved_lkey != RDMA_RESERVED_LKEY) { 702 DP_NOTICE(p_hwfn, 703 "Reserved lkey should be equal to RDMA_RESERVED_LKEY\n"); 704 return -EINVAL; 705 } 706 707 return 0; 708 } 709 710 static int qed_rdma_setup(struct qed_hwfn *p_hwfn, 711 struct qed_ptt *p_ptt, 712 struct qed_rdma_start_in_params *params) 713 { 714 int rc; 715 716 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA setup\n"); 717 718 qed_rdma_init_devinfo(p_hwfn, params); 719 qed_rdma_init_port(p_hwfn); 720 qed_rdma_init_events(p_hwfn, params); 721 722 rc = qed_rdma_reserve_lkey(p_hwfn); 723 if (rc) 724 return rc; 725 726 rc = qed_rdma_init_hw(p_hwfn, p_ptt); 727 if (rc) 728 return rc; 729 730 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) { 731 rc = qed_iwarp_setup(p_hwfn, params); 732 if (rc) 733 return rc; 734 } else { 735 rc = qed_roce_setup(p_hwfn); 736 if (rc) 737 return rc; 738 } 739 740 return qed_rdma_start_fw(p_hwfn, params, p_ptt); 741 } 742 743 static int qed_rdma_stop(void *rdma_cxt) 744 { 745 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 746 struct rdma_close_func_ramrod_data *p_ramrod; 747 struct qed_sp_init_data init_data; 748 struct qed_spq_entry *p_ent; 749 struct qed_ptt *p_ptt; 750 u32 ll2_ethertype_en; 751 int rc = -EBUSY; 752 753 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop\n"); 754 755 p_ptt = qed_ptt_acquire(p_hwfn); 756 if (!p_ptt) { 757 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Failed to acquire PTT\n"); 758 return rc; 759 } 760 761 /* Disable RoCE search */ 762 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0); 763 p_hwfn->b_rdma_enabled_in_prs = false; 764 p_hwfn->p_rdma_info->active = 0; 765 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 0); 766 767 ll2_ethertype_en = qed_rd(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN); 768 769 qed_wr(p_hwfn, p_ptt, PRS_REG_LIGHT_L2_ETHERTYPE_EN, 770 (ll2_ethertype_en & 0xFFFE)); 771 772 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) { 773 rc = qed_iwarp_stop(p_hwfn); 774 if (rc) { 775 qed_ptt_release(p_hwfn, p_ptt); 776 return rc; 777 } 778 } else { 779 qed_roce_stop(p_hwfn); 780 } 781 782 qed_ptt_release(p_hwfn, p_ptt); 783 784 /* Get SPQ entry */ 785 memset(&init_data, 0, sizeof(init_data)); 786 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 787 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 788 789 /* Stop RoCE */ 790 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_FUNC_CLOSE, 791 p_hwfn->p_rdma_info->proto, &init_data); 792 if (rc) 793 goto out; 794 795 p_ramrod = &p_ent->ramrod.rdma_close_func; 796 797 p_ramrod->num_cnqs = p_hwfn->p_rdma_info->num_cnqs; 798 p_ramrod->cnq_start_offset = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM); 799 800 rc = qed_spq_post(p_hwfn, p_ent, NULL); 801 802 out: 803 qed_rdma_free(p_hwfn); 804 805 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA stop done, rc = %d\n", rc); 806 return rc; 807 } 808 809 static int qed_rdma_add_user(void *rdma_cxt, 810 struct qed_rdma_add_user_out_params *out_params) 811 { 812 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 813 u32 dpi_start_offset; 814 u32 returned_id = 0; 815 int rc; 816 817 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding User\n"); 818 819 /* Allocate DPI */ 820 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 821 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, 822 &returned_id); 823 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 824 825 out_params->dpi = (u16)returned_id; 826 827 /* Calculate the corresponding DPI address */ 828 dpi_start_offset = p_hwfn->dpi_start_offset; 829 830 out_params->dpi_addr = p_hwfn->doorbells + dpi_start_offset + 831 out_params->dpi * p_hwfn->dpi_size; 832 833 out_params->dpi_phys_addr = p_hwfn->db_phys_addr + 834 dpi_start_offset + 835 ((out_params->dpi) * p_hwfn->dpi_size); 836 837 out_params->dpi_size = p_hwfn->dpi_size; 838 out_params->wid_count = p_hwfn->wid_count; 839 840 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Adding user - done, rc = %d\n", rc); 841 return rc; 842 } 843 844 static struct qed_rdma_port *qed_rdma_query_port(void *rdma_cxt) 845 { 846 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 847 struct qed_rdma_port *p_port = p_hwfn->p_rdma_info->port; 848 struct qed_mcp_link_state *p_link_output; 849 850 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA Query port\n"); 851 852 /* The link state is saved only for the leading hwfn */ 853 p_link_output = &QED_LEADING_HWFN(p_hwfn->cdev)->mcp_info->link_output; 854 855 p_port->port_state = p_link_output->link_up ? QED_RDMA_PORT_UP 856 : QED_RDMA_PORT_DOWN; 857 858 p_port->link_speed = p_link_output->speed; 859 860 p_port->max_msg_size = RDMA_MAX_DATA_SIZE_IN_WQE; 861 862 return p_port; 863 } 864 865 static struct qed_rdma_device *qed_rdma_query_device(void *rdma_cxt) 866 { 867 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 868 869 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query device\n"); 870 871 /* Return struct with device parameters */ 872 return p_hwfn->p_rdma_info->dev; 873 } 874 875 static void qed_rdma_cnq_prod_update(void *rdma_cxt, u8 qz_offset, u16 prod) 876 { 877 struct qed_hwfn *p_hwfn; 878 u16 qz_num; 879 u32 addr; 880 881 p_hwfn = (struct qed_hwfn *)rdma_cxt; 882 883 if (qz_offset > p_hwfn->p_rdma_info->max_queue_zones) { 884 DP_NOTICE(p_hwfn, 885 "queue zone offset %d is too large (max is %d)\n", 886 qz_offset, p_hwfn->p_rdma_info->max_queue_zones); 887 return; 888 } 889 890 qz_num = p_hwfn->p_rdma_info->queue_zone_base + qz_offset; 891 addr = GTT_BAR0_MAP_REG_USDM_RAM + 892 USTORM_COMMON_QUEUE_CONS_OFFSET(qz_num); 893 894 REG_WR16(p_hwfn, addr, prod); 895 896 /* keep prod updates ordered */ 897 wmb(); 898 } 899 900 static int qed_fill_rdma_dev_info(struct qed_dev *cdev, 901 struct qed_dev_rdma_info *info) 902 { 903 struct qed_hwfn *p_hwfn = QED_AFFIN_HWFN(cdev); 904 905 memset(info, 0, sizeof(*info)); 906 907 info->rdma_type = QED_IS_ROCE_PERSONALITY(p_hwfn) ? 908 QED_RDMA_TYPE_ROCE : QED_RDMA_TYPE_IWARP; 909 910 info->user_dpm_enabled = (p_hwfn->db_bar_no_edpm == 0); 911 912 qed_fill_dev_info(cdev, &info->common); 913 914 return 0; 915 } 916 917 static int qed_rdma_get_sb_start(struct qed_dev *cdev) 918 { 919 int feat_num; 920 921 if (cdev->num_hwfns > 1) 922 feat_num = FEAT_NUM(QED_AFFIN_HWFN(cdev), QED_PF_L2_QUE); 923 else 924 feat_num = FEAT_NUM(QED_AFFIN_HWFN(cdev), QED_PF_L2_QUE) * 925 cdev->num_hwfns; 926 927 return feat_num; 928 } 929 930 static int qed_rdma_get_min_cnq_msix(struct qed_dev *cdev) 931 { 932 int n_cnq = FEAT_NUM(QED_AFFIN_HWFN(cdev), QED_RDMA_CNQ); 933 int n_msix = cdev->int_params.rdma_msix_cnt; 934 935 return min_t(int, n_cnq, n_msix); 936 } 937 938 static int qed_rdma_set_int(struct qed_dev *cdev, u16 cnt) 939 { 940 int limit = 0; 941 942 /* Mark the fastpath as free/used */ 943 cdev->int_params.fp_initialized = cnt ? true : false; 944 945 if (cdev->int_params.out.int_mode != QED_INT_MODE_MSIX) { 946 DP_ERR(cdev, 947 "qed roce supports only MSI-X interrupts (detected %d).\n", 948 cdev->int_params.out.int_mode); 949 return -EINVAL; 950 } else if (cdev->int_params.fp_msix_cnt) { 951 limit = cdev->int_params.rdma_msix_cnt; 952 } 953 954 if (!limit) 955 return -ENOMEM; 956 957 return min_t(int, cnt, limit); 958 } 959 960 static int qed_rdma_get_int(struct qed_dev *cdev, struct qed_int_info *info) 961 { 962 memset(info, 0, sizeof(*info)); 963 964 if (!cdev->int_params.fp_initialized) { 965 DP_INFO(cdev, 966 "Protocol driver requested interrupt information, but its support is not yet configured\n"); 967 return -EINVAL; 968 } 969 970 if (cdev->int_params.out.int_mode == QED_INT_MODE_MSIX) { 971 int msix_base = cdev->int_params.rdma_msix_base; 972 973 info->msix_cnt = cdev->int_params.rdma_msix_cnt; 974 info->msix = &cdev->int_params.msix_table[msix_base]; 975 976 DP_VERBOSE(cdev, QED_MSG_RDMA, "msix_cnt = %d msix_base=%d\n", 977 info->msix_cnt, msix_base); 978 } 979 980 return 0; 981 } 982 983 static int qed_rdma_alloc_pd(void *rdma_cxt, u16 *pd) 984 { 985 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 986 u32 returned_id; 987 int rc; 988 989 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD\n"); 990 991 /* Allocates an unused protection domain */ 992 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 993 rc = qed_rdma_bmap_alloc_id(p_hwfn, 994 &p_hwfn->p_rdma_info->pd_map, &returned_id); 995 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 996 997 *pd = (u16)returned_id; 998 999 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc PD - done, rc = %d\n", rc); 1000 return rc; 1001 } 1002 1003 static void qed_rdma_free_pd(void *rdma_cxt, u16 pd) 1004 { 1005 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1006 1007 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "pd = %08x\n", pd); 1008 1009 /* Returns a previously allocated protection domain for reuse */ 1010 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1011 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->pd_map, pd); 1012 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1013 } 1014 1015 static int qed_rdma_alloc_xrcd(void *rdma_cxt, u16 *xrcd_id) 1016 { 1017 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1018 u32 returned_id; 1019 int rc; 1020 1021 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc XRCD\n"); 1022 1023 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1024 rc = qed_rdma_bmap_alloc_id(p_hwfn, 1025 &p_hwfn->p_rdma_info->xrcd_map, 1026 &returned_id); 1027 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1028 if (rc) { 1029 DP_NOTICE(p_hwfn, "Failed in allocating xrcd id\n"); 1030 return rc; 1031 } 1032 1033 *xrcd_id = (u16)returned_id; 1034 1035 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Alloc XRCD - done, rc = %d\n", rc); 1036 return rc; 1037 } 1038 1039 static void qed_rdma_free_xrcd(void *rdma_cxt, u16 xrcd_id) 1040 { 1041 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1042 1043 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "xrcd_id = %08x\n", xrcd_id); 1044 1045 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1046 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->xrcd_map, xrcd_id); 1047 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1048 } 1049 1050 static enum qed_rdma_toggle_bit 1051 qed_rdma_toggle_bit_create_resize_cq(struct qed_hwfn *p_hwfn, u16 icid) 1052 { 1053 struct qed_rdma_info *p_info = p_hwfn->p_rdma_info; 1054 enum qed_rdma_toggle_bit toggle_bit; 1055 u32 bmap_id; 1056 1057 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", icid); 1058 1059 /* the function toggle the bit that is related to a given icid 1060 * and returns the new toggle bit's value 1061 */ 1062 bmap_id = icid - qed_cxt_get_proto_cid_start(p_hwfn, p_info->proto); 1063 1064 spin_lock_bh(&p_info->lock); 1065 toggle_bit = !test_and_change_bit(bmap_id, 1066 p_info->toggle_bits.bitmap); 1067 spin_unlock_bh(&p_info->lock); 1068 1069 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QED_RDMA_TOGGLE_BIT_= %d\n", 1070 toggle_bit); 1071 1072 return toggle_bit; 1073 } 1074 1075 static int qed_rdma_create_cq(void *rdma_cxt, 1076 struct qed_rdma_create_cq_in_params *params, 1077 u16 *icid) 1078 { 1079 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1080 struct qed_rdma_info *p_info = p_hwfn->p_rdma_info; 1081 struct rdma_create_cq_ramrod_data *p_ramrod; 1082 enum qed_rdma_toggle_bit toggle_bit; 1083 struct qed_sp_init_data init_data; 1084 struct qed_spq_entry *p_ent; 1085 u32 returned_id, start_cid; 1086 int rc; 1087 1088 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "cq_handle = %08x%08x\n", 1089 params->cq_handle_hi, params->cq_handle_lo); 1090 1091 /* Allocate icid */ 1092 spin_lock_bh(&p_info->lock); 1093 rc = qed_rdma_bmap_alloc_id(p_hwfn, &p_info->cq_map, &returned_id); 1094 spin_unlock_bh(&p_info->lock); 1095 1096 if (rc) { 1097 DP_NOTICE(p_hwfn, "Can't create CQ, rc = %d\n", rc); 1098 return rc; 1099 } 1100 1101 start_cid = qed_cxt_get_proto_cid_start(p_hwfn, 1102 p_info->proto); 1103 *icid = returned_id + start_cid; 1104 1105 /* Check if icid requires a page allocation */ 1106 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, QED_ELEM_CXT, *icid); 1107 if (rc) 1108 goto err; 1109 1110 /* Get SPQ entry */ 1111 memset(&init_data, 0, sizeof(init_data)); 1112 init_data.cid = *icid; 1113 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1114 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1115 1116 /* Send create CQ ramrod */ 1117 rc = qed_sp_init_request(p_hwfn, &p_ent, 1118 RDMA_RAMROD_CREATE_CQ, 1119 p_info->proto, &init_data); 1120 if (rc) 1121 goto err; 1122 1123 p_ramrod = &p_ent->ramrod.rdma_create_cq; 1124 1125 p_ramrod->cq_handle.hi = cpu_to_le32(params->cq_handle_hi); 1126 p_ramrod->cq_handle.lo = cpu_to_le32(params->cq_handle_lo); 1127 p_ramrod->dpi = cpu_to_le16(params->dpi); 1128 p_ramrod->is_two_level_pbl = params->pbl_two_level; 1129 p_ramrod->max_cqes = cpu_to_le32(params->cq_size); 1130 DMA_REGPAIR_LE(p_ramrod->pbl_addr, params->pbl_ptr); 1131 p_ramrod->pbl_num_pages = cpu_to_le16(params->pbl_num_pages); 1132 p_ramrod->cnq_id = (u8)RESC_START(p_hwfn, QED_RDMA_CNQ_RAM) + 1133 params->cnq_id; 1134 p_ramrod->int_timeout = params->int_timeout; 1135 1136 /* toggle the bit for every resize or create cq for a given icid */ 1137 toggle_bit = qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid); 1138 1139 p_ramrod->toggle_bit = toggle_bit; 1140 1141 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1142 if (rc) { 1143 /* restore toggle bit */ 1144 qed_rdma_toggle_bit_create_resize_cq(p_hwfn, *icid); 1145 goto err; 1146 } 1147 1148 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Created CQ, rc = %d\n", rc); 1149 return rc; 1150 1151 err: 1152 /* release allocated icid */ 1153 spin_lock_bh(&p_info->lock); 1154 qed_bmap_release_id(p_hwfn, &p_info->cq_map, returned_id); 1155 spin_unlock_bh(&p_info->lock); 1156 DP_NOTICE(p_hwfn, "Create CQ failed, rc = %d\n", rc); 1157 1158 return rc; 1159 } 1160 1161 static int 1162 qed_rdma_destroy_cq(void *rdma_cxt, 1163 struct qed_rdma_destroy_cq_in_params *in_params, 1164 struct qed_rdma_destroy_cq_out_params *out_params) 1165 { 1166 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1167 struct rdma_destroy_cq_output_params *p_ramrod_res; 1168 struct rdma_destroy_cq_ramrod_data *p_ramrod; 1169 struct qed_sp_init_data init_data; 1170 struct qed_spq_entry *p_ent; 1171 dma_addr_t ramrod_res_phys; 1172 enum protocol_type proto; 1173 int rc = -ENOMEM; 1174 1175 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", in_params->icid); 1176 1177 p_ramrod_res = 1178 (struct rdma_destroy_cq_output_params *) 1179 dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1180 sizeof(struct rdma_destroy_cq_output_params), 1181 &ramrod_res_phys, GFP_KERNEL); 1182 if (!p_ramrod_res) { 1183 DP_NOTICE(p_hwfn, 1184 "qed destroy cq failed: cannot allocate memory (ramrod)\n"); 1185 return rc; 1186 } 1187 1188 /* Get SPQ entry */ 1189 memset(&init_data, 0, sizeof(init_data)); 1190 init_data.cid = in_params->icid; 1191 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1192 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1193 proto = p_hwfn->p_rdma_info->proto; 1194 /* Send destroy CQ ramrod */ 1195 rc = qed_sp_init_request(p_hwfn, &p_ent, 1196 RDMA_RAMROD_DESTROY_CQ, 1197 proto, &init_data); 1198 if (rc) 1199 goto err; 1200 1201 p_ramrod = &p_ent->ramrod.rdma_destroy_cq; 1202 DMA_REGPAIR_LE(p_ramrod->output_params_addr, ramrod_res_phys); 1203 1204 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1205 if (rc) 1206 goto err; 1207 1208 out_params->num_cq_notif = le16_to_cpu(p_ramrod_res->cnq_num); 1209 1210 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1211 sizeof(struct rdma_destroy_cq_output_params), 1212 p_ramrod_res, ramrod_res_phys); 1213 1214 /* Free icid */ 1215 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1216 1217 qed_bmap_release_id(p_hwfn, 1218 &p_hwfn->p_rdma_info->cq_map, 1219 (in_params->icid - 1220 qed_cxt_get_proto_cid_start(p_hwfn, proto))); 1221 1222 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1223 1224 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Destroyed CQ, rc = %d\n", rc); 1225 return rc; 1226 1227 err: dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1228 sizeof(struct rdma_destroy_cq_output_params), 1229 p_ramrod_res, ramrod_res_phys); 1230 1231 return rc; 1232 } 1233 1234 void qed_rdma_set_fw_mac(u16 *p_fw_mac, u8 *p_qed_mac) 1235 { 1236 p_fw_mac[0] = cpu_to_le16((p_qed_mac[0] << 8) + p_qed_mac[1]); 1237 p_fw_mac[1] = cpu_to_le16((p_qed_mac[2] << 8) + p_qed_mac[3]); 1238 p_fw_mac[2] = cpu_to_le16((p_qed_mac[4] << 8) + p_qed_mac[5]); 1239 } 1240 1241 static int qed_rdma_query_qp(void *rdma_cxt, 1242 struct qed_rdma_qp *qp, 1243 struct qed_rdma_query_qp_out_params *out_params) 1244 { 1245 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1246 int rc = 0; 1247 1248 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1249 1250 /* The following fields are filled in from qp and not FW as they can't 1251 * be modified by FW 1252 */ 1253 out_params->mtu = qp->mtu; 1254 out_params->dest_qp = qp->dest_qp; 1255 out_params->incoming_atomic_en = qp->incoming_atomic_en; 1256 out_params->e2e_flow_control_en = qp->e2e_flow_control_en; 1257 out_params->incoming_rdma_read_en = qp->incoming_rdma_read_en; 1258 out_params->incoming_rdma_write_en = qp->incoming_rdma_write_en; 1259 out_params->dgid = qp->dgid; 1260 out_params->flow_label = qp->flow_label; 1261 out_params->hop_limit_ttl = qp->hop_limit_ttl; 1262 out_params->traffic_class_tos = qp->traffic_class_tos; 1263 out_params->timeout = qp->ack_timeout; 1264 out_params->rnr_retry = qp->rnr_retry_cnt; 1265 out_params->retry_cnt = qp->retry_cnt; 1266 out_params->min_rnr_nak_timer = qp->min_rnr_nak_timer; 1267 out_params->pkey_index = 0; 1268 out_params->max_rd_atomic = qp->max_rd_atomic_req; 1269 out_params->max_dest_rd_atomic = qp->max_rd_atomic_resp; 1270 out_params->sqd_async = qp->sqd_async; 1271 1272 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 1273 qed_iwarp_query_qp(qp, out_params); 1274 else 1275 rc = qed_roce_query_qp(p_hwfn, qp, out_params); 1276 1277 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Query QP, rc = %d\n", rc); 1278 return rc; 1279 } 1280 1281 static int qed_rdma_destroy_qp(void *rdma_cxt, struct qed_rdma_qp *qp) 1282 { 1283 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1284 int rc = 0; 1285 1286 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x\n", qp->icid); 1287 1288 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) 1289 rc = qed_iwarp_destroy_qp(p_hwfn, qp); 1290 else 1291 rc = qed_roce_destroy_qp(p_hwfn, qp); 1292 1293 /* free qp params struct */ 1294 kfree(qp); 1295 1296 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "QP destroyed\n"); 1297 return rc; 1298 } 1299 1300 static struct qed_rdma_qp * 1301 qed_rdma_create_qp(void *rdma_cxt, 1302 struct qed_rdma_create_qp_in_params *in_params, 1303 struct qed_rdma_create_qp_out_params *out_params) 1304 { 1305 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1306 struct qed_rdma_qp *qp; 1307 u8 max_stats_queues; 1308 int rc; 1309 1310 if (!rdma_cxt || !in_params || !out_params || 1311 !p_hwfn->p_rdma_info->active) { 1312 DP_ERR(p_hwfn->cdev, 1313 "qed roce create qp failed due to NULL entry (rdma_cxt=%p, in=%p, out=%p, roce_info=?\n", 1314 rdma_cxt, in_params, out_params); 1315 return NULL; 1316 } 1317 1318 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1319 "qed rdma create qp called with qp_handle = %08x%08x\n", 1320 in_params->qp_handle_hi, in_params->qp_handle_lo); 1321 1322 /* Some sanity checks... */ 1323 max_stats_queues = p_hwfn->p_rdma_info->dev->max_stats_queues; 1324 if (in_params->stats_queue >= max_stats_queues) { 1325 DP_ERR(p_hwfn->cdev, 1326 "qed rdma create qp failed due to invalid statistics queue %d. maximum is %d\n", 1327 in_params->stats_queue, max_stats_queues); 1328 return NULL; 1329 } 1330 1331 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) { 1332 if (in_params->sq_num_pages * sizeof(struct regpair) > 1333 IWARP_SHARED_QUEUE_PAGE_SQ_PBL_MAX_SIZE) { 1334 DP_NOTICE(p_hwfn->cdev, 1335 "Sq num pages: %d exceeds maximum\n", 1336 in_params->sq_num_pages); 1337 return NULL; 1338 } 1339 if (in_params->rq_num_pages * sizeof(struct regpair) > 1340 IWARP_SHARED_QUEUE_PAGE_RQ_PBL_MAX_SIZE) { 1341 DP_NOTICE(p_hwfn->cdev, 1342 "Rq num pages: %d exceeds maximum\n", 1343 in_params->rq_num_pages); 1344 return NULL; 1345 } 1346 } 1347 1348 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1349 if (!qp) 1350 return NULL; 1351 1352 qp->cur_state = QED_ROCE_QP_STATE_RESET; 1353 qp->qp_handle.hi = cpu_to_le32(in_params->qp_handle_hi); 1354 qp->qp_handle.lo = cpu_to_le32(in_params->qp_handle_lo); 1355 qp->qp_handle_async.hi = cpu_to_le32(in_params->qp_handle_async_hi); 1356 qp->qp_handle_async.lo = cpu_to_le32(in_params->qp_handle_async_lo); 1357 qp->use_srq = in_params->use_srq; 1358 qp->signal_all = in_params->signal_all; 1359 qp->fmr_and_reserved_lkey = in_params->fmr_and_reserved_lkey; 1360 qp->pd = in_params->pd; 1361 qp->dpi = in_params->dpi; 1362 qp->sq_cq_id = in_params->sq_cq_id; 1363 qp->sq_num_pages = in_params->sq_num_pages; 1364 qp->sq_pbl_ptr = in_params->sq_pbl_ptr; 1365 qp->rq_cq_id = in_params->rq_cq_id; 1366 qp->rq_num_pages = in_params->rq_num_pages; 1367 qp->rq_pbl_ptr = in_params->rq_pbl_ptr; 1368 qp->srq_id = in_params->srq_id; 1369 qp->req_offloaded = false; 1370 qp->resp_offloaded = false; 1371 qp->e2e_flow_control_en = qp->use_srq ? false : true; 1372 qp->stats_queue = in_params->stats_queue; 1373 qp->qp_type = in_params->qp_type; 1374 qp->xrcd_id = in_params->xrcd_id; 1375 1376 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) { 1377 rc = qed_iwarp_create_qp(p_hwfn, qp, out_params); 1378 qp->qpid = qp->icid; 1379 } else { 1380 qp->edpm_mode = GET_FIELD(in_params->flags, QED_ROCE_EDPM_MODE); 1381 rc = qed_roce_alloc_cid(p_hwfn, &qp->icid); 1382 qp->qpid = ((0xFF << 16) | qp->icid); 1383 } 1384 1385 if (rc) { 1386 kfree(qp); 1387 return NULL; 1388 } 1389 1390 out_params->icid = qp->icid; 1391 out_params->qp_id = qp->qpid; 1392 1393 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Create QP, rc = %d\n", rc); 1394 return qp; 1395 } 1396 1397 static int qed_rdma_modify_qp(void *rdma_cxt, 1398 struct qed_rdma_qp *qp, 1399 struct qed_rdma_modify_qp_in_params *params) 1400 { 1401 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1402 enum qed_roce_qp_state prev_state; 1403 int rc = 0; 1404 1405 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "icid = %08x params->new_state=%d\n", 1406 qp->icid, params->new_state); 1407 1408 if (rc) { 1409 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 1410 return rc; 1411 } 1412 1413 if (GET_FIELD(params->modify_flags, 1414 QED_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN)) { 1415 qp->incoming_rdma_read_en = params->incoming_rdma_read_en; 1416 qp->incoming_rdma_write_en = params->incoming_rdma_write_en; 1417 qp->incoming_atomic_en = params->incoming_atomic_en; 1418 } 1419 1420 /* Update QP structure with the updated values */ 1421 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_ROCE_MODE)) 1422 qp->roce_mode = params->roce_mode; 1423 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_PKEY)) 1424 qp->pkey = params->pkey; 1425 if (GET_FIELD(params->modify_flags, 1426 QED_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN)) 1427 qp->e2e_flow_control_en = params->e2e_flow_control_en; 1428 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_DEST_QP)) 1429 qp->dest_qp = params->dest_qp; 1430 if (GET_FIELD(params->modify_flags, 1431 QED_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR)) { 1432 /* Indicates that the following parameters have changed: 1433 * Traffic class, flow label, hop limit, source GID, 1434 * destination GID, loopback indicator 1435 */ 1436 qp->traffic_class_tos = params->traffic_class_tos; 1437 qp->flow_label = params->flow_label; 1438 qp->hop_limit_ttl = params->hop_limit_ttl; 1439 1440 qp->sgid = params->sgid; 1441 qp->dgid = params->dgid; 1442 qp->udp_src_port = 0; 1443 qp->vlan_id = params->vlan_id; 1444 qp->mtu = params->mtu; 1445 qp->lb_indication = params->lb_indication; 1446 memcpy((u8 *)&qp->remote_mac_addr[0], 1447 (u8 *)¶ms->remote_mac_addr[0], ETH_ALEN); 1448 if (params->use_local_mac) { 1449 memcpy((u8 *)&qp->local_mac_addr[0], 1450 (u8 *)¶ms->local_mac_addr[0], ETH_ALEN); 1451 } else { 1452 memcpy((u8 *)&qp->local_mac_addr[0], 1453 (u8 *)&p_hwfn->hw_info.hw_mac_addr, ETH_ALEN); 1454 } 1455 } 1456 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RQ_PSN)) 1457 qp->rq_psn = params->rq_psn; 1458 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_SQ_PSN)) 1459 qp->sq_psn = params->sq_psn; 1460 if (GET_FIELD(params->modify_flags, 1461 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ)) 1462 qp->max_rd_atomic_req = params->max_rd_atomic_req; 1463 if (GET_FIELD(params->modify_flags, 1464 QED_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP)) 1465 qp->max_rd_atomic_resp = params->max_rd_atomic_resp; 1466 if (GET_FIELD(params->modify_flags, 1467 QED_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT)) 1468 qp->ack_timeout = params->ack_timeout; 1469 if (GET_FIELD(params->modify_flags, QED_ROCE_MODIFY_QP_VALID_RETRY_CNT)) 1470 qp->retry_cnt = params->retry_cnt; 1471 if (GET_FIELD(params->modify_flags, 1472 QED_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT)) 1473 qp->rnr_retry_cnt = params->rnr_retry_cnt; 1474 if (GET_FIELD(params->modify_flags, 1475 QED_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER)) 1476 qp->min_rnr_nak_timer = params->min_rnr_nak_timer; 1477 1478 qp->sqd_async = params->sqd_async; 1479 1480 prev_state = qp->cur_state; 1481 if (GET_FIELD(params->modify_flags, 1482 QED_RDMA_MODIFY_QP_VALID_NEW_STATE)) { 1483 qp->cur_state = params->new_state; 1484 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "qp->cur_state=%d\n", 1485 qp->cur_state); 1486 } 1487 1488 switch (qp->qp_type) { 1489 case QED_RDMA_QP_TYPE_XRC_INI: 1490 qp->has_req = 1; 1491 break; 1492 case QED_RDMA_QP_TYPE_XRC_TGT: 1493 qp->has_resp = 1; 1494 break; 1495 default: 1496 qp->has_req = 1; 1497 qp->has_resp = 1; 1498 } 1499 1500 if (QED_IS_IWARP_PERSONALITY(p_hwfn)) { 1501 enum qed_iwarp_qp_state new_state = 1502 qed_roce2iwarp_state(qp->cur_state); 1503 1504 rc = qed_iwarp_modify_qp(p_hwfn, qp, new_state, 0); 1505 } else { 1506 rc = qed_roce_modify_qp(p_hwfn, qp, prev_state, params); 1507 } 1508 1509 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Modify QP, rc = %d\n", rc); 1510 return rc; 1511 } 1512 1513 static int 1514 qed_rdma_register_tid(void *rdma_cxt, 1515 struct qed_rdma_register_tid_in_params *params) 1516 { 1517 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1518 struct rdma_register_tid_ramrod_data *p_ramrod; 1519 struct qed_sp_init_data init_data; 1520 struct qed_spq_entry *p_ent; 1521 enum rdma_tid_type tid_type; 1522 u8 fw_return_code; 1523 int rc; 1524 1525 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", params->itid); 1526 1527 /* Get SPQ entry */ 1528 memset(&init_data, 0, sizeof(init_data)); 1529 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1530 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1531 1532 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_REGISTER_MR, 1533 p_hwfn->p_rdma_info->proto, &init_data); 1534 if (rc) { 1535 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 1536 return rc; 1537 } 1538 1539 if (p_hwfn->p_rdma_info->last_tid < params->itid) 1540 p_hwfn->p_rdma_info->last_tid = params->itid; 1541 1542 p_ramrod = &p_ent->ramrod.rdma_register_tid; 1543 1544 p_ramrod->flags = 0; 1545 SET_FIELD(p_ramrod->flags, 1546 RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL, 1547 params->pbl_two_level); 1548 1549 SET_FIELD(p_ramrod->flags, 1550 RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED, params->zbva); 1551 1552 SET_FIELD(p_ramrod->flags, 1553 RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR, params->phy_mr); 1554 1555 /* Don't initialize D/C field, as it may override other bits. */ 1556 if (!(params->tid_type == QED_RDMA_TID_FMR) && !(params->dma_mr)) 1557 SET_FIELD(p_ramrod->flags, 1558 RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG, 1559 params->page_size_log - 12); 1560 1561 SET_FIELD(p_ramrod->flags, 1562 RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ, 1563 params->remote_read); 1564 1565 SET_FIELD(p_ramrod->flags, 1566 RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE, 1567 params->remote_write); 1568 1569 SET_FIELD(p_ramrod->flags, 1570 RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC, 1571 params->remote_atomic); 1572 1573 SET_FIELD(p_ramrod->flags, 1574 RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE, 1575 params->local_write); 1576 1577 SET_FIELD(p_ramrod->flags, 1578 RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ, params->local_read); 1579 1580 SET_FIELD(p_ramrod->flags, 1581 RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND, 1582 params->mw_bind); 1583 1584 SET_FIELD(p_ramrod->flags1, 1585 RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG, 1586 params->pbl_page_size_log - 12); 1587 1588 SET_FIELD(p_ramrod->flags2, 1589 RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR, params->dma_mr); 1590 1591 switch (params->tid_type) { 1592 case QED_RDMA_TID_REGISTERED_MR: 1593 tid_type = RDMA_TID_REGISTERED_MR; 1594 break; 1595 case QED_RDMA_TID_FMR: 1596 tid_type = RDMA_TID_FMR; 1597 break; 1598 case QED_RDMA_TID_MW: 1599 tid_type = RDMA_TID_MW; 1600 break; 1601 default: 1602 rc = -EINVAL; 1603 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 1604 qed_sp_destroy_request(p_hwfn, p_ent); 1605 return rc; 1606 } 1607 SET_FIELD(p_ramrod->flags1, 1608 RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE, tid_type); 1609 1610 p_ramrod->itid = cpu_to_le32(params->itid); 1611 p_ramrod->key = params->key; 1612 p_ramrod->pd = cpu_to_le16(params->pd); 1613 p_ramrod->length_hi = (u8)(params->length >> 32); 1614 p_ramrod->length_lo = DMA_LO_LE(params->length); 1615 if (params->zbva) { 1616 /* Lower 32 bits of the registered MR address. 1617 * In case of zero based MR, will hold FBO 1618 */ 1619 p_ramrod->va.hi = 0; 1620 p_ramrod->va.lo = cpu_to_le32(params->fbo); 1621 } else { 1622 DMA_REGPAIR_LE(p_ramrod->va, params->vaddr); 1623 } 1624 DMA_REGPAIR_LE(p_ramrod->pbl_base, params->pbl_ptr); 1625 1626 /* DIF */ 1627 if (params->dif_enabled) { 1628 SET_FIELD(p_ramrod->flags2, 1629 RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG, 1); 1630 DMA_REGPAIR_LE(p_ramrod->dif_error_addr, 1631 params->dif_error_addr); 1632 } 1633 1634 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code); 1635 if (rc) 1636 return rc; 1637 1638 if (fw_return_code != RDMA_RETURN_OK) { 1639 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code); 1640 return -EINVAL; 1641 } 1642 1643 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "Register TID, rc = %d\n", rc); 1644 return rc; 1645 } 1646 1647 static int qed_rdma_deregister_tid(void *rdma_cxt, u32 itid) 1648 { 1649 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1650 struct rdma_deregister_tid_ramrod_data *p_ramrod; 1651 struct qed_sp_init_data init_data; 1652 struct qed_spq_entry *p_ent; 1653 struct qed_ptt *p_ptt; 1654 u8 fw_return_code; 1655 int rc; 1656 1657 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "itid = %08x\n", itid); 1658 1659 /* Get SPQ entry */ 1660 memset(&init_data, 0, sizeof(init_data)); 1661 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1662 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1663 1664 rc = qed_sp_init_request(p_hwfn, &p_ent, RDMA_RAMROD_DEREGISTER_MR, 1665 p_hwfn->p_rdma_info->proto, &init_data); 1666 if (rc) { 1667 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 1668 return rc; 1669 } 1670 1671 p_ramrod = &p_ent->ramrod.rdma_deregister_tid; 1672 p_ramrod->itid = cpu_to_le32(itid); 1673 1674 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code); 1675 if (rc) { 1676 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "rc = %d\n", rc); 1677 return rc; 1678 } 1679 1680 if (fw_return_code == RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR) { 1681 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", fw_return_code); 1682 return -EINVAL; 1683 } else if (fw_return_code == RDMA_RETURN_NIG_DRAIN_REQ) { 1684 /* Bit indicating that the TID is in use and a nig drain is 1685 * required before sending the ramrod again 1686 */ 1687 p_ptt = qed_ptt_acquire(p_hwfn); 1688 if (!p_ptt) { 1689 rc = -EBUSY; 1690 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1691 "Failed to acquire PTT\n"); 1692 return rc; 1693 } 1694 1695 rc = qed_mcp_drain(p_hwfn, p_ptt); 1696 if (rc) { 1697 qed_ptt_release(p_hwfn, p_ptt); 1698 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1699 "Drain failed\n"); 1700 return rc; 1701 } 1702 1703 qed_ptt_release(p_hwfn, p_ptt); 1704 1705 /* Resend the ramrod */ 1706 rc = qed_sp_init_request(p_hwfn, &p_ent, 1707 RDMA_RAMROD_DEREGISTER_MR, 1708 p_hwfn->p_rdma_info->proto, 1709 &init_data); 1710 if (rc) { 1711 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1712 "Failed to init sp-element\n"); 1713 return rc; 1714 } 1715 1716 rc = qed_spq_post(p_hwfn, p_ent, &fw_return_code); 1717 if (rc) { 1718 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1719 "Ramrod failed\n"); 1720 return rc; 1721 } 1722 1723 if (fw_return_code != RDMA_RETURN_OK) { 1724 DP_NOTICE(p_hwfn, "fw_return_code = %d\n", 1725 fw_return_code); 1726 return rc; 1727 } 1728 } 1729 1730 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "De-registered TID, rc = %d\n", rc); 1731 return rc; 1732 } 1733 1734 static void *qed_rdma_get_rdma_ctx(struct qed_dev *cdev) 1735 { 1736 return QED_AFFIN_HWFN(cdev); 1737 } 1738 1739 static struct qed_bmap *qed_rdma_get_srq_bmap(struct qed_hwfn *p_hwfn, 1740 bool is_xrc) 1741 { 1742 if (is_xrc) 1743 return &p_hwfn->p_rdma_info->xrc_srq_map; 1744 1745 return &p_hwfn->p_rdma_info->srq_map; 1746 } 1747 1748 static int qed_rdma_modify_srq(void *rdma_cxt, 1749 struct qed_rdma_modify_srq_in_params *in_params) 1750 { 1751 struct rdma_srq_modify_ramrod_data *p_ramrod; 1752 struct qed_sp_init_data init_data = {}; 1753 struct qed_hwfn *p_hwfn = rdma_cxt; 1754 struct qed_spq_entry *p_ent; 1755 u16 opaque_fid; 1756 int rc; 1757 1758 init_data.opaque_fid = p_hwfn->hw_info.opaque_fid; 1759 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1760 1761 rc = qed_sp_init_request(p_hwfn, &p_ent, 1762 RDMA_RAMROD_MODIFY_SRQ, 1763 p_hwfn->p_rdma_info->proto, &init_data); 1764 if (rc) 1765 return rc; 1766 1767 p_ramrod = &p_ent->ramrod.rdma_modify_srq; 1768 p_ramrod->srq_id.srq_idx = cpu_to_le16(in_params->srq_id); 1769 opaque_fid = p_hwfn->hw_info.opaque_fid; 1770 p_ramrod->srq_id.opaque_fid = cpu_to_le16(opaque_fid); 1771 p_ramrod->wqe_limit = cpu_to_le32(in_params->wqe_limit); 1772 1773 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1774 if (rc) 1775 return rc; 1776 1777 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "modified SRQ id = %x, is_xrc=%u\n", 1778 in_params->srq_id, in_params->is_xrc); 1779 1780 return rc; 1781 } 1782 1783 static int 1784 qed_rdma_destroy_srq(void *rdma_cxt, 1785 struct qed_rdma_destroy_srq_in_params *in_params) 1786 { 1787 struct rdma_srq_destroy_ramrod_data *p_ramrod; 1788 struct qed_sp_init_data init_data = {}; 1789 struct qed_hwfn *p_hwfn = rdma_cxt; 1790 struct qed_spq_entry *p_ent; 1791 struct qed_bmap *bmap; 1792 u16 opaque_fid; 1793 u16 offset; 1794 int rc; 1795 1796 opaque_fid = p_hwfn->hw_info.opaque_fid; 1797 1798 init_data.opaque_fid = opaque_fid; 1799 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1800 1801 rc = qed_sp_init_request(p_hwfn, &p_ent, 1802 RDMA_RAMROD_DESTROY_SRQ, 1803 p_hwfn->p_rdma_info->proto, &init_data); 1804 if (rc) 1805 return rc; 1806 1807 p_ramrod = &p_ent->ramrod.rdma_destroy_srq; 1808 p_ramrod->srq_id.srq_idx = cpu_to_le16(in_params->srq_id); 1809 p_ramrod->srq_id.opaque_fid = cpu_to_le16(opaque_fid); 1810 1811 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1812 if (rc) 1813 return rc; 1814 1815 bmap = qed_rdma_get_srq_bmap(p_hwfn, in_params->is_xrc); 1816 offset = (in_params->is_xrc) ? 0 : p_hwfn->p_rdma_info->srq_id_offset; 1817 1818 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1819 qed_bmap_release_id(p_hwfn, bmap, in_params->srq_id - offset); 1820 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1821 1822 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1823 "XRC/SRQ destroyed Id = %x, is_xrc=%u\n", 1824 in_params->srq_id, in_params->is_xrc); 1825 1826 return rc; 1827 } 1828 1829 static int 1830 qed_rdma_create_srq(void *rdma_cxt, 1831 struct qed_rdma_create_srq_in_params *in_params, 1832 struct qed_rdma_create_srq_out_params *out_params) 1833 { 1834 struct rdma_srq_create_ramrod_data *p_ramrod; 1835 struct qed_sp_init_data init_data = {}; 1836 struct qed_hwfn *p_hwfn = rdma_cxt; 1837 enum qed_cxt_elem_type elem_type; 1838 struct qed_spq_entry *p_ent; 1839 u16 opaque_fid, srq_id; 1840 struct qed_bmap *bmap; 1841 u32 returned_id; 1842 u16 offset; 1843 int rc; 1844 1845 bmap = qed_rdma_get_srq_bmap(p_hwfn, in_params->is_xrc); 1846 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1847 rc = qed_rdma_bmap_alloc_id(p_hwfn, bmap, &returned_id); 1848 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1849 1850 if (rc) { 1851 DP_NOTICE(p_hwfn, 1852 "failed to allocate xrc/srq id (is_xrc=%u)\n", 1853 in_params->is_xrc); 1854 return rc; 1855 } 1856 1857 elem_type = (in_params->is_xrc) ? (QED_ELEM_XRC_SRQ) : (QED_ELEM_SRQ); 1858 rc = qed_cxt_dynamic_ilt_alloc(p_hwfn, elem_type, returned_id); 1859 if (rc) 1860 goto err; 1861 1862 opaque_fid = p_hwfn->hw_info.opaque_fid; 1863 1864 opaque_fid = p_hwfn->hw_info.opaque_fid; 1865 init_data.opaque_fid = opaque_fid; 1866 init_data.comp_mode = QED_SPQ_MODE_EBLOCK; 1867 1868 rc = qed_sp_init_request(p_hwfn, &p_ent, 1869 RDMA_RAMROD_CREATE_SRQ, 1870 p_hwfn->p_rdma_info->proto, &init_data); 1871 if (rc) 1872 goto err; 1873 1874 p_ramrod = &p_ent->ramrod.rdma_create_srq; 1875 DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, in_params->pbl_base_addr); 1876 p_ramrod->pages_in_srq_pbl = cpu_to_le16(in_params->num_pages); 1877 p_ramrod->pd_id = cpu_to_le16(in_params->pd_id); 1878 p_ramrod->srq_id.opaque_fid = cpu_to_le16(opaque_fid); 1879 p_ramrod->page_size = cpu_to_le16(in_params->page_size); 1880 DMA_REGPAIR_LE(p_ramrod->producers_addr, in_params->prod_pair_addr); 1881 offset = (in_params->is_xrc) ? 0 : p_hwfn->p_rdma_info->srq_id_offset; 1882 srq_id = (u16)returned_id + offset; 1883 p_ramrod->srq_id.srq_idx = cpu_to_le16(srq_id); 1884 1885 if (in_params->is_xrc) { 1886 SET_FIELD(p_ramrod->flags, 1887 RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG, 1); 1888 SET_FIELD(p_ramrod->flags, 1889 RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN, 1890 in_params->reserved_key_en); 1891 p_ramrod->xrc_srq_cq_cid = 1892 cpu_to_le32((p_hwfn->hw_info.opaque_fid << 16) | 1893 in_params->cq_cid); 1894 p_ramrod->xrc_domain = cpu_to_le16(in_params->xrcd_id); 1895 } 1896 rc = qed_spq_post(p_hwfn, p_ent, NULL); 1897 if (rc) 1898 goto err; 1899 1900 out_params->srq_id = srq_id; 1901 1902 DP_VERBOSE(p_hwfn, 1903 QED_MSG_RDMA, 1904 "XRC/SRQ created Id = %x (is_xrc=%u)\n", 1905 out_params->srq_id, in_params->is_xrc); 1906 return rc; 1907 1908 err: 1909 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1910 qed_bmap_release_id(p_hwfn, bmap, returned_id); 1911 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1912 1913 return rc; 1914 } 1915 1916 bool qed_rdma_allocated_qps(struct qed_hwfn *p_hwfn) 1917 { 1918 bool result; 1919 1920 /* if rdma wasn't activated yet, naturally there are no qps */ 1921 if (!p_hwfn->p_rdma_info->active) 1922 return false; 1923 1924 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 1925 if (!p_hwfn->p_rdma_info->cid_map.bitmap) 1926 result = false; 1927 else 1928 result = !qed_bmap_is_empty(&p_hwfn->p_rdma_info->cid_map); 1929 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 1930 return result; 1931 } 1932 1933 void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1934 { 1935 u32 val; 1936 1937 val = (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm) ? 0 : 1; 1938 1939 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPM_ENABLE, val); 1940 DP_VERBOSE(p_hwfn, (QED_MSG_DCB | QED_MSG_RDMA), 1941 "Changing DPM_EN state to %d (DCBX=%d, DB_BAR=%d)\n", 1942 val, p_hwfn->dcbx_no_edpm, p_hwfn->db_bar_no_edpm); 1943 } 1944 1945 1946 void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1947 { 1948 p_hwfn->db_bar_no_edpm = true; 1949 1950 qed_rdma_dpm_conf(p_hwfn, p_ptt); 1951 } 1952 1953 static int qed_rdma_start(void *rdma_cxt, 1954 struct qed_rdma_start_in_params *params) 1955 { 1956 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1957 struct qed_ptt *p_ptt; 1958 int rc = -EBUSY; 1959 1960 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, 1961 "desired_cnq = %08x\n", params->desired_cnq); 1962 1963 p_ptt = qed_ptt_acquire(p_hwfn); 1964 if (!p_ptt) 1965 goto err; 1966 1967 rc = qed_rdma_alloc(p_hwfn); 1968 if (rc) 1969 goto err1; 1970 1971 rc = qed_rdma_setup(p_hwfn, p_ptt, params); 1972 if (rc) 1973 goto err2; 1974 1975 qed_ptt_release(p_hwfn, p_ptt); 1976 p_hwfn->p_rdma_info->active = 1; 1977 1978 return rc; 1979 1980 err2: 1981 qed_rdma_free(p_hwfn); 1982 err1: 1983 qed_ptt_release(p_hwfn, p_ptt); 1984 err: 1985 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "RDMA start - error, rc = %d\n", rc); 1986 return rc; 1987 } 1988 1989 static int qed_rdma_init(struct qed_dev *cdev, 1990 struct qed_rdma_start_in_params *params) 1991 { 1992 return qed_rdma_start(QED_AFFIN_HWFN(cdev), params); 1993 } 1994 1995 static void qed_rdma_remove_user(void *rdma_cxt, u16 dpi) 1996 { 1997 struct qed_hwfn *p_hwfn = (struct qed_hwfn *)rdma_cxt; 1998 1999 DP_VERBOSE(p_hwfn, QED_MSG_RDMA, "dpi = %08x\n", dpi); 2000 2001 spin_lock_bh(&p_hwfn->p_rdma_info->lock); 2002 qed_bmap_release_id(p_hwfn, &p_hwfn->p_rdma_info->dpi_map, dpi); 2003 spin_unlock_bh(&p_hwfn->p_rdma_info->lock); 2004 } 2005 2006 static int qed_roce_ll2_set_mac_filter(struct qed_dev *cdev, 2007 u8 *old_mac_address, 2008 u8 *new_mac_address) 2009 { 2010 int rc = 0; 2011 2012 if (old_mac_address) 2013 qed_llh_remove_mac_filter(cdev, 0, old_mac_address); 2014 if (new_mac_address) 2015 rc = qed_llh_add_mac_filter(cdev, 0, new_mac_address); 2016 2017 if (rc) 2018 DP_ERR(cdev, 2019 "qed roce ll2 mac filter set: failed to add MAC filter\n"); 2020 2021 return rc; 2022 } 2023 2024 static int qed_iwarp_set_engine_affin(struct qed_dev *cdev, bool b_reset) 2025 { 2026 enum qed_eng eng; 2027 u8 ppfid = 0; 2028 int rc; 2029 2030 /* Make sure iwarp cmt mode is enabled before setting affinity */ 2031 if (!cdev->iwarp_cmt) 2032 return -EINVAL; 2033 2034 if (b_reset) 2035 eng = QED_BOTH_ENG; 2036 else 2037 eng = cdev->l2_affin_hint ? QED_ENG1 : QED_ENG0; 2038 2039 rc = qed_llh_set_ppfid_affinity(cdev, ppfid, eng); 2040 if (rc) { 2041 DP_NOTICE(cdev, 2042 "Failed to set the engine affinity of ppfid %d\n", 2043 ppfid); 2044 return rc; 2045 } 2046 2047 DP_VERBOSE(cdev, (QED_MSG_RDMA | QED_MSG_SP), 2048 "LLH: Set the engine affinity of non-RoCE packets as %d\n", 2049 eng); 2050 2051 return 0; 2052 } 2053 2054 static const struct qed_rdma_ops qed_rdma_ops_pass = { 2055 .common = &qed_common_ops_pass, 2056 .fill_dev_info = &qed_fill_rdma_dev_info, 2057 .rdma_get_rdma_ctx = &qed_rdma_get_rdma_ctx, 2058 .rdma_init = &qed_rdma_init, 2059 .rdma_add_user = &qed_rdma_add_user, 2060 .rdma_remove_user = &qed_rdma_remove_user, 2061 .rdma_stop = &qed_rdma_stop, 2062 .rdma_query_port = &qed_rdma_query_port, 2063 .rdma_query_device = &qed_rdma_query_device, 2064 .rdma_get_start_sb = &qed_rdma_get_sb_start, 2065 .rdma_get_rdma_int = &qed_rdma_get_int, 2066 .rdma_set_rdma_int = &qed_rdma_set_int, 2067 .rdma_get_min_cnq_msix = &qed_rdma_get_min_cnq_msix, 2068 .rdma_cnq_prod_update = &qed_rdma_cnq_prod_update, 2069 .rdma_alloc_pd = &qed_rdma_alloc_pd, 2070 .rdma_dealloc_pd = &qed_rdma_free_pd, 2071 .rdma_alloc_xrcd = &qed_rdma_alloc_xrcd, 2072 .rdma_dealloc_xrcd = &qed_rdma_free_xrcd, 2073 .rdma_create_cq = &qed_rdma_create_cq, 2074 .rdma_destroy_cq = &qed_rdma_destroy_cq, 2075 .rdma_create_qp = &qed_rdma_create_qp, 2076 .rdma_modify_qp = &qed_rdma_modify_qp, 2077 .rdma_query_qp = &qed_rdma_query_qp, 2078 .rdma_destroy_qp = &qed_rdma_destroy_qp, 2079 .rdma_alloc_tid = &qed_rdma_alloc_tid, 2080 .rdma_free_tid = &qed_rdma_free_tid, 2081 .rdma_register_tid = &qed_rdma_register_tid, 2082 .rdma_deregister_tid = &qed_rdma_deregister_tid, 2083 .rdma_create_srq = &qed_rdma_create_srq, 2084 .rdma_modify_srq = &qed_rdma_modify_srq, 2085 .rdma_destroy_srq = &qed_rdma_destroy_srq, 2086 .ll2_acquire_connection = &qed_ll2_acquire_connection, 2087 .ll2_establish_connection = &qed_ll2_establish_connection, 2088 .ll2_terminate_connection = &qed_ll2_terminate_connection, 2089 .ll2_release_connection = &qed_ll2_release_connection, 2090 .ll2_post_rx_buffer = &qed_ll2_post_rx_buffer, 2091 .ll2_prepare_tx_packet = &qed_ll2_prepare_tx_packet, 2092 .ll2_set_fragment_of_tx_packet = &qed_ll2_set_fragment_of_tx_packet, 2093 .ll2_set_mac_filter = &qed_roce_ll2_set_mac_filter, 2094 .ll2_get_stats = &qed_ll2_get_stats, 2095 .iwarp_set_engine_affin = &qed_iwarp_set_engine_affin, 2096 .iwarp_connect = &qed_iwarp_connect, 2097 .iwarp_create_listen = &qed_iwarp_create_listen, 2098 .iwarp_destroy_listen = &qed_iwarp_destroy_listen, 2099 .iwarp_accept = &qed_iwarp_accept, 2100 .iwarp_reject = &qed_iwarp_reject, 2101 .iwarp_send_rtr = &qed_iwarp_send_rtr, 2102 }; 2103 2104 const struct qed_rdma_ops *qed_get_rdma_ops(void) 2105 { 2106 return &qed_rdma_ops_pass; 2107 } 2108 EXPORT_SYMBOL(qed_get_rdma_ops); 2109