1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2 /************************************************************************** 3 * 4 * Copyright 2008-2015 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 /* 29 * svga3d_surfacedefs.h -- 30 * 31 * Surface definitions and inlineable utilities for SVGA3d. 32 */ 33 34 #ifndef _SVGA3D_SURFACEDEFS_H_ 35 #define _SVGA3D_SURFACEDEFS_H_ 36 37 #define INCLUDE_ALLOW_USERLEVEL 38 #define INCLUDE_ALLOW_MODULE 39 #include "includeCheck.h" 40 41 #include <linux/kernel.h> 42 #include <drm/vmwgfx_drm.h> 43 44 #include "svga3d_reg.h" 45 46 #define surf_size_struct struct drm_vmw_size 47 48 /* 49 * enum svga3d_block_desc - describes generic properties about formats. 50 */ 51 enum svga3d_block_desc { 52 /* Nothing special can be said about this format. */ 53 SVGA3DBLOCKDESC_NONE = 0, 54 55 /* Format contains Blue/U data */ 56 SVGA3DBLOCKDESC_BLUE = 1 << 0, 57 SVGA3DBLOCKDESC_W = 1 << 0, 58 SVGA3DBLOCKDESC_BUMP_L = 1 << 0, 59 60 /* Format contains Green/V data */ 61 SVGA3DBLOCKDESC_GREEN = 1 << 1, 62 SVGA3DBLOCKDESC_V = 1 << 1, 63 64 /* Format contains Red/W/Luminance data */ 65 SVGA3DBLOCKDESC_RED = 1 << 2, 66 SVGA3DBLOCKDESC_U = 1 << 2, 67 SVGA3DBLOCKDESC_LUMINANCE = 1 << 2, 68 69 /* Format contains Alpha/Q data */ 70 SVGA3DBLOCKDESC_ALPHA = 1 << 3, 71 SVGA3DBLOCKDESC_Q = 1 << 3, 72 73 /* Format is a buffer */ 74 SVGA3DBLOCKDESC_BUFFER = 1 << 4, 75 76 /* Format is compressed */ 77 SVGA3DBLOCKDESC_COMPRESSED = 1 << 5, 78 79 /* Format uses IEEE floating point */ 80 SVGA3DBLOCKDESC_FP = 1 << 6, 81 82 /* Three separate blocks store data. */ 83 SVGA3DBLOCKDESC_PLANAR_YUV = 1 << 7, 84 85 /* 2 planes of Y, UV, e.g., NV12. */ 86 SVGA3DBLOCKDESC_2PLANAR_YUV = 1 << 8, 87 88 /* 3 planes of separate Y, U, V, e.g., YV12. */ 89 SVGA3DBLOCKDESC_3PLANAR_YUV = 1 << 9, 90 91 /* Block with a stencil channel */ 92 SVGA3DBLOCKDESC_STENCIL = 1 << 11, 93 94 /* Typeless format */ 95 SVGA3DBLOCKDESC_TYPELESS = 1 << 12, 96 97 /* Channels are signed integers */ 98 SVGA3DBLOCKDESC_SINT = 1 << 13, 99 100 /* Channels are unsigned integers */ 101 SVGA3DBLOCKDESC_UINT = 1 << 14, 102 103 /* Channels are normalized (when sampling) */ 104 SVGA3DBLOCKDESC_NORM = 1 << 15, 105 106 /* Channels are in SRGB */ 107 SVGA3DBLOCKDESC_SRGB = 1 << 16, 108 109 /* Shared exponent */ 110 SVGA3DBLOCKDESC_EXP = 1 << 17, 111 112 /* Format contains color data. */ 113 SVGA3DBLOCKDESC_COLOR = 1 << 18, 114 /* Format contains depth data. */ 115 SVGA3DBLOCKDESC_DEPTH = 1 << 19, 116 /* Format contains bump data. */ 117 SVGA3DBLOCKDESC_BUMP = 1 << 20, 118 119 /* Format contains YUV video data. */ 120 SVGA3DBLOCKDESC_YUV_VIDEO = 1 << 21, 121 122 /* For mixed unsigned/signed formats. */ 123 SVGA3DBLOCKDESC_MIXED = 1 << 22, 124 125 /* For distingushing CxV8U8. */ 126 SVGA3DBLOCKDESC_CX = 1 << 23, 127 128 /* Different compressed format groups. */ 129 SVGA3DBLOCKDESC_BC1 = 1 << 24, 130 SVGA3DBLOCKDESC_BC2 = 1 << 25, 131 SVGA3DBLOCKDESC_BC3 = 1 << 26, 132 SVGA3DBLOCKDESC_BC4 = 1 << 27, 133 SVGA3DBLOCKDESC_BC5 = 1 << 28, 134 135 SVGA3DBLOCKDESC_A_UINT = SVGA3DBLOCKDESC_ALPHA | 136 SVGA3DBLOCKDESC_UINT | 137 SVGA3DBLOCKDESC_COLOR, 138 SVGA3DBLOCKDESC_A_UNORM = SVGA3DBLOCKDESC_A_UINT | 139 SVGA3DBLOCKDESC_NORM, 140 SVGA3DBLOCKDESC_R_UINT = SVGA3DBLOCKDESC_RED | 141 SVGA3DBLOCKDESC_UINT | 142 SVGA3DBLOCKDESC_COLOR, 143 SVGA3DBLOCKDESC_R_UNORM = SVGA3DBLOCKDESC_R_UINT | 144 SVGA3DBLOCKDESC_NORM, 145 SVGA3DBLOCKDESC_R_SINT = SVGA3DBLOCKDESC_RED | 146 SVGA3DBLOCKDESC_SINT | 147 SVGA3DBLOCKDESC_COLOR, 148 SVGA3DBLOCKDESC_R_SNORM = SVGA3DBLOCKDESC_R_SINT | 149 SVGA3DBLOCKDESC_NORM, 150 SVGA3DBLOCKDESC_G_UINT = SVGA3DBLOCKDESC_GREEN | 151 SVGA3DBLOCKDESC_UINT | 152 SVGA3DBLOCKDESC_COLOR, 153 SVGA3DBLOCKDESC_RG_UINT = SVGA3DBLOCKDESC_RED | 154 SVGA3DBLOCKDESC_GREEN | 155 SVGA3DBLOCKDESC_UINT | 156 SVGA3DBLOCKDESC_COLOR, 157 SVGA3DBLOCKDESC_RG_UNORM = SVGA3DBLOCKDESC_RG_UINT | 158 SVGA3DBLOCKDESC_NORM, 159 SVGA3DBLOCKDESC_RG_SINT = SVGA3DBLOCKDESC_RED | 160 SVGA3DBLOCKDESC_GREEN | 161 SVGA3DBLOCKDESC_SINT | 162 SVGA3DBLOCKDESC_COLOR, 163 SVGA3DBLOCKDESC_RG_SNORM = SVGA3DBLOCKDESC_RG_SINT | 164 SVGA3DBLOCKDESC_NORM, 165 SVGA3DBLOCKDESC_RGB_UINT = SVGA3DBLOCKDESC_RED | 166 SVGA3DBLOCKDESC_GREEN | 167 SVGA3DBLOCKDESC_BLUE | 168 SVGA3DBLOCKDESC_UINT | 169 SVGA3DBLOCKDESC_COLOR, 170 SVGA3DBLOCKDESC_RGB_SINT = SVGA3DBLOCKDESC_RED | 171 SVGA3DBLOCKDESC_GREEN | 172 SVGA3DBLOCKDESC_BLUE | 173 SVGA3DBLOCKDESC_SINT | 174 SVGA3DBLOCKDESC_COLOR, 175 SVGA3DBLOCKDESC_RGB_UNORM = SVGA3DBLOCKDESC_RGB_UINT | 176 SVGA3DBLOCKDESC_NORM, 177 SVGA3DBLOCKDESC_RGB_UNORM_SRGB = SVGA3DBLOCKDESC_RGB_UNORM | 178 SVGA3DBLOCKDESC_SRGB, 179 SVGA3DBLOCKDESC_RGBA_UINT = SVGA3DBLOCKDESC_RED | 180 SVGA3DBLOCKDESC_GREEN | 181 SVGA3DBLOCKDESC_BLUE | 182 SVGA3DBLOCKDESC_ALPHA | 183 SVGA3DBLOCKDESC_UINT | 184 SVGA3DBLOCKDESC_COLOR, 185 SVGA3DBLOCKDESC_RGBA_UNORM = SVGA3DBLOCKDESC_RGBA_UINT | 186 SVGA3DBLOCKDESC_NORM, 187 SVGA3DBLOCKDESC_RGBA_UNORM_SRGB = SVGA3DBLOCKDESC_RGBA_UNORM | 188 SVGA3DBLOCKDESC_SRGB, 189 SVGA3DBLOCKDESC_RGBA_SINT = SVGA3DBLOCKDESC_RED | 190 SVGA3DBLOCKDESC_GREEN | 191 SVGA3DBLOCKDESC_BLUE | 192 SVGA3DBLOCKDESC_ALPHA | 193 SVGA3DBLOCKDESC_SINT | 194 SVGA3DBLOCKDESC_COLOR, 195 SVGA3DBLOCKDESC_RGBA_SNORM = SVGA3DBLOCKDESC_RGBA_SINT | 196 SVGA3DBLOCKDESC_NORM, 197 SVGA3DBLOCKDESC_RGBA_FP = SVGA3DBLOCKDESC_RED | 198 SVGA3DBLOCKDESC_GREEN | 199 SVGA3DBLOCKDESC_BLUE | 200 SVGA3DBLOCKDESC_ALPHA | 201 SVGA3DBLOCKDESC_FP | 202 SVGA3DBLOCKDESC_COLOR, 203 SVGA3DBLOCKDESC_UV = SVGA3DBLOCKDESC_U | 204 SVGA3DBLOCKDESC_V | 205 SVGA3DBLOCKDESC_BUMP, 206 SVGA3DBLOCKDESC_UVL = SVGA3DBLOCKDESC_UV | 207 SVGA3DBLOCKDESC_BUMP_L | 208 SVGA3DBLOCKDESC_MIXED | 209 SVGA3DBLOCKDESC_BUMP, 210 SVGA3DBLOCKDESC_UVW = SVGA3DBLOCKDESC_UV | 211 SVGA3DBLOCKDESC_W | 212 SVGA3DBLOCKDESC_BUMP, 213 SVGA3DBLOCKDESC_UVWA = SVGA3DBLOCKDESC_UVW | 214 SVGA3DBLOCKDESC_ALPHA | 215 SVGA3DBLOCKDESC_MIXED | 216 SVGA3DBLOCKDESC_BUMP, 217 SVGA3DBLOCKDESC_UVWQ = SVGA3DBLOCKDESC_U | 218 SVGA3DBLOCKDESC_V | 219 SVGA3DBLOCKDESC_W | 220 SVGA3DBLOCKDESC_Q | 221 SVGA3DBLOCKDESC_BUMP, 222 SVGA3DBLOCKDESC_L_UNORM = SVGA3DBLOCKDESC_LUMINANCE | 223 SVGA3DBLOCKDESC_UINT | 224 SVGA3DBLOCKDESC_NORM | 225 SVGA3DBLOCKDESC_COLOR, 226 SVGA3DBLOCKDESC_LA_UNORM = SVGA3DBLOCKDESC_LUMINANCE | 227 SVGA3DBLOCKDESC_ALPHA | 228 SVGA3DBLOCKDESC_UINT | 229 SVGA3DBLOCKDESC_NORM | 230 SVGA3DBLOCKDESC_COLOR, 231 SVGA3DBLOCKDESC_R_FP = SVGA3DBLOCKDESC_RED | 232 SVGA3DBLOCKDESC_FP | 233 SVGA3DBLOCKDESC_COLOR, 234 SVGA3DBLOCKDESC_RG_FP = SVGA3DBLOCKDESC_R_FP | 235 SVGA3DBLOCKDESC_GREEN | 236 SVGA3DBLOCKDESC_COLOR, 237 SVGA3DBLOCKDESC_RGB_FP = SVGA3DBLOCKDESC_RG_FP | 238 SVGA3DBLOCKDESC_BLUE | 239 SVGA3DBLOCKDESC_COLOR, 240 SVGA3DBLOCKDESC_YUV = SVGA3DBLOCKDESC_YUV_VIDEO | 241 SVGA3DBLOCKDESC_COLOR, 242 SVGA3DBLOCKDESC_AYUV = SVGA3DBLOCKDESC_ALPHA | 243 SVGA3DBLOCKDESC_YUV_VIDEO | 244 SVGA3DBLOCKDESC_COLOR, 245 SVGA3DBLOCKDESC_RGB_EXP = SVGA3DBLOCKDESC_RED | 246 SVGA3DBLOCKDESC_GREEN | 247 SVGA3DBLOCKDESC_BLUE | 248 SVGA3DBLOCKDESC_EXP | 249 SVGA3DBLOCKDESC_COLOR, 250 251 SVGA3DBLOCKDESC_COMP_TYPELESS = SVGA3DBLOCKDESC_COMPRESSED | 252 SVGA3DBLOCKDESC_TYPELESS, 253 SVGA3DBLOCKDESC_COMP_UNORM = SVGA3DBLOCKDESC_COMPRESSED | 254 SVGA3DBLOCKDESC_UINT | 255 SVGA3DBLOCKDESC_NORM | 256 SVGA3DBLOCKDESC_COLOR, 257 SVGA3DBLOCKDESC_COMP_SNORM = SVGA3DBLOCKDESC_COMPRESSED | 258 SVGA3DBLOCKDESC_SINT | 259 SVGA3DBLOCKDESC_NORM | 260 SVGA3DBLOCKDESC_COLOR, 261 SVGA3DBLOCKDESC_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_COMP_UNORM | 262 SVGA3DBLOCKDESC_SRGB, 263 SVGA3DBLOCKDESC_BC1_COMP_TYPELESS = SVGA3DBLOCKDESC_BC1 | 264 SVGA3DBLOCKDESC_COMP_TYPELESS, 265 SVGA3DBLOCKDESC_BC1_COMP_UNORM = SVGA3DBLOCKDESC_BC1 | 266 SVGA3DBLOCKDESC_COMP_UNORM, 267 SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC1_COMP_UNORM | 268 SVGA3DBLOCKDESC_SRGB, 269 SVGA3DBLOCKDESC_BC2_COMP_TYPELESS = SVGA3DBLOCKDESC_BC2 | 270 SVGA3DBLOCKDESC_COMP_TYPELESS, 271 SVGA3DBLOCKDESC_BC2_COMP_UNORM = SVGA3DBLOCKDESC_BC2 | 272 SVGA3DBLOCKDESC_COMP_UNORM, 273 SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC2_COMP_UNORM | 274 SVGA3DBLOCKDESC_SRGB, 275 SVGA3DBLOCKDESC_BC3_COMP_TYPELESS = SVGA3DBLOCKDESC_BC3 | 276 SVGA3DBLOCKDESC_COMP_TYPELESS, 277 SVGA3DBLOCKDESC_BC3_COMP_UNORM = SVGA3DBLOCKDESC_BC3 | 278 SVGA3DBLOCKDESC_COMP_UNORM, 279 SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC3_COMP_UNORM | 280 SVGA3DBLOCKDESC_SRGB, 281 SVGA3DBLOCKDESC_BC4_COMP_TYPELESS = SVGA3DBLOCKDESC_BC4 | 282 SVGA3DBLOCKDESC_COMP_TYPELESS, 283 SVGA3DBLOCKDESC_BC4_COMP_UNORM = SVGA3DBLOCKDESC_BC4 | 284 SVGA3DBLOCKDESC_COMP_UNORM, 285 SVGA3DBLOCKDESC_BC4_COMP_SNORM = SVGA3DBLOCKDESC_BC4 | 286 SVGA3DBLOCKDESC_COMP_SNORM, 287 SVGA3DBLOCKDESC_BC5_COMP_TYPELESS = SVGA3DBLOCKDESC_BC5 | 288 SVGA3DBLOCKDESC_COMP_TYPELESS, 289 SVGA3DBLOCKDESC_BC5_COMP_UNORM = SVGA3DBLOCKDESC_BC5 | 290 SVGA3DBLOCKDESC_COMP_UNORM, 291 SVGA3DBLOCKDESC_BC5_COMP_SNORM = SVGA3DBLOCKDESC_BC5 | 292 SVGA3DBLOCKDESC_COMP_SNORM, 293 294 SVGA3DBLOCKDESC_NV12 = SVGA3DBLOCKDESC_YUV_VIDEO | 295 SVGA3DBLOCKDESC_PLANAR_YUV | 296 SVGA3DBLOCKDESC_2PLANAR_YUV | 297 SVGA3DBLOCKDESC_COLOR, 298 SVGA3DBLOCKDESC_YV12 = SVGA3DBLOCKDESC_YUV_VIDEO | 299 SVGA3DBLOCKDESC_PLANAR_YUV | 300 SVGA3DBLOCKDESC_3PLANAR_YUV | 301 SVGA3DBLOCKDESC_COLOR, 302 303 SVGA3DBLOCKDESC_DEPTH_UINT = SVGA3DBLOCKDESC_DEPTH | 304 SVGA3DBLOCKDESC_UINT, 305 SVGA3DBLOCKDESC_DEPTH_UNORM = SVGA3DBLOCKDESC_DEPTH_UINT | 306 SVGA3DBLOCKDESC_NORM, 307 SVGA3DBLOCKDESC_DS = SVGA3DBLOCKDESC_DEPTH | 308 SVGA3DBLOCKDESC_STENCIL, 309 SVGA3DBLOCKDESC_DS_UINT = SVGA3DBLOCKDESC_DEPTH | 310 SVGA3DBLOCKDESC_STENCIL | 311 SVGA3DBLOCKDESC_UINT, 312 SVGA3DBLOCKDESC_DS_UNORM = SVGA3DBLOCKDESC_DS_UINT | 313 SVGA3DBLOCKDESC_NORM, 314 SVGA3DBLOCKDESC_DEPTH_FP = SVGA3DBLOCKDESC_DEPTH | 315 SVGA3DBLOCKDESC_FP, 316 317 SVGA3DBLOCKDESC_UV_UINT = SVGA3DBLOCKDESC_UV | 318 SVGA3DBLOCKDESC_UINT, 319 SVGA3DBLOCKDESC_UV_SNORM = SVGA3DBLOCKDESC_UV | 320 SVGA3DBLOCKDESC_SINT | 321 SVGA3DBLOCKDESC_NORM, 322 SVGA3DBLOCKDESC_UVCX_SNORM = SVGA3DBLOCKDESC_UV_SNORM | 323 SVGA3DBLOCKDESC_CX, 324 SVGA3DBLOCKDESC_UVWQ_SNORM = SVGA3DBLOCKDESC_UVWQ | 325 SVGA3DBLOCKDESC_SINT | 326 SVGA3DBLOCKDESC_NORM, 327 }; 328 329 struct svga3d_channel_def { 330 union { 331 u8 blue; 332 u8 w_bump; 333 u8 l_bump; 334 u8 uv_video; 335 u8 u_video; 336 }; 337 union { 338 u8 green; 339 u8 stencil; 340 u8 v_bump; 341 u8 v_video; 342 }; 343 union { 344 u8 red; 345 u8 u_bump; 346 u8 luminance; 347 u8 y_video; 348 u8 depth; 349 u8 data; 350 }; 351 union { 352 u8 alpha; 353 u8 q_bump; 354 u8 exp; 355 }; 356 }; 357 358 /* 359 * struct svga3d_surface_desc - describes the actual pixel data. 360 * 361 * @format: Format 362 * @block_desc: Block description 363 * @block_size: Dimensions in pixels of a block 364 * @bytes_per_block: Size of block in bytes 365 * @pitch_bytes_per_block: Size of a block in bytes for purposes of pitch 366 * @bit_depth: Channel bit depths 367 * @bit_offset: Channel bit masks (in bits offset from the start of the pointer) 368 */ 369 struct svga3d_surface_desc { 370 SVGA3dSurfaceFormat format; 371 enum svga3d_block_desc block_desc; 372 373 surf_size_struct block_size; 374 u32 bytes_per_block; 375 u32 pitch_bytes_per_block; 376 377 struct svga3d_channel_def bit_depth; 378 struct svga3d_channel_def bit_offset; 379 }; 380 381 static const struct svga3d_surface_desc svga3d_surface_descs[] = { 382 {SVGA3D_FORMAT_INVALID, SVGA3DBLOCKDESC_NONE, 383 {1, 1, 1}, 0, 0, 384 {{0}, {0}, {0}, {0}}, 385 {{0}, {0}, {0}, {0}}}, 386 387 {SVGA3D_X8R8G8B8, SVGA3DBLOCKDESC_RGB_UNORM, 388 {1, 1, 1}, 4, 4, 389 {{8}, {8}, {8}, {0}}, 390 {{0}, {8}, {16}, {24}}}, 391 392 {SVGA3D_A8R8G8B8, SVGA3DBLOCKDESC_RGBA_UNORM, 393 {1, 1, 1}, 4, 4, 394 {{8}, {8}, {8}, {8}}, 395 {{0}, {8}, {16}, {24}}}, 396 397 {SVGA3D_R5G6B5, SVGA3DBLOCKDESC_RGB_UNORM, 398 {1, 1, 1}, 2, 2, 399 {{5}, {6}, {5}, {0}}, 400 {{0}, {5}, {11}, {0}}}, 401 402 {SVGA3D_X1R5G5B5, SVGA3DBLOCKDESC_RGB_UNORM, 403 {1, 1, 1}, 2, 2, 404 {{5}, {5}, {5}, {0}}, 405 {{0}, {5}, {10}, {0}}}, 406 407 {SVGA3D_A1R5G5B5, SVGA3DBLOCKDESC_RGBA_UNORM, 408 {1, 1, 1}, 2, 2, 409 {{5}, {5}, {5}, {1}}, 410 {{0}, {5}, {10}, {15}}}, 411 412 {SVGA3D_A4R4G4B4, SVGA3DBLOCKDESC_RGBA_UNORM, 413 {1, 1, 1}, 2, 2, 414 {{4}, {4}, {4}, {4}}, 415 {{0}, {4}, {8}, {12}}}, 416 417 {SVGA3D_Z_D32, SVGA3DBLOCKDESC_DEPTH_UNORM, 418 {1, 1, 1}, 4, 4, 419 {{0}, {0}, {32}, {0}}, 420 {{0}, {0}, {0}, {0}}}, 421 422 {SVGA3D_Z_D16, SVGA3DBLOCKDESC_DEPTH_UNORM, 423 {1, 1, 1}, 2, 2, 424 {{0}, {0}, {16}, {0}}, 425 {{0}, {0}, {0}, {0}}}, 426 427 {SVGA3D_Z_D24S8, SVGA3DBLOCKDESC_DS_UNORM, 428 {1, 1, 1}, 4, 4, 429 {{0}, {8}, {24}, {0}}, 430 {{0}, {0}, {8}, {0}}}, 431 432 {SVGA3D_Z_D15S1, SVGA3DBLOCKDESC_DS_UNORM, 433 {1, 1, 1}, 2, 2, 434 {{0}, {1}, {15}, {0}}, 435 {{0}, {0}, {1}, {0}}}, 436 437 {SVGA3D_LUMINANCE8, SVGA3DBLOCKDESC_L_UNORM, 438 {1, 1, 1}, 1, 1, 439 {{0}, {0}, {8}, {0}}, 440 {{0}, {0}, {0}, {0}}}, 441 442 {SVGA3D_LUMINANCE4_ALPHA4, SVGA3DBLOCKDESC_LA_UNORM, 443 {1, 1, 1}, 1, 1, 444 {{0}, {0}, {4}, {4}}, 445 {{0}, {0}, {0}, {4}}}, 446 447 {SVGA3D_LUMINANCE16, SVGA3DBLOCKDESC_L_UNORM, 448 {1, 1, 1}, 2, 2, 449 {{0}, {0}, {16}, {0}}, 450 {{0}, {0}, {0}, {0}}}, 451 452 {SVGA3D_LUMINANCE8_ALPHA8, SVGA3DBLOCKDESC_LA_UNORM, 453 {1, 1, 1}, 2, 2, 454 {{0}, {0}, {8}, {8}}, 455 {{0}, {0}, {0}, {8}}}, 456 457 {SVGA3D_DXT1, SVGA3DBLOCKDESC_BC1_COMP_UNORM, 458 {4, 4, 1}, 8, 8, 459 {{0}, {0}, {64}, {0}}, 460 {{0}, {0}, {0}, {0}}}, 461 462 {SVGA3D_DXT2, SVGA3DBLOCKDESC_BC2_COMP_UNORM, 463 {4, 4, 1}, 16, 16, 464 {{0}, {0}, {128}, {0}}, 465 {{0}, {0}, {0}, {0}}}, 466 467 {SVGA3D_DXT3, SVGA3DBLOCKDESC_BC2_COMP_UNORM, 468 {4, 4, 1}, 16, 16, 469 {{0}, {0}, {128}, {0}}, 470 {{0}, {0}, {0}, {0}}}, 471 472 {SVGA3D_DXT4, SVGA3DBLOCKDESC_BC3_COMP_UNORM, 473 {4, 4, 1}, 16, 16, 474 {{0}, {0}, {128}, {0}}, 475 {{0}, {0}, {0}, {0}}}, 476 477 {SVGA3D_DXT5, SVGA3DBLOCKDESC_BC3_COMP_UNORM, 478 {4, 4, 1}, 16, 16, 479 {{0}, {0}, {128}, {0}}, 480 {{0}, {0}, {0}, {0}}}, 481 482 {SVGA3D_BUMPU8V8, SVGA3DBLOCKDESC_UV_SNORM, 483 {1, 1, 1}, 2, 2, 484 {{0}, {8}, {8}, {0}}, 485 {{0}, {8}, {0}, {0}}}, 486 487 {SVGA3D_BUMPL6V5U5, SVGA3DBLOCKDESC_UVL, 488 {1, 1, 1}, 2, 2, 489 {{6}, {5}, {5}, {0}}, 490 {{10}, {5}, {0}, {0}}}, 491 492 {SVGA3D_BUMPX8L8V8U8, SVGA3DBLOCKDESC_UVL, 493 {1, 1, 1}, 4, 4, 494 {{8}, {8}, {8}, {0}}, 495 {{16}, {8}, {0}, {0}}}, 496 497 {SVGA3D_FORMAT_DEAD1, SVGA3DBLOCKDESC_UVL, 498 {1, 1, 1}, 3, 3, 499 {{8}, {8}, {8}, {0}}, 500 {{16}, {8}, {0}, {0}}}, 501 502 {SVGA3D_ARGB_S10E5, SVGA3DBLOCKDESC_RGBA_FP, 503 {1, 1, 1}, 8, 8, 504 {{16}, {16}, {16}, {16}}, 505 {{32}, {16}, {0}, {48}}}, 506 507 {SVGA3D_ARGB_S23E8, SVGA3DBLOCKDESC_RGBA_FP, 508 {1, 1, 1}, 16, 16, 509 {{32}, {32}, {32}, {32}}, 510 {{64}, {32}, {0}, {96}}}, 511 512 {SVGA3D_A2R10G10B10, SVGA3DBLOCKDESC_RGBA_UNORM, 513 {1, 1, 1}, 4, 4, 514 {{10}, {10}, {10}, {2}}, 515 {{0}, {10}, {20}, {30}}}, 516 517 {SVGA3D_V8U8, SVGA3DBLOCKDESC_UV_SNORM, 518 {1, 1, 1}, 2, 2, 519 {{0}, {8}, {8}, {0}}, 520 {{0}, {8}, {0}, {0}}}, 521 522 {SVGA3D_Q8W8V8U8, SVGA3DBLOCKDESC_UVWQ_SNORM, 523 {1, 1, 1}, 4, 4, 524 {{8}, {8}, {8}, {8}}, 525 {{16}, {8}, {0}, {24}}}, 526 527 {SVGA3D_CxV8U8, SVGA3DBLOCKDESC_UVCX_SNORM, 528 {1, 1, 1}, 2, 2, 529 {{0}, {8}, {8}, {0}}, 530 {{0}, {8}, {0}, {0}}}, 531 532 {SVGA3D_X8L8V8U8, SVGA3DBLOCKDESC_UVL, 533 {1, 1, 1}, 4, 4, 534 {{8}, {8}, {8}, {0}}, 535 {{16}, {8}, {0}, {0}}}, 536 537 {SVGA3D_A2W10V10U10, SVGA3DBLOCKDESC_UVWA, 538 {1, 1, 1}, 4, 4, 539 {{10}, {10}, {10}, {2}}, 540 {{20}, {10}, {0}, {30}}}, 541 542 {SVGA3D_ALPHA8, SVGA3DBLOCKDESC_A_UNORM, 543 {1, 1, 1}, 1, 1, 544 {{0}, {0}, {0}, {8}}, 545 {{0}, {0}, {0}, {0}}}, 546 547 {SVGA3D_R_S10E5, SVGA3DBLOCKDESC_R_FP, 548 {1, 1, 1}, 2, 2, 549 {{0}, {0}, {16}, {0}}, 550 {{0}, {0}, {0}, {0}}}, 551 552 {SVGA3D_R_S23E8, SVGA3DBLOCKDESC_R_FP, 553 {1, 1, 1}, 4, 4, 554 {{0}, {0}, {32}, {0}}, 555 {{0}, {0}, {0}, {0}}}, 556 557 {SVGA3D_RG_S10E5, SVGA3DBLOCKDESC_RG_FP, 558 {1, 1, 1}, 4, 4, 559 {{0}, {16}, {16}, {0}}, 560 {{0}, {16}, {0}, {0}}}, 561 562 {SVGA3D_RG_S23E8, SVGA3DBLOCKDESC_RG_FP, 563 {1, 1, 1}, 8, 8, 564 {{0}, {32}, {32}, {0}}, 565 {{0}, {32}, {0}, {0}}}, 566 567 {SVGA3D_BUFFER, SVGA3DBLOCKDESC_BUFFER, 568 {1, 1, 1}, 1, 1, 569 {{0}, {0}, {8}, {0}}, 570 {{0}, {0}, {0}, {0}}}, 571 572 {SVGA3D_Z_D24X8, SVGA3DBLOCKDESC_DEPTH_UNORM, 573 {1, 1, 1}, 4, 4, 574 {{0}, {0}, {24}, {0}}, 575 {{0}, {0}, {8}, {0}}}, 576 577 {SVGA3D_V16U16, SVGA3DBLOCKDESC_UV_SNORM, 578 {1, 1, 1}, 4, 4, 579 {{0}, {16}, {16}, {0}}, 580 {{0}, {16}, {0}, {0}}}, 581 582 {SVGA3D_G16R16, SVGA3DBLOCKDESC_RG_UNORM, 583 {1, 1, 1}, 4, 4, 584 {{0}, {16}, {16}, {0}}, 585 {{0}, {16}, {0}, {0}}}, 586 587 {SVGA3D_A16B16G16R16, SVGA3DBLOCKDESC_RGBA_UNORM, 588 {1, 1, 1}, 8, 8, 589 {{16}, {16}, {16}, {16}}, 590 {{32}, {16}, {0}, {48}}}, 591 592 {SVGA3D_UYVY, SVGA3DBLOCKDESC_YUV, 593 {2, 1, 1}, 4, 4, 594 {{8}, {0}, {8}, {0}}, 595 {{0}, {0}, {8}, {0}}}, 596 597 {SVGA3D_YUY2, SVGA3DBLOCKDESC_YUV, 598 {2, 1, 1}, 4, 4, 599 {{8}, {0}, {8}, {0}}, 600 {{8}, {0}, {0}, {0}}}, 601 602 {SVGA3D_NV12, SVGA3DBLOCKDESC_NV12, 603 {2, 2, 1}, 6, 2, 604 {{0}, {0}, {48}, {0}}, 605 {{0}, {0}, {0}, {0}}}, 606 607 {SVGA3D_AYUV, SVGA3DBLOCKDESC_AYUV, 608 {1, 1, 1}, 4, 4, 609 {{8}, {8}, {8}, {8}}, 610 {{0}, {8}, {16}, {24}}}, 611 612 {SVGA3D_R32G32B32A32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 613 {1, 1, 1}, 16, 16, 614 {{32}, {32}, {32}, {32}}, 615 {{64}, {32}, {0}, {96}}}, 616 617 {SVGA3D_R32G32B32A32_UINT, SVGA3DBLOCKDESC_RGBA_UINT, 618 {1, 1, 1}, 16, 16, 619 {{32}, {32}, {32}, {32}}, 620 {{64}, {32}, {0}, {96}}}, 621 622 {SVGA3D_R32G32B32A32_SINT, SVGA3DBLOCKDESC_RGBA_SINT, 623 {1, 1, 1}, 16, 16, 624 {{32}, {32}, {32}, {32}}, 625 {{64}, {32}, {0}, {96}}}, 626 627 {SVGA3D_R32G32B32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 628 {1, 1, 1}, 12, 12, 629 {{32}, {32}, {32}, {0}}, 630 {{64}, {32}, {0}, {0}}}, 631 632 {SVGA3D_R32G32B32_FLOAT, SVGA3DBLOCKDESC_RGB_FP, 633 {1, 1, 1}, 12, 12, 634 {{32}, {32}, {32}, {0}}, 635 {{64}, {32}, {0}, {0}}}, 636 637 {SVGA3D_R32G32B32_UINT, SVGA3DBLOCKDESC_RGB_UINT, 638 {1, 1, 1}, 12, 12, 639 {{32}, {32}, {32}, {0}}, 640 {{64}, {32}, {0}, {0}}}, 641 642 {SVGA3D_R32G32B32_SINT, SVGA3DBLOCKDESC_RGB_SINT, 643 {1, 1, 1}, 12, 12, 644 {{32}, {32}, {32}, {0}}, 645 {{64}, {32}, {0}, {0}}}, 646 647 {SVGA3D_R16G16B16A16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 648 {1, 1, 1}, 8, 8, 649 {{16}, {16}, {16}, {16}}, 650 {{32}, {16}, {0}, {48}}}, 651 652 {SVGA3D_R16G16B16A16_UINT, SVGA3DBLOCKDESC_RGBA_UINT, 653 {1, 1, 1}, 8, 8, 654 {{16}, {16}, {16}, {16}}, 655 {{32}, {16}, {0}, {48}}}, 656 657 {SVGA3D_R16G16B16A16_SNORM, SVGA3DBLOCKDESC_RGBA_SNORM, 658 {1, 1, 1}, 8, 8, 659 {{16}, {16}, {16}, {16}}, 660 {{32}, {16}, {0}, {48}}}, 661 662 {SVGA3D_R16G16B16A16_SINT, SVGA3DBLOCKDESC_RGBA_SINT, 663 {1, 1, 1}, 8, 8, 664 {{16}, {16}, {16}, {16}}, 665 {{32}, {16}, {0}, {48}}}, 666 667 {SVGA3D_R32G32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 668 {1, 1, 1}, 8, 8, 669 {{0}, {32}, {32}, {0}}, 670 {{0}, {32}, {0}, {0}}}, 671 672 {SVGA3D_R32G32_UINT, SVGA3DBLOCKDESC_RG_UINT, 673 {1, 1, 1}, 8, 8, 674 {{0}, {32}, {32}, {0}}, 675 {{0}, {32}, {0}, {0}}}, 676 677 {SVGA3D_R32G32_SINT, SVGA3DBLOCKDESC_RG_SINT, 678 {1, 1, 1}, 8, 8, 679 {{0}, {32}, {32}, {0}}, 680 {{0}, {32}, {0}, {0}}}, 681 682 {SVGA3D_R32G8X24_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 683 {1, 1, 1}, 8, 8, 684 {{0}, {8}, {32}, {0}}, 685 {{0}, {32}, {0}, {0}}}, 686 687 {SVGA3D_D32_FLOAT_S8X24_UINT, SVGA3DBLOCKDESC_DS, 688 {1, 1, 1}, 8, 8, 689 {{0}, {8}, {32}, {0}}, 690 {{0}, {32}, {0}, {0}}}, 691 692 {SVGA3D_R32_FLOAT_X8X24, SVGA3DBLOCKDESC_R_FP, 693 {1, 1, 1}, 8, 8, 694 {{0}, {0}, {32}, {0}}, 695 {{0}, {0}, {0}, {0}}}, 696 697 {SVGA3D_X32_G8X24_UINT, SVGA3DBLOCKDESC_G_UINT, 698 {1, 1, 1}, 8, 8, 699 {{0}, {8}, {0}, {0}}, 700 {{0}, {32}, {0}, {0}}}, 701 702 {SVGA3D_R10G10B10A2_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 703 {1, 1, 1}, 4, 4, 704 {{10}, {10}, {10}, {2}}, 705 {{20}, {10}, {0}, {30}}}, 706 707 {SVGA3D_R10G10B10A2_UINT, SVGA3DBLOCKDESC_RGBA_UINT, 708 {1, 1, 1}, 4, 4, 709 {{10}, {10}, {10}, {2}}, 710 {{20}, {10}, {0}, {30}}}, 711 712 {SVGA3D_R11G11B10_FLOAT, SVGA3DBLOCKDESC_RGB_FP, 713 {1, 1, 1}, 4, 4, 714 {{10}, {11}, {11}, {0}}, 715 {{22}, {11}, {0}, {0}}}, 716 717 {SVGA3D_R8G8B8A8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 718 {1, 1, 1}, 4, 4, 719 {{8}, {8}, {8}, {8}}, 720 {{16}, {8}, {0}, {24}}}, 721 722 {SVGA3D_R8G8B8A8_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, 723 {1, 1, 1}, 4, 4, 724 {{8}, {8}, {8}, {8}}, 725 {{16}, {8}, {0}, {24}}}, 726 727 {SVGA3D_R8G8B8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_UNORM_SRGB, 728 {1, 1, 1}, 4, 4, 729 {{8}, {8}, {8}, {8}}, 730 {{16}, {8}, {0}, {24}}}, 731 732 {SVGA3D_R8G8B8A8_UINT, SVGA3DBLOCKDESC_RGBA_UINT, 733 {1, 1, 1}, 4, 4, 734 {{8}, {8}, {8}, {8}}, 735 {{16}, {8}, {0}, {24}}}, 736 737 {SVGA3D_R8G8B8A8_SINT, SVGA3DBLOCKDESC_RGBA_SINT, 738 {1, 1, 1}, 4, 4, 739 {{8}, {8}, {8}, {8}}, 740 {{16}, {8}, {0}, {24}}}, 741 742 {SVGA3D_R16G16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 743 {1, 1, 1}, 4, 4, 744 {{0}, {16}, {16}, {0}}, 745 {{0}, {16}, {0}, {0}}}, 746 747 {SVGA3D_R16G16_UINT, SVGA3DBLOCKDESC_RG_UINT, 748 {1, 1, 1}, 4, 4, 749 {{0}, {16}, {16}, {0}}, 750 {{0}, {16}, {0}, {0}}}, 751 752 {SVGA3D_R16G16_SINT, SVGA3DBLOCKDESC_RG_SINT, 753 {1, 1, 1}, 4, 4, 754 {{0}, {16}, {16}, {0}}, 755 {{0}, {16}, {0}, {0}}}, 756 757 {SVGA3D_R32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 758 {1, 1, 1}, 4, 4, 759 {{0}, {0}, {32}, {0}}, 760 {{0}, {0}, {0}, {0}}}, 761 762 {SVGA3D_D32_FLOAT, SVGA3DBLOCKDESC_DEPTH_FP, 763 {1, 1, 1}, 4, 4, 764 {{0}, {0}, {32}, {0}}, 765 {{0}, {0}, {0}, {0}}}, 766 767 {SVGA3D_R32_UINT, SVGA3DBLOCKDESC_R_UINT, 768 {1, 1, 1}, 4, 4, 769 {{0}, {0}, {32}, {0}}, 770 {{0}, {0}, {0}, {0}}}, 771 772 {SVGA3D_R32_SINT, SVGA3DBLOCKDESC_R_SINT, 773 {1, 1, 1}, 4, 4, 774 {{0}, {0}, {32}, {0}}, 775 {{0}, {0}, {0}, {0}}}, 776 777 {SVGA3D_R24G8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 778 {1, 1, 1}, 4, 4, 779 {{0}, {8}, {24}, {0}}, 780 {{0}, {24}, {0}, {0}}}, 781 782 {SVGA3D_D24_UNORM_S8_UINT, SVGA3DBLOCKDESC_DS_UNORM, 783 {1, 1, 1}, 4, 4, 784 {{0}, {8}, {24}, {0}}, 785 {{0}, {24}, {0}, {0}}}, 786 787 {SVGA3D_R24_UNORM_X8, SVGA3DBLOCKDESC_R_UNORM, 788 {1, 1, 1}, 4, 4, 789 {{0}, {0}, {24}, {0}}, 790 {{0}, {0}, {0}, {0}}}, 791 792 {SVGA3D_X24_G8_UINT, SVGA3DBLOCKDESC_G_UINT, 793 {1, 1, 1}, 4, 4, 794 {{0}, {8}, {0}, {0}}, 795 {{0}, {24}, {0}, {0}}}, 796 797 {SVGA3D_R8G8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 798 {1, 1, 1}, 2, 2, 799 {{0}, {8}, {8}, {0}}, 800 {{0}, {8}, {0}, {0}}}, 801 802 {SVGA3D_R8G8_UNORM, SVGA3DBLOCKDESC_RG_UNORM, 803 {1, 1, 1}, 2, 2, 804 {{0}, {8}, {8}, {0}}, 805 {{0}, {8}, {0}, {0}}}, 806 807 {SVGA3D_R8G8_UINT, SVGA3DBLOCKDESC_RG_UINT, 808 {1, 1, 1}, 2, 2, 809 {{0}, {8}, {8}, {0}}, 810 {{0}, {8}, {0}, {0}}}, 811 812 {SVGA3D_R8G8_SINT, SVGA3DBLOCKDESC_RG_SINT, 813 {1, 1, 1}, 2, 2, 814 {{0}, {8}, {8}, {0}}, 815 {{0}, {8}, {0}, {0}}}, 816 817 {SVGA3D_R16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 818 {1, 1, 1}, 2, 2, 819 {{0}, {0}, {16}, {0}}, 820 {{0}, {0}, {0}, {0}}}, 821 822 {SVGA3D_R16_UNORM, SVGA3DBLOCKDESC_R_UNORM, 823 {1, 1, 1}, 2, 2, 824 {{0}, {0}, {16}, {0}}, 825 {{0}, {0}, {0}, {0}}}, 826 827 {SVGA3D_R16_UINT, SVGA3DBLOCKDESC_R_UINT, 828 {1, 1, 1}, 2, 2, 829 {{0}, {0}, {16}, {0}}, 830 {{0}, {0}, {0}, {0}}}, 831 832 {SVGA3D_R16_SNORM, SVGA3DBLOCKDESC_R_SNORM, 833 {1, 1, 1}, 2, 2, 834 {{0}, {0}, {16}, {0}}, 835 {{0}, {0}, {0}, {0}}}, 836 837 {SVGA3D_R16_SINT, SVGA3DBLOCKDESC_R_SINT, 838 {1, 1, 1}, 2, 2, 839 {{0}, {0}, {16}, {0}}, 840 {{0}, {0}, {0}, {0}}}, 841 842 {SVGA3D_R8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 843 {1, 1, 1}, 1, 1, 844 {{0}, {0}, {8}, {0}}, 845 {{0}, {0}, {0}, {0}}}, 846 847 {SVGA3D_R8_UNORM, SVGA3DBLOCKDESC_R_UNORM, 848 {1, 1, 1}, 1, 1, 849 {{0}, {0}, {8}, {0}}, 850 {{0}, {0}, {0}, {0}}}, 851 852 {SVGA3D_R8_UINT, SVGA3DBLOCKDESC_R_UINT, 853 {1, 1, 1}, 1, 1, 854 {{0}, {0}, {8}, {0}}, 855 {{0}, {0}, {0}, {0}}}, 856 857 {SVGA3D_R8_SNORM, SVGA3DBLOCKDESC_R_SNORM, 858 {1, 1, 1}, 1, 1, 859 {{0}, {0}, {8}, {0}}, 860 {{0}, {0}, {0}, {0}}}, 861 862 {SVGA3D_R8_SINT, SVGA3DBLOCKDESC_R_SINT, 863 {1, 1, 1}, 1, 1, 864 {{0}, {0}, {8}, {0}}, 865 {{0}, {0}, {0}, {0}}}, 866 867 {SVGA3D_P8, SVGA3DBLOCKDESC_NONE, 868 {1, 1, 1}, 1, 1, 869 {{0}, {0}, {8}, {0}}, 870 {{0}, {0}, {0}, {0}}}, 871 872 {SVGA3D_R9G9B9E5_SHAREDEXP, SVGA3DBLOCKDESC_RGB_EXP, 873 {1, 1, 1}, 4, 4, 874 {{9}, {9}, {9}, {5}}, 875 {{18}, {9}, {0}, {27}}}, 876 877 {SVGA3D_R8G8_B8G8_UNORM, SVGA3DBLOCKDESC_NONE, 878 {2, 1, 1}, 4, 4, 879 {{0}, {8}, {8}, {0}}, 880 {{0}, {0}, {8}, {0}}}, 881 882 {SVGA3D_G8R8_G8B8_UNORM, SVGA3DBLOCKDESC_NONE, 883 {2, 1, 1}, 4, 4, 884 {{0}, {8}, {8}, {0}}, 885 {{0}, {8}, {0}, {0}}}, 886 887 {SVGA3D_BC1_TYPELESS, SVGA3DBLOCKDESC_BC1_COMP_TYPELESS, 888 {4, 4, 1}, 8, 8, 889 {{0}, {0}, {64}, {0}}, 890 {{0}, {0}, {0}, {0}}}, 891 892 {SVGA3D_BC1_UNORM_SRGB, SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB, 893 {4, 4, 1}, 8, 8, 894 {{0}, {0}, {64}, {0}}, 895 {{0}, {0}, {0}, {0}}}, 896 897 {SVGA3D_BC2_TYPELESS, SVGA3DBLOCKDESC_BC2_COMP_TYPELESS, 898 {4, 4, 1}, 16, 16, 899 {{0}, {0}, {128}, {0}}, 900 {{0}, {0}, {0}, {0}}}, 901 902 {SVGA3D_BC2_UNORM_SRGB, SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB, 903 {4, 4, 1}, 16, 16, 904 {{0}, {0}, {128}, {0}}, 905 {{0}, {0}, {0}, {0}}}, 906 907 {SVGA3D_BC3_TYPELESS, SVGA3DBLOCKDESC_BC3_COMP_TYPELESS, 908 {4, 4, 1}, 16, 16, 909 {{0}, {0}, {128}, {0}}, 910 {{0}, {0}, {0}, {0}}}, 911 912 {SVGA3D_BC3_UNORM_SRGB, SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB, 913 {4, 4, 1}, 16, 16, 914 {{0}, {0}, {128}, {0}}, 915 {{0}, {0}, {0}, {0}}}, 916 917 {SVGA3D_BC4_TYPELESS, SVGA3DBLOCKDESC_BC4_COMP_TYPELESS, 918 {4, 4, 1}, 8, 8, 919 {{0}, {0}, {64}, {0}}, 920 {{0}, {0}, {0}, {0}}}, 921 922 {SVGA3D_ATI1, SVGA3DBLOCKDESC_BC4_COMP_UNORM, 923 {4, 4, 1}, 8, 8, 924 {{0}, {0}, {64}, {0}}, 925 {{0}, {0}, {0}, {0}}}, 926 927 {SVGA3D_BC4_SNORM, SVGA3DBLOCKDESC_BC4_COMP_SNORM, 928 {4, 4, 1}, 8, 8, 929 {{0}, {0}, {64}, {0}}, 930 {{0}, {0}, {0}, {0}}}, 931 932 {SVGA3D_BC5_TYPELESS, SVGA3DBLOCKDESC_BC5_COMP_TYPELESS, 933 {4, 4, 1}, 16, 16, 934 {{0}, {0}, {128}, {0}}, 935 {{0}, {0}, {0}, {0}}}, 936 937 {SVGA3D_ATI2, SVGA3DBLOCKDESC_BC5_COMP_UNORM, 938 {4, 4, 1}, 16, 16, 939 {{0}, {0}, {128}, {0}}, 940 {{0}, {0}, {0}, {0}}}, 941 942 {SVGA3D_BC5_SNORM, SVGA3DBLOCKDESC_BC5_COMP_SNORM, 943 {4, 4, 1}, 16, 16, 944 {{0}, {0}, {128}, {0}}, 945 {{0}, {0}, {0}, {0}}}, 946 947 {SVGA3D_R10G10B10_XR_BIAS_A2_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, 948 {1, 1, 1}, 4, 4, 949 {{10}, {10}, {10}, {2}}, 950 {{20}, {10}, {0}, {30}}}, 951 952 {SVGA3D_B8G8R8A8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 953 {1, 1, 1}, 4, 4, 954 {{8}, {8}, {8}, {8}}, 955 {{0}, {8}, {16}, {24}}}, 956 957 {SVGA3D_B8G8R8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_UNORM_SRGB, 958 {1, 1, 1}, 4, 4, 959 {{8}, {8}, {8}, {8}}, 960 {{0}, {8}, {16}, {24}}}, 961 962 {SVGA3D_B8G8R8X8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS, 963 {1, 1, 1}, 4, 4, 964 {{8}, {8}, {8}, {0}}, 965 {{0}, {8}, {16}, {24}}}, 966 967 {SVGA3D_B8G8R8X8_UNORM_SRGB, SVGA3DBLOCKDESC_RGB_UNORM_SRGB, 968 {1, 1, 1}, 4, 4, 969 {{8}, {8}, {8}, {0}}, 970 {{0}, {8}, {16}, {24}}}, 971 972 {SVGA3D_Z_DF16, SVGA3DBLOCKDESC_DEPTH_UNORM, 973 {1, 1, 1}, 2, 2, 974 {{0}, {0}, {16}, {0}}, 975 {{0}, {0}, {0}, {0}}}, 976 977 {SVGA3D_Z_DF24, SVGA3DBLOCKDESC_DEPTH_UNORM, 978 {1, 1, 1}, 4, 4, 979 {{0}, {0}, {24}, {0}}, 980 {{0}, {0}, {8}, {0}}}, 981 982 {SVGA3D_Z_D24S8_INT, SVGA3DBLOCKDESC_DS_UNORM, 983 {1, 1, 1}, 4, 4, 984 {{0}, {8}, {24}, {0}}, 985 {{0}, {0}, {8}, {0}}}, 986 987 {SVGA3D_YV12, SVGA3DBLOCKDESC_YV12, 988 {2, 2, 1}, 6, 2, 989 {{0}, {0}, {48}, {0}}, 990 {{0}, {0}, {0}, {0}}}, 991 992 {SVGA3D_R32G32B32A32_FLOAT, SVGA3DBLOCKDESC_RGBA_FP, 993 {1, 1, 1}, 16, 16, 994 {{32}, {32}, {32}, {32}}, 995 {{64}, {32}, {0}, {96}}}, 996 997 {SVGA3D_R16G16B16A16_FLOAT, SVGA3DBLOCKDESC_RGBA_FP, 998 {1, 1, 1}, 8, 8, 999 {{16}, {16}, {16}, {16}}, 1000 {{32}, {16}, {0}, {48}}}, 1001 1002 {SVGA3D_R16G16B16A16_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, 1003 {1, 1, 1}, 8, 8, 1004 {{16}, {16}, {16}, {16}}, 1005 {{32}, {16}, {0}, {48}}}, 1006 1007 {SVGA3D_R32G32_FLOAT, SVGA3DBLOCKDESC_RG_FP, 1008 {1, 1, 1}, 8, 8, 1009 {{0}, {32}, {32}, {0}}, 1010 {{0}, {32}, {0}, {0}}}, 1011 1012 {SVGA3D_R10G10B10A2_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, 1013 {1, 1, 1}, 4, 4, 1014 {{10}, {10}, {10}, {2}}, 1015 {{20}, {10}, {0}, {30}}}, 1016 1017 {SVGA3D_R8G8B8A8_SNORM, SVGA3DBLOCKDESC_RGBA_SNORM, 1018 {1, 1, 1}, 4, 4, 1019 {{8}, {8}, {8}, {8}}, 1020 {{16}, {8}, {0}, {24}}}, 1021 1022 {SVGA3D_R16G16_FLOAT, SVGA3DBLOCKDESC_RG_FP, 1023 {1, 1, 1}, 4, 4, 1024 {{0}, {16}, {16}, {0}}, 1025 {{0}, {16}, {0}, {0}}}, 1026 1027 {SVGA3D_R16G16_UNORM, SVGA3DBLOCKDESC_RG_UNORM, 1028 {1, 1, 1}, 4, 4, 1029 {{0}, {16}, {16}, {0}}, 1030 {{0}, {16}, {0}, {0}}}, 1031 1032 {SVGA3D_R16G16_SNORM, SVGA3DBLOCKDESC_RG_SNORM, 1033 {1, 1, 1}, 4, 4, 1034 {{0}, {16}, {16}, {0}}, 1035 {{0}, {16}, {0}, {0}}}, 1036 1037 {SVGA3D_R32_FLOAT, SVGA3DBLOCKDESC_R_FP, 1038 {1, 1, 1}, 4, 4, 1039 {{0}, {0}, {32}, {0}}, 1040 {{0}, {0}, {0}, {0}}}, 1041 1042 {SVGA3D_R8G8_SNORM, SVGA3DBLOCKDESC_RG_SNORM, 1043 {1, 1, 1}, 2, 2, 1044 {{0}, {8}, {8}, {0}}, 1045 {{0}, {8}, {0}, {0}}}, 1046 1047 {SVGA3D_R16_FLOAT, SVGA3DBLOCKDESC_R_FP, 1048 {1, 1, 1}, 2, 2, 1049 {{0}, {0}, {16}, {0}}, 1050 {{0}, {0}, {0}, {0}}}, 1051 1052 {SVGA3D_D16_UNORM, SVGA3DBLOCKDESC_DEPTH_UNORM, 1053 {1, 1, 1}, 2, 2, 1054 {{0}, {0}, {16}, {0}}, 1055 {{0}, {0}, {0}, {0}}}, 1056 1057 {SVGA3D_A8_UNORM, SVGA3DBLOCKDESC_A_UNORM, 1058 {1, 1, 1}, 1, 1, 1059 {{0}, {0}, {0}, {8}}, 1060 {{0}, {0}, {0}, {0}}}, 1061 1062 {SVGA3D_BC1_UNORM, SVGA3DBLOCKDESC_BC1_COMP_UNORM, 1063 {4, 4, 1}, 8, 8, 1064 {{0}, {0}, {64}, {0}}, 1065 {{0}, {0}, {0}, {0}}}, 1066 1067 {SVGA3D_BC2_UNORM, SVGA3DBLOCKDESC_BC2_COMP_UNORM, 1068 {4, 4, 1}, 16, 16, 1069 {{0}, {0}, {128}, {0}}, 1070 {{0}, {0}, {0}, {0}}}, 1071 1072 {SVGA3D_BC3_UNORM, SVGA3DBLOCKDESC_BC3_COMP_UNORM, 1073 {4, 4, 1}, 16, 16, 1074 {{0}, {0}, {128}, {0}}, 1075 {{0}, {0}, {0}, {0}}}, 1076 1077 {SVGA3D_B5G6R5_UNORM, SVGA3DBLOCKDESC_RGB_UNORM, 1078 {1, 1, 1}, 2, 2, 1079 {{5}, {6}, {5}, {0}}, 1080 {{0}, {5}, {11}, {0}}}, 1081 1082 {SVGA3D_B5G5R5A1_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, 1083 {1, 1, 1}, 2, 2, 1084 {{5}, {5}, {5}, {1}}, 1085 {{0}, {5}, {10}, {15}}}, 1086 1087 {SVGA3D_B8G8R8A8_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM, 1088 {1, 1, 1}, 4, 4, 1089 {{8}, {8}, {8}, {8}}, 1090 {{0}, {8}, {16}, {24}}}, 1091 1092 {SVGA3D_B8G8R8X8_UNORM, SVGA3DBLOCKDESC_RGB_UNORM, 1093 {1, 1, 1}, 4, 4, 1094 {{8}, {8}, {8}, {0}}, 1095 {{0}, {8}, {16}, {24}}}, 1096 1097 {SVGA3D_BC4_UNORM, SVGA3DBLOCKDESC_BC4_COMP_UNORM, 1098 {4, 4, 1}, 8, 8, 1099 {{0}, {0}, {64}, {0}}, 1100 {{0}, {0}, {0}, {0}}}, 1101 1102 {SVGA3D_BC5_UNORM, SVGA3DBLOCKDESC_BC5_COMP_UNORM, 1103 {4, 4, 1}, 16, 16, 1104 {{0}, {0}, {128}, {0}}, 1105 {{0}, {0}, {0}, {0}}}, 1106 }; 1107 1108 static inline u32 clamped_umul32(u32 a, u32 b) 1109 { 1110 uint64_t tmp = (uint64_t) a*b; 1111 return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp; 1112 } 1113 1114 /** 1115 * svga3dsurface_get_desc - Look up the appropriate SVGA3dSurfaceDesc for the 1116 * given format. 1117 */ 1118 static inline const struct svga3d_surface_desc * 1119 svga3dsurface_get_desc(SVGA3dSurfaceFormat format) 1120 { 1121 if (format < ARRAY_SIZE(svga3d_surface_descs)) 1122 return &svga3d_surface_descs[format]; 1123 1124 return &svga3d_surface_descs[SVGA3D_FORMAT_INVALID]; 1125 } 1126 1127 /** 1128 * svga3dsurface_get_mip_size - Given a base level size and the mip level, 1129 * compute the size of the mip level. 1130 */ 1131 static inline surf_size_struct 1132 svga3dsurface_get_mip_size(surf_size_struct base_level, u32 mip_level) 1133 { 1134 surf_size_struct size; 1135 1136 size.width = max_t(u32, base_level.width >> mip_level, 1); 1137 size.height = max_t(u32, base_level.height >> mip_level, 1); 1138 size.depth = max_t(u32, base_level.depth >> mip_level, 1); 1139 size.pad64 = 0; 1140 1141 return size; 1142 } 1143 1144 static inline void 1145 svga3dsurface_get_size_in_blocks(const struct svga3d_surface_desc *desc, 1146 const surf_size_struct *pixel_size, 1147 surf_size_struct *block_size) 1148 { 1149 block_size->width = __KERNEL_DIV_ROUND_UP(pixel_size->width, 1150 desc->block_size.width); 1151 block_size->height = __KERNEL_DIV_ROUND_UP(pixel_size->height, 1152 desc->block_size.height); 1153 block_size->depth = __KERNEL_DIV_ROUND_UP(pixel_size->depth, 1154 desc->block_size.depth); 1155 } 1156 1157 static inline bool 1158 svga3dsurface_is_planar_surface(const struct svga3d_surface_desc *desc) 1159 { 1160 return (desc->block_desc & SVGA3DBLOCKDESC_PLANAR_YUV) != 0; 1161 } 1162 1163 static inline u32 1164 svga3dsurface_calculate_pitch(const struct svga3d_surface_desc *desc, 1165 const surf_size_struct *size) 1166 { 1167 u32 pitch; 1168 surf_size_struct blocks; 1169 1170 svga3dsurface_get_size_in_blocks(desc, size, &blocks); 1171 1172 pitch = blocks.width * desc->pitch_bytes_per_block; 1173 1174 return pitch; 1175 } 1176 1177 /** 1178 * svga3dsurface_get_image_buffer_size - Calculates image buffer size. 1179 * 1180 * Return the number of bytes of buffer space required to store one image of a 1181 * surface, optionally using the specified pitch. 1182 * 1183 * If pitch is zero, it is assumed that rows are tightly packed. 1184 * 1185 * This function is overflow-safe. If the result would have overflowed, instead 1186 * we return MAX_UINT32. 1187 */ 1188 static inline u32 1189 svga3dsurface_get_image_buffer_size(const struct svga3d_surface_desc *desc, 1190 const surf_size_struct *size, 1191 u32 pitch) 1192 { 1193 surf_size_struct image_blocks; 1194 u32 slice_size, total_size; 1195 1196 svga3dsurface_get_size_in_blocks(desc, size, &image_blocks); 1197 1198 if (svga3dsurface_is_planar_surface(desc)) { 1199 total_size = clamped_umul32(image_blocks.width, 1200 image_blocks.height); 1201 total_size = clamped_umul32(total_size, image_blocks.depth); 1202 total_size = clamped_umul32(total_size, desc->bytes_per_block); 1203 return total_size; 1204 } 1205 1206 if (pitch == 0) 1207 pitch = svga3dsurface_calculate_pitch(desc, size); 1208 1209 slice_size = clamped_umul32(image_blocks.height, pitch); 1210 total_size = clamped_umul32(slice_size, image_blocks.depth); 1211 1212 return total_size; 1213 } 1214 1215 /** 1216 * svga3dsurface_get_serialized_size - Get the serialized size for the image. 1217 */ 1218 static inline u32 1219 svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format, 1220 surf_size_struct base_level_size, 1221 u32 num_mip_levels, 1222 u32 num_layers) 1223 { 1224 const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format); 1225 u32 total_size = 0; 1226 u32 mip; 1227 1228 for (mip = 0; mip < num_mip_levels; mip++) { 1229 surf_size_struct size = 1230 svga3dsurface_get_mip_size(base_level_size, mip); 1231 total_size += svga3dsurface_get_image_buffer_size(desc, 1232 &size, 0); 1233 } 1234 1235 return total_size * num_layers; 1236 } 1237 1238 /** 1239 * svga3dsurface_get_serialized_size_extended - Returns the number of bytes 1240 * required for a surface with given parameters. Support for sample count. 1241 */ 1242 static inline u32 1243 svga3dsurface_get_serialized_size_extended(SVGA3dSurfaceFormat format, 1244 surf_size_struct base_level_size, 1245 u32 num_mip_levels, 1246 u32 num_layers, 1247 u32 num_samples) 1248 { 1249 uint64_t total_size = 1250 svga3dsurface_get_serialized_size(format, 1251 base_level_size, 1252 num_mip_levels, 1253 num_layers); 1254 total_size *= max_t(u32, 1, num_samples); 1255 1256 return min_t(uint64_t, total_size, (uint64_t)U32_MAX); 1257 } 1258 1259 /** 1260 * svga3dsurface_get_pixel_offset - Compute the offset (in bytes) to a pixel 1261 * in an image (or volume). 1262 * 1263 * @width: The image width in pixels. 1264 * @height: The image height in pixels 1265 */ 1266 static inline u32 1267 svga3dsurface_get_pixel_offset(SVGA3dSurfaceFormat format, 1268 u32 width, u32 height, 1269 u32 x, u32 y, u32 z) 1270 { 1271 const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format); 1272 const u32 bw = desc->block_size.width, bh = desc->block_size.height; 1273 const u32 bd = desc->block_size.depth; 1274 const u32 rowstride = __KERNEL_DIV_ROUND_UP(width, bw) * 1275 desc->bytes_per_block; 1276 const u32 imgstride = __KERNEL_DIV_ROUND_UP(height, bh) * rowstride; 1277 const u32 offset = (z / bd * imgstride + 1278 y / bh * rowstride + 1279 x / bw * desc->bytes_per_block); 1280 return offset; 1281 } 1282 1283 static inline u32 1284 svga3dsurface_get_image_offset(SVGA3dSurfaceFormat format, 1285 surf_size_struct baseLevelSize, 1286 u32 numMipLevels, 1287 u32 face, 1288 u32 mip) 1289 1290 { 1291 u32 offset; 1292 u32 mipChainBytes; 1293 u32 mipChainBytesToLevel; 1294 u32 i; 1295 const struct svga3d_surface_desc *desc; 1296 surf_size_struct mipSize; 1297 u32 bytes; 1298 1299 desc = svga3dsurface_get_desc(format); 1300 1301 mipChainBytes = 0; 1302 mipChainBytesToLevel = 0; 1303 for (i = 0; i < numMipLevels; i++) { 1304 mipSize = svga3dsurface_get_mip_size(baseLevelSize, i); 1305 bytes = svga3dsurface_get_image_buffer_size(desc, &mipSize, 0); 1306 mipChainBytes += bytes; 1307 if (i < mip) 1308 mipChainBytesToLevel += bytes; 1309 } 1310 1311 offset = mipChainBytes * face + mipChainBytesToLevel; 1312 1313 return offset; 1314 } 1315 1316 1317 /** 1318 * svga3dsurface_is_gb_screen_target_format - Is the specified format usable as 1319 * a ScreenTarget? 1320 * (with just the GBObjects cap-bit 1321 * set) 1322 * @format: format to queried 1323 * 1324 * RETURNS: 1325 * true if queried format is valid for screen targets 1326 */ 1327 static inline bool 1328 svga3dsurface_is_gb_screen_target_format(SVGA3dSurfaceFormat format) 1329 { 1330 return (format == SVGA3D_X8R8G8B8 || 1331 format == SVGA3D_A8R8G8B8 || 1332 format == SVGA3D_R5G6B5 || 1333 format == SVGA3D_X1R5G5B5 || 1334 format == SVGA3D_A1R5G5B5 || 1335 format == SVGA3D_P8); 1336 } 1337 1338 1339 /** 1340 * svga3dsurface_is_dx_screen_target_format - Is the specified format usable as 1341 * a ScreenTarget? 1342 * (with DX10 enabled) 1343 * 1344 * @format: format to queried 1345 * 1346 * Results: 1347 * true if queried format is valid for screen targets 1348 */ 1349 static inline bool 1350 svga3dsurface_is_dx_screen_target_format(SVGA3dSurfaceFormat format) 1351 { 1352 return (format == SVGA3D_R8G8B8A8_UNORM || 1353 format == SVGA3D_B8G8R8A8_UNORM || 1354 format == SVGA3D_B8G8R8X8_UNORM); 1355 } 1356 1357 1358 /** 1359 * svga3dsurface_is_screen_target_format - Is the specified format usable as a 1360 * ScreenTarget? 1361 * (for some combination of caps) 1362 * 1363 * @format: format to queried 1364 * 1365 * Results: 1366 * true if queried format is valid for screen targets 1367 */ 1368 static inline bool 1369 svga3dsurface_is_screen_target_format(SVGA3dSurfaceFormat format) 1370 { 1371 if (svga3dsurface_is_gb_screen_target_format(format)) { 1372 return true; 1373 } 1374 return svga3dsurface_is_dx_screen_target_format(format); 1375 } 1376 1377 /** 1378 * struct svga3dsurface_mip - Mimpmap level information 1379 * @bytes: Bytes required in the backing store of this mipmap level. 1380 * @img_stride: Byte stride per image. 1381 * @row_stride: Byte stride per block row. 1382 * @size: The size of the mipmap. 1383 */ 1384 struct svga3dsurface_mip { 1385 size_t bytes; 1386 size_t img_stride; 1387 size_t row_stride; 1388 struct drm_vmw_size size; 1389 1390 }; 1391 1392 /** 1393 * struct svga3dsurface_cache - Cached surface information 1394 * @desc: Pointer to the surface descriptor 1395 * @mip: Array of mipmap level information. Valid size is @num_mip_levels. 1396 * @mip_chain_bytes: Bytes required in the backing store for the whole chain 1397 * of mip levels. 1398 * @sheet_bytes: Bytes required in the backing store for a sheet 1399 * representing a single sample. 1400 * @num_mip_levels: Valid size of the @mip array. Number of mipmap levels in 1401 * a chain. 1402 * @num_layers: Number of slices in an array texture or number of faces in 1403 * a cubemap texture. 1404 */ 1405 struct svga3dsurface_cache { 1406 const struct svga3d_surface_desc *desc; 1407 struct svga3dsurface_mip mip[DRM_VMW_MAX_MIP_LEVELS]; 1408 size_t mip_chain_bytes; 1409 size_t sheet_bytes; 1410 u32 num_mip_levels; 1411 u32 num_layers; 1412 }; 1413 1414 /** 1415 * struct svga3dsurface_loc - Surface location 1416 * @sub_resource: Surface subresource. Defined as layer * num_mip_levels + 1417 * mip_level. 1418 * @x: X coordinate. 1419 * @y: Y coordinate. 1420 * @z: Z coordinate. 1421 */ 1422 struct svga3dsurface_loc { 1423 u32 sub_resource; 1424 u32 x, y, z; 1425 }; 1426 1427 /** 1428 * svga3dsurface_subres - Compute the subresource from layer and mipmap. 1429 * @cache: Surface layout data. 1430 * @mip_level: The mipmap level. 1431 * @layer: The surface layer (face or array slice). 1432 * 1433 * Return: The subresource. 1434 */ 1435 static inline u32 svga3dsurface_subres(const struct svga3dsurface_cache *cache, 1436 u32 mip_level, u32 layer) 1437 { 1438 return cache->num_mip_levels * layer + mip_level; 1439 } 1440 1441 /** 1442 * svga3dsurface_setup_cache - Build a surface cache entry 1443 * @size: The surface base level dimensions. 1444 * @format: The surface format. 1445 * @num_mip_levels: Number of mipmap levels. 1446 * @num_layers: Number of layers. 1447 * @cache: Pointer to a struct svga3dsurface_cach object to be filled in. 1448 * 1449 * Return: Zero on success, -EINVAL on invalid surface layout. 1450 */ 1451 static inline int svga3dsurface_setup_cache(const struct drm_vmw_size *size, 1452 SVGA3dSurfaceFormat format, 1453 u32 num_mip_levels, 1454 u32 num_layers, 1455 u32 num_samples, 1456 struct svga3dsurface_cache *cache) 1457 { 1458 const struct svga3d_surface_desc *desc; 1459 u32 i; 1460 1461 memset(cache, 0, sizeof(*cache)); 1462 cache->desc = desc = svga3dsurface_get_desc(format); 1463 cache->num_mip_levels = num_mip_levels; 1464 cache->num_layers = num_layers; 1465 for (i = 0; i < cache->num_mip_levels; i++) { 1466 struct svga3dsurface_mip *mip = &cache->mip[i]; 1467 1468 mip->size = svga3dsurface_get_mip_size(*size, i); 1469 mip->bytes = svga3dsurface_get_image_buffer_size 1470 (desc, &mip->size, 0); 1471 mip->row_stride = 1472 __KERNEL_DIV_ROUND_UP(mip->size.width, 1473 desc->block_size.width) * 1474 desc->bytes_per_block * num_samples; 1475 if (!mip->row_stride) 1476 goto invalid_dim; 1477 1478 mip->img_stride = 1479 __KERNEL_DIV_ROUND_UP(mip->size.height, 1480 desc->block_size.height) * 1481 mip->row_stride; 1482 if (!mip->img_stride) 1483 goto invalid_dim; 1484 1485 cache->mip_chain_bytes += mip->bytes; 1486 } 1487 cache->sheet_bytes = cache->mip_chain_bytes * num_layers; 1488 if (!cache->sheet_bytes) 1489 goto invalid_dim; 1490 1491 return 0; 1492 1493 invalid_dim: 1494 VMW_DEBUG_USER("Invalid surface layout for dirty tracking.\n"); 1495 return -EINVAL; 1496 } 1497 1498 /** 1499 * svga3dsurface_get_loc - Get a surface location from an offset into the 1500 * backing store 1501 * @cache: Surface layout data. 1502 * @loc: Pointer to a struct svga3dsurface_loc to be filled in. 1503 * @offset: Offset into the surface backing store. 1504 */ 1505 static inline void 1506 svga3dsurface_get_loc(const struct svga3dsurface_cache *cache, 1507 struct svga3dsurface_loc *loc, 1508 size_t offset) 1509 { 1510 const struct svga3dsurface_mip *mip = &cache->mip[0]; 1511 const struct svga3d_surface_desc *desc = cache->desc; 1512 u32 layer; 1513 int i; 1514 1515 if (offset >= cache->sheet_bytes) 1516 offset %= cache->sheet_bytes; 1517 1518 layer = offset / cache->mip_chain_bytes; 1519 offset -= layer * cache->mip_chain_bytes; 1520 for (i = 0; i < cache->num_mip_levels; ++i, ++mip) { 1521 if (mip->bytes > offset) 1522 break; 1523 offset -= mip->bytes; 1524 } 1525 1526 loc->sub_resource = svga3dsurface_subres(cache, i, layer); 1527 loc->z = offset / mip->img_stride; 1528 offset -= loc->z * mip->img_stride; 1529 loc->z *= desc->block_size.depth; 1530 loc->y = offset / mip->row_stride; 1531 offset -= loc->y * mip->row_stride; 1532 loc->y *= desc->block_size.height; 1533 loc->x = offset / desc->bytes_per_block; 1534 loc->x *= desc->block_size.width; 1535 } 1536 1537 /** 1538 * svga3dsurface_inc_loc - Clamp increment a surface location with one block 1539 * size 1540 * in each dimension. 1541 * @loc: Pointer to a struct svga3dsurface_loc to be incremented. 1542 * 1543 * When computing the size of a range as size = end - start, the range does not 1544 * include the end element. However a location representing the last byte 1545 * of a touched region in the backing store *is* included in the range. 1546 * This function modifies such a location to match the end definition 1547 * given as start + size which is the one used in a SVGA3dBox. 1548 */ 1549 static inline void 1550 svga3dsurface_inc_loc(const struct svga3dsurface_cache *cache, 1551 struct svga3dsurface_loc *loc) 1552 { 1553 const struct svga3d_surface_desc *desc = cache->desc; 1554 u32 mip = loc->sub_resource % cache->num_mip_levels; 1555 const struct drm_vmw_size *size = &cache->mip[mip].size; 1556 1557 loc->sub_resource++; 1558 loc->x += desc->block_size.width; 1559 if (loc->x > size->width) 1560 loc->x = size->width; 1561 loc->y += desc->block_size.height; 1562 if (loc->y > size->height) 1563 loc->y = size->height; 1564 loc->z += desc->block_size.depth; 1565 if (loc->z > size->depth) 1566 loc->z = size->depth; 1567 } 1568 1569 /** 1570 * svga3dsurface_min_loc - The start location in a subresource 1571 * @cache: Surface layout data. 1572 * @sub_resource: The subresource. 1573 * @loc: Pointer to a struct svga3dsurface_loc to be filled in. 1574 */ 1575 static inline void 1576 svga3dsurface_min_loc(const struct svga3dsurface_cache *cache, 1577 u32 sub_resource, 1578 struct svga3dsurface_loc *loc) 1579 { 1580 loc->sub_resource = sub_resource; 1581 loc->x = loc->y = loc->z = 0; 1582 } 1583 1584 /** 1585 * svga3dsurface_min_loc - The end location in a subresource 1586 * @cache: Surface layout data. 1587 * @sub_resource: The subresource. 1588 * @loc: Pointer to a struct svga3dsurface_loc to be filled in. 1589 * 1590 * Following the end definition given in svga3dsurface_inc_loc(), 1591 * Compute the end location of a surface subresource. 1592 */ 1593 static inline void 1594 svga3dsurface_max_loc(const struct svga3dsurface_cache *cache, 1595 u32 sub_resource, 1596 struct svga3dsurface_loc *loc) 1597 { 1598 const struct drm_vmw_size *size; 1599 u32 mip; 1600 1601 loc->sub_resource = sub_resource + 1; 1602 mip = sub_resource % cache->num_mip_levels; 1603 size = &cache->mip[mip].size; 1604 loc->x = size->width; 1605 loc->y = size->height; 1606 loc->z = size->depth; 1607 } 1608 1609 #endif /* _SVGA3D_SURFACEDEFS_H_ */ 1610