1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVM Express device driver 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #include <linux/aer.h> 8 #include <linux/async.h> 9 #include <linux/blkdev.h> 10 #include <linux/blk-mq.h> 11 #include <linux/blk-mq-pci.h> 12 #include <linux/dmi.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/mm.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/once.h> 20 #include <linux/pci.h> 21 #include <linux/suspend.h> 22 #include <linux/t10-pi.h> 23 #include <linux/types.h> 24 #include <linux/io-64-nonatomic-lo-hi.h> 25 #include <linux/sed-opal.h> 26 #include <linux/pci-p2pdma.h> 27 28 #include "trace.h" 29 #include "nvme.h" 30 31 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 32 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 33 34 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 35 36 /* 37 * These can be higher, but we need to ensure that any command doesn't 38 * require an sg allocation that needs more than a page of data. 39 */ 40 #define NVME_MAX_KB_SZ 4096 41 #define NVME_MAX_SEGS 127 42 43 static int use_threaded_interrupts; 44 module_param(use_threaded_interrupts, int, 0); 45 46 static bool use_cmb_sqes = true; 47 module_param(use_cmb_sqes, bool, 0444); 48 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 49 50 static unsigned int max_host_mem_size_mb = 128; 51 module_param(max_host_mem_size_mb, uint, 0444); 52 MODULE_PARM_DESC(max_host_mem_size_mb, 53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 54 55 static unsigned int sgl_threshold = SZ_32K; 56 module_param(sgl_threshold, uint, 0644); 57 MODULE_PARM_DESC(sgl_threshold, 58 "Use SGLs when average request segment size is larger or equal to " 59 "this size. Use 0 to disable SGLs."); 60 61 static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 62 static const struct kernel_param_ops io_queue_depth_ops = { 63 .set = io_queue_depth_set, 64 .get = param_get_int, 65 }; 66 67 static int io_queue_depth = 1024; 68 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 69 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 70 71 static unsigned int write_queues; 72 module_param(write_queues, uint, 0644); 73 MODULE_PARM_DESC(write_queues, 74 "Number of queues to use for writes. If not set, reads and writes " 75 "will share a queue set."); 76 77 static unsigned int poll_queues; 78 module_param(poll_queues, uint, 0644); 79 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 80 81 struct nvme_dev; 82 struct nvme_queue; 83 84 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 85 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 86 87 /* 88 * Represents an NVM Express device. Each nvme_dev is a PCI function. 89 */ 90 struct nvme_dev { 91 struct nvme_queue *queues; 92 struct blk_mq_tag_set tagset; 93 struct blk_mq_tag_set admin_tagset; 94 u32 __iomem *dbs; 95 struct device *dev; 96 struct dma_pool *prp_page_pool; 97 struct dma_pool *prp_small_pool; 98 unsigned online_queues; 99 unsigned max_qid; 100 unsigned io_queues[HCTX_MAX_TYPES]; 101 unsigned int num_vecs; 102 int q_depth; 103 int io_sqes; 104 u32 db_stride; 105 void __iomem *bar; 106 unsigned long bar_mapped_size; 107 struct work_struct remove_work; 108 struct mutex shutdown_lock; 109 bool subsystem; 110 u64 cmb_size; 111 bool cmb_use_sqes; 112 u32 cmbsz; 113 u32 cmbloc; 114 struct nvme_ctrl ctrl; 115 u32 last_ps; 116 117 mempool_t *iod_mempool; 118 119 /* shadow doorbell buffer support: */ 120 u32 *dbbuf_dbs; 121 dma_addr_t dbbuf_dbs_dma_addr; 122 u32 *dbbuf_eis; 123 dma_addr_t dbbuf_eis_dma_addr; 124 125 /* host memory buffer support: */ 126 u64 host_mem_size; 127 u32 nr_host_mem_descs; 128 dma_addr_t host_mem_descs_dma; 129 struct nvme_host_mem_buf_desc *host_mem_descs; 130 void **host_mem_desc_bufs; 131 }; 132 133 static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 134 { 135 int n = 0, ret; 136 137 ret = kstrtoint(val, 10, &n); 138 if (ret != 0 || n < 2) 139 return -EINVAL; 140 141 return param_set_int(val, kp); 142 } 143 144 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 145 { 146 return qid * 2 * stride; 147 } 148 149 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 150 { 151 return (qid * 2 + 1) * stride; 152 } 153 154 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 155 { 156 return container_of(ctrl, struct nvme_dev, ctrl); 157 } 158 159 /* 160 * An NVM Express queue. Each device has at least two (one for admin 161 * commands and one for I/O commands). 162 */ 163 struct nvme_queue { 164 struct nvme_dev *dev; 165 spinlock_t sq_lock; 166 void *sq_cmds; 167 /* only used for poll queues: */ 168 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 169 volatile struct nvme_completion *cqes; 170 dma_addr_t sq_dma_addr; 171 dma_addr_t cq_dma_addr; 172 u32 __iomem *q_db; 173 u16 q_depth; 174 u16 cq_vector; 175 u16 sq_tail; 176 u16 last_sq_tail; 177 u16 cq_head; 178 u16 qid; 179 u8 cq_phase; 180 u8 sqes; 181 unsigned long flags; 182 #define NVMEQ_ENABLED 0 183 #define NVMEQ_SQ_CMB 1 184 #define NVMEQ_DELETE_ERROR 2 185 #define NVMEQ_POLLED 3 186 u32 *dbbuf_sq_db; 187 u32 *dbbuf_cq_db; 188 u32 *dbbuf_sq_ei; 189 u32 *dbbuf_cq_ei; 190 struct completion delete_done; 191 }; 192 193 /* 194 * The nvme_iod describes the data in an I/O. 195 * 196 * The sg pointer contains the list of PRP/SGL chunk allocations in addition 197 * to the actual struct scatterlist. 198 */ 199 struct nvme_iod { 200 struct nvme_request req; 201 struct nvme_queue *nvmeq; 202 bool use_sgl; 203 int aborted; 204 int npages; /* In the PRP list. 0 means small pool in use */ 205 int nents; /* Used in scatterlist */ 206 dma_addr_t first_dma; 207 unsigned int dma_len; /* length of single DMA segment mapping */ 208 dma_addr_t meta_dma; 209 struct scatterlist *sg; 210 }; 211 212 static unsigned int max_io_queues(void) 213 { 214 return num_possible_cpus() + write_queues + poll_queues; 215 } 216 217 static unsigned int max_queue_count(void) 218 { 219 /* IO queues + admin queue */ 220 return 1 + max_io_queues(); 221 } 222 223 static inline unsigned int nvme_dbbuf_size(u32 stride) 224 { 225 return (max_queue_count() * 8 * stride); 226 } 227 228 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 229 { 230 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 231 232 if (dev->dbbuf_dbs) 233 return 0; 234 235 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 236 &dev->dbbuf_dbs_dma_addr, 237 GFP_KERNEL); 238 if (!dev->dbbuf_dbs) 239 return -ENOMEM; 240 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 241 &dev->dbbuf_eis_dma_addr, 242 GFP_KERNEL); 243 if (!dev->dbbuf_eis) { 244 dma_free_coherent(dev->dev, mem_size, 245 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 246 dev->dbbuf_dbs = NULL; 247 return -ENOMEM; 248 } 249 250 return 0; 251 } 252 253 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 254 { 255 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 256 257 if (dev->dbbuf_dbs) { 258 dma_free_coherent(dev->dev, mem_size, 259 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 260 dev->dbbuf_dbs = NULL; 261 } 262 if (dev->dbbuf_eis) { 263 dma_free_coherent(dev->dev, mem_size, 264 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 265 dev->dbbuf_eis = NULL; 266 } 267 } 268 269 static void nvme_dbbuf_init(struct nvme_dev *dev, 270 struct nvme_queue *nvmeq, int qid) 271 { 272 if (!dev->dbbuf_dbs || !qid) 273 return; 274 275 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 276 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 277 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 278 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 279 } 280 281 static void nvme_dbbuf_set(struct nvme_dev *dev) 282 { 283 struct nvme_command c; 284 285 if (!dev->dbbuf_dbs) 286 return; 287 288 memset(&c, 0, sizeof(c)); 289 c.dbbuf.opcode = nvme_admin_dbbuf; 290 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 291 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 292 293 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 294 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 295 /* Free memory and continue on */ 296 nvme_dbbuf_dma_free(dev); 297 } 298 } 299 300 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 301 { 302 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 303 } 304 305 /* Update dbbuf and return true if an MMIO is required */ 306 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 307 volatile u32 *dbbuf_ei) 308 { 309 if (dbbuf_db) { 310 u16 old_value; 311 312 /* 313 * Ensure that the queue is written before updating 314 * the doorbell in memory 315 */ 316 wmb(); 317 318 old_value = *dbbuf_db; 319 *dbbuf_db = value; 320 321 /* 322 * Ensure that the doorbell is updated before reading the event 323 * index from memory. The controller needs to provide similar 324 * ordering to ensure the envent index is updated before reading 325 * the doorbell. 326 */ 327 mb(); 328 329 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 330 return false; 331 } 332 333 return true; 334 } 335 336 /* 337 * Will slightly overestimate the number of pages needed. This is OK 338 * as it only leads to a small amount of wasted memory for the lifetime of 339 * the I/O. 340 */ 341 static int nvme_npages(unsigned size, struct nvme_dev *dev) 342 { 343 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 344 dev->ctrl.page_size); 345 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 346 } 347 348 /* 349 * Calculates the number of pages needed for the SGL segments. For example a 4k 350 * page can accommodate 256 SGL descriptors. 351 */ 352 static int nvme_pci_npages_sgl(unsigned int num_seg) 353 { 354 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 355 } 356 357 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 358 unsigned int size, unsigned int nseg, bool use_sgl) 359 { 360 size_t alloc_size; 361 362 if (use_sgl) 363 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 364 else 365 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 366 367 return alloc_size + sizeof(struct scatterlist) * nseg; 368 } 369 370 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 371 unsigned int hctx_idx) 372 { 373 struct nvme_dev *dev = data; 374 struct nvme_queue *nvmeq = &dev->queues[0]; 375 376 WARN_ON(hctx_idx != 0); 377 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 378 379 hctx->driver_data = nvmeq; 380 return 0; 381 } 382 383 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 384 unsigned int hctx_idx) 385 { 386 struct nvme_dev *dev = data; 387 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 388 389 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 390 hctx->driver_data = nvmeq; 391 return 0; 392 } 393 394 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 395 unsigned int hctx_idx, unsigned int numa_node) 396 { 397 struct nvme_dev *dev = set->driver_data; 398 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 399 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 400 struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 401 402 BUG_ON(!nvmeq); 403 iod->nvmeq = nvmeq; 404 405 nvme_req(req)->ctrl = &dev->ctrl; 406 return 0; 407 } 408 409 static int queue_irq_offset(struct nvme_dev *dev) 410 { 411 /* if we have more than 1 vec, admin queue offsets us by 1 */ 412 if (dev->num_vecs > 1) 413 return 1; 414 415 return 0; 416 } 417 418 static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 419 { 420 struct nvme_dev *dev = set->driver_data; 421 int i, qoff, offset; 422 423 offset = queue_irq_offset(dev); 424 for (i = 0, qoff = 0; i < set->nr_maps; i++) { 425 struct blk_mq_queue_map *map = &set->map[i]; 426 427 map->nr_queues = dev->io_queues[i]; 428 if (!map->nr_queues) { 429 BUG_ON(i == HCTX_TYPE_DEFAULT); 430 continue; 431 } 432 433 /* 434 * The poll queue(s) doesn't have an IRQ (and hence IRQ 435 * affinity), so use the regular blk-mq cpu mapping 436 */ 437 map->queue_offset = qoff; 438 if (i != HCTX_TYPE_POLL && offset) 439 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 440 else 441 blk_mq_map_queues(map); 442 qoff += map->nr_queues; 443 offset += map->nr_queues; 444 } 445 446 return 0; 447 } 448 449 /* 450 * Write sq tail if we are asked to, or if the next command would wrap. 451 */ 452 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 453 { 454 if (!write_sq) { 455 u16 next_tail = nvmeq->sq_tail + 1; 456 457 if (next_tail == nvmeq->q_depth) 458 next_tail = 0; 459 if (next_tail != nvmeq->last_sq_tail) 460 return; 461 } 462 463 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 464 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 465 writel(nvmeq->sq_tail, nvmeq->q_db); 466 nvmeq->last_sq_tail = nvmeq->sq_tail; 467 } 468 469 /** 470 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 471 * @nvmeq: The queue to use 472 * @cmd: The command to send 473 * @write_sq: whether to write to the SQ doorbell 474 */ 475 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 476 bool write_sq) 477 { 478 spin_lock(&nvmeq->sq_lock); 479 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 480 cmd, sizeof(*cmd)); 481 if (++nvmeq->sq_tail == nvmeq->q_depth) 482 nvmeq->sq_tail = 0; 483 nvme_write_sq_db(nvmeq, write_sq); 484 spin_unlock(&nvmeq->sq_lock); 485 } 486 487 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 488 { 489 struct nvme_queue *nvmeq = hctx->driver_data; 490 491 spin_lock(&nvmeq->sq_lock); 492 if (nvmeq->sq_tail != nvmeq->last_sq_tail) 493 nvme_write_sq_db(nvmeq, true); 494 spin_unlock(&nvmeq->sq_lock); 495 } 496 497 static void **nvme_pci_iod_list(struct request *req) 498 { 499 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 500 return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 501 } 502 503 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 504 { 505 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 506 int nseg = blk_rq_nr_phys_segments(req); 507 unsigned int avg_seg_size; 508 509 if (nseg == 0) 510 return false; 511 512 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 513 514 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 515 return false; 516 if (!iod->nvmeq->qid) 517 return false; 518 if (!sgl_threshold || avg_seg_size < sgl_threshold) 519 return false; 520 return true; 521 } 522 523 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 524 { 525 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 526 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 527 dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 528 int i; 529 530 if (iod->dma_len) { 531 dma_unmap_page(dev->dev, dma_addr, iod->dma_len, 532 rq_dma_dir(req)); 533 return; 534 } 535 536 WARN_ON_ONCE(!iod->nents); 537 538 if (is_pci_p2pdma_page(sg_page(iod->sg))) 539 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 540 rq_dma_dir(req)); 541 else 542 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 543 544 545 if (iod->npages == 0) 546 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 547 dma_addr); 548 549 for (i = 0; i < iod->npages; i++) { 550 void *addr = nvme_pci_iod_list(req)[i]; 551 552 if (iod->use_sgl) { 553 struct nvme_sgl_desc *sg_list = addr; 554 555 next_dma_addr = 556 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 557 } else { 558 __le64 *prp_list = addr; 559 560 next_dma_addr = le64_to_cpu(prp_list[last_prp]); 561 } 562 563 dma_pool_free(dev->prp_page_pool, addr, dma_addr); 564 dma_addr = next_dma_addr; 565 } 566 567 mempool_free(iod->sg, dev->iod_mempool); 568 } 569 570 static void nvme_print_sgl(struct scatterlist *sgl, int nents) 571 { 572 int i; 573 struct scatterlist *sg; 574 575 for_each_sg(sgl, sg, nents, i) { 576 dma_addr_t phys = sg_phys(sg); 577 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 578 "dma_address:%pad dma_length:%d\n", 579 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 580 sg_dma_len(sg)); 581 } 582 } 583 584 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 585 struct request *req, struct nvme_rw_command *cmnd) 586 { 587 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 588 struct dma_pool *pool; 589 int length = blk_rq_payload_bytes(req); 590 struct scatterlist *sg = iod->sg; 591 int dma_len = sg_dma_len(sg); 592 u64 dma_addr = sg_dma_address(sg); 593 u32 page_size = dev->ctrl.page_size; 594 int offset = dma_addr & (page_size - 1); 595 __le64 *prp_list; 596 void **list = nvme_pci_iod_list(req); 597 dma_addr_t prp_dma; 598 int nprps, i; 599 600 length -= (page_size - offset); 601 if (length <= 0) { 602 iod->first_dma = 0; 603 goto done; 604 } 605 606 dma_len -= (page_size - offset); 607 if (dma_len) { 608 dma_addr += (page_size - offset); 609 } else { 610 sg = sg_next(sg); 611 dma_addr = sg_dma_address(sg); 612 dma_len = sg_dma_len(sg); 613 } 614 615 if (length <= page_size) { 616 iod->first_dma = dma_addr; 617 goto done; 618 } 619 620 nprps = DIV_ROUND_UP(length, page_size); 621 if (nprps <= (256 / 8)) { 622 pool = dev->prp_small_pool; 623 iod->npages = 0; 624 } else { 625 pool = dev->prp_page_pool; 626 iod->npages = 1; 627 } 628 629 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 630 if (!prp_list) { 631 iod->first_dma = dma_addr; 632 iod->npages = -1; 633 return BLK_STS_RESOURCE; 634 } 635 list[0] = prp_list; 636 iod->first_dma = prp_dma; 637 i = 0; 638 for (;;) { 639 if (i == page_size >> 3) { 640 __le64 *old_prp_list = prp_list; 641 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 642 if (!prp_list) 643 return BLK_STS_RESOURCE; 644 list[iod->npages++] = prp_list; 645 prp_list[0] = old_prp_list[i - 1]; 646 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 647 i = 1; 648 } 649 prp_list[i++] = cpu_to_le64(dma_addr); 650 dma_len -= page_size; 651 dma_addr += page_size; 652 length -= page_size; 653 if (length <= 0) 654 break; 655 if (dma_len > 0) 656 continue; 657 if (unlikely(dma_len < 0)) 658 goto bad_sgl; 659 sg = sg_next(sg); 660 dma_addr = sg_dma_address(sg); 661 dma_len = sg_dma_len(sg); 662 } 663 664 done: 665 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 666 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 667 668 return BLK_STS_OK; 669 670 bad_sgl: 671 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 672 "Invalid SGL for payload:%d nents:%d\n", 673 blk_rq_payload_bytes(req), iod->nents); 674 return BLK_STS_IOERR; 675 } 676 677 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 678 struct scatterlist *sg) 679 { 680 sge->addr = cpu_to_le64(sg_dma_address(sg)); 681 sge->length = cpu_to_le32(sg_dma_len(sg)); 682 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 683 } 684 685 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 686 dma_addr_t dma_addr, int entries) 687 { 688 sge->addr = cpu_to_le64(dma_addr); 689 if (entries < SGES_PER_PAGE) { 690 sge->length = cpu_to_le32(entries * sizeof(*sge)); 691 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 692 } else { 693 sge->length = cpu_to_le32(PAGE_SIZE); 694 sge->type = NVME_SGL_FMT_SEG_DESC << 4; 695 } 696 } 697 698 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 699 struct request *req, struct nvme_rw_command *cmd, int entries) 700 { 701 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 702 struct dma_pool *pool; 703 struct nvme_sgl_desc *sg_list; 704 struct scatterlist *sg = iod->sg; 705 dma_addr_t sgl_dma; 706 int i = 0; 707 708 /* setting the transfer type as SGL */ 709 cmd->flags = NVME_CMD_SGL_METABUF; 710 711 if (entries == 1) { 712 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 713 return BLK_STS_OK; 714 } 715 716 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 717 pool = dev->prp_small_pool; 718 iod->npages = 0; 719 } else { 720 pool = dev->prp_page_pool; 721 iod->npages = 1; 722 } 723 724 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 725 if (!sg_list) { 726 iod->npages = -1; 727 return BLK_STS_RESOURCE; 728 } 729 730 nvme_pci_iod_list(req)[0] = sg_list; 731 iod->first_dma = sgl_dma; 732 733 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 734 735 do { 736 if (i == SGES_PER_PAGE) { 737 struct nvme_sgl_desc *old_sg_desc = sg_list; 738 struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 739 740 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 741 if (!sg_list) 742 return BLK_STS_RESOURCE; 743 744 i = 0; 745 nvme_pci_iod_list(req)[iod->npages++] = sg_list; 746 sg_list[i++] = *link; 747 nvme_pci_sgl_set_seg(link, sgl_dma, entries); 748 } 749 750 nvme_pci_sgl_set_data(&sg_list[i++], sg); 751 sg = sg_next(sg); 752 } while (--entries > 0); 753 754 return BLK_STS_OK; 755 } 756 757 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 758 struct request *req, struct nvme_rw_command *cmnd, 759 struct bio_vec *bv) 760 { 761 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 762 unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1); 763 unsigned int first_prp_len = dev->ctrl.page_size - offset; 764 765 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 766 if (dma_mapping_error(dev->dev, iod->first_dma)) 767 return BLK_STS_RESOURCE; 768 iod->dma_len = bv->bv_len; 769 770 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 771 if (bv->bv_len > first_prp_len) 772 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 773 return 0; 774 } 775 776 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 777 struct request *req, struct nvme_rw_command *cmnd, 778 struct bio_vec *bv) 779 { 780 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 781 782 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 783 if (dma_mapping_error(dev->dev, iod->first_dma)) 784 return BLK_STS_RESOURCE; 785 iod->dma_len = bv->bv_len; 786 787 cmnd->flags = NVME_CMD_SGL_METABUF; 788 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 789 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 790 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 791 return 0; 792 } 793 794 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 795 struct nvme_command *cmnd) 796 { 797 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 798 blk_status_t ret = BLK_STS_RESOURCE; 799 int nr_mapped; 800 801 if (blk_rq_nr_phys_segments(req) == 1) { 802 struct bio_vec bv = req_bvec(req); 803 804 if (!is_pci_p2pdma_page(bv.bv_page)) { 805 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2) 806 return nvme_setup_prp_simple(dev, req, 807 &cmnd->rw, &bv); 808 809 if (iod->nvmeq->qid && 810 dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 811 return nvme_setup_sgl_simple(dev, req, 812 &cmnd->rw, &bv); 813 } 814 } 815 816 iod->dma_len = 0; 817 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 818 if (!iod->sg) 819 return BLK_STS_RESOURCE; 820 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 821 iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 822 if (!iod->nents) 823 goto out; 824 825 if (is_pci_p2pdma_page(sg_page(iod->sg))) 826 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 827 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 828 else 829 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 830 rq_dma_dir(req), DMA_ATTR_NO_WARN); 831 if (!nr_mapped) 832 goto out; 833 834 iod->use_sgl = nvme_pci_use_sgls(dev, req); 835 if (iod->use_sgl) 836 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 837 else 838 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 839 out: 840 if (ret != BLK_STS_OK) 841 nvme_unmap_data(dev, req); 842 return ret; 843 } 844 845 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 846 struct nvme_command *cmnd) 847 { 848 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 849 850 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 851 rq_dma_dir(req), 0); 852 if (dma_mapping_error(dev->dev, iod->meta_dma)) 853 return BLK_STS_IOERR; 854 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 855 return 0; 856 } 857 858 /* 859 * NOTE: ns is NULL when called on the admin queue. 860 */ 861 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 862 const struct blk_mq_queue_data *bd) 863 { 864 struct nvme_ns *ns = hctx->queue->queuedata; 865 struct nvme_queue *nvmeq = hctx->driver_data; 866 struct nvme_dev *dev = nvmeq->dev; 867 struct request *req = bd->rq; 868 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 869 struct nvme_command cmnd; 870 blk_status_t ret; 871 872 iod->aborted = 0; 873 iod->npages = -1; 874 iod->nents = 0; 875 876 /* 877 * We should not need to do this, but we're still using this to 878 * ensure we can drain requests on a dying queue. 879 */ 880 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 881 return BLK_STS_IOERR; 882 883 ret = nvme_setup_cmd(ns, req, &cmnd); 884 if (ret) 885 return ret; 886 887 if (blk_rq_nr_phys_segments(req)) { 888 ret = nvme_map_data(dev, req, &cmnd); 889 if (ret) 890 goto out_free_cmd; 891 } 892 893 if (blk_integrity_rq(req)) { 894 ret = nvme_map_metadata(dev, req, &cmnd); 895 if (ret) 896 goto out_unmap_data; 897 } 898 899 blk_mq_start_request(req); 900 nvme_submit_cmd(nvmeq, &cmnd, bd->last); 901 return BLK_STS_OK; 902 out_unmap_data: 903 nvme_unmap_data(dev, req); 904 out_free_cmd: 905 nvme_cleanup_cmd(req); 906 return ret; 907 } 908 909 static void nvme_pci_complete_rq(struct request *req) 910 { 911 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 912 struct nvme_dev *dev = iod->nvmeq->dev; 913 914 if (blk_integrity_rq(req)) 915 dma_unmap_page(dev->dev, iod->meta_dma, 916 rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 917 if (blk_rq_nr_phys_segments(req)) 918 nvme_unmap_data(dev, req); 919 nvme_complete_rq(req); 920 } 921 922 /* We read the CQE phase first to check if the rest of the entry is valid */ 923 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 924 { 925 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 926 nvmeq->cq_phase; 927 } 928 929 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 930 { 931 u16 head = nvmeq->cq_head; 932 933 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 934 nvmeq->dbbuf_cq_ei)) 935 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 936 } 937 938 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 939 { 940 if (!nvmeq->qid) 941 return nvmeq->dev->admin_tagset.tags[0]; 942 return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 943 } 944 945 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 946 { 947 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 948 struct request *req; 949 950 if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 951 dev_warn(nvmeq->dev->ctrl.device, 952 "invalid id %d completed on queue %d\n", 953 cqe->command_id, le16_to_cpu(cqe->sq_id)); 954 return; 955 } 956 957 /* 958 * AEN requests are special as they don't time out and can 959 * survive any kind of queue freeze and often don't respond to 960 * aborts. We don't even bother to allocate a struct request 961 * for them but rather special case them here. 962 */ 963 if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) { 964 nvme_complete_async_event(&nvmeq->dev->ctrl, 965 cqe->status, &cqe->result); 966 return; 967 } 968 969 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id); 970 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 971 nvme_end_request(req, cqe->status, cqe->result); 972 } 973 974 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 975 { 976 while (start != end) { 977 nvme_handle_cqe(nvmeq, start); 978 if (++start == nvmeq->q_depth) 979 start = 0; 980 } 981 } 982 983 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 984 { 985 if (nvmeq->cq_head == nvmeq->q_depth - 1) { 986 nvmeq->cq_head = 0; 987 nvmeq->cq_phase = !nvmeq->cq_phase; 988 } else { 989 nvmeq->cq_head++; 990 } 991 } 992 993 static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 994 u16 *end, unsigned int tag) 995 { 996 int found = 0; 997 998 *start = nvmeq->cq_head; 999 while (nvme_cqe_pending(nvmeq)) { 1000 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 1001 found++; 1002 nvme_update_cq_head(nvmeq); 1003 } 1004 *end = nvmeq->cq_head; 1005 1006 if (*start != *end) 1007 nvme_ring_cq_doorbell(nvmeq); 1008 return found; 1009 } 1010 1011 static irqreturn_t nvme_irq(int irq, void *data) 1012 { 1013 struct nvme_queue *nvmeq = data; 1014 irqreturn_t ret = IRQ_NONE; 1015 u16 start, end; 1016 1017 /* 1018 * The rmb/wmb pair ensures we see all updates from a previous run of 1019 * the irq handler, even if that was on another CPU. 1020 */ 1021 rmb(); 1022 nvme_process_cq(nvmeq, &start, &end, -1); 1023 wmb(); 1024 1025 if (start != end) { 1026 nvme_complete_cqes(nvmeq, start, end); 1027 return IRQ_HANDLED; 1028 } 1029 1030 return ret; 1031 } 1032 1033 static irqreturn_t nvme_irq_check(int irq, void *data) 1034 { 1035 struct nvme_queue *nvmeq = data; 1036 if (nvme_cqe_pending(nvmeq)) 1037 return IRQ_WAKE_THREAD; 1038 return IRQ_NONE; 1039 } 1040 1041 /* 1042 * Poll for completions any queue, including those not dedicated to polling. 1043 * Can be called from any context. 1044 */ 1045 static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) 1046 { 1047 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1048 u16 start, end; 1049 int found; 1050 1051 /* 1052 * For a poll queue we need to protect against the polling thread 1053 * using the CQ lock. For normal interrupt driven threads we have 1054 * to disable the interrupt to avoid racing with it. 1055 */ 1056 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) { 1057 spin_lock(&nvmeq->cq_poll_lock); 1058 found = nvme_process_cq(nvmeq, &start, &end, tag); 1059 spin_unlock(&nvmeq->cq_poll_lock); 1060 } else { 1061 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1062 found = nvme_process_cq(nvmeq, &start, &end, tag); 1063 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1064 } 1065 1066 nvme_complete_cqes(nvmeq, start, end); 1067 return found; 1068 } 1069 1070 static int nvme_poll(struct blk_mq_hw_ctx *hctx) 1071 { 1072 struct nvme_queue *nvmeq = hctx->driver_data; 1073 u16 start, end; 1074 bool found; 1075 1076 if (!nvme_cqe_pending(nvmeq)) 1077 return 0; 1078 1079 spin_lock(&nvmeq->cq_poll_lock); 1080 found = nvme_process_cq(nvmeq, &start, &end, -1); 1081 spin_unlock(&nvmeq->cq_poll_lock); 1082 1083 nvme_complete_cqes(nvmeq, start, end); 1084 return found; 1085 } 1086 1087 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 1088 { 1089 struct nvme_dev *dev = to_nvme_dev(ctrl); 1090 struct nvme_queue *nvmeq = &dev->queues[0]; 1091 struct nvme_command c; 1092 1093 memset(&c, 0, sizeof(c)); 1094 c.common.opcode = nvme_admin_async_event; 1095 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1096 nvme_submit_cmd(nvmeq, &c, true); 1097 } 1098 1099 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1100 { 1101 struct nvme_command c; 1102 1103 memset(&c, 0, sizeof(c)); 1104 c.delete_queue.opcode = opcode; 1105 c.delete_queue.qid = cpu_to_le16(id); 1106 1107 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1108 } 1109 1110 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1111 struct nvme_queue *nvmeq, s16 vector) 1112 { 1113 struct nvme_command c; 1114 int flags = NVME_QUEUE_PHYS_CONTIG; 1115 1116 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1117 flags |= NVME_CQ_IRQ_ENABLED; 1118 1119 /* 1120 * Note: we (ab)use the fact that the prp fields survive if no data 1121 * is attached to the request. 1122 */ 1123 memset(&c, 0, sizeof(c)); 1124 c.create_cq.opcode = nvme_admin_create_cq; 1125 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1126 c.create_cq.cqid = cpu_to_le16(qid); 1127 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1128 c.create_cq.cq_flags = cpu_to_le16(flags); 1129 c.create_cq.irq_vector = cpu_to_le16(vector); 1130 1131 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1132 } 1133 1134 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1135 struct nvme_queue *nvmeq) 1136 { 1137 struct nvme_ctrl *ctrl = &dev->ctrl; 1138 struct nvme_command c; 1139 int flags = NVME_QUEUE_PHYS_CONTIG; 1140 1141 /* 1142 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1143 * set. Since URGENT priority is zeroes, it makes all queues 1144 * URGENT. 1145 */ 1146 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1147 flags |= NVME_SQ_PRIO_MEDIUM; 1148 1149 /* 1150 * Note: we (ab)use the fact that the prp fields survive if no data 1151 * is attached to the request. 1152 */ 1153 memset(&c, 0, sizeof(c)); 1154 c.create_sq.opcode = nvme_admin_create_sq; 1155 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1156 c.create_sq.sqid = cpu_to_le16(qid); 1157 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1158 c.create_sq.sq_flags = cpu_to_le16(flags); 1159 c.create_sq.cqid = cpu_to_le16(qid); 1160 1161 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1162 } 1163 1164 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1165 { 1166 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1167 } 1168 1169 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1170 { 1171 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1172 } 1173 1174 static void abort_endio(struct request *req, blk_status_t error) 1175 { 1176 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1177 struct nvme_queue *nvmeq = iod->nvmeq; 1178 1179 dev_warn(nvmeq->dev->ctrl.device, 1180 "Abort status: 0x%x", nvme_req(req)->status); 1181 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1182 blk_mq_free_request(req); 1183 } 1184 1185 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1186 { 1187 1188 /* If true, indicates loss of adapter communication, possibly by a 1189 * NVMe Subsystem reset. 1190 */ 1191 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1192 1193 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1194 switch (dev->ctrl.state) { 1195 case NVME_CTRL_RESETTING: 1196 case NVME_CTRL_CONNECTING: 1197 return false; 1198 default: 1199 break; 1200 } 1201 1202 /* We shouldn't reset unless the controller is on fatal error state 1203 * _or_ if we lost the communication with it. 1204 */ 1205 if (!(csts & NVME_CSTS_CFS) && !nssro) 1206 return false; 1207 1208 return true; 1209 } 1210 1211 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1212 { 1213 /* Read a config register to help see what died. */ 1214 u16 pci_status; 1215 int result; 1216 1217 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1218 &pci_status); 1219 if (result == PCIBIOS_SUCCESSFUL) 1220 dev_warn(dev->ctrl.device, 1221 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1222 csts, pci_status); 1223 else 1224 dev_warn(dev->ctrl.device, 1225 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1226 csts, result); 1227 } 1228 1229 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 1230 { 1231 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1232 struct nvme_queue *nvmeq = iod->nvmeq; 1233 struct nvme_dev *dev = nvmeq->dev; 1234 struct request *abort_req; 1235 struct nvme_command cmd; 1236 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1237 1238 /* If PCI error recovery process is happening, we cannot reset or 1239 * the recovery mechanism will surely fail. 1240 */ 1241 mb(); 1242 if (pci_channel_offline(to_pci_dev(dev->dev))) 1243 return BLK_EH_RESET_TIMER; 1244 1245 /* 1246 * Reset immediately if the controller is failed 1247 */ 1248 if (nvme_should_reset(dev, csts)) { 1249 nvme_warn_reset(dev, csts); 1250 nvme_dev_disable(dev, false); 1251 nvme_reset_ctrl(&dev->ctrl); 1252 return BLK_EH_DONE; 1253 } 1254 1255 /* 1256 * Did we miss an interrupt? 1257 */ 1258 if (nvme_poll_irqdisable(nvmeq, req->tag)) { 1259 dev_warn(dev->ctrl.device, 1260 "I/O %d QID %d timeout, completion polled\n", 1261 req->tag, nvmeq->qid); 1262 return BLK_EH_DONE; 1263 } 1264 1265 /* 1266 * Shutdown immediately if controller times out while starting. The 1267 * reset work will see the pci device disabled when it gets the forced 1268 * cancellation error. All outstanding requests are completed on 1269 * shutdown, so we return BLK_EH_DONE. 1270 */ 1271 switch (dev->ctrl.state) { 1272 case NVME_CTRL_CONNECTING: 1273 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1274 /* fall through */ 1275 case NVME_CTRL_DELETING: 1276 dev_warn_ratelimited(dev->ctrl.device, 1277 "I/O %d QID %d timeout, disable controller\n", 1278 req->tag, nvmeq->qid); 1279 nvme_dev_disable(dev, true); 1280 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1281 return BLK_EH_DONE; 1282 case NVME_CTRL_RESETTING: 1283 return BLK_EH_RESET_TIMER; 1284 default: 1285 break; 1286 } 1287 1288 /* 1289 * Shutdown the controller immediately and schedule a reset if the 1290 * command was already aborted once before and still hasn't been 1291 * returned to the driver, or if this is the admin queue. 1292 */ 1293 if (!nvmeq->qid || iod->aborted) { 1294 dev_warn(dev->ctrl.device, 1295 "I/O %d QID %d timeout, reset controller\n", 1296 req->tag, nvmeq->qid); 1297 nvme_dev_disable(dev, false); 1298 nvme_reset_ctrl(&dev->ctrl); 1299 1300 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1301 return BLK_EH_DONE; 1302 } 1303 1304 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1305 atomic_inc(&dev->ctrl.abort_limit); 1306 return BLK_EH_RESET_TIMER; 1307 } 1308 iod->aborted = 1; 1309 1310 memset(&cmd, 0, sizeof(cmd)); 1311 cmd.abort.opcode = nvme_admin_abort_cmd; 1312 cmd.abort.cid = req->tag; 1313 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1314 1315 dev_warn(nvmeq->dev->ctrl.device, 1316 "I/O %d QID %d timeout, aborting\n", 1317 req->tag, nvmeq->qid); 1318 1319 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1320 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1321 if (IS_ERR(abort_req)) { 1322 atomic_inc(&dev->ctrl.abort_limit); 1323 return BLK_EH_RESET_TIMER; 1324 } 1325 1326 abort_req->timeout = ADMIN_TIMEOUT; 1327 abort_req->end_io_data = NULL; 1328 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 1329 1330 /* 1331 * The aborted req will be completed on receiving the abort req. 1332 * We enable the timer again. If hit twice, it'll cause a device reset, 1333 * as the device then is in a faulty state. 1334 */ 1335 return BLK_EH_RESET_TIMER; 1336 } 1337 1338 static void nvme_free_queue(struct nvme_queue *nvmeq) 1339 { 1340 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 1341 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1342 if (!nvmeq->sq_cmds) 1343 return; 1344 1345 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 1346 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 1347 nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1348 } else { 1349 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 1350 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1351 } 1352 } 1353 1354 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1355 { 1356 int i; 1357 1358 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1359 dev->ctrl.queue_count--; 1360 nvme_free_queue(&dev->queues[i]); 1361 } 1362 } 1363 1364 /** 1365 * nvme_suspend_queue - put queue into suspended state 1366 * @nvmeq: queue to suspend 1367 */ 1368 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1369 { 1370 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 1371 return 1; 1372 1373 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1374 mb(); 1375 1376 nvmeq->dev->online_queues--; 1377 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1378 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 1379 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 1380 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 1381 return 0; 1382 } 1383 1384 static void nvme_suspend_io_queues(struct nvme_dev *dev) 1385 { 1386 int i; 1387 1388 for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1389 nvme_suspend_queue(&dev->queues[i]); 1390 } 1391 1392 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 1393 { 1394 struct nvme_queue *nvmeq = &dev->queues[0]; 1395 1396 if (shutdown) 1397 nvme_shutdown_ctrl(&dev->ctrl); 1398 else 1399 nvme_disable_ctrl(&dev->ctrl); 1400 1401 nvme_poll_irqdisable(nvmeq, -1); 1402 } 1403 1404 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1405 int entry_size) 1406 { 1407 int q_depth = dev->q_depth; 1408 unsigned q_size_aligned = roundup(q_depth * entry_size, 1409 dev->ctrl.page_size); 1410 1411 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1412 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1413 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 1414 q_depth = div_u64(mem_per_q, entry_size); 1415 1416 /* 1417 * Ensure the reduced q_depth is above some threshold where it 1418 * would be better to map queues in system memory with the 1419 * original depth 1420 */ 1421 if (q_depth < 64) 1422 return -ENOMEM; 1423 } 1424 1425 return q_depth; 1426 } 1427 1428 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1429 int qid) 1430 { 1431 struct pci_dev *pdev = to_pci_dev(dev->dev); 1432 1433 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1434 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1435 if (nvmeq->sq_cmds) { 1436 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 1437 nvmeq->sq_cmds); 1438 if (nvmeq->sq_dma_addr) { 1439 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 1440 return 0; 1441 } 1442 1443 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1444 } 1445 } 1446 1447 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 1448 &nvmeq->sq_dma_addr, GFP_KERNEL); 1449 if (!nvmeq->sq_cmds) 1450 return -ENOMEM; 1451 return 0; 1452 } 1453 1454 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1455 { 1456 struct nvme_queue *nvmeq = &dev->queues[qid]; 1457 1458 if (dev->ctrl.queue_count > qid) 1459 return 0; 1460 1461 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 1462 nvmeq->q_depth = depth; 1463 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 1464 &nvmeq->cq_dma_addr, GFP_KERNEL); 1465 if (!nvmeq->cqes) 1466 goto free_nvmeq; 1467 1468 if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 1469 goto free_cqdma; 1470 1471 nvmeq->dev = dev; 1472 spin_lock_init(&nvmeq->sq_lock); 1473 spin_lock_init(&nvmeq->cq_poll_lock); 1474 nvmeq->cq_head = 0; 1475 nvmeq->cq_phase = 1; 1476 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1477 nvmeq->qid = qid; 1478 dev->ctrl.queue_count++; 1479 1480 return 0; 1481 1482 free_cqdma: 1483 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 1484 nvmeq->cq_dma_addr); 1485 free_nvmeq: 1486 return -ENOMEM; 1487 } 1488 1489 static int queue_request_irq(struct nvme_queue *nvmeq) 1490 { 1491 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1492 int nr = nvmeq->dev->ctrl.instance; 1493 1494 if (use_threaded_interrupts) { 1495 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1496 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1497 } else { 1498 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1499 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1500 } 1501 } 1502 1503 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1504 { 1505 struct nvme_dev *dev = nvmeq->dev; 1506 1507 nvmeq->sq_tail = 0; 1508 nvmeq->last_sq_tail = 0; 1509 nvmeq->cq_head = 0; 1510 nvmeq->cq_phase = 1; 1511 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1512 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1513 nvme_dbbuf_init(dev, nvmeq, qid); 1514 dev->online_queues++; 1515 wmb(); /* ensure the first interrupt sees the initialization */ 1516 } 1517 1518 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 1519 { 1520 struct nvme_dev *dev = nvmeq->dev; 1521 int result; 1522 u16 vector = 0; 1523 1524 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1525 1526 /* 1527 * A queue's vector matches the queue identifier unless the controller 1528 * has only one vector available. 1529 */ 1530 if (!polled) 1531 vector = dev->num_vecs == 1 ? 0 : qid; 1532 else 1533 set_bit(NVMEQ_POLLED, &nvmeq->flags); 1534 1535 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1536 if (result) 1537 return result; 1538 1539 result = adapter_alloc_sq(dev, qid, nvmeq); 1540 if (result < 0) 1541 return result; 1542 if (result) 1543 goto release_cq; 1544 1545 nvmeq->cq_vector = vector; 1546 nvme_init_queue(nvmeq, qid); 1547 1548 if (!polled) { 1549 result = queue_request_irq(nvmeq); 1550 if (result < 0) 1551 goto release_sq; 1552 } 1553 1554 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1555 return result; 1556 1557 release_sq: 1558 dev->online_queues--; 1559 adapter_delete_sq(dev, qid); 1560 release_cq: 1561 adapter_delete_cq(dev, qid); 1562 return result; 1563 } 1564 1565 static const struct blk_mq_ops nvme_mq_admin_ops = { 1566 .queue_rq = nvme_queue_rq, 1567 .complete = nvme_pci_complete_rq, 1568 .init_hctx = nvme_admin_init_hctx, 1569 .init_request = nvme_init_request, 1570 .timeout = nvme_timeout, 1571 }; 1572 1573 static const struct blk_mq_ops nvme_mq_ops = { 1574 .queue_rq = nvme_queue_rq, 1575 .complete = nvme_pci_complete_rq, 1576 .commit_rqs = nvme_commit_rqs, 1577 .init_hctx = nvme_init_hctx, 1578 .init_request = nvme_init_request, 1579 .map_queues = nvme_pci_map_queues, 1580 .timeout = nvme_timeout, 1581 .poll = nvme_poll, 1582 }; 1583 1584 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1585 { 1586 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1587 /* 1588 * If the controller was reset during removal, it's possible 1589 * user requests may be waiting on a stopped queue. Start the 1590 * queue to flush these to completion. 1591 */ 1592 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1593 blk_cleanup_queue(dev->ctrl.admin_q); 1594 blk_mq_free_tag_set(&dev->admin_tagset); 1595 } 1596 } 1597 1598 static int nvme_alloc_admin_tags(struct nvme_dev *dev) 1599 { 1600 if (!dev->ctrl.admin_q) { 1601 dev->admin_tagset.ops = &nvme_mq_admin_ops; 1602 dev->admin_tagset.nr_hw_queues = 1; 1603 1604 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1605 dev->admin_tagset.timeout = ADMIN_TIMEOUT; 1606 dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1607 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1608 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 1609 dev->admin_tagset.driver_data = dev; 1610 1611 if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 1612 return -ENOMEM; 1613 dev->ctrl.admin_tagset = &dev->admin_tagset; 1614 1615 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 1616 if (IS_ERR(dev->ctrl.admin_q)) { 1617 blk_mq_free_tag_set(&dev->admin_tagset); 1618 return -ENOMEM; 1619 } 1620 if (!blk_get_queue(dev->ctrl.admin_q)) { 1621 nvme_dev_remove_admin(dev); 1622 dev->ctrl.admin_q = NULL; 1623 return -ENODEV; 1624 } 1625 } else 1626 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1627 1628 return 0; 1629 } 1630 1631 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1632 { 1633 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1634 } 1635 1636 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1637 { 1638 struct pci_dev *pdev = to_pci_dev(dev->dev); 1639 1640 if (size <= dev->bar_mapped_size) 1641 return 0; 1642 if (size > pci_resource_len(pdev, 0)) 1643 return -ENOMEM; 1644 if (dev->bar) 1645 iounmap(dev->bar); 1646 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1647 if (!dev->bar) { 1648 dev->bar_mapped_size = 0; 1649 return -ENOMEM; 1650 } 1651 dev->bar_mapped_size = size; 1652 dev->dbs = dev->bar + NVME_REG_DBS; 1653 1654 return 0; 1655 } 1656 1657 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1658 { 1659 int result; 1660 u32 aqa; 1661 struct nvme_queue *nvmeq; 1662 1663 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1664 if (result < 0) 1665 return result; 1666 1667 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1668 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1669 1670 if (dev->subsystem && 1671 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1672 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1673 1674 result = nvme_disable_ctrl(&dev->ctrl); 1675 if (result < 0) 1676 return result; 1677 1678 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1679 if (result) 1680 return result; 1681 1682 nvmeq = &dev->queues[0]; 1683 aqa = nvmeq->q_depth - 1; 1684 aqa |= aqa << 16; 1685 1686 writel(aqa, dev->bar + NVME_REG_AQA); 1687 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1688 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1689 1690 result = nvme_enable_ctrl(&dev->ctrl); 1691 if (result) 1692 return result; 1693 1694 nvmeq->cq_vector = 0; 1695 nvme_init_queue(nvmeq, 0); 1696 result = queue_request_irq(nvmeq); 1697 if (result) { 1698 dev->online_queues--; 1699 return result; 1700 } 1701 1702 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1703 return result; 1704 } 1705 1706 static int nvme_create_io_queues(struct nvme_dev *dev) 1707 { 1708 unsigned i, max, rw_queues; 1709 int ret = 0; 1710 1711 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1712 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1713 ret = -ENOMEM; 1714 break; 1715 } 1716 } 1717 1718 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1719 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1720 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1721 dev->io_queues[HCTX_TYPE_READ]; 1722 } else { 1723 rw_queues = max; 1724 } 1725 1726 for (i = dev->online_queues; i <= max; i++) { 1727 bool polled = i > rw_queues; 1728 1729 ret = nvme_create_queue(&dev->queues[i], i, polled); 1730 if (ret) 1731 break; 1732 } 1733 1734 /* 1735 * Ignore failing Create SQ/CQ commands, we can continue with less 1736 * than the desired amount of queues, and even a controller without 1737 * I/O queues can still be used to issue admin commands. This might 1738 * be useful to upgrade a buggy firmware for example. 1739 */ 1740 return ret >= 0 ? 0 : ret; 1741 } 1742 1743 static ssize_t nvme_cmb_show(struct device *dev, 1744 struct device_attribute *attr, 1745 char *buf) 1746 { 1747 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1748 1749 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1750 ndev->cmbloc, ndev->cmbsz); 1751 } 1752 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1753 1754 static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1755 { 1756 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1757 1758 return 1ULL << (12 + 4 * szu); 1759 } 1760 1761 static u32 nvme_cmb_size(struct nvme_dev *dev) 1762 { 1763 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1764 } 1765 1766 static void nvme_map_cmb(struct nvme_dev *dev) 1767 { 1768 u64 size, offset; 1769 resource_size_t bar_size; 1770 struct pci_dev *pdev = to_pci_dev(dev->dev); 1771 int bar; 1772 1773 if (dev->cmb_size) 1774 return; 1775 1776 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1777 if (!dev->cmbsz) 1778 return; 1779 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1780 1781 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1782 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1783 bar = NVME_CMB_BIR(dev->cmbloc); 1784 bar_size = pci_resource_len(pdev, bar); 1785 1786 if (offset > bar_size) 1787 return; 1788 1789 /* 1790 * Controllers may support a CMB size larger than their BAR, 1791 * for example, due to being behind a bridge. Reduce the CMB to 1792 * the reported size of the BAR 1793 */ 1794 if (size > bar_size - offset) 1795 size = bar_size - offset; 1796 1797 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 1798 dev_warn(dev->ctrl.device, 1799 "failed to register the CMB\n"); 1800 return; 1801 } 1802 1803 dev->cmb_size = size; 1804 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 1805 1806 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 1807 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 1808 pci_p2pmem_publish(pdev, true); 1809 1810 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1811 &dev_attr_cmb.attr, NULL)) 1812 dev_warn(dev->ctrl.device, 1813 "failed to add sysfs attribute for CMB\n"); 1814 } 1815 1816 static inline void nvme_release_cmb(struct nvme_dev *dev) 1817 { 1818 if (dev->cmb_size) { 1819 sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1820 &dev_attr_cmb.attr, NULL); 1821 dev->cmb_size = 0; 1822 } 1823 } 1824 1825 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1826 { 1827 u64 dma_addr = dev->host_mem_descs_dma; 1828 struct nvme_command c; 1829 int ret; 1830 1831 memset(&c, 0, sizeof(c)); 1832 c.features.opcode = nvme_admin_set_features; 1833 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1834 c.features.dword11 = cpu_to_le32(bits); 1835 c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 1836 ilog2(dev->ctrl.page_size)); 1837 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1838 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1839 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1840 1841 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1842 if (ret) { 1843 dev_warn(dev->ctrl.device, 1844 "failed to set host mem (err %d, flags %#x).\n", 1845 ret, bits); 1846 } 1847 return ret; 1848 } 1849 1850 static void nvme_free_host_mem(struct nvme_dev *dev) 1851 { 1852 int i; 1853 1854 for (i = 0; i < dev->nr_host_mem_descs; i++) { 1855 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 1856 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 1857 1858 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1859 le64_to_cpu(desc->addr), 1860 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1861 } 1862 1863 kfree(dev->host_mem_desc_bufs); 1864 dev->host_mem_desc_bufs = NULL; 1865 dma_free_coherent(dev->dev, 1866 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 1867 dev->host_mem_descs, dev->host_mem_descs_dma); 1868 dev->host_mem_descs = NULL; 1869 dev->nr_host_mem_descs = 0; 1870 } 1871 1872 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 1873 u32 chunk_size) 1874 { 1875 struct nvme_host_mem_buf_desc *descs; 1876 u32 max_entries, len; 1877 dma_addr_t descs_dma; 1878 int i = 0; 1879 void **bufs; 1880 u64 size, tmp; 1881 1882 tmp = (preferred + chunk_size - 1); 1883 do_div(tmp, chunk_size); 1884 max_entries = tmp; 1885 1886 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1887 max_entries = dev->ctrl.hmmaxd; 1888 1889 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 1890 &descs_dma, GFP_KERNEL); 1891 if (!descs) 1892 goto out; 1893 1894 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 1895 if (!bufs) 1896 goto out_free_descs; 1897 1898 for (size = 0; size < preferred && i < max_entries; size += len) { 1899 dma_addr_t dma_addr; 1900 1901 len = min_t(u64, chunk_size, preferred - size); 1902 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 1903 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1904 if (!bufs[i]) 1905 break; 1906 1907 descs[i].addr = cpu_to_le64(dma_addr); 1908 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 1909 i++; 1910 } 1911 1912 if (!size) 1913 goto out_free_bufs; 1914 1915 dev->nr_host_mem_descs = i; 1916 dev->host_mem_size = size; 1917 dev->host_mem_descs = descs; 1918 dev->host_mem_descs_dma = descs_dma; 1919 dev->host_mem_desc_bufs = bufs; 1920 return 0; 1921 1922 out_free_bufs: 1923 while (--i >= 0) { 1924 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 1925 1926 dma_free_attrs(dev->dev, size, bufs[i], 1927 le64_to_cpu(descs[i].addr), 1928 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1929 } 1930 1931 kfree(bufs); 1932 out_free_descs: 1933 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 1934 descs_dma); 1935 out: 1936 dev->host_mem_descs = NULL; 1937 return -ENOMEM; 1938 } 1939 1940 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 1941 { 1942 u32 chunk_size; 1943 1944 /* start big and work our way down */ 1945 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1946 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 1947 chunk_size /= 2) { 1948 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 1949 if (!min || dev->host_mem_size >= min) 1950 return 0; 1951 nvme_free_host_mem(dev); 1952 } 1953 } 1954 1955 return -ENOMEM; 1956 } 1957 1958 static int nvme_setup_host_mem(struct nvme_dev *dev) 1959 { 1960 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 1961 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 1962 u64 min = (u64)dev->ctrl.hmmin * 4096; 1963 u32 enable_bits = NVME_HOST_MEM_ENABLE; 1964 int ret; 1965 1966 preferred = min(preferred, max); 1967 if (min > max) { 1968 dev_warn(dev->ctrl.device, 1969 "min host memory (%lld MiB) above limit (%d MiB).\n", 1970 min >> ilog2(SZ_1M), max_host_mem_size_mb); 1971 nvme_free_host_mem(dev); 1972 return 0; 1973 } 1974 1975 /* 1976 * If we already have a buffer allocated check if we can reuse it. 1977 */ 1978 if (dev->host_mem_descs) { 1979 if (dev->host_mem_size >= min) 1980 enable_bits |= NVME_HOST_MEM_RETURN; 1981 else 1982 nvme_free_host_mem(dev); 1983 } 1984 1985 if (!dev->host_mem_descs) { 1986 if (nvme_alloc_host_mem(dev, min, preferred)) { 1987 dev_warn(dev->ctrl.device, 1988 "failed to allocate host memory buffer.\n"); 1989 return 0; /* controller must work without HMB */ 1990 } 1991 1992 dev_info(dev->ctrl.device, 1993 "allocated %lld MiB host memory buffer.\n", 1994 dev->host_mem_size >> ilog2(SZ_1M)); 1995 } 1996 1997 ret = nvme_set_host_mem(dev, enable_bits); 1998 if (ret) 1999 nvme_free_host_mem(dev); 2000 return ret; 2001 } 2002 2003 /* 2004 * nirqs is the number of interrupts available for write and read 2005 * queues. The core already reserved an interrupt for the admin queue. 2006 */ 2007 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 2008 { 2009 struct nvme_dev *dev = affd->priv; 2010 unsigned int nr_read_queues; 2011 2012 /* 2013 * If there is no interupt available for queues, ensure that 2014 * the default queue is set to 1. The affinity set size is 2015 * also set to one, but the irq core ignores it for this case. 2016 * 2017 * If only one interrupt is available or 'write_queue' == 0, combine 2018 * write and read queues. 2019 * 2020 * If 'write_queues' > 0, ensure it leaves room for at least one read 2021 * queue. 2022 */ 2023 if (!nrirqs) { 2024 nrirqs = 1; 2025 nr_read_queues = 0; 2026 } else if (nrirqs == 1 || !write_queues) { 2027 nr_read_queues = 0; 2028 } else if (write_queues >= nrirqs) { 2029 nr_read_queues = 1; 2030 } else { 2031 nr_read_queues = nrirqs - write_queues; 2032 } 2033 2034 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2035 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2036 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2037 affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2038 affd->nr_sets = nr_read_queues ? 2 : 1; 2039 } 2040 2041 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 2042 { 2043 struct pci_dev *pdev = to_pci_dev(dev->dev); 2044 struct irq_affinity affd = { 2045 .pre_vectors = 1, 2046 .calc_sets = nvme_calc_irq_sets, 2047 .priv = dev, 2048 }; 2049 unsigned int irq_queues, this_p_queues; 2050 2051 /* 2052 * Poll queues don't need interrupts, but we need at least one IO 2053 * queue left over for non-polled IO. 2054 */ 2055 this_p_queues = poll_queues; 2056 if (this_p_queues >= nr_io_queues) { 2057 this_p_queues = nr_io_queues - 1; 2058 irq_queues = 1; 2059 } else { 2060 irq_queues = nr_io_queues - this_p_queues + 1; 2061 } 2062 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 2063 2064 /* Initialize for the single interrupt case */ 2065 dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2066 dev->io_queues[HCTX_TYPE_READ] = 0; 2067 2068 /* 2069 * Some Apple controllers require all queues to use the 2070 * first vector. 2071 */ 2072 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR) 2073 irq_queues = 1; 2074 2075 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 2076 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 2077 } 2078 2079 static void nvme_disable_io_queues(struct nvme_dev *dev) 2080 { 2081 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 2082 __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 2083 } 2084 2085 static int nvme_setup_io_queues(struct nvme_dev *dev) 2086 { 2087 struct nvme_queue *adminq = &dev->queues[0]; 2088 struct pci_dev *pdev = to_pci_dev(dev->dev); 2089 int result, nr_io_queues; 2090 unsigned long size; 2091 2092 nr_io_queues = max_io_queues(); 2093 2094 /* 2095 * If tags are shared with admin queue (Apple bug), then 2096 * make sure we only use one IO queue. 2097 */ 2098 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2099 nr_io_queues = 1; 2100 2101 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 2102 if (result < 0) 2103 return result; 2104 2105 if (nr_io_queues == 0) 2106 return 0; 2107 2108 clear_bit(NVMEQ_ENABLED, &adminq->flags); 2109 2110 if (dev->cmb_use_sqes) { 2111 result = nvme_cmb_qdepth(dev, nr_io_queues, 2112 sizeof(struct nvme_command)); 2113 if (result > 0) 2114 dev->q_depth = result; 2115 else 2116 dev->cmb_use_sqes = false; 2117 } 2118 2119 do { 2120 size = db_bar_size(dev, nr_io_queues); 2121 result = nvme_remap_bar(dev, size); 2122 if (!result) 2123 break; 2124 if (!--nr_io_queues) 2125 return -ENOMEM; 2126 } while (1); 2127 adminq->q_db = dev->dbs; 2128 2129 retry: 2130 /* Deregister the admin queue's interrupt */ 2131 pci_free_irq(pdev, 0, adminq); 2132 2133 /* 2134 * If we enable msix early due to not intx, disable it again before 2135 * setting up the full range we need. 2136 */ 2137 pci_free_irq_vectors(pdev); 2138 2139 result = nvme_setup_irqs(dev, nr_io_queues); 2140 if (result <= 0) 2141 return -EIO; 2142 2143 dev->num_vecs = result; 2144 result = max(result - 1, 1); 2145 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 2146 2147 /* 2148 * Should investigate if there's a performance win from allocating 2149 * more queues than interrupt vectors; it might allow the submission 2150 * path to scale better, even if the receive path is limited by the 2151 * number of interrupts. 2152 */ 2153 result = queue_request_irq(adminq); 2154 if (result) 2155 return result; 2156 set_bit(NVMEQ_ENABLED, &adminq->flags); 2157 2158 result = nvme_create_io_queues(dev); 2159 if (result || dev->online_queues < 2) 2160 return result; 2161 2162 if (dev->online_queues - 1 < dev->max_qid) { 2163 nr_io_queues = dev->online_queues - 1; 2164 nvme_disable_io_queues(dev); 2165 nvme_suspend_io_queues(dev); 2166 goto retry; 2167 } 2168 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2169 dev->io_queues[HCTX_TYPE_DEFAULT], 2170 dev->io_queues[HCTX_TYPE_READ], 2171 dev->io_queues[HCTX_TYPE_POLL]); 2172 return 0; 2173 } 2174 2175 static void nvme_del_queue_end(struct request *req, blk_status_t error) 2176 { 2177 struct nvme_queue *nvmeq = req->end_io_data; 2178 2179 blk_mq_free_request(req); 2180 complete(&nvmeq->delete_done); 2181 } 2182 2183 static void nvme_del_cq_end(struct request *req, blk_status_t error) 2184 { 2185 struct nvme_queue *nvmeq = req->end_io_data; 2186 2187 if (error) 2188 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2189 2190 nvme_del_queue_end(req, error); 2191 } 2192 2193 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2194 { 2195 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2196 struct request *req; 2197 struct nvme_command cmd; 2198 2199 memset(&cmd, 0, sizeof(cmd)); 2200 cmd.delete_queue.opcode = opcode; 2201 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2202 2203 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2204 if (IS_ERR(req)) 2205 return PTR_ERR(req); 2206 2207 req->timeout = ADMIN_TIMEOUT; 2208 req->end_io_data = nvmeq; 2209 2210 init_completion(&nvmeq->delete_done); 2211 blk_execute_rq_nowait(q, NULL, req, false, 2212 opcode == nvme_admin_delete_cq ? 2213 nvme_del_cq_end : nvme_del_queue_end); 2214 return 0; 2215 } 2216 2217 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2218 { 2219 int nr_queues = dev->online_queues - 1, sent = 0; 2220 unsigned long timeout; 2221 2222 retry: 2223 timeout = ADMIN_TIMEOUT; 2224 while (nr_queues > 0) { 2225 if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2226 break; 2227 nr_queues--; 2228 sent++; 2229 } 2230 while (sent) { 2231 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2232 2233 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 2234 timeout); 2235 if (timeout == 0) 2236 return false; 2237 2238 /* handle any remaining CQEs */ 2239 if (opcode == nvme_admin_delete_cq && 2240 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags)) 2241 nvme_poll_irqdisable(nvmeq, -1); 2242 2243 sent--; 2244 if (nr_queues) 2245 goto retry; 2246 } 2247 return true; 2248 } 2249 2250 static void nvme_dev_add(struct nvme_dev *dev) 2251 { 2252 int ret; 2253 2254 if (!dev->ctrl.tagset) { 2255 dev->tagset.ops = &nvme_mq_ops; 2256 dev->tagset.nr_hw_queues = dev->online_queues - 1; 2257 dev->tagset.nr_maps = 2; /* default + read */ 2258 if (dev->io_queues[HCTX_TYPE_POLL]) 2259 dev->tagset.nr_maps++; 2260 dev->tagset.timeout = NVME_IO_TIMEOUT; 2261 dev->tagset.numa_node = dev_to_node(dev->dev); 2262 dev->tagset.queue_depth = 2263 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2264 dev->tagset.cmd_size = sizeof(struct nvme_iod); 2265 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 2266 dev->tagset.driver_data = dev; 2267 2268 /* 2269 * Some Apple controllers requires tags to be unique 2270 * across admin and IO queue, so reserve the first 32 2271 * tags of the IO queue. 2272 */ 2273 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2274 dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2275 2276 ret = blk_mq_alloc_tag_set(&dev->tagset); 2277 if (ret) { 2278 dev_warn(dev->ctrl.device, 2279 "IO queues tagset allocation failed %d\n", ret); 2280 return; 2281 } 2282 dev->ctrl.tagset = &dev->tagset; 2283 } else { 2284 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2285 2286 /* Free previously allocated queues that are no longer usable */ 2287 nvme_free_queues(dev, dev->online_queues); 2288 } 2289 2290 nvme_dbbuf_set(dev); 2291 } 2292 2293 static int nvme_pci_enable(struct nvme_dev *dev) 2294 { 2295 int result = -ENOMEM; 2296 struct pci_dev *pdev = to_pci_dev(dev->dev); 2297 2298 if (pci_enable_device_mem(pdev)) 2299 return result; 2300 2301 pci_set_master(pdev); 2302 2303 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64))) 2304 goto disable; 2305 2306 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2307 result = -ENODEV; 2308 goto disable; 2309 } 2310 2311 /* 2312 * Some devices and/or platforms don't advertise or work with INTx 2313 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2314 * adjust this later. 2315 */ 2316 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2317 if (result < 0) 2318 return result; 2319 2320 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2321 2322 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2323 io_queue_depth); 2324 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 2325 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2326 dev->dbs = dev->bar + 4096; 2327 2328 /* 2329 * Some Apple controllers require a non-standard SQE size. 2330 * Interestingly they also seem to ignore the CC:IOSQES register 2331 * so we don't bother updating it here. 2332 */ 2333 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 2334 dev->io_sqes = 7; 2335 else 2336 dev->io_sqes = NVME_NVM_IOSQES; 2337 2338 /* 2339 * Temporary fix for the Apple controller found in the MacBook8,1 and 2340 * some MacBook7,1 to avoid controller resets and data loss. 2341 */ 2342 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 2343 dev->q_depth = 2; 2344 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 2345 "set queue depth=%u to work around controller resets\n", 2346 dev->q_depth); 2347 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2348 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2349 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2350 dev->q_depth = 64; 2351 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2352 "set queue depth=%u\n", dev->q_depth); 2353 } 2354 2355 /* 2356 * Controllers with the shared tags quirk need the IO queue to be 2357 * big enough so that we get 32 tags for the admin queue 2358 */ 2359 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2360 (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2361 dev->q_depth = NVME_AQ_DEPTH + 2; 2362 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2363 dev->q_depth); 2364 } 2365 2366 2367 nvme_map_cmb(dev); 2368 2369 pci_enable_pcie_error_reporting(pdev); 2370 pci_save_state(pdev); 2371 return 0; 2372 2373 disable: 2374 pci_disable_device(pdev); 2375 return result; 2376 } 2377 2378 static void nvme_dev_unmap(struct nvme_dev *dev) 2379 { 2380 if (dev->bar) 2381 iounmap(dev->bar); 2382 pci_release_mem_regions(to_pci_dev(dev->dev)); 2383 } 2384 2385 static void nvme_pci_disable(struct nvme_dev *dev) 2386 { 2387 struct pci_dev *pdev = to_pci_dev(dev->dev); 2388 2389 pci_free_irq_vectors(pdev); 2390 2391 if (pci_is_enabled(pdev)) { 2392 pci_disable_pcie_error_reporting(pdev); 2393 pci_disable_device(pdev); 2394 } 2395 } 2396 2397 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2398 { 2399 bool dead = true, freeze = false; 2400 struct pci_dev *pdev = to_pci_dev(dev->dev); 2401 2402 mutex_lock(&dev->shutdown_lock); 2403 if (pci_is_enabled(pdev)) { 2404 u32 csts = readl(dev->bar + NVME_REG_CSTS); 2405 2406 if (dev->ctrl.state == NVME_CTRL_LIVE || 2407 dev->ctrl.state == NVME_CTRL_RESETTING) { 2408 freeze = true; 2409 nvme_start_freeze(&dev->ctrl); 2410 } 2411 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2412 pdev->error_state != pci_channel_io_normal); 2413 } 2414 2415 /* 2416 * Give the controller a chance to complete all entered requests if 2417 * doing a safe shutdown. 2418 */ 2419 if (!dead && shutdown && freeze) 2420 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2421 2422 nvme_stop_queues(&dev->ctrl); 2423 2424 if (!dead && dev->ctrl.queue_count > 0) { 2425 nvme_disable_io_queues(dev); 2426 nvme_disable_admin_queue(dev, shutdown); 2427 } 2428 nvme_suspend_io_queues(dev); 2429 nvme_suspend_queue(&dev->queues[0]); 2430 nvme_pci_disable(dev); 2431 2432 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2433 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2434 blk_mq_tagset_wait_completed_request(&dev->tagset); 2435 blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2436 2437 /* 2438 * The driver will not be starting up queues again if shutting down so 2439 * must flush all entered requests to their failed completion to avoid 2440 * deadlocking blk-mq hot-cpu notifier. 2441 */ 2442 if (shutdown) { 2443 nvme_start_queues(&dev->ctrl); 2444 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2445 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2446 } 2447 mutex_unlock(&dev->shutdown_lock); 2448 } 2449 2450 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2451 { 2452 if (!nvme_wait_reset(&dev->ctrl)) 2453 return -EBUSY; 2454 nvme_dev_disable(dev, shutdown); 2455 return 0; 2456 } 2457 2458 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2459 { 2460 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2461 PAGE_SIZE, PAGE_SIZE, 0); 2462 if (!dev->prp_page_pool) 2463 return -ENOMEM; 2464 2465 /* Optimisation for I/Os between 4k and 128k */ 2466 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2467 256, 256, 0); 2468 if (!dev->prp_small_pool) { 2469 dma_pool_destroy(dev->prp_page_pool); 2470 return -ENOMEM; 2471 } 2472 return 0; 2473 } 2474 2475 static void nvme_release_prp_pools(struct nvme_dev *dev) 2476 { 2477 dma_pool_destroy(dev->prp_page_pool); 2478 dma_pool_destroy(dev->prp_small_pool); 2479 } 2480 2481 static void nvme_free_tagset(struct nvme_dev *dev) 2482 { 2483 if (dev->tagset.tags) 2484 blk_mq_free_tag_set(&dev->tagset); 2485 dev->ctrl.tagset = NULL; 2486 } 2487 2488 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2489 { 2490 struct nvme_dev *dev = to_nvme_dev(ctrl); 2491 2492 nvme_dbbuf_dma_free(dev); 2493 put_device(dev->dev); 2494 nvme_free_tagset(dev); 2495 if (dev->ctrl.admin_q) 2496 blk_put_queue(dev->ctrl.admin_q); 2497 kfree(dev->queues); 2498 free_opal_dev(dev->ctrl.opal_dev); 2499 mempool_destroy(dev->iod_mempool); 2500 kfree(dev); 2501 } 2502 2503 static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2504 { 2505 /* 2506 * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2507 * may be holding this pci_dev's device lock. 2508 */ 2509 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2510 nvme_get_ctrl(&dev->ctrl); 2511 nvme_dev_disable(dev, false); 2512 nvme_kill_queues(&dev->ctrl); 2513 if (!queue_work(nvme_wq, &dev->remove_work)) 2514 nvme_put_ctrl(&dev->ctrl); 2515 } 2516 2517 static void nvme_reset_work(struct work_struct *work) 2518 { 2519 struct nvme_dev *dev = 2520 container_of(work, struct nvme_dev, ctrl.reset_work); 2521 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2522 int result; 2523 2524 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) { 2525 result = -ENODEV; 2526 goto out; 2527 } 2528 2529 /* 2530 * If we're called to reset a live controller first shut it down before 2531 * moving on. 2532 */ 2533 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2534 nvme_dev_disable(dev, false); 2535 nvme_sync_queues(&dev->ctrl); 2536 2537 mutex_lock(&dev->shutdown_lock); 2538 result = nvme_pci_enable(dev); 2539 if (result) 2540 goto out_unlock; 2541 2542 result = nvme_pci_configure_admin_queue(dev); 2543 if (result) 2544 goto out_unlock; 2545 2546 result = nvme_alloc_admin_tags(dev); 2547 if (result) 2548 goto out_unlock; 2549 2550 /* 2551 * Limit the max command size to prevent iod->sg allocations going 2552 * over a single page. 2553 */ 2554 dev->ctrl.max_hw_sectors = min_t(u32, 2555 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2556 dev->ctrl.max_segments = NVME_MAX_SEGS; 2557 2558 /* 2559 * Don't limit the IOMMU merged segment size. 2560 */ 2561 dma_set_max_seg_size(dev->dev, 0xffffffff); 2562 2563 mutex_unlock(&dev->shutdown_lock); 2564 2565 /* 2566 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2567 * initializing procedure here. 2568 */ 2569 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2570 dev_warn(dev->ctrl.device, 2571 "failed to mark controller CONNECTING\n"); 2572 result = -EBUSY; 2573 goto out; 2574 } 2575 2576 result = nvme_init_identify(&dev->ctrl); 2577 if (result) 2578 goto out; 2579 2580 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2581 if (!dev->ctrl.opal_dev) 2582 dev->ctrl.opal_dev = 2583 init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2584 else if (was_suspend) 2585 opal_unlock_from_suspend(dev->ctrl.opal_dev); 2586 } else { 2587 free_opal_dev(dev->ctrl.opal_dev); 2588 dev->ctrl.opal_dev = NULL; 2589 } 2590 2591 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2592 result = nvme_dbbuf_dma_alloc(dev); 2593 if (result) 2594 dev_warn(dev->dev, 2595 "unable to allocate dma for dbbuf\n"); 2596 } 2597 2598 if (dev->ctrl.hmpre) { 2599 result = nvme_setup_host_mem(dev); 2600 if (result < 0) 2601 goto out; 2602 } 2603 2604 result = nvme_setup_io_queues(dev); 2605 if (result) 2606 goto out; 2607 2608 /* 2609 * Keep the controller around but remove all namespaces if we don't have 2610 * any working I/O queue. 2611 */ 2612 if (dev->online_queues < 2) { 2613 dev_warn(dev->ctrl.device, "IO queues not created\n"); 2614 nvme_kill_queues(&dev->ctrl); 2615 nvme_remove_namespaces(&dev->ctrl); 2616 nvme_free_tagset(dev); 2617 } else { 2618 nvme_start_queues(&dev->ctrl); 2619 nvme_wait_freeze(&dev->ctrl); 2620 nvme_dev_add(dev); 2621 nvme_unfreeze(&dev->ctrl); 2622 } 2623 2624 /* 2625 * If only admin queue live, keep it to do further investigation or 2626 * recovery. 2627 */ 2628 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 2629 dev_warn(dev->ctrl.device, 2630 "failed to mark controller live state\n"); 2631 result = -ENODEV; 2632 goto out; 2633 } 2634 2635 nvme_start_ctrl(&dev->ctrl); 2636 return; 2637 2638 out_unlock: 2639 mutex_unlock(&dev->shutdown_lock); 2640 out: 2641 if (result) 2642 dev_warn(dev->ctrl.device, 2643 "Removing after probe failure status: %d\n", result); 2644 nvme_remove_dead_ctrl(dev); 2645 } 2646 2647 static void nvme_remove_dead_ctrl_work(struct work_struct *work) 2648 { 2649 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 2650 struct pci_dev *pdev = to_pci_dev(dev->dev); 2651 2652 if (pci_get_drvdata(pdev)) 2653 device_release_driver(&pdev->dev); 2654 nvme_put_ctrl(&dev->ctrl); 2655 } 2656 2657 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2658 { 2659 *val = readl(to_nvme_dev(ctrl)->bar + off); 2660 return 0; 2661 } 2662 2663 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2664 { 2665 writel(val, to_nvme_dev(ctrl)->bar + off); 2666 return 0; 2667 } 2668 2669 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2670 { 2671 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 2672 return 0; 2673 } 2674 2675 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2676 { 2677 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2678 2679 return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 2680 } 2681 2682 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2683 .name = "pcie", 2684 .module = THIS_MODULE, 2685 .flags = NVME_F_METADATA_SUPPORTED | 2686 NVME_F_PCI_P2PDMA, 2687 .reg_read32 = nvme_pci_reg_read32, 2688 .reg_write32 = nvme_pci_reg_write32, 2689 .reg_read64 = nvme_pci_reg_read64, 2690 .free_ctrl = nvme_pci_free_ctrl, 2691 .submit_async_event = nvme_pci_submit_async_event, 2692 .get_address = nvme_pci_get_address, 2693 }; 2694 2695 static int nvme_dev_map(struct nvme_dev *dev) 2696 { 2697 struct pci_dev *pdev = to_pci_dev(dev->dev); 2698 2699 if (pci_request_mem_regions(pdev, "nvme")) 2700 return -ENODEV; 2701 2702 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2703 goto release; 2704 2705 return 0; 2706 release: 2707 pci_release_mem_regions(pdev); 2708 return -ENODEV; 2709 } 2710 2711 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2712 { 2713 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2714 /* 2715 * Several Samsung devices seem to drop off the PCIe bus 2716 * randomly when APST is on and uses the deepest sleep state. 2717 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2718 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2719 * 950 PRO 256GB", but it seems to be restricted to two Dell 2720 * laptops. 2721 */ 2722 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2723 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2724 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2725 return NVME_QUIRK_NO_DEEPEST_PS; 2726 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 2727 /* 2728 * Samsung SSD 960 EVO drops off the PCIe bus after system 2729 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2730 * within few minutes after bootup on a Coffee Lake board - 2731 * ASUS PRIME Z370-A 2732 */ 2733 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2734 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2735 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 2736 return NVME_QUIRK_NO_APST; 2737 } 2738 2739 return 0; 2740 } 2741 2742 static void nvme_async_probe(void *data, async_cookie_t cookie) 2743 { 2744 struct nvme_dev *dev = data; 2745 2746 flush_work(&dev->ctrl.reset_work); 2747 flush_work(&dev->ctrl.scan_work); 2748 nvme_put_ctrl(&dev->ctrl); 2749 } 2750 2751 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2752 { 2753 int node, result = -ENOMEM; 2754 struct nvme_dev *dev; 2755 unsigned long quirks = id->driver_data; 2756 size_t alloc_size; 2757 2758 node = dev_to_node(&pdev->dev); 2759 if (node == NUMA_NO_NODE) 2760 set_dev_node(&pdev->dev, first_memory_node); 2761 2762 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2763 if (!dev) 2764 return -ENOMEM; 2765 2766 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 2767 GFP_KERNEL, node); 2768 if (!dev->queues) 2769 goto free; 2770 2771 dev->dev = get_device(&pdev->dev); 2772 pci_set_drvdata(pdev, dev); 2773 2774 result = nvme_dev_map(dev); 2775 if (result) 2776 goto put_pci; 2777 2778 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 2779 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 2780 mutex_init(&dev->shutdown_lock); 2781 2782 result = nvme_setup_prp_pools(dev); 2783 if (result) 2784 goto unmap; 2785 2786 quirks |= check_vendor_combination_bug(pdev); 2787 2788 /* 2789 * Double check that our mempool alloc size will cover the biggest 2790 * command we support. 2791 */ 2792 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2793 NVME_MAX_SEGS, true); 2794 WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2795 2796 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2797 mempool_kfree, 2798 (void *) alloc_size, 2799 GFP_KERNEL, node); 2800 if (!dev->iod_mempool) { 2801 result = -ENOMEM; 2802 goto release_pools; 2803 } 2804 2805 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2806 quirks); 2807 if (result) 2808 goto release_mempool; 2809 2810 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 2811 2812 nvme_reset_ctrl(&dev->ctrl); 2813 nvme_get_ctrl(&dev->ctrl); 2814 async_schedule(nvme_async_probe, dev); 2815 2816 return 0; 2817 2818 release_mempool: 2819 mempool_destroy(dev->iod_mempool); 2820 release_pools: 2821 nvme_release_prp_pools(dev); 2822 unmap: 2823 nvme_dev_unmap(dev); 2824 put_pci: 2825 put_device(dev->dev); 2826 free: 2827 kfree(dev->queues); 2828 kfree(dev); 2829 return result; 2830 } 2831 2832 static void nvme_reset_prepare(struct pci_dev *pdev) 2833 { 2834 struct nvme_dev *dev = pci_get_drvdata(pdev); 2835 2836 /* 2837 * We don't need to check the return value from waiting for the reset 2838 * state as pci_dev device lock is held, making it impossible to race 2839 * with ->remove(). 2840 */ 2841 nvme_disable_prepare_reset(dev, false); 2842 nvme_sync_queues(&dev->ctrl); 2843 } 2844 2845 static void nvme_reset_done(struct pci_dev *pdev) 2846 { 2847 struct nvme_dev *dev = pci_get_drvdata(pdev); 2848 2849 if (!nvme_try_sched_reset(&dev->ctrl)) 2850 flush_work(&dev->ctrl.reset_work); 2851 } 2852 2853 static void nvme_shutdown(struct pci_dev *pdev) 2854 { 2855 struct nvme_dev *dev = pci_get_drvdata(pdev); 2856 nvme_disable_prepare_reset(dev, true); 2857 } 2858 2859 /* 2860 * The driver's remove may be called on a device in a partially initialized 2861 * state. This function must not have any dependencies on the device state in 2862 * order to proceed. 2863 */ 2864 static void nvme_remove(struct pci_dev *pdev) 2865 { 2866 struct nvme_dev *dev = pci_get_drvdata(pdev); 2867 2868 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2869 pci_set_drvdata(pdev, NULL); 2870 2871 if (!pci_device_is_present(pdev)) { 2872 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 2873 nvme_dev_disable(dev, true); 2874 nvme_dev_remove_admin(dev); 2875 } 2876 2877 flush_work(&dev->ctrl.reset_work); 2878 nvme_stop_ctrl(&dev->ctrl); 2879 nvme_remove_namespaces(&dev->ctrl); 2880 nvme_dev_disable(dev, true); 2881 nvme_release_cmb(dev); 2882 nvme_free_host_mem(dev); 2883 nvme_dev_remove_admin(dev); 2884 nvme_free_queues(dev, 0); 2885 nvme_uninit_ctrl(&dev->ctrl); 2886 nvme_release_prp_pools(dev); 2887 nvme_dev_unmap(dev); 2888 nvme_put_ctrl(&dev->ctrl); 2889 } 2890 2891 #ifdef CONFIG_PM_SLEEP 2892 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 2893 { 2894 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 2895 } 2896 2897 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 2898 { 2899 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 2900 } 2901 2902 static int nvme_resume(struct device *dev) 2903 { 2904 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2905 struct nvme_ctrl *ctrl = &ndev->ctrl; 2906 2907 if (ndev->last_ps == U32_MAX || 2908 nvme_set_power_state(ctrl, ndev->last_ps) != 0) 2909 return nvme_try_sched_reset(&ndev->ctrl); 2910 return 0; 2911 } 2912 2913 static int nvme_suspend(struct device *dev) 2914 { 2915 struct pci_dev *pdev = to_pci_dev(dev); 2916 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2917 struct nvme_ctrl *ctrl = &ndev->ctrl; 2918 int ret = -EBUSY; 2919 2920 ndev->last_ps = U32_MAX; 2921 2922 /* 2923 * The platform does not remove power for a kernel managed suspend so 2924 * use host managed nvme power settings for lowest idle power if 2925 * possible. This should have quicker resume latency than a full device 2926 * shutdown. But if the firmware is involved after the suspend or the 2927 * device does not support any non-default power states, shut down the 2928 * device fully. 2929 * 2930 * If ASPM is not enabled for the device, shut down the device and allow 2931 * the PCI bus layer to put it into D3 in order to take the PCIe link 2932 * down, so as to allow the platform to achieve its minimum low-power 2933 * state (which may not be possible if the link is up). 2934 */ 2935 if (pm_suspend_via_firmware() || !ctrl->npss || 2936 !pcie_aspm_enabled(pdev) || 2937 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 2938 return nvme_disable_prepare_reset(ndev, true); 2939 2940 nvme_start_freeze(ctrl); 2941 nvme_wait_freeze(ctrl); 2942 nvme_sync_queues(ctrl); 2943 2944 if (ctrl->state != NVME_CTRL_LIVE) 2945 goto unfreeze; 2946 2947 ret = nvme_get_power_state(ctrl, &ndev->last_ps); 2948 if (ret < 0) 2949 goto unfreeze; 2950 2951 /* 2952 * A saved state prevents pci pm from generically controlling the 2953 * device's power. If we're using protocol specific settings, we don't 2954 * want pci interfering. 2955 */ 2956 pci_save_state(pdev); 2957 2958 ret = nvme_set_power_state(ctrl, ctrl->npss); 2959 if (ret < 0) 2960 goto unfreeze; 2961 2962 if (ret) { 2963 /* discard the saved state */ 2964 pci_load_saved_state(pdev, NULL); 2965 2966 /* 2967 * Clearing npss forces a controller reset on resume. The 2968 * correct value will be rediscovered then. 2969 */ 2970 ret = nvme_disable_prepare_reset(ndev, true); 2971 ctrl->npss = 0; 2972 } 2973 unfreeze: 2974 nvme_unfreeze(ctrl); 2975 return ret; 2976 } 2977 2978 static int nvme_simple_suspend(struct device *dev) 2979 { 2980 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2981 return nvme_disable_prepare_reset(ndev, true); 2982 } 2983 2984 static int nvme_simple_resume(struct device *dev) 2985 { 2986 struct pci_dev *pdev = to_pci_dev(dev); 2987 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2988 2989 return nvme_try_sched_reset(&ndev->ctrl); 2990 } 2991 2992 static const struct dev_pm_ops nvme_dev_pm_ops = { 2993 .suspend = nvme_suspend, 2994 .resume = nvme_resume, 2995 .freeze = nvme_simple_suspend, 2996 .thaw = nvme_simple_resume, 2997 .poweroff = nvme_simple_suspend, 2998 .restore = nvme_simple_resume, 2999 }; 3000 #endif /* CONFIG_PM_SLEEP */ 3001 3002 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3003 pci_channel_state_t state) 3004 { 3005 struct nvme_dev *dev = pci_get_drvdata(pdev); 3006 3007 /* 3008 * A frozen channel requires a reset. When detected, this method will 3009 * shutdown the controller to quiesce. The controller will be restarted 3010 * after the slot reset through driver's slot_reset callback. 3011 */ 3012 switch (state) { 3013 case pci_channel_io_normal: 3014 return PCI_ERS_RESULT_CAN_RECOVER; 3015 case pci_channel_io_frozen: 3016 dev_warn(dev->ctrl.device, 3017 "frozen state error detected, reset controller\n"); 3018 nvme_dev_disable(dev, false); 3019 return PCI_ERS_RESULT_NEED_RESET; 3020 case pci_channel_io_perm_failure: 3021 dev_warn(dev->ctrl.device, 3022 "failure state error detected, request disconnect\n"); 3023 return PCI_ERS_RESULT_DISCONNECT; 3024 } 3025 return PCI_ERS_RESULT_NEED_RESET; 3026 } 3027 3028 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3029 { 3030 struct nvme_dev *dev = pci_get_drvdata(pdev); 3031 3032 dev_info(dev->ctrl.device, "restart after slot reset\n"); 3033 pci_restore_state(pdev); 3034 nvme_reset_ctrl(&dev->ctrl); 3035 return PCI_ERS_RESULT_RECOVERED; 3036 } 3037 3038 static void nvme_error_resume(struct pci_dev *pdev) 3039 { 3040 struct nvme_dev *dev = pci_get_drvdata(pdev); 3041 3042 flush_work(&dev->ctrl.reset_work); 3043 } 3044 3045 static const struct pci_error_handlers nvme_err_handler = { 3046 .error_detected = nvme_error_detected, 3047 .slot_reset = nvme_slot_reset, 3048 .resume = nvme_error_resume, 3049 .reset_prepare = nvme_reset_prepare, 3050 .reset_done = nvme_reset_done, 3051 }; 3052 3053 static const struct pci_device_id nvme_id_table[] = { 3054 { PCI_VDEVICE(INTEL, 0x0953), 3055 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3056 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3057 { PCI_VDEVICE(INTEL, 0x0a53), 3058 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3059 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3060 { PCI_VDEVICE(INTEL, 0x0a54), 3061 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3062 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3063 { PCI_VDEVICE(INTEL, 0x0a55), 3064 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3065 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3066 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 3067 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3068 NVME_QUIRK_MEDIUM_PRIO_SQ | 3069 NVME_QUIRK_NO_TEMP_THRESH_CHANGE }, 3070 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 3071 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3072 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 3073 .driver_data = NVME_QUIRK_IDENTIFY_CNS | 3074 NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3075 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 3076 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3077 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 3078 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3079 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 3080 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3081 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3082 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3083 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3084 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3085 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3086 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3087 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 3088 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3089 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 3090 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3091 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3092 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3093 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 3094 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3095 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3096 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3097 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3098 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3099 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 3100 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 3101 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 3102 .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3103 NVME_QUIRK_128_BYTES_SQES | 3104 NVME_QUIRK_SHARED_TAGS }, 3105 { 0, } 3106 }; 3107 MODULE_DEVICE_TABLE(pci, nvme_id_table); 3108 3109 static struct pci_driver nvme_driver = { 3110 .name = "nvme", 3111 .id_table = nvme_id_table, 3112 .probe = nvme_probe, 3113 .remove = nvme_remove, 3114 .shutdown = nvme_shutdown, 3115 #ifdef CONFIG_PM_SLEEP 3116 .driver = { 3117 .pm = &nvme_dev_pm_ops, 3118 }, 3119 #endif 3120 .sriov_configure = pci_sriov_configure_simple, 3121 .err_handler = &nvme_err_handler, 3122 }; 3123 3124 static int __init nvme_init(void) 3125 { 3126 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 3127 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 3128 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3129 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3130 3131 write_queues = min(write_queues, num_possible_cpus()); 3132 poll_queues = min(poll_queues, num_possible_cpus()); 3133 return pci_register_driver(&nvme_driver); 3134 } 3135 3136 static void __exit nvme_exit(void) 3137 { 3138 pci_unregister_driver(&nvme_driver); 3139 flush_workqueue(nvme_wq); 3140 } 3141 3142 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 3143 MODULE_LICENSE("GPL"); 3144 MODULE_VERSION("1.0"); 3145 module_init(nvme_init); 3146 module_exit(nvme_exit); 3147