1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ASM_POWERPC_CPUTABLE_H 3 #define __ASM_POWERPC_CPUTABLE_H 4 5 6 #include <linux/types.h> 7 #include <uapi/asm/cputable.h> 8 #include <asm/asm-const.h> 9 10 #ifndef __ASSEMBLY__ 11 12 /* This structure can grow, it's real size is used by head.S code 13 * via the mkdefs mechanism. 14 */ 15 struct cpu_spec; 16 17 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec); 18 typedef void (*cpu_restore_t)(void); 19 20 enum powerpc_oprofile_type { 21 PPC_OPROFILE_INVALID = 0, 22 PPC_OPROFILE_RS64 = 1, 23 PPC_OPROFILE_POWER4 = 2, 24 PPC_OPROFILE_G4 = 3, 25 PPC_OPROFILE_FSL_EMB = 4, 26 PPC_OPROFILE_CELL = 5, 27 PPC_OPROFILE_PA6T = 6, 28 }; 29 30 enum powerpc_pmc_type { 31 PPC_PMC_DEFAULT = 0, 32 PPC_PMC_IBM = 1, 33 PPC_PMC_PA6T = 2, 34 PPC_PMC_G4 = 3, 35 }; 36 37 struct pt_regs; 38 39 extern int machine_check_generic(struct pt_regs *regs); 40 extern int machine_check_4xx(struct pt_regs *regs); 41 extern int machine_check_440A(struct pt_regs *regs); 42 extern int machine_check_e500mc(struct pt_regs *regs); 43 extern int machine_check_e500(struct pt_regs *regs); 44 extern int machine_check_e200(struct pt_regs *regs); 45 extern int machine_check_47x(struct pt_regs *regs); 46 int machine_check_8xx(struct pt_regs *regs); 47 int machine_check_83xx(struct pt_regs *regs); 48 49 extern void cpu_down_flush_e500v2(void); 50 extern void cpu_down_flush_e500mc(void); 51 extern void cpu_down_flush_e5500(void); 52 extern void cpu_down_flush_e6500(void); 53 54 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */ 55 struct cpu_spec { 56 /* CPU is matched via (PVR & pvr_mask) == pvr_value */ 57 unsigned int pvr_mask; 58 unsigned int pvr_value; 59 60 char *cpu_name; 61 unsigned long cpu_features; /* Kernel features */ 62 unsigned int cpu_user_features; /* Userland features */ 63 unsigned int cpu_user_features2; /* Userland features v2 */ 64 unsigned int mmu_features; /* MMU features */ 65 66 /* cache line sizes */ 67 unsigned int icache_bsize; 68 unsigned int dcache_bsize; 69 70 /* flush caches inside the current cpu */ 71 void (*cpu_down_flush)(void); 72 73 /* number of performance monitor counters */ 74 unsigned int num_pmcs; 75 enum powerpc_pmc_type pmc_type; 76 77 /* this is called to initialize various CPU bits like L1 cache, 78 * BHT, SPD, etc... from head.S before branching to identify_machine 79 */ 80 cpu_setup_t cpu_setup; 81 /* Used to restore cpu setup on secondary processors and at resume */ 82 cpu_restore_t cpu_restore; 83 84 /* Used by oprofile userspace to select the right counters */ 85 char *oprofile_cpu_type; 86 87 /* Processor specific oprofile operations */ 88 enum powerpc_oprofile_type oprofile_type; 89 90 /* Bit locations inside the mmcra change */ 91 unsigned long oprofile_mmcra_sihv; 92 unsigned long oprofile_mmcra_sipr; 93 94 /* Bits to clear during an oprofile exception */ 95 unsigned long oprofile_mmcra_clear; 96 97 /* Name of processor class, for the ELF AT_PLATFORM entry */ 98 char *platform; 99 100 /* Processor specific machine check handling. Return negative 101 * if the error is fatal, 1 if it was fully recovered and 0 to 102 * pass up (not CPU originated) */ 103 int (*machine_check)(struct pt_regs *regs); 104 105 /* 106 * Processor specific early machine check handler which is 107 * called in real mode to handle SLB and TLB errors. 108 */ 109 long (*machine_check_early)(struct pt_regs *regs); 110 }; 111 112 extern struct cpu_spec *cur_cpu_spec; 113 114 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup; 115 116 extern void set_cur_cpu_spec(struct cpu_spec *s); 117 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr); 118 extern void identify_cpu_name(unsigned int pvr); 119 extern void do_feature_fixups(unsigned long value, void *fixup_start, 120 void *fixup_end); 121 122 extern const char *powerpc_base_platform; 123 124 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS 125 extern void cpu_feature_keys_init(void); 126 #else 127 static inline void cpu_feature_keys_init(void) { } 128 #endif 129 130 #endif /* __ASSEMBLY__ */ 131 132 /* CPU kernel features */ 133 134 /* Definitions for features that we have on both 32-bit and 64-bit chips */ 135 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001) 136 #define CPU_FTR_ALTIVEC ASM_CONST(0x00000002) 137 #define CPU_FTR_DBELL ASM_CONST(0x00000004) 138 #define CPU_FTR_CAN_NAP ASM_CONST(0x00000008) 139 #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00000010) 140 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x00000020) 141 #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00000040) 142 #define CPU_FTR_LWSYNC ASM_CONST(0x00000080) 143 #define CPU_FTR_NOEXECUTE ASM_CONST(0x00000100) 144 #define CPU_FTR_EMB_HV ASM_CONST(0x00000200) 145 146 /* Definitions for features that only exist on 32-bit chips */ 147 #ifdef CONFIG_PPC32 148 #define CPU_FTR_L2CR ASM_CONST(0x00002000) 149 #define CPU_FTR_SPEC7450 ASM_CONST(0x00004000) 150 #define CPU_FTR_TAU ASM_CONST(0x00008000) 151 #define CPU_FTR_CAN_DOZE ASM_CONST(0x00010000) 152 #define CPU_FTR_L3CR ASM_CONST(0x00040000) 153 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00080000) 154 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00100000) 155 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00200000) 156 #define CPU_FTR_NO_DPM ASM_CONST(0x00400000) 157 #define CPU_FTR_476_DD2 ASM_CONST(0x00800000) 158 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x01000000) 159 #define CPU_FTR_NO_BTIC ASM_CONST(0x02000000) 160 #define CPU_FTR_PPC_LE ASM_CONST(0x04000000) 161 #define CPU_FTR_SPE ASM_CONST(0x10000000) 162 #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x20000000) 163 #define CPU_FTR_INDEXED_DCR ASM_CONST(0x40000000) 164 165 #else /* CONFIG_PPC32 */ 166 /* Define these to 0 for the sake of tests in common code */ 167 #define CPU_FTR_PPC_LE (0) 168 #endif 169 170 /* 171 * Definitions for the 64-bit processor unique features; 172 * on 32-bit, make the names available but defined to be 0. 173 */ 174 #ifdef __powerpc64__ 175 #define LONG_ASM_CONST(x) ASM_CONST(x) 176 #else 177 #define LONG_ASM_CONST(x) 0 178 #endif 179 180 #define CPU_FTR_REAL_LE LONG_ASM_CONST(0x0000000000001000) 181 #define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000000002000) 182 #define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000000008000) 183 #define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000000010000) 184 #define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000000000020000) 185 #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000000000040000) 186 #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000000000080000) 187 #define CPU_FTR_SMT LONG_ASM_CONST(0x0000000000100000) 188 #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000000000200000) 189 #define CPU_FTR_PURR LONG_ASM_CONST(0x0000000000400000) 190 #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000000000800000) 191 #define CPU_FTR_SPURR LONG_ASM_CONST(0x0000000001000000) 192 #define CPU_FTR_DSCR LONG_ASM_CONST(0x0000000002000000) 193 #define CPU_FTR_VSX LONG_ASM_CONST(0x0000000004000000) 194 // Free LONG_ASM_CONST(0x0000000008000000) 195 #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000000010000000) 196 #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0000000020000000) 197 #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0000000040000000) 198 #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0000000080000000) 199 #define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0000000100000000) 200 #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0000000200000000) 201 /* LONG_ASM_CONST(0x0000000400000000) Free */ 202 #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0000000800000000) 203 #define CPU_FTR_TM LONG_ASM_CONST(0x0000001000000000) 204 #define CPU_FTR_CFAR LONG_ASM_CONST(0x0000002000000000) 205 #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0000004000000000) 206 #define CPU_FTR_DAWR LONG_ASM_CONST(0x0000008000000000) 207 #define CPU_FTR_DABRX LONG_ASM_CONST(0x0000010000000000) 208 #define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x0000020000000000) 209 #define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000) 210 #define CPU_FTR_P9_TM_HV_ASSIST LONG_ASM_CONST(0x0000100000000000) 211 #define CPU_FTR_P9_TM_XER_SO_BUG LONG_ASM_CONST(0x0000200000000000) 212 #define CPU_FTR_P9_TLBIE_STQ_BUG LONG_ASM_CONST(0x0000400000000000) 213 #define CPU_FTR_P9_TIDR LONG_ASM_CONST(0x0000800000000000) 214 #define CPU_FTR_P9_TLBIE_ERAT_BUG LONG_ASM_CONST(0x0001000000000000) 215 #define CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002000000000000) 216 #define CPU_FTR_ARCH_31 LONG_ASM_CONST(0x0004000000000000) 217 #define CPU_FTR_DAWR1 LONG_ASM_CONST(0x0008000000000000) 218 219 #ifndef __ASSEMBLY__ 220 221 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN) 222 223 #define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE) 224 225 /* We only set the altivec features if the kernel was compiled with altivec 226 * support 227 */ 228 #ifdef CONFIG_ALTIVEC 229 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC 230 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC 231 #else 232 #define CPU_FTR_ALTIVEC_COMP 0 233 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0 234 #endif 235 236 /* We only set the VSX features if the kernel was compiled with VSX 237 * support 238 */ 239 #ifdef CONFIG_VSX 240 #define CPU_FTR_VSX_COMP CPU_FTR_VSX 241 #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX 242 #else 243 #define CPU_FTR_VSX_COMP 0 244 #define PPC_FEATURE_HAS_VSX_COMP 0 245 #endif 246 247 /* We only set the spe features if the kernel was compiled with spe 248 * support 249 */ 250 #ifdef CONFIG_SPE 251 #define CPU_FTR_SPE_COMP CPU_FTR_SPE 252 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE 253 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE 254 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE 255 #else 256 #define CPU_FTR_SPE_COMP 0 257 #define PPC_FEATURE_HAS_SPE_COMP 0 258 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0 259 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0 260 #endif 261 262 /* We only set the TM feature if the kernel was compiled with TM supprt */ 263 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 264 #define CPU_FTR_TM_COMP CPU_FTR_TM 265 #define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM 266 #define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC 267 #else 268 #define CPU_FTR_TM_COMP 0 269 #define PPC_FEATURE2_HTM_COMP 0 270 #define PPC_FEATURE2_HTM_NOSC_COMP 0 271 #endif 272 273 /* We need to mark all pages as being coherent if we're SMP or we have a 274 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II 275 * require it for PCI "streaming/prefetch" to work properly. 276 * This is also required by 52xx family. 277 */ 278 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ 279 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \ 280 || defined(CONFIG_PPC_MPC52xx) 281 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT 282 #else 283 #define CPU_FTR_COMMON 0 284 #endif 285 286 /* The powersave features NAP & DOZE seems to confuse BDI when 287 debugging. So if a BDI is used, disable theses 288 */ 289 #ifndef CONFIG_BDI_SWITCH 290 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE 291 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP 292 #else 293 #define CPU_FTR_MAYBE_CAN_DOZE 0 294 #define CPU_FTR_MAYBE_CAN_NAP 0 295 #endif 296 297 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | \ 298 CPU_FTR_COHERENT_ICACHE) 299 #define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ 300 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE | CPU_FTR_NOEXECUTE) 301 #define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_PPC_LE) 302 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \ 303 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 304 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 305 #define CPU_FTRS_740 (CPU_FTR_COMMON | \ 306 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 307 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 308 CPU_FTR_PPC_LE) 309 #define CPU_FTRS_750 (CPU_FTR_COMMON | \ 310 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 311 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ 312 CPU_FTR_PPC_LE) 313 #define CPU_FTRS_750CL (CPU_FTRS_750) 314 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) 315 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM) 316 #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX) 317 #define CPU_FTRS_750GX (CPU_FTRS_750FX) 318 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \ 319 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 320 CPU_FTR_ALTIVEC_COMP | \ 321 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 322 #define CPU_FTRS_7400 (CPU_FTR_COMMON | \ 323 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \ 324 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \ 325 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) 326 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ 327 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 328 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 329 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 330 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ 331 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 332 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 333 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 334 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 335 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ 336 CPU_FTR_NEED_PAIRED_STWCX | \ 337 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 338 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 339 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 340 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ 341 CPU_FTR_NEED_PAIRED_STWCX | \ 342 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ 343 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 344 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ 345 CPU_FTR_NEED_PAIRED_STWCX | \ 346 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 347 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ 348 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ 349 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) 350 #define CPU_FTRS_7455 (CPU_FTR_COMMON | \ 351 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 352 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 353 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 354 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ 355 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 356 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 357 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \ 358 CPU_FTR_NEED_PAIRED_STWCX) 359 #define CPU_FTRS_7447 (CPU_FTR_COMMON | \ 360 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 361 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 362 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 363 #define CPU_FTRS_7447A (CPU_FTR_COMMON | \ 364 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 365 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 366 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 367 #define CPU_FTRS_7448 (CPU_FTR_COMMON | \ 368 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ 369 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ 370 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) 371 #define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_NOEXECUTE) 372 #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ 373 CPU_FTR_MAYBE_CAN_NAP) 374 #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ 375 CPU_FTR_MAYBE_CAN_NAP | \ 376 CPU_FTR_COMMON | CPU_FTR_NOEXECUTE) 377 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \ 378 CPU_FTR_MAYBE_CAN_NAP | \ 379 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE | CPU_FTR_NOEXECUTE) 380 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON) 381 #define CPU_FTRS_8XX (CPU_FTR_NOEXECUTE) 382 #define CPU_FTRS_40X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 383 #define CPU_FTRS_44X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 384 #define CPU_FTRS_440x6 (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \ 385 CPU_FTR_INDEXED_DCR) 386 #define CPU_FTRS_47X (CPU_FTRS_440x6) 387 #define CPU_FTRS_E200 (CPU_FTR_SPE_COMP | \ 388 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \ 389 CPU_FTR_NOEXECUTE | \ 390 CPU_FTR_DEBUG_LVL_EXC) 391 #define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | \ 392 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \ 393 CPU_FTR_NOEXECUTE) 394 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | \ 395 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ 396 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) 397 #define CPU_FTRS_E500MC (CPU_FTR_NODSISRALIGN | \ 398 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 399 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV) 400 /* 401 * e5500/e6500 erratum A-006958 is a timebase bug that can use the 402 * same workaround as CPU_FTR_CELL_TB_BUG. 403 */ 404 #define CPU_FTRS_E5500 (CPU_FTR_NODSISRALIGN | \ 405 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 406 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 407 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG) 408 #define CPU_FTRS_E6500 (CPU_FTR_NODSISRALIGN | \ 409 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 410 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 411 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \ 412 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT) 413 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) 414 415 /* 64-bit CPUs */ 416 #define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \ 417 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 418 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ 419 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \ 420 CPU_FTR_HVMODE | CPU_FTR_DABRX) 421 #define CPU_FTRS_POWER5 (CPU_FTR_LWSYNC | \ 422 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 423 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 424 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \ 425 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX) 426 #define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \ 427 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 428 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 429 CPU_FTR_COHERENT_ICACHE | \ 430 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 431 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ 432 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \ 433 CPU_FTR_DABRX) 434 #define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \ 435 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 436 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 437 CPU_FTR_COHERENT_ICACHE | \ 438 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 439 CPU_FTR_DSCR | CPU_FTR_ASYM_SMT | \ 440 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 441 CPU_FTR_CFAR | CPU_FTR_HVMODE | \ 442 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX ) 443 #define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \ 444 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 445 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 446 CPU_FTR_COHERENT_ICACHE | \ 447 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 448 CPU_FTR_DSCR | \ 449 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 450 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 451 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \ 452 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP ) 453 #define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG) 454 #define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \ 455 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 456 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 457 CPU_FTR_COHERENT_ICACHE | \ 458 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 459 CPU_FTR_DSCR | \ 460 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 461 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 462 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \ 463 CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_P9_TLBIE_STQ_BUG | \ 464 CPU_FTR_P9_TLBIE_ERAT_BUG | CPU_FTR_P9_TIDR) 465 #define CPU_FTRS_POWER9_DD2_0 (CPU_FTRS_POWER9 | CPU_FTR_P9_RADIX_PREFETCH_BUG) 466 #define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | \ 467 CPU_FTR_P9_RADIX_PREFETCH_BUG | \ 468 CPU_FTR_POWER9_DD2_1) 469 #define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \ 470 CPU_FTR_P9_TM_HV_ASSIST | \ 471 CPU_FTR_P9_TM_XER_SO_BUG) 472 #define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \ 473 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 474 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 475 CPU_FTR_COHERENT_ICACHE | \ 476 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 477 CPU_FTR_DSCR | \ 478 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 479 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \ 480 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \ 481 CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_ARCH_31 | \ 482 CPU_FTR_DAWR | CPU_FTR_DAWR1) 483 #define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \ 484 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 485 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 486 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ 487 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX) 488 #define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \ 489 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \ 490 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX) 491 #define CPU_FTRS_COMPATIBLE (CPU_FTR_PPCAS_ARCH_V2) 492 493 #ifdef __powerpc64__ 494 #ifdef CONFIG_PPC_BOOK3E 495 #define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500) 496 #else 497 #ifdef CONFIG_CPU_LITTLE_ENDIAN 498 #define CPU_FTRS_POSSIBLE \ 499 (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \ 500 CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \ 501 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10) 502 #else 503 #define CPU_FTRS_POSSIBLE \ 504 (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \ 505 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \ 506 CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \ 507 CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \ 508 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10) 509 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 510 #endif 511 #else 512 enum { 513 CPU_FTRS_POSSIBLE = 514 #ifdef CONFIG_PPC_BOOK3S_601 515 CPU_FTRS_PPC601 | 516 #elif defined(CONFIG_PPC_BOOK3S_32) 517 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU | 518 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 | 519 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX | 520 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 | 521 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | 522 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | 523 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX | 524 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 | 525 CPU_FTRS_CLASSIC32 | 526 #else 527 CPU_FTRS_GENERIC_32 | 528 #endif 529 #ifdef CONFIG_PPC_8xx 530 CPU_FTRS_8XX | 531 #endif 532 #ifdef CONFIG_40x 533 CPU_FTRS_40X | 534 #endif 535 #ifdef CONFIG_44x 536 CPU_FTRS_44X | CPU_FTRS_440x6 | 537 #endif 538 #ifdef CONFIG_PPC_47x 539 CPU_FTRS_47X | CPU_FTR_476_DD2 | 540 #endif 541 #ifdef CONFIG_E200 542 CPU_FTRS_E200 | 543 #endif 544 #ifdef CONFIG_E500 545 CPU_FTRS_E500 | CPU_FTRS_E500_2 | 546 #endif 547 #ifdef CONFIG_PPC_E500MC 548 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 | 549 #endif 550 0, 551 }; 552 #endif /* __powerpc64__ */ 553 554 #ifdef __powerpc64__ 555 #ifdef CONFIG_PPC_BOOK3E 556 #define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500) 557 #else 558 559 #ifdef CONFIG_PPC_DT_CPU_FTRS 560 #define CPU_FTRS_DT_CPU_BASE \ 561 (CPU_FTR_LWSYNC | \ 562 CPU_FTR_FPU_UNAVAILABLE | \ 563 CPU_FTR_NODSISRALIGN | \ 564 CPU_FTR_NOEXECUTE | \ 565 CPU_FTR_COHERENT_ICACHE | \ 566 CPU_FTR_STCX_CHECKS_ADDRESS | \ 567 CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 568 CPU_FTR_DAWR | \ 569 CPU_FTR_ARCH_206 | \ 570 CPU_FTR_ARCH_207S) 571 #else 572 #define CPU_FTRS_DT_CPU_BASE (~0ul) 573 #endif 574 575 #ifdef CONFIG_CPU_LITTLE_ENDIAN 576 #define CPU_FTRS_ALWAYS \ 577 (CPU_FTRS_POSSIBLE & ~CPU_FTR_HVMODE & CPU_FTRS_POWER7 & \ 578 CPU_FTRS_POWER8E & CPU_FTRS_POWER8 & CPU_FTRS_POWER9 & \ 579 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE) 580 #else 581 #define CPU_FTRS_ALWAYS \ 582 (CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \ 583 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \ 584 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \ 585 ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & CPU_FTRS_POWER9 & \ 586 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE) 587 #endif /* CONFIG_CPU_LITTLE_ENDIAN */ 588 #endif 589 #else 590 enum { 591 CPU_FTRS_ALWAYS = 592 #ifdef CONFIG_PPC_BOOK3S_601 593 CPU_FTRS_PPC601 & 594 #elif defined(CONFIG_PPC_BOOK3S_32) 595 CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU & 596 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 & 597 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX & 598 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 & 599 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & 600 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & 601 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX & 602 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 & 603 CPU_FTRS_CLASSIC32 & 604 #else 605 CPU_FTRS_GENERIC_32 & 606 #endif 607 #ifdef CONFIG_PPC_8xx 608 CPU_FTRS_8XX & 609 #endif 610 #ifdef CONFIG_40x 611 CPU_FTRS_40X & 612 #endif 613 #ifdef CONFIG_44x 614 CPU_FTRS_44X & CPU_FTRS_440x6 & 615 #endif 616 #ifdef CONFIG_E200 617 CPU_FTRS_E200 & 618 #endif 619 #ifdef CONFIG_E500 620 CPU_FTRS_E500 & CPU_FTRS_E500_2 & 621 #endif 622 #ifdef CONFIG_PPC_E500MC 623 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 & 624 #endif 625 ~CPU_FTR_EMB_HV & /* can be removed at runtime */ 626 CPU_FTRS_POSSIBLE, 627 }; 628 #endif /* __powerpc64__ */ 629 630 /* 631 * Maximum number of hw breakpoint supported on powerpc. Number of 632 * breakpoints supported by actual hw might be less than this, which 633 * is decided at run time in nr_wp_slots(). 634 */ 635 #define HBP_NUM_MAX 2 636 637 #endif /* !__ASSEMBLY__ */ 638 639 #endif /* __ASM_POWERPC_CPUTABLE_H */ 640