1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for STMicroelectronics STM32F7 I2C controller 4 * 5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc 6 * reference manual. 7 * Please see below a link to the documentation: 8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf 9 * 10 * Copyright (C) M'boumba Cedric Madianga 2017 11 * Copyright (C) STMicroelectronics 2017 12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> 13 * 14 * This driver is based on i2c-stm32f4.c 15 * 16 */ 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/err.h> 20 #include <linux/i2c.h> 21 #include <linux/interrupt.h> 22 #include <linux/io.h> 23 #include <linux/iopoll.h> 24 #include <linux/mfd/syscon.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_address.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regmap.h> 33 #include <linux/reset.h> 34 #include <linux/slab.h> 35 36 #include "i2c-stm32.h" 37 38 /* STM32F7 I2C registers */ 39 #define STM32F7_I2C_CR1 0x00 40 #define STM32F7_I2C_CR2 0x04 41 #define STM32F7_I2C_OAR1 0x08 42 #define STM32F7_I2C_OAR2 0x0C 43 #define STM32F7_I2C_PECR 0x20 44 #define STM32F7_I2C_TIMINGR 0x10 45 #define STM32F7_I2C_ISR 0x18 46 #define STM32F7_I2C_ICR 0x1C 47 #define STM32F7_I2C_RXDR 0x24 48 #define STM32F7_I2C_TXDR 0x28 49 50 /* STM32F7 I2C control 1 */ 51 #define STM32F7_I2C_CR1_PECEN BIT(23) 52 #define STM32F7_I2C_CR1_SBC BIT(16) 53 #define STM32F7_I2C_CR1_RXDMAEN BIT(15) 54 #define STM32F7_I2C_CR1_TXDMAEN BIT(14) 55 #define STM32F7_I2C_CR1_ANFOFF BIT(12) 56 #define STM32F7_I2C_CR1_ERRIE BIT(7) 57 #define STM32F7_I2C_CR1_TCIE BIT(6) 58 #define STM32F7_I2C_CR1_STOPIE BIT(5) 59 #define STM32F7_I2C_CR1_NACKIE BIT(4) 60 #define STM32F7_I2C_CR1_ADDRIE BIT(3) 61 #define STM32F7_I2C_CR1_RXIE BIT(2) 62 #define STM32F7_I2C_CR1_TXIE BIT(1) 63 #define STM32F7_I2C_CR1_PE BIT(0) 64 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \ 65 | STM32F7_I2C_CR1_TCIE \ 66 | STM32F7_I2C_CR1_STOPIE \ 67 | STM32F7_I2C_CR1_NACKIE \ 68 | STM32F7_I2C_CR1_RXIE \ 69 | STM32F7_I2C_CR1_TXIE) 70 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \ 71 | STM32F7_I2C_CR1_STOPIE \ 72 | STM32F7_I2C_CR1_NACKIE \ 73 | STM32F7_I2C_CR1_RXIE \ 74 | STM32F7_I2C_CR1_TXIE) 75 76 /* STM32F7 I2C control 2 */ 77 #define STM32F7_I2C_CR2_PECBYTE BIT(26) 78 #define STM32F7_I2C_CR2_RELOAD BIT(24) 79 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16) 80 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16) 81 #define STM32F7_I2C_CR2_NACK BIT(15) 82 #define STM32F7_I2C_CR2_STOP BIT(14) 83 #define STM32F7_I2C_CR2_START BIT(13) 84 #define STM32F7_I2C_CR2_HEAD10R BIT(12) 85 #define STM32F7_I2C_CR2_ADD10 BIT(11) 86 #define STM32F7_I2C_CR2_RD_WRN BIT(10) 87 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0) 88 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \ 89 STM32F7_I2C_CR2_SADD10_MASK)) 90 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1) 91 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1) 92 93 /* STM32F7 I2C Own Address 1 */ 94 #define STM32F7_I2C_OAR1_OA1EN BIT(15) 95 #define STM32F7_I2C_OAR1_OA1MODE BIT(10) 96 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0) 97 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \ 98 STM32F7_I2C_OAR1_OA1_10_MASK)) 99 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1) 100 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1) 101 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \ 102 | STM32F7_I2C_OAR1_OA1_10_MASK \ 103 | STM32F7_I2C_OAR1_OA1EN \ 104 | STM32F7_I2C_OAR1_OA1MODE) 105 106 /* STM32F7 I2C Own Address 2 */ 107 #define STM32F7_I2C_OAR2_OA2EN BIT(15) 108 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8) 109 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8) 110 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1) 111 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1) 112 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \ 113 | STM32F7_I2C_OAR2_OA2_7_MASK \ 114 | STM32F7_I2C_OAR2_OA2EN) 115 116 /* STM32F7 I2C Interrupt Status */ 117 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17) 118 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \ 119 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17) 120 #define STM32F7_I2C_ISR_DIR BIT(16) 121 #define STM32F7_I2C_ISR_BUSY BIT(15) 122 #define STM32F7_I2C_ISR_PECERR BIT(11) 123 #define STM32F7_I2C_ISR_ARLO BIT(9) 124 #define STM32F7_I2C_ISR_BERR BIT(8) 125 #define STM32F7_I2C_ISR_TCR BIT(7) 126 #define STM32F7_I2C_ISR_TC BIT(6) 127 #define STM32F7_I2C_ISR_STOPF BIT(5) 128 #define STM32F7_I2C_ISR_NACKF BIT(4) 129 #define STM32F7_I2C_ISR_ADDR BIT(3) 130 #define STM32F7_I2C_ISR_RXNE BIT(2) 131 #define STM32F7_I2C_ISR_TXIS BIT(1) 132 #define STM32F7_I2C_ISR_TXE BIT(0) 133 134 /* STM32F7 I2C Interrupt Clear */ 135 #define STM32F7_I2C_ICR_PECCF BIT(11) 136 #define STM32F7_I2C_ICR_ARLOCF BIT(9) 137 #define STM32F7_I2C_ICR_BERRCF BIT(8) 138 #define STM32F7_I2C_ICR_STOPCF BIT(5) 139 #define STM32F7_I2C_ICR_NACKCF BIT(4) 140 #define STM32F7_I2C_ICR_ADDRCF BIT(3) 141 142 /* STM32F7 I2C Timing */ 143 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28) 144 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20) 145 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16) 146 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8) 147 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff) 148 149 #define STM32F7_I2C_MAX_LEN 0xff 150 #define STM32F7_I2C_DMA_LEN_MIN 0x16 151 #define STM32F7_I2C_MAX_SLAVE 0x2 152 153 #define STM32F7_I2C_DNF_DEFAULT 0 154 #define STM32F7_I2C_DNF_MAX 16 155 156 #define STM32F7_I2C_ANALOG_FILTER_ENABLE 1 157 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ 158 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ 159 160 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */ 161 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */ 162 163 #define STM32F7_PRESC_MAX BIT(4) 164 #define STM32F7_SCLDEL_MAX BIT(4) 165 #define STM32F7_SDADEL_MAX BIT(4) 166 #define STM32F7_SCLH_MAX BIT(8) 167 #define STM32F7_SCLL_MAX BIT(8) 168 169 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100) 170 171 /** 172 * struct stm32f7_i2c_spec - private i2c specification timing 173 * @rate: I2C bus speed (Hz) 174 * @rate_min: 80% of I2C bus speed (Hz) 175 * @rate_max: 100% of I2C bus speed (Hz) 176 * @fall_max: Max fall time of both SDA and SCL signals (ns) 177 * @rise_max: Max rise time of both SDA and SCL signals (ns) 178 * @hddat_min: Min data hold time (ns) 179 * @vddat_max: Max data valid time (ns) 180 * @sudat_min: Min data setup time (ns) 181 * @l_min: Min low period of the SCL clock (ns) 182 * @h_min: Min high period of the SCL clock (ns) 183 */ 184 struct stm32f7_i2c_spec { 185 u32 rate; 186 u32 rate_min; 187 u32 rate_max; 188 u32 fall_max; 189 u32 rise_max; 190 u32 hddat_min; 191 u32 vddat_max; 192 u32 sudat_min; 193 u32 l_min; 194 u32 h_min; 195 }; 196 197 /** 198 * struct stm32f7_i2c_setup - private I2C timing setup parameters 199 * @speed: I2C speed mode (standard, Fast Plus) 200 * @speed_freq: I2C speed frequency (Hz) 201 * @clock_src: I2C clock source frequency (Hz) 202 * @rise_time: Rise time (ns) 203 * @fall_time: Fall time (ns) 204 * @dnf: Digital filter coefficient (0-16) 205 * @analog_filter: Analog filter delay (On/Off) 206 */ 207 struct stm32f7_i2c_setup { 208 enum stm32_i2c_speed speed; 209 u32 speed_freq; 210 u32 clock_src; 211 u32 rise_time; 212 u32 fall_time; 213 u8 dnf; 214 bool analog_filter; 215 }; 216 217 /** 218 * struct stm32f7_i2c_timings - private I2C output parameters 219 * @node: List entry 220 * @presc: Prescaler value 221 * @scldel: Data setup time 222 * @sdadel: Data hold time 223 * @sclh: SCL high period (master mode) 224 * @scll: SCL low period (master mode) 225 */ 226 struct stm32f7_i2c_timings { 227 struct list_head node; 228 u8 presc; 229 u8 scldel; 230 u8 sdadel; 231 u8 sclh; 232 u8 scll; 233 }; 234 235 /** 236 * struct stm32f7_i2c_msg - client specific data 237 * @addr: 8-bit or 10-bit slave addr, including r/w bit 238 * @count: number of bytes to be transferred 239 * @buf: data buffer 240 * @result: result of the transfer 241 * @stop: last I2C msg to be sent, i.e. STOP to be generated 242 * @smbus: boolean to know if the I2C IP is used in SMBus mode 243 * @size: type of SMBus protocol 244 * @read_write: direction of SMBus protocol 245 * SMBus block read and SMBus block write - block read process call protocols 246 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will 247 * contain a maximum of 32 bytes of data + byte command + byte count + PEC 248 * This buffer has to be 32-bit aligned to be compliant with memory address 249 * register in DMA mode. 250 */ 251 struct stm32f7_i2c_msg { 252 u16 addr; 253 u32 count; 254 u8 *buf; 255 int result; 256 bool stop; 257 bool smbus; 258 int size; 259 char read_write; 260 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4); 261 }; 262 263 /** 264 * struct stm32f7_i2c_dev - private data of the controller 265 * @adap: I2C adapter for this controller 266 * @dev: device for this controller 267 * @base: virtual memory area 268 * @complete: completion of I2C message 269 * @clk: hw i2c clock 270 * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+ 271 * @msg: Pointer to data to be written 272 * @msg_num: number of I2C messages to be executed 273 * @msg_id: message identifiant 274 * @f7_msg: customized i2c msg for driver usage 275 * @setup: I2C timing input setup 276 * @timing: I2C computed timings 277 * @slave: list of slave devices registered on the I2C bus 278 * @slave_running: slave device currently used 279 * @slave_dir: transfer direction for the current slave device 280 * @master_mode: boolean to know in which mode the I2C is running (master or 281 * slave) 282 * @dma: dma data 283 * @use_dma: boolean to know if dma is used in the current transfer 284 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits 285 */ 286 struct stm32f7_i2c_dev { 287 struct i2c_adapter adap; 288 struct device *dev; 289 void __iomem *base; 290 struct completion complete; 291 struct clk *clk; 292 int speed; 293 struct i2c_msg *msg; 294 unsigned int msg_num; 295 unsigned int msg_id; 296 struct stm32f7_i2c_msg f7_msg; 297 struct stm32f7_i2c_setup setup; 298 struct stm32f7_i2c_timings timing; 299 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE]; 300 struct i2c_client *slave_running; 301 u32 slave_dir; 302 bool master_mode; 303 struct stm32_i2c_dma *dma; 304 bool use_dma; 305 struct regmap *regmap; 306 }; 307 308 /** 309 * All these values are coming from I2C Specification, Version 6.0, 4th of 310 * April 2014. 311 * 312 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast, 313 * and Fast-mode Plus I2C-bus devices 314 */ 315 static struct stm32f7_i2c_spec i2c_specs[] = { 316 [STM32_I2C_SPEED_STANDARD] = { 317 .rate = 100000, 318 .rate_min = 80000, 319 .rate_max = 100000, 320 .fall_max = 300, 321 .rise_max = 1000, 322 .hddat_min = 0, 323 .vddat_max = 3450, 324 .sudat_min = 250, 325 .l_min = 4700, 326 .h_min = 4000, 327 }, 328 [STM32_I2C_SPEED_FAST] = { 329 .rate = 400000, 330 .rate_min = 320000, 331 .rate_max = 400000, 332 .fall_max = 300, 333 .rise_max = 300, 334 .hddat_min = 0, 335 .vddat_max = 900, 336 .sudat_min = 100, 337 .l_min = 1300, 338 .h_min = 600, 339 }, 340 [STM32_I2C_SPEED_FAST_PLUS] = { 341 .rate = 1000000, 342 .rate_min = 800000, 343 .rate_max = 1000000, 344 .fall_max = 100, 345 .rise_max = 120, 346 .hddat_min = 0, 347 .vddat_max = 450, 348 .sudat_min = 50, 349 .l_min = 500, 350 .h_min = 260, 351 }, 352 }; 353 354 static const struct stm32f7_i2c_setup stm32f7_setup = { 355 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT, 356 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT, 357 .dnf = STM32F7_I2C_DNF_DEFAULT, 358 .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE, 359 }; 360 361 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask) 362 { 363 writel_relaxed(readl_relaxed(reg) | mask, reg); 364 } 365 366 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask) 367 { 368 writel_relaxed(readl_relaxed(reg) & ~mask, reg); 369 } 370 371 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask) 372 { 373 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask); 374 } 375 376 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev, 377 struct stm32f7_i2c_setup *setup, 378 struct stm32f7_i2c_timings *output) 379 { 380 u32 p_prev = STM32F7_PRESC_MAX; 381 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 382 setup->clock_src); 383 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC, 384 setup->speed_freq); 385 u32 clk_error_prev = i2cbus; 386 u32 tsync; 387 u32 af_delay_min, af_delay_max; 388 u32 dnf_delay; 389 u32 clk_min, clk_max; 390 int sdadel_min, sdadel_max; 391 int scldel_min; 392 struct stm32f7_i2c_timings *v, *_v, *s; 393 struct list_head solutions; 394 u16 p, l, a, h; 395 int ret = 0; 396 397 if (setup->speed >= STM32_I2C_SPEED_END) { 398 dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n", 399 setup->speed, STM32_I2C_SPEED_END - 1); 400 return -EINVAL; 401 } 402 403 if ((setup->rise_time > i2c_specs[setup->speed].rise_max) || 404 (setup->fall_time > i2c_specs[setup->speed].fall_max)) { 405 dev_err(i2c_dev->dev, 406 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", 407 setup->rise_time, i2c_specs[setup->speed].rise_max, 408 setup->fall_time, i2c_specs[setup->speed].fall_max); 409 return -EINVAL; 410 } 411 412 if (setup->dnf > STM32F7_I2C_DNF_MAX) { 413 dev_err(i2c_dev->dev, 414 "DNF out of bound %d/%d\n", 415 setup->dnf, STM32F7_I2C_DNF_MAX); 416 return -EINVAL; 417 } 418 419 if (setup->speed_freq > i2c_specs[setup->speed].rate) { 420 dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n", 421 setup->speed_freq, i2c_specs[setup->speed].rate); 422 return -EINVAL; 423 } 424 425 /* Analog and Digital Filters */ 426 af_delay_min = 427 (setup->analog_filter ? 428 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0); 429 af_delay_max = 430 (setup->analog_filter ? 431 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0); 432 dnf_delay = setup->dnf * i2cclk; 433 434 sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time - 435 af_delay_min - (setup->dnf + 3) * i2cclk; 436 437 sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time - 438 af_delay_max - (setup->dnf + 4) * i2cclk; 439 440 scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min; 441 442 if (sdadel_min < 0) 443 sdadel_min = 0; 444 if (sdadel_max < 0) 445 sdadel_max = 0; 446 447 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", 448 sdadel_min, sdadel_max, scldel_min); 449 450 INIT_LIST_HEAD(&solutions); 451 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 452 for (p = 0; p < STM32F7_PRESC_MAX; p++) { 453 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) { 454 u32 scldel = (l + 1) * (p + 1) * i2cclk; 455 456 if (scldel < scldel_min) 457 continue; 458 459 for (a = 0; a < STM32F7_SDADEL_MAX; a++) { 460 u32 sdadel = (a * (p + 1) + 1) * i2cclk; 461 462 if (((sdadel >= sdadel_min) && 463 (sdadel <= sdadel_max)) && 464 (p != p_prev)) { 465 v = kmalloc(sizeof(*v), GFP_KERNEL); 466 if (!v) { 467 ret = -ENOMEM; 468 goto exit; 469 } 470 471 v->presc = p; 472 v->scldel = l; 473 v->sdadel = a; 474 p_prev = p; 475 476 list_add_tail(&v->node, 477 &solutions); 478 break; 479 } 480 } 481 482 if (p_prev == p) 483 break; 484 } 485 } 486 487 if (list_empty(&solutions)) { 488 dev_err(i2c_dev->dev, "no Prescaler solution\n"); 489 ret = -EPERM; 490 goto exit; 491 } 492 493 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 494 s = NULL; 495 clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min; 496 clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max; 497 498 /* 499 * Among Prescaler possibilities discovered above figures out SCL Low 500 * and High Period. Provided: 501 * - SCL Low Period has to be higher than SCL Clock Low Period 502 * defined by I2C Specification. I2C Clock has to be lower than 503 * (SCL Low Period - Analog/Digital filters) / 4. 504 * - SCL High Period has to be lower than SCL Clock High Period 505 * defined by I2C Specification 506 * - I2C Clock has to be lower than SCL High Period 507 */ 508 list_for_each_entry(v, &solutions, node) { 509 u32 prescaler = (v->presc + 1) * i2cclk; 510 511 for (l = 0; l < STM32F7_SCLL_MAX; l++) { 512 u32 tscl_l = (l + 1) * prescaler + tsync; 513 514 if ((tscl_l < i2c_specs[setup->speed].l_min) || 515 (i2cclk >= 516 ((tscl_l - af_delay_min - dnf_delay) / 4))) { 517 continue; 518 } 519 520 for (h = 0; h < STM32F7_SCLH_MAX; h++) { 521 u32 tscl_h = (h + 1) * prescaler + tsync; 522 u32 tscl = tscl_l + tscl_h + 523 setup->rise_time + setup->fall_time; 524 525 if ((tscl >= clk_min) && (tscl <= clk_max) && 526 (tscl_h >= i2c_specs[setup->speed].h_min) && 527 (i2cclk < tscl_h)) { 528 int clk_error = tscl - i2cbus; 529 530 if (clk_error < 0) 531 clk_error = -clk_error; 532 533 if (clk_error < clk_error_prev) { 534 clk_error_prev = clk_error; 535 v->scll = l; 536 v->sclh = h; 537 s = v; 538 } 539 } 540 } 541 } 542 } 543 544 if (!s) { 545 dev_err(i2c_dev->dev, "no solution at all\n"); 546 ret = -EPERM; 547 goto exit; 548 } 549 550 output->presc = s->presc; 551 output->scldel = s->scldel; 552 output->sdadel = s->sdadel; 553 output->scll = s->scll; 554 output->sclh = s->sclh; 555 556 dev_dbg(i2c_dev->dev, 557 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n", 558 output->presc, 559 output->scldel, output->sdadel, 560 output->scll, output->sclh); 561 562 exit: 563 /* Release list and memory */ 564 list_for_each_entry_safe(v, _v, &solutions, node) { 565 list_del(&v->node); 566 kfree(v); 567 } 568 569 return ret; 570 } 571 572 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev, 573 struct stm32f7_i2c_setup *setup) 574 { 575 int ret = 0; 576 577 setup->speed = i2c_dev->speed; 578 setup->speed_freq = i2c_specs[setup->speed].rate; 579 setup->clock_src = clk_get_rate(i2c_dev->clk); 580 581 if (!setup->clock_src) { 582 dev_err(i2c_dev->dev, "clock rate is 0\n"); 583 return -EINVAL; 584 } 585 586 do { 587 ret = stm32f7_i2c_compute_timing(i2c_dev, setup, 588 &i2c_dev->timing); 589 if (ret) { 590 dev_err(i2c_dev->dev, 591 "failed to compute I2C timings.\n"); 592 if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) { 593 i2c_dev->speed--; 594 setup->speed = i2c_dev->speed; 595 setup->speed_freq = 596 i2c_specs[setup->speed].rate; 597 dev_warn(i2c_dev->dev, 598 "downgrade I2C Speed Freq to (%i)\n", 599 i2c_specs[setup->speed].rate); 600 } else { 601 break; 602 } 603 } 604 } while (ret); 605 606 if (ret) { 607 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n"); 608 return ret; 609 } 610 611 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n", 612 setup->speed, setup->speed_freq, setup->clock_src); 613 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n", 614 setup->rise_time, setup->fall_time); 615 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n", 616 (setup->analog_filter ? "On" : "Off"), setup->dnf); 617 618 return 0; 619 } 620 621 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev) 622 { 623 void __iomem *base = i2c_dev->base; 624 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN; 625 626 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 627 } 628 629 static void stm32f7_i2c_dma_callback(void *arg) 630 { 631 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg; 632 struct stm32_i2c_dma *dma = i2c_dev->dma; 633 struct device *dev = dma->chan_using->device->dev; 634 635 stm32f7_i2c_disable_dma_req(i2c_dev); 636 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir); 637 complete(&dma->dma_complete); 638 } 639 640 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev) 641 { 642 struct stm32f7_i2c_timings *t = &i2c_dev->timing; 643 u32 timing = 0; 644 645 /* Timing settings */ 646 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc); 647 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel); 648 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel); 649 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh); 650 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll); 651 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR); 652 653 /* Enable I2C */ 654 if (i2c_dev->setup.analog_filter) 655 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 656 STM32F7_I2C_CR1_ANFOFF); 657 else 658 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 659 STM32F7_I2C_CR1_ANFOFF); 660 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, 661 STM32F7_I2C_CR1_PE); 662 } 663 664 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev) 665 { 666 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 667 void __iomem *base = i2c_dev->base; 668 669 if (f7_msg->count) { 670 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR); 671 f7_msg->count--; 672 } 673 } 674 675 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev) 676 { 677 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 678 void __iomem *base = i2c_dev->base; 679 680 if (f7_msg->count) { 681 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR); 682 f7_msg->count--; 683 } else { 684 /* Flush RX buffer has no data is expected */ 685 readb_relaxed(base + STM32F7_I2C_RXDR); 686 } 687 } 688 689 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev) 690 { 691 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 692 u32 cr2; 693 694 if (i2c_dev->use_dma) 695 f7_msg->count -= STM32F7_I2C_MAX_LEN; 696 697 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 698 699 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK; 700 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 701 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 702 } else { 703 cr2 &= ~STM32F7_I2C_CR2_RELOAD; 704 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 705 } 706 707 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 708 } 709 710 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev) 711 { 712 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 713 u32 cr2; 714 u8 *val; 715 716 /* 717 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first 718 * data received inform us how many data will follow. 719 */ 720 stm32f7_i2c_read_rx_data(i2c_dev); 721 722 /* 723 * Update NBYTES with the value read to continue the transfer 724 */ 725 val = f7_msg->buf - sizeof(u8); 726 f7_msg->count = *val; 727 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 728 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 729 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 730 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 731 } 732 733 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap) 734 { 735 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 736 737 dev_info(i2c_dev->dev, "Trying to recover bus\n"); 738 739 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, 740 STM32F7_I2C_CR1_PE); 741 742 stm32f7_i2c_hw_config(i2c_dev); 743 744 return 0; 745 } 746 747 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev) 748 { 749 u32 status; 750 int ret; 751 752 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR, 753 status, 754 !(status & STM32F7_I2C_ISR_BUSY), 755 10, 1000); 756 if (!ret) 757 return 0; 758 759 dev_info(i2c_dev->dev, "bus busy\n"); 760 761 ret = stm32f7_i2c_release_bus(&i2c_dev->adap); 762 if (ret) { 763 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret); 764 return ret; 765 } 766 767 return -EBUSY; 768 } 769 770 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 771 struct i2c_msg *msg) 772 { 773 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 774 void __iomem *base = i2c_dev->base; 775 u32 cr1, cr2; 776 int ret; 777 778 f7_msg->addr = msg->addr; 779 f7_msg->buf = msg->buf; 780 f7_msg->count = msg->len; 781 f7_msg->result = 0; 782 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1); 783 784 reinit_completion(&i2c_dev->complete); 785 786 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 787 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 788 789 /* Set transfer direction */ 790 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 791 if (msg->flags & I2C_M_RD) 792 cr2 |= STM32F7_I2C_CR2_RD_WRN; 793 794 /* Set slave address */ 795 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10); 796 if (msg->flags & I2C_M_TEN) { 797 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK; 798 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr); 799 cr2 |= STM32F7_I2C_CR2_ADD10; 800 } else { 801 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK; 802 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 803 } 804 805 /* Set nb bytes to transfer and reload if needed */ 806 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 807 if (f7_msg->count > STM32F7_I2C_MAX_LEN) { 808 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN); 809 cr2 |= STM32F7_I2C_CR2_RELOAD; 810 } else { 811 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 812 } 813 814 /* Enable NACK, STOP, error and transfer complete interrupts */ 815 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 816 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 817 818 /* Clear DMA req and TX/RX interrupt */ 819 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 820 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 821 822 /* Configure DMA or enable RX/TX interrupt */ 823 i2c_dev->use_dma = false; 824 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { 825 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 826 msg->flags & I2C_M_RD, 827 f7_msg->count, f7_msg->buf, 828 stm32f7_i2c_dma_callback, 829 i2c_dev); 830 if (!ret) 831 i2c_dev->use_dma = true; 832 else 833 dev_warn(i2c_dev->dev, "can't use DMA\n"); 834 } 835 836 if (!i2c_dev->use_dma) { 837 if (msg->flags & I2C_M_RD) 838 cr1 |= STM32F7_I2C_CR1_RXIE; 839 else 840 cr1 |= STM32F7_I2C_CR1_TXIE; 841 } else { 842 if (msg->flags & I2C_M_RD) 843 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 844 else 845 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 846 } 847 848 /* Configure Start/Repeated Start */ 849 cr2 |= STM32F7_I2C_CR2_START; 850 851 i2c_dev->master_mode = true; 852 853 /* Write configurations registers */ 854 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 855 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 856 } 857 858 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, 859 unsigned short flags, u8 command, 860 union i2c_smbus_data *data) 861 { 862 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 863 struct device *dev = i2c_dev->dev; 864 void __iomem *base = i2c_dev->base; 865 u32 cr1, cr2; 866 int i, ret; 867 868 f7_msg->result = 0; 869 reinit_completion(&i2c_dev->complete); 870 871 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 872 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 873 874 /* Set transfer direction */ 875 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 876 if (f7_msg->read_write) 877 cr2 |= STM32F7_I2C_CR2_RD_WRN; 878 879 /* Set slave address */ 880 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK); 881 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr); 882 883 f7_msg->smbus_buf[0] = command; 884 switch (f7_msg->size) { 885 case I2C_SMBUS_QUICK: 886 f7_msg->stop = true; 887 f7_msg->count = 0; 888 break; 889 case I2C_SMBUS_BYTE: 890 f7_msg->stop = true; 891 f7_msg->count = 1; 892 break; 893 case I2C_SMBUS_BYTE_DATA: 894 if (f7_msg->read_write) { 895 f7_msg->stop = false; 896 f7_msg->count = 1; 897 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 898 } else { 899 f7_msg->stop = true; 900 f7_msg->count = 2; 901 f7_msg->smbus_buf[1] = data->byte; 902 } 903 break; 904 case I2C_SMBUS_WORD_DATA: 905 if (f7_msg->read_write) { 906 f7_msg->stop = false; 907 f7_msg->count = 1; 908 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 909 } else { 910 f7_msg->stop = true; 911 f7_msg->count = 3; 912 f7_msg->smbus_buf[1] = data->word & 0xff; 913 f7_msg->smbus_buf[2] = data->word >> 8; 914 } 915 break; 916 case I2C_SMBUS_BLOCK_DATA: 917 if (f7_msg->read_write) { 918 f7_msg->stop = false; 919 f7_msg->count = 1; 920 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 921 } else { 922 f7_msg->stop = true; 923 if (data->block[0] > I2C_SMBUS_BLOCK_MAX || 924 !data->block[0]) { 925 dev_err(dev, "Invalid block write size %d\n", 926 data->block[0]); 927 return -EINVAL; 928 } 929 f7_msg->count = data->block[0] + 2; 930 for (i = 1; i < f7_msg->count; i++) 931 f7_msg->smbus_buf[i] = data->block[i - 1]; 932 } 933 break; 934 case I2C_SMBUS_PROC_CALL: 935 f7_msg->stop = false; 936 f7_msg->count = 3; 937 f7_msg->smbus_buf[1] = data->word & 0xff; 938 f7_msg->smbus_buf[2] = data->word >> 8; 939 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 940 f7_msg->read_write = I2C_SMBUS_READ; 941 break; 942 case I2C_SMBUS_BLOCK_PROC_CALL: 943 f7_msg->stop = false; 944 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) { 945 dev_err(dev, "Invalid block write size %d\n", 946 data->block[0]); 947 return -EINVAL; 948 } 949 f7_msg->count = data->block[0] + 2; 950 for (i = 1; i < f7_msg->count; i++) 951 f7_msg->smbus_buf[i] = data->block[i - 1]; 952 cr2 &= ~STM32F7_I2C_CR2_RD_WRN; 953 f7_msg->read_write = I2C_SMBUS_READ; 954 break; 955 case I2C_SMBUS_I2C_BLOCK_DATA: 956 /* Rely on emulated i2c transfer (through master_xfer) */ 957 return -EOPNOTSUPP; 958 default: 959 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size); 960 return -EOPNOTSUPP; 961 } 962 963 f7_msg->buf = f7_msg->smbus_buf; 964 965 /* Configure PEC */ 966 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) { 967 cr1 |= STM32F7_I2C_CR1_PECEN; 968 cr2 |= STM32F7_I2C_CR2_PECBYTE; 969 if (!f7_msg->read_write) 970 f7_msg->count++; 971 } else { 972 cr1 &= ~STM32F7_I2C_CR1_PECEN; 973 cr2 &= ~STM32F7_I2C_CR2_PECBYTE; 974 } 975 976 /* Set number of bytes to be transferred */ 977 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD); 978 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 979 980 /* Enable NACK, STOP, error and transfer complete interrupts */ 981 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE | 982 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE; 983 984 /* Clear DMA req and TX/RX interrupt */ 985 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 986 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 987 988 /* Configure DMA or enable RX/TX interrupt */ 989 i2c_dev->use_dma = false; 990 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) { 991 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 992 cr2 & STM32F7_I2C_CR2_RD_WRN, 993 f7_msg->count, f7_msg->buf, 994 stm32f7_i2c_dma_callback, 995 i2c_dev); 996 if (!ret) 997 i2c_dev->use_dma = true; 998 else 999 dev_warn(i2c_dev->dev, "can't use DMA\n"); 1000 } 1001 1002 if (!i2c_dev->use_dma) { 1003 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1004 cr1 |= STM32F7_I2C_CR1_RXIE; 1005 else 1006 cr1 |= STM32F7_I2C_CR1_TXIE; 1007 } else { 1008 if (cr2 & STM32F7_I2C_CR2_RD_WRN) 1009 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1010 else 1011 cr1 |= STM32F7_I2C_CR1_TXDMAEN; 1012 } 1013 1014 /* Set Start bit */ 1015 cr2 |= STM32F7_I2C_CR2_START; 1016 1017 i2c_dev->master_mode = true; 1018 1019 /* Write configurations registers */ 1020 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1021 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1022 1023 return 0; 1024 } 1025 1026 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev) 1027 { 1028 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1029 void __iomem *base = i2c_dev->base; 1030 u32 cr1, cr2; 1031 int ret; 1032 1033 cr2 = readl_relaxed(base + STM32F7_I2C_CR2); 1034 cr1 = readl_relaxed(base + STM32F7_I2C_CR1); 1035 1036 /* Set transfer direction */ 1037 cr2 |= STM32F7_I2C_CR2_RD_WRN; 1038 1039 switch (f7_msg->size) { 1040 case I2C_SMBUS_BYTE_DATA: 1041 f7_msg->count = 1; 1042 break; 1043 case I2C_SMBUS_WORD_DATA: 1044 case I2C_SMBUS_PROC_CALL: 1045 f7_msg->count = 2; 1046 break; 1047 case I2C_SMBUS_BLOCK_DATA: 1048 case I2C_SMBUS_BLOCK_PROC_CALL: 1049 f7_msg->count = 1; 1050 cr2 |= STM32F7_I2C_CR2_RELOAD; 1051 break; 1052 } 1053 1054 f7_msg->buf = f7_msg->smbus_buf; 1055 f7_msg->stop = true; 1056 1057 /* Add one byte for PEC if needed */ 1058 if (cr1 & STM32F7_I2C_CR1_PECEN) 1059 f7_msg->count++; 1060 1061 /* Set number of bytes to be transferred */ 1062 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK); 1063 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count); 1064 1065 /* 1066 * Configure RX/TX interrupt: 1067 */ 1068 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE); 1069 cr1 |= STM32F7_I2C_CR1_RXIE; 1070 1071 /* 1072 * Configure DMA or enable RX/TX interrupt: 1073 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use 1074 * dma as we don't know in advance how many data will be received 1075 */ 1076 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE | 1077 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN); 1078 1079 i2c_dev->use_dma = false; 1080 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN && 1081 f7_msg->size != I2C_SMBUS_BLOCK_DATA && 1082 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) { 1083 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma, 1084 cr2 & STM32F7_I2C_CR2_RD_WRN, 1085 f7_msg->count, f7_msg->buf, 1086 stm32f7_i2c_dma_callback, 1087 i2c_dev); 1088 1089 if (!ret) 1090 i2c_dev->use_dma = true; 1091 else 1092 dev_warn(i2c_dev->dev, "can't use DMA\n"); 1093 } 1094 1095 if (!i2c_dev->use_dma) 1096 cr1 |= STM32F7_I2C_CR1_RXIE; 1097 else 1098 cr1 |= STM32F7_I2C_CR1_RXDMAEN; 1099 1100 /* Configure Repeated Start */ 1101 cr2 |= STM32F7_I2C_CR2_START; 1102 1103 /* Write configurations registers */ 1104 writel_relaxed(cr1, base + STM32F7_I2C_CR1); 1105 writel_relaxed(cr2, base + STM32F7_I2C_CR2); 1106 } 1107 1108 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev) 1109 { 1110 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1111 u8 count, internal_pec, received_pec; 1112 1113 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR); 1114 1115 switch (f7_msg->size) { 1116 case I2C_SMBUS_BYTE: 1117 case I2C_SMBUS_BYTE_DATA: 1118 received_pec = f7_msg->smbus_buf[1]; 1119 break; 1120 case I2C_SMBUS_WORD_DATA: 1121 case I2C_SMBUS_PROC_CALL: 1122 received_pec = f7_msg->smbus_buf[2]; 1123 break; 1124 case I2C_SMBUS_BLOCK_DATA: 1125 case I2C_SMBUS_BLOCK_PROC_CALL: 1126 count = f7_msg->smbus_buf[0]; 1127 received_pec = f7_msg->smbus_buf[count]; 1128 break; 1129 default: 1130 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n"); 1131 return -EINVAL; 1132 } 1133 1134 if (internal_pec != received_pec) { 1135 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n", 1136 internal_pec, received_pec); 1137 return -EBADMSG; 1138 } 1139 1140 return 0; 1141 } 1142 1143 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode) 1144 { 1145 u32 addr; 1146 1147 if (!slave) 1148 return false; 1149 1150 if (slave->flags & I2C_CLIENT_TEN) { 1151 /* 1152 * For 10-bit addr, addcode = 11110XY with 1153 * X = Bit 9 of slave address 1154 * Y = Bit 8 of slave address 1155 */ 1156 addr = slave->addr >> 8; 1157 addr |= 0x78; 1158 if (addr == addcode) 1159 return true; 1160 } else { 1161 addr = slave->addr & 0x7f; 1162 if (addr == addcode) 1163 return true; 1164 } 1165 1166 return false; 1167 } 1168 1169 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev) 1170 { 1171 struct i2c_client *slave = i2c_dev->slave_running; 1172 void __iomem *base = i2c_dev->base; 1173 u32 mask; 1174 u8 value = 0; 1175 1176 if (i2c_dev->slave_dir) { 1177 /* Notify i2c slave that new read transfer is starting */ 1178 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 1179 1180 /* 1181 * Disable slave TX config in case of I2C combined message 1182 * (I2C Write followed by I2C Read) 1183 */ 1184 mask = STM32F7_I2C_CR2_RELOAD; 1185 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask); 1186 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1187 STM32F7_I2C_CR1_TCIE; 1188 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask); 1189 1190 /* Enable TX empty, STOP, NACK interrupts */ 1191 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1192 STM32F7_I2C_CR1_TXIE; 1193 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1194 1195 } else { 1196 /* Notify i2c slave that new write transfer is starting */ 1197 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1198 1199 /* Set reload mode to be able to ACK/NACK each received byte */ 1200 mask = STM32F7_I2C_CR2_RELOAD; 1201 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1202 1203 /* 1204 * Set STOP, NACK, RX empty and transfer complete interrupts.* 1205 * Set Slave Byte Control to be able to ACK/NACK each data 1206 * byte received 1207 */ 1208 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE | 1209 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE | 1210 STM32F7_I2C_CR1_TCIE; 1211 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1212 } 1213 } 1214 1215 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev) 1216 { 1217 void __iomem *base = i2c_dev->base; 1218 u32 isr, addcode, dir, mask; 1219 int i; 1220 1221 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1222 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr); 1223 dir = isr & STM32F7_I2C_ISR_DIR; 1224 1225 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1226 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) { 1227 i2c_dev->slave_running = i2c_dev->slave[i]; 1228 i2c_dev->slave_dir = dir; 1229 1230 /* Start I2C slave processing */ 1231 stm32f7_i2c_slave_start(i2c_dev); 1232 1233 /* Clear ADDR flag */ 1234 mask = STM32F7_I2C_ICR_ADDRCF; 1235 writel_relaxed(mask, base + STM32F7_I2C_ICR); 1236 break; 1237 } 1238 } 1239 } 1240 1241 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1242 struct i2c_client *slave, int *id) 1243 { 1244 int i; 1245 1246 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1247 if (i2c_dev->slave[i] == slave) { 1248 *id = i; 1249 return 0; 1250 } 1251 } 1252 1253 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr); 1254 1255 return -ENODEV; 1256 } 1257 1258 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev, 1259 struct i2c_client *slave, int *id) 1260 { 1261 struct device *dev = i2c_dev->dev; 1262 int i; 1263 1264 /* 1265 * slave[0] supports 7-bit and 10-bit slave address 1266 * slave[1] supports 7-bit slave address only 1267 */ 1268 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1269 if (i == 1 && (slave->flags & I2C_CLIENT_PEC)) 1270 continue; 1271 if (!i2c_dev->slave[i]) { 1272 *id = i; 1273 return 0; 1274 } 1275 } 1276 1277 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr); 1278 1279 return -EINVAL; 1280 } 1281 1282 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev) 1283 { 1284 int i; 1285 1286 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1287 if (i2c_dev->slave[i]) 1288 return true; 1289 } 1290 1291 return false; 1292 } 1293 1294 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev) 1295 { 1296 int i, busy; 1297 1298 busy = 0; 1299 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) { 1300 if (i2c_dev->slave[i]) 1301 busy++; 1302 } 1303 1304 return i == busy; 1305 } 1306 1307 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev) 1308 { 1309 void __iomem *base = i2c_dev->base; 1310 u32 cr2, status, mask; 1311 u8 val; 1312 int ret; 1313 1314 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1315 1316 /* Slave transmitter mode */ 1317 if (status & STM32F7_I2C_ISR_TXIS) { 1318 i2c_slave_event(i2c_dev->slave_running, 1319 I2C_SLAVE_READ_PROCESSED, 1320 &val); 1321 1322 /* Write data byte */ 1323 writel_relaxed(val, base + STM32F7_I2C_TXDR); 1324 } 1325 1326 /* Transfer Complete Reload for Slave receiver mode */ 1327 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) { 1328 /* 1329 * Read data byte then set NBYTES to receive next byte or NACK 1330 * the current received byte 1331 */ 1332 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR); 1333 ret = i2c_slave_event(i2c_dev->slave_running, 1334 I2C_SLAVE_WRITE_RECEIVED, 1335 &val); 1336 if (!ret) { 1337 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2); 1338 cr2 |= STM32F7_I2C_CR2_NBYTES(1); 1339 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2); 1340 } else { 1341 mask = STM32F7_I2C_CR2_NACK; 1342 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1343 } 1344 } 1345 1346 /* NACK received */ 1347 if (status & STM32F7_I2C_ISR_NACKF) { 1348 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__); 1349 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1350 } 1351 1352 /* STOP received */ 1353 if (status & STM32F7_I2C_ISR_STOPF) { 1354 /* Disable interrupts */ 1355 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK); 1356 1357 if (i2c_dev->slave_dir) { 1358 /* 1359 * Flush TX buffer in order to not used the byte in 1360 * TXDR for the next transfer 1361 */ 1362 mask = STM32F7_I2C_ISR_TXE; 1363 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask); 1364 } 1365 1366 /* Clear STOP flag */ 1367 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1368 1369 /* Notify i2c slave that a STOP flag has been detected */ 1370 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val); 1371 1372 i2c_dev->slave_running = NULL; 1373 } 1374 1375 /* Address match received */ 1376 if (status & STM32F7_I2C_ISR_ADDR) 1377 stm32f7_i2c_slave_addr(i2c_dev); 1378 1379 return IRQ_HANDLED; 1380 } 1381 1382 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data) 1383 { 1384 struct stm32f7_i2c_dev *i2c_dev = data; 1385 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1386 void __iomem *base = i2c_dev->base; 1387 u32 status, mask; 1388 int ret = IRQ_HANDLED; 1389 1390 /* Check if the interrupt if for a slave device */ 1391 if (!i2c_dev->master_mode) { 1392 ret = stm32f7_i2c_slave_isr_event(i2c_dev); 1393 return ret; 1394 } 1395 1396 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1397 1398 /* Tx empty */ 1399 if (status & STM32F7_I2C_ISR_TXIS) 1400 stm32f7_i2c_write_tx_data(i2c_dev); 1401 1402 /* RX not empty */ 1403 if (status & STM32F7_I2C_ISR_RXNE) 1404 stm32f7_i2c_read_rx_data(i2c_dev); 1405 1406 /* NACK received */ 1407 if (status & STM32F7_I2C_ISR_NACKF) { 1408 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__); 1409 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR); 1410 f7_msg->result = -ENXIO; 1411 } 1412 1413 /* STOP detection flag */ 1414 if (status & STM32F7_I2C_ISR_STOPF) { 1415 /* Disable interrupts */ 1416 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1417 mask = STM32F7_I2C_XFER_IRQ_MASK; 1418 else 1419 mask = STM32F7_I2C_ALL_IRQ_MASK; 1420 stm32f7_i2c_disable_irq(i2c_dev, mask); 1421 1422 /* Clear STOP flag */ 1423 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR); 1424 1425 if (i2c_dev->use_dma) { 1426 ret = IRQ_WAKE_THREAD; 1427 } else { 1428 i2c_dev->master_mode = false; 1429 complete(&i2c_dev->complete); 1430 } 1431 } 1432 1433 /* Transfer complete */ 1434 if (status & STM32F7_I2C_ISR_TC) { 1435 if (f7_msg->stop) { 1436 mask = STM32F7_I2C_CR2_STOP; 1437 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask); 1438 } else if (i2c_dev->use_dma) { 1439 ret = IRQ_WAKE_THREAD; 1440 } else if (f7_msg->smbus) { 1441 stm32f7_i2c_smbus_rep_start(i2c_dev); 1442 } else { 1443 i2c_dev->msg_id++; 1444 i2c_dev->msg++; 1445 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); 1446 } 1447 } 1448 1449 if (status & STM32F7_I2C_ISR_TCR) { 1450 if (f7_msg->smbus) 1451 stm32f7_i2c_smbus_reload(i2c_dev); 1452 else 1453 stm32f7_i2c_reload(i2c_dev); 1454 } 1455 1456 return ret; 1457 } 1458 1459 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data) 1460 { 1461 struct stm32f7_i2c_dev *i2c_dev = data; 1462 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1463 struct stm32_i2c_dma *dma = i2c_dev->dma; 1464 u32 status; 1465 int ret; 1466 1467 /* 1468 * Wait for dma transfer completion before sending next message or 1469 * notity the end of xfer to the client 1470 */ 1471 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ); 1472 if (!ret) { 1473 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__); 1474 stm32f7_i2c_disable_dma_req(i2c_dev); 1475 dmaengine_terminate_all(dma->chan_using); 1476 f7_msg->result = -ETIMEDOUT; 1477 } 1478 1479 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1480 1481 if (status & STM32F7_I2C_ISR_TC) { 1482 if (f7_msg->smbus) { 1483 stm32f7_i2c_smbus_rep_start(i2c_dev); 1484 } else { 1485 i2c_dev->msg_id++; 1486 i2c_dev->msg++; 1487 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg); 1488 } 1489 } else { 1490 i2c_dev->master_mode = false; 1491 complete(&i2c_dev->complete); 1492 } 1493 1494 return IRQ_HANDLED; 1495 } 1496 1497 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data) 1498 { 1499 struct stm32f7_i2c_dev *i2c_dev = data; 1500 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1501 void __iomem *base = i2c_dev->base; 1502 struct device *dev = i2c_dev->dev; 1503 struct stm32_i2c_dma *dma = i2c_dev->dma; 1504 u32 mask, status; 1505 1506 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR); 1507 1508 /* Bus error */ 1509 if (status & STM32F7_I2C_ISR_BERR) { 1510 dev_err(dev, "<%s>: Bus error\n", __func__); 1511 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR); 1512 stm32f7_i2c_release_bus(&i2c_dev->adap); 1513 f7_msg->result = -EIO; 1514 } 1515 1516 /* Arbitration loss */ 1517 if (status & STM32F7_I2C_ISR_ARLO) { 1518 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__); 1519 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR); 1520 f7_msg->result = -EAGAIN; 1521 } 1522 1523 if (status & STM32F7_I2C_ISR_PECERR) { 1524 dev_err(dev, "<%s>: PEC error in reception\n", __func__); 1525 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR); 1526 f7_msg->result = -EINVAL; 1527 } 1528 1529 /* Disable interrupts */ 1530 if (stm32f7_i2c_is_slave_registered(i2c_dev)) 1531 mask = STM32F7_I2C_XFER_IRQ_MASK; 1532 else 1533 mask = STM32F7_I2C_ALL_IRQ_MASK; 1534 stm32f7_i2c_disable_irq(i2c_dev, mask); 1535 1536 /* Disable dma */ 1537 if (i2c_dev->use_dma) { 1538 stm32f7_i2c_disable_dma_req(i2c_dev); 1539 dmaengine_terminate_all(dma->chan_using); 1540 } 1541 1542 i2c_dev->master_mode = false; 1543 complete(&i2c_dev->complete); 1544 1545 return IRQ_HANDLED; 1546 } 1547 1548 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap, 1549 struct i2c_msg msgs[], int num) 1550 { 1551 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap); 1552 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1553 struct stm32_i2c_dma *dma = i2c_dev->dma; 1554 unsigned long time_left; 1555 int ret; 1556 1557 i2c_dev->msg = msgs; 1558 i2c_dev->msg_num = num; 1559 i2c_dev->msg_id = 0; 1560 f7_msg->smbus = false; 1561 1562 ret = pm_runtime_get_sync(i2c_dev->dev); 1563 if (ret < 0) 1564 return ret; 1565 1566 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1567 if (ret) 1568 goto pm_free; 1569 1570 stm32f7_i2c_xfer_msg(i2c_dev, msgs); 1571 1572 time_left = wait_for_completion_timeout(&i2c_dev->complete, 1573 i2c_dev->adap.timeout); 1574 ret = f7_msg->result; 1575 1576 if (!time_left) { 1577 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n", 1578 i2c_dev->msg->addr); 1579 if (i2c_dev->use_dma) 1580 dmaengine_terminate_all(dma->chan_using); 1581 ret = -ETIMEDOUT; 1582 } 1583 1584 pm_free: 1585 pm_runtime_mark_last_busy(i2c_dev->dev); 1586 pm_runtime_put_autosuspend(i2c_dev->dev); 1587 1588 return (ret < 0) ? ret : num; 1589 } 1590 1591 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr, 1592 unsigned short flags, char read_write, 1593 u8 command, int size, 1594 union i2c_smbus_data *data) 1595 { 1596 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter); 1597 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg; 1598 struct stm32_i2c_dma *dma = i2c_dev->dma; 1599 struct device *dev = i2c_dev->dev; 1600 unsigned long timeout; 1601 int i, ret; 1602 1603 f7_msg->addr = addr; 1604 f7_msg->size = size; 1605 f7_msg->read_write = read_write; 1606 f7_msg->smbus = true; 1607 1608 ret = pm_runtime_get_sync(dev); 1609 if (ret < 0) 1610 return ret; 1611 1612 ret = stm32f7_i2c_wait_free_bus(i2c_dev); 1613 if (ret) 1614 goto pm_free; 1615 1616 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data); 1617 if (ret) 1618 goto pm_free; 1619 1620 timeout = wait_for_completion_timeout(&i2c_dev->complete, 1621 i2c_dev->adap.timeout); 1622 ret = f7_msg->result; 1623 if (ret) 1624 goto pm_free; 1625 1626 if (!timeout) { 1627 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr); 1628 if (i2c_dev->use_dma) 1629 dmaengine_terminate_all(dma->chan_using); 1630 ret = -ETIMEDOUT; 1631 goto pm_free; 1632 } 1633 1634 /* Check PEC */ 1635 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) { 1636 ret = stm32f7_i2c_smbus_check_pec(i2c_dev); 1637 if (ret) 1638 goto pm_free; 1639 } 1640 1641 if (read_write && size != I2C_SMBUS_QUICK) { 1642 switch (size) { 1643 case I2C_SMBUS_BYTE: 1644 case I2C_SMBUS_BYTE_DATA: 1645 data->byte = f7_msg->smbus_buf[0]; 1646 break; 1647 case I2C_SMBUS_WORD_DATA: 1648 case I2C_SMBUS_PROC_CALL: 1649 data->word = f7_msg->smbus_buf[0] | 1650 (f7_msg->smbus_buf[1] << 8); 1651 break; 1652 case I2C_SMBUS_BLOCK_DATA: 1653 case I2C_SMBUS_BLOCK_PROC_CALL: 1654 for (i = 0; i <= f7_msg->smbus_buf[0]; i++) 1655 data->block[i] = f7_msg->smbus_buf[i]; 1656 break; 1657 default: 1658 dev_err(dev, "Unsupported smbus transaction\n"); 1659 ret = -EINVAL; 1660 } 1661 } 1662 1663 pm_free: 1664 pm_runtime_mark_last_busy(dev); 1665 pm_runtime_put_autosuspend(dev); 1666 return ret; 1667 } 1668 1669 static int stm32f7_i2c_reg_slave(struct i2c_client *slave) 1670 { 1671 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1672 void __iomem *base = i2c_dev->base; 1673 struct device *dev = i2c_dev->dev; 1674 u32 oar1, oar2, mask; 1675 int id, ret; 1676 1677 if (slave->flags & I2C_CLIENT_PEC) { 1678 dev_err(dev, "SMBus PEC not supported in slave mode\n"); 1679 return -EINVAL; 1680 } 1681 1682 if (stm32f7_i2c_is_slave_busy(i2c_dev)) { 1683 dev_err(dev, "Too much slave registered\n"); 1684 return -EBUSY; 1685 } 1686 1687 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id); 1688 if (ret) 1689 return ret; 1690 1691 ret = pm_runtime_get_sync(dev); 1692 if (ret < 0) 1693 return ret; 1694 1695 if (id == 0) { 1696 /* Configure Own Address 1 */ 1697 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1); 1698 oar1 &= ~STM32F7_I2C_OAR1_MASK; 1699 if (slave->flags & I2C_CLIENT_TEN) { 1700 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr); 1701 oar1 |= STM32F7_I2C_OAR1_OA1MODE; 1702 } else { 1703 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr); 1704 } 1705 oar1 |= STM32F7_I2C_OAR1_OA1EN; 1706 i2c_dev->slave[id] = slave; 1707 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1); 1708 } else if (id == 1) { 1709 /* Configure Own Address 2 */ 1710 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2); 1711 oar2 &= ~STM32F7_I2C_OAR2_MASK; 1712 if (slave->flags & I2C_CLIENT_TEN) { 1713 ret = -EOPNOTSUPP; 1714 goto pm_free; 1715 } 1716 1717 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr); 1718 oar2 |= STM32F7_I2C_OAR2_OA2EN; 1719 i2c_dev->slave[id] = slave; 1720 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2); 1721 } else { 1722 ret = -ENODEV; 1723 goto pm_free; 1724 } 1725 1726 /* Enable ACK */ 1727 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK); 1728 1729 /* Enable Address match interrupt, error interrupt and enable I2C */ 1730 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE | 1731 STM32F7_I2C_CR1_PE; 1732 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask); 1733 1734 ret = 0; 1735 pm_free: 1736 pm_runtime_mark_last_busy(dev); 1737 pm_runtime_put_autosuspend(dev); 1738 1739 return ret; 1740 } 1741 1742 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave) 1743 { 1744 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter); 1745 void __iomem *base = i2c_dev->base; 1746 u32 mask; 1747 int id, ret; 1748 1749 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id); 1750 if (ret) 1751 return ret; 1752 1753 WARN_ON(!i2c_dev->slave[id]); 1754 1755 ret = pm_runtime_get_sync(i2c_dev->dev); 1756 if (ret < 0) 1757 return ret; 1758 1759 if (id == 0) { 1760 mask = STM32F7_I2C_OAR1_OA1EN; 1761 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask); 1762 } else { 1763 mask = STM32F7_I2C_OAR2_OA2EN; 1764 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask); 1765 } 1766 1767 i2c_dev->slave[id] = NULL; 1768 1769 if (!(stm32f7_i2c_is_slave_registered(i2c_dev))) 1770 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK); 1771 1772 pm_runtime_mark_last_busy(i2c_dev->dev); 1773 pm_runtime_put_autosuspend(i2c_dev->dev); 1774 1775 return 0; 1776 } 1777 1778 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev, 1779 struct stm32f7_i2c_dev *i2c_dev) 1780 { 1781 struct device_node *np = pdev->dev.of_node; 1782 int ret; 1783 u32 reg, mask; 1784 1785 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp"); 1786 if (IS_ERR(i2c_dev->regmap)) { 1787 /* Optional */ 1788 return 0; 1789 } 1790 1791 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1, ®); 1792 if (ret) 1793 return ret; 1794 1795 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 2, &mask); 1796 if (ret) 1797 return ret; 1798 1799 return regmap_update_bits(i2c_dev->regmap, reg, mask, mask); 1800 } 1801 1802 static u32 stm32f7_i2c_func(struct i2c_adapter *adap) 1803 { 1804 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE | 1805 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 1806 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 1807 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 1808 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC | 1809 I2C_FUNC_SMBUS_I2C_BLOCK; 1810 } 1811 1812 static const struct i2c_algorithm stm32f7_i2c_algo = { 1813 .master_xfer = stm32f7_i2c_xfer, 1814 .smbus_xfer = stm32f7_i2c_smbus_xfer, 1815 .functionality = stm32f7_i2c_func, 1816 .reg_slave = stm32f7_i2c_reg_slave, 1817 .unreg_slave = stm32f7_i2c_unreg_slave, 1818 }; 1819 1820 static int stm32f7_i2c_probe(struct platform_device *pdev) 1821 { 1822 struct stm32f7_i2c_dev *i2c_dev; 1823 const struct stm32f7_i2c_setup *setup; 1824 struct resource *res; 1825 u32 clk_rate, rise_time, fall_time; 1826 struct i2c_adapter *adap; 1827 struct reset_control *rst; 1828 dma_addr_t phy_addr; 1829 int irq_error, irq_event, ret; 1830 1831 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 1832 if (!i2c_dev) 1833 return -ENOMEM; 1834 1835 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1836 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); 1837 if (IS_ERR(i2c_dev->base)) 1838 return PTR_ERR(i2c_dev->base); 1839 phy_addr = (dma_addr_t)res->start; 1840 1841 irq_event = platform_get_irq(pdev, 0); 1842 if (irq_event <= 0) { 1843 if (irq_event != -EPROBE_DEFER) 1844 dev_err(&pdev->dev, "Failed to get IRQ event: %d\n", 1845 irq_event); 1846 return irq_event ? : -ENOENT; 1847 } 1848 1849 irq_error = platform_get_irq(pdev, 1); 1850 if (irq_error <= 0) { 1851 if (irq_error != -EPROBE_DEFER) 1852 dev_err(&pdev->dev, "Failed to get IRQ error: %d\n", 1853 irq_error); 1854 return irq_error ? : -ENOENT; 1855 } 1856 1857 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL); 1858 if (IS_ERR(i2c_dev->clk)) { 1859 dev_err(&pdev->dev, "Error: Missing controller clock\n"); 1860 return PTR_ERR(i2c_dev->clk); 1861 } 1862 1863 ret = clk_prepare_enable(i2c_dev->clk); 1864 if (ret) { 1865 dev_err(&pdev->dev, "Failed to prepare_enable clock\n"); 1866 return ret; 1867 } 1868 1869 i2c_dev->speed = STM32_I2C_SPEED_STANDARD; 1870 ret = device_property_read_u32(&pdev->dev, "clock-frequency", 1871 &clk_rate); 1872 if (!ret && clk_rate >= 1000000) { 1873 i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS; 1874 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev); 1875 if (ret) 1876 goto clk_free; 1877 } else if (!ret && clk_rate >= 400000) { 1878 i2c_dev->speed = STM32_I2C_SPEED_FAST; 1879 } else if (!ret && clk_rate >= 100000) { 1880 i2c_dev->speed = STM32_I2C_SPEED_STANDARD; 1881 } 1882 1883 rst = devm_reset_control_get(&pdev->dev, NULL); 1884 if (IS_ERR(rst)) { 1885 dev_err(&pdev->dev, "Error: Missing controller reset\n"); 1886 ret = PTR_ERR(rst); 1887 goto clk_free; 1888 } 1889 reset_control_assert(rst); 1890 udelay(2); 1891 reset_control_deassert(rst); 1892 1893 i2c_dev->dev = &pdev->dev; 1894 1895 ret = devm_request_threaded_irq(&pdev->dev, irq_event, 1896 stm32f7_i2c_isr_event, 1897 stm32f7_i2c_isr_event_thread, 1898 IRQF_ONESHOT, 1899 pdev->name, i2c_dev); 1900 if (ret) { 1901 dev_err(&pdev->dev, "Failed to request irq event %i\n", 1902 irq_event); 1903 goto clk_free; 1904 } 1905 1906 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0, 1907 pdev->name, i2c_dev); 1908 if (ret) { 1909 dev_err(&pdev->dev, "Failed to request irq error %i\n", 1910 irq_error); 1911 goto clk_free; 1912 } 1913 1914 setup = of_device_get_match_data(&pdev->dev); 1915 if (!setup) { 1916 dev_err(&pdev->dev, "Can't get device data\n"); 1917 ret = -ENODEV; 1918 goto clk_free; 1919 } 1920 i2c_dev->setup = *setup; 1921 1922 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-rising-time-ns", 1923 &rise_time); 1924 if (!ret) 1925 i2c_dev->setup.rise_time = rise_time; 1926 1927 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-falling-time-ns", 1928 &fall_time); 1929 if (!ret) 1930 i2c_dev->setup.fall_time = fall_time; 1931 1932 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup); 1933 if (ret) 1934 goto clk_free; 1935 1936 adap = &i2c_dev->adap; 1937 i2c_set_adapdata(adap, i2c_dev); 1938 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)", 1939 &res->start); 1940 adap->owner = THIS_MODULE; 1941 adap->timeout = 2 * HZ; 1942 adap->retries = 3; 1943 adap->algo = &stm32f7_i2c_algo; 1944 adap->dev.parent = &pdev->dev; 1945 adap->dev.of_node = pdev->dev.of_node; 1946 1947 init_completion(&i2c_dev->complete); 1948 1949 /* Init DMA config if supported */ 1950 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr, 1951 STM32F7_I2C_TXDR, 1952 STM32F7_I2C_RXDR); 1953 1954 platform_set_drvdata(pdev, i2c_dev); 1955 1956 pm_runtime_set_autosuspend_delay(i2c_dev->dev, 1957 STM32F7_AUTOSUSPEND_DELAY); 1958 pm_runtime_use_autosuspend(i2c_dev->dev); 1959 pm_runtime_set_active(i2c_dev->dev); 1960 pm_runtime_enable(i2c_dev->dev); 1961 1962 pm_runtime_get_noresume(&pdev->dev); 1963 1964 stm32f7_i2c_hw_config(i2c_dev); 1965 1966 ret = i2c_add_adapter(adap); 1967 if (ret) 1968 goto pm_disable; 1969 1970 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr); 1971 1972 pm_runtime_mark_last_busy(i2c_dev->dev); 1973 pm_runtime_put_autosuspend(i2c_dev->dev); 1974 1975 return 0; 1976 1977 pm_disable: 1978 pm_runtime_put_noidle(i2c_dev->dev); 1979 pm_runtime_disable(i2c_dev->dev); 1980 pm_runtime_set_suspended(i2c_dev->dev); 1981 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 1982 1983 clk_free: 1984 clk_disable_unprepare(i2c_dev->clk); 1985 1986 return ret; 1987 } 1988 1989 static int stm32f7_i2c_remove(struct platform_device *pdev) 1990 { 1991 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 1992 1993 if (i2c_dev->dma) { 1994 stm32_i2c_dma_free(i2c_dev->dma); 1995 i2c_dev->dma = NULL; 1996 } 1997 1998 i2c_del_adapter(&i2c_dev->adap); 1999 pm_runtime_get_sync(i2c_dev->dev); 2000 2001 clk_disable_unprepare(i2c_dev->clk); 2002 2003 pm_runtime_put_noidle(i2c_dev->dev); 2004 pm_runtime_disable(i2c_dev->dev); 2005 pm_runtime_set_suspended(i2c_dev->dev); 2006 pm_runtime_dont_use_autosuspend(i2c_dev->dev); 2007 2008 return 0; 2009 } 2010 2011 #ifdef CONFIG_PM 2012 static int stm32f7_i2c_runtime_suspend(struct device *dev) 2013 { 2014 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2015 2016 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) 2017 clk_disable_unprepare(i2c_dev->clk); 2018 2019 return 0; 2020 } 2021 2022 static int stm32f7_i2c_runtime_resume(struct device *dev) 2023 { 2024 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev); 2025 int ret; 2026 2027 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) { 2028 ret = clk_prepare_enable(i2c_dev->clk); 2029 if (ret) { 2030 dev_err(dev, "failed to prepare_enable clock\n"); 2031 return ret; 2032 } 2033 } 2034 2035 return 0; 2036 } 2037 #endif 2038 2039 static const struct dev_pm_ops stm32f7_i2c_pm_ops = { 2040 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend, 2041 stm32f7_i2c_runtime_resume, NULL) 2042 }; 2043 2044 static const struct of_device_id stm32f7_i2c_match[] = { 2045 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup}, 2046 {}, 2047 }; 2048 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match); 2049 2050 static struct platform_driver stm32f7_i2c_driver = { 2051 .driver = { 2052 .name = "stm32f7-i2c", 2053 .of_match_table = stm32f7_i2c_match, 2054 .pm = &stm32f7_i2c_pm_ops, 2055 }, 2056 .probe = stm32f7_i2c_probe, 2057 .remove = stm32f7_i2c_remove, 2058 }; 2059 2060 module_platform_driver(stm32f7_i2c_driver); 2061 2062 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>"); 2063 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver"); 2064 MODULE_LICENSE("GPL v2"); 2065