1 /* 2 * Copyright 2012-14 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "grph_object_defs.h" 31 #include "logger_types.h" 32 #if defined(CONFIG_DRM_AMD_DC_HDCP) 33 #include "hdcp_types.h" 34 #endif 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "inc/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #define DC_VER "3.2.84" 46 47 #define MAX_SURFACES 3 48 #define MAX_PLANES 6 49 #define MAX_STREAMS 6 50 #define MAX_SINKS_PER_LINK 4 51 52 /******************************************************************************* 53 * Display Core Interfaces 54 ******************************************************************************/ 55 struct dc_versions { 56 const char *dc_ver; 57 struct dmcu_version dmcu_version; 58 }; 59 60 enum dp_protocol_version { 61 DP_VERSION_1_4, 62 }; 63 64 enum dc_plane_type { 65 DC_PLANE_TYPE_INVALID, 66 DC_PLANE_TYPE_DCE_RGB, 67 DC_PLANE_TYPE_DCE_UNDERLAY, 68 DC_PLANE_TYPE_DCN_UNIVERSAL, 69 }; 70 71 struct dc_plane_cap { 72 enum dc_plane_type type; 73 uint32_t blends_with_above : 1; 74 uint32_t blends_with_below : 1; 75 uint32_t per_pixel_alpha : 1; 76 struct { 77 uint32_t argb8888 : 1; 78 uint32_t nv12 : 1; 79 uint32_t fp16 : 1; 80 uint32_t p010 : 1; 81 uint32_t ayuv : 1; 82 } pixel_format_support; 83 // max upscaling factor x1000 84 // upscaling factors are always >= 1 85 // for example, 1080p -> 8K is 4.0, or 4000 raw value 86 struct { 87 uint32_t argb8888; 88 uint32_t nv12; 89 uint32_t fp16; 90 } max_upscale_factor; 91 // max downscale factor x1000 92 // downscale factors are always <= 1 93 // for example, 8K -> 1080p is 0.25, or 250 raw value 94 struct { 95 uint32_t argb8888; 96 uint32_t nv12; 97 uint32_t fp16; 98 } max_downscale_factor; 99 }; 100 101 // Color management caps (DPP and MPC) 102 struct rom_curve_caps { 103 uint16_t srgb : 1; 104 uint16_t bt2020 : 1; 105 uint16_t gamma2_2 : 1; 106 uint16_t pq : 1; 107 uint16_t hlg : 1; 108 }; 109 110 struct dpp_color_caps { 111 uint16_t dcn_arch : 1; // all DCE generations treated the same 112 // input lut is different than most LUTs, just plain 256-entry lookup 113 uint16_t input_lut_shared : 1; // shared with DGAM 114 uint16_t icsc : 1; 115 uint16_t dgam_ram : 1; 116 uint16_t post_csc : 1; // before gamut remap 117 uint16_t gamma_corr : 1; 118 119 // hdr_mult and gamut remap always available in DPP (in that order) 120 // 3d lut implies shaper LUT, 121 // it may be shared with MPC - check MPC:shared_3d_lut flag 122 uint16_t hw_3d_lut : 1; 123 uint16_t ogam_ram : 1; // blnd gam 124 uint16_t ocsc : 1; 125 struct rom_curve_caps dgam_rom_caps; 126 struct rom_curve_caps ogam_rom_caps; 127 }; 128 129 struct mpc_color_caps { 130 uint16_t gamut_remap : 1; 131 uint16_t ogam_ram : 1; 132 uint16_t ocsc : 1; 133 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT 134 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance 135 136 struct rom_curve_caps ogam_rom_caps; 137 }; 138 139 struct dc_color_caps { 140 struct dpp_color_caps dpp; 141 struct mpc_color_caps mpc; 142 }; 143 144 struct dc_caps { 145 uint32_t max_streams; 146 uint32_t max_links; 147 uint32_t max_audios; 148 uint32_t max_slave_planes; 149 uint32_t max_planes; 150 uint32_t max_downscale_ratio; 151 uint32_t i2c_speed_in_khz; 152 uint32_t dmdata_alloc_size; 153 unsigned int max_cursor_size; 154 unsigned int max_video_width; 155 int linear_pitch_alignment; 156 bool dcc_const_color; 157 bool dynamic_audio; 158 bool is_apu; 159 bool dual_link_dvi; 160 bool post_blend_color_processing; 161 bool force_dp_tps4_for_cp2520; 162 bool disable_dp_clk_share; 163 bool psp_setup_panel_mode; 164 bool extended_aux_timeout_support; 165 bool dmcub_support; 166 enum dp_protocol_version max_dp_protocol_version; 167 struct dc_plane_cap planes[MAX_PLANES]; 168 struct dc_color_caps color; 169 }; 170 171 struct dc_bug_wa { 172 bool no_connect_phy_config; 173 bool dedcn20_305_wa; 174 bool skip_clock_update; 175 bool lt_early_cr_pattern; 176 }; 177 178 struct dc_dcc_surface_param { 179 struct dc_size surface_size; 180 enum surface_pixel_format format; 181 enum swizzle_mode_values swizzle_mode; 182 enum dc_scan_direction scan; 183 }; 184 185 struct dc_dcc_setting { 186 unsigned int max_compressed_blk_size; 187 unsigned int max_uncompressed_blk_size; 188 bool independent_64b_blks; 189 }; 190 191 struct dc_surface_dcc_cap { 192 union { 193 struct { 194 struct dc_dcc_setting rgb; 195 } grph; 196 197 struct { 198 struct dc_dcc_setting luma; 199 struct dc_dcc_setting chroma; 200 } video; 201 }; 202 203 bool capable; 204 bool const_color_support; 205 }; 206 207 struct dc_static_screen_params { 208 struct { 209 bool force_trigger; 210 bool cursor_update; 211 bool surface_update; 212 bool overlay_update; 213 } triggers; 214 unsigned int num_frames; 215 }; 216 217 218 /* Surface update type is used by dc_update_surfaces_and_stream 219 * The update type is determined at the very beginning of the function based 220 * on parameters passed in and decides how much programming (or updating) is 221 * going to be done during the call. 222 * 223 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 224 * logical calculations or hardware register programming. This update MUST be 225 * ISR safe on windows. Currently fast update will only be used to flip surface 226 * address. 227 * 228 * UPDATE_TYPE_MED is used for slower updates which require significant hw 229 * re-programming however do not affect bandwidth consumption or clock 230 * requirements. At present, this is the level at which front end updates 231 * that do not require us to run bw_calcs happen. These are in/out transfer func 232 * updates, viewport offset changes, recout size changes and pixel depth changes. 233 * This update can be done at ISR, but we want to minimize how often this happens. 234 * 235 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 236 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 237 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 238 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 239 * a full update. This cannot be done at ISR level and should be a rare event. 240 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 241 * underscan we don't expect to see this call at all. 242 */ 243 244 enum surface_update_type { 245 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 246 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 247 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 248 }; 249 250 /* Forward declaration*/ 251 struct dc; 252 struct dc_plane_state; 253 struct dc_state; 254 255 256 struct dc_cap_funcs { 257 bool (*get_dcc_compression_cap)(const struct dc *dc, 258 const struct dc_dcc_surface_param *input, 259 struct dc_surface_dcc_cap *output); 260 }; 261 262 struct link_training_settings; 263 264 265 /* Structure to hold configuration flags set by dm at dc creation. */ 266 struct dc_config { 267 bool gpu_vm_support; 268 bool disable_disp_pll_sharing; 269 bool fbc_support; 270 bool optimize_edp_link_rate; 271 bool disable_fractional_pwm; 272 bool allow_seamless_boot_optimization; 273 bool power_down_display_on_boot; 274 bool edp_not_connected; 275 bool force_enum_edp; 276 bool forced_clocks; 277 bool disable_extended_timeout_support; // Used to disable extended timeout and lttpr feature as well 278 bool multi_mon_pp_mclk_switch; 279 bool disable_dmcu; 280 bool enable_4to1MPC; 281 }; 282 283 enum visual_confirm { 284 VISUAL_CONFIRM_DISABLE = 0, 285 VISUAL_CONFIRM_SURFACE = 1, 286 VISUAL_CONFIRM_HDR = 2, 287 VISUAL_CONFIRM_MPCTREE = 4, 288 VISUAL_CONFIRM_PSR = 5, 289 }; 290 291 enum dcc_option { 292 DCC_ENABLE = 0, 293 DCC_DISABLE = 1, 294 DCC_HALF_REQ_DISALBE = 2, 295 }; 296 297 enum pipe_split_policy { 298 MPC_SPLIT_DYNAMIC = 0, 299 MPC_SPLIT_AVOID = 1, 300 MPC_SPLIT_AVOID_MULT_DISP = 2, 301 }; 302 303 enum wm_report_mode { 304 WM_REPORT_DEFAULT = 0, 305 WM_REPORT_OVERRIDE = 1, 306 }; 307 enum dtm_pstate{ 308 dtm_level_p0 = 0,/*highest voltage*/ 309 dtm_level_p1, 310 dtm_level_p2, 311 dtm_level_p3, 312 dtm_level_p4,/*when active_display_count = 0*/ 313 }; 314 315 enum dcn_pwr_state { 316 DCN_PWR_STATE_UNKNOWN = -1, 317 DCN_PWR_STATE_MISSION_MODE = 0, 318 DCN_PWR_STATE_LOW_POWER = 3, 319 }; 320 321 /* 322 * For any clocks that may differ per pipe 323 * only the max is stored in this structure 324 */ 325 struct dc_clocks { 326 int dispclk_khz; 327 int dppclk_khz; 328 int dcfclk_khz; 329 int socclk_khz; 330 int dcfclk_deep_sleep_khz; 331 int fclk_khz; 332 int phyclk_khz; 333 int dramclk_khz; 334 bool p_state_change_support; 335 enum dcn_pwr_state pwr_state; 336 /* 337 * Elements below are not compared for the purposes of 338 * optimization required 339 */ 340 bool prev_p_state_change_support; 341 enum dtm_pstate dtm_level; 342 int max_supported_dppclk_khz; 343 int max_supported_dispclk_khz; 344 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 345 int bw_dispclk_khz; 346 }; 347 348 struct dc_bw_validation_profile { 349 bool enable; 350 351 unsigned long long total_ticks; 352 unsigned long long voltage_level_ticks; 353 unsigned long long watermark_ticks; 354 unsigned long long rq_dlg_ticks; 355 356 unsigned long long total_count; 357 unsigned long long skip_fast_count; 358 unsigned long long skip_pass_count; 359 unsigned long long skip_fail_count; 360 }; 361 362 #define BW_VAL_TRACE_SETUP() \ 363 unsigned long long end_tick = 0; \ 364 unsigned long long voltage_level_tick = 0; \ 365 unsigned long long watermark_tick = 0; \ 366 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 367 dm_get_timestamp(dc->ctx) : 0 368 369 #define BW_VAL_TRACE_COUNT() \ 370 if (dc->debug.bw_val_profile.enable) \ 371 dc->debug.bw_val_profile.total_count++ 372 373 #define BW_VAL_TRACE_SKIP(status) \ 374 if (dc->debug.bw_val_profile.enable) { \ 375 if (!voltage_level_tick) \ 376 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 377 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 378 } 379 380 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 381 if (dc->debug.bw_val_profile.enable) \ 382 voltage_level_tick = dm_get_timestamp(dc->ctx) 383 384 #define BW_VAL_TRACE_END_WATERMARKS() \ 385 if (dc->debug.bw_val_profile.enable) \ 386 watermark_tick = dm_get_timestamp(dc->ctx) 387 388 #define BW_VAL_TRACE_FINISH() \ 389 if (dc->debug.bw_val_profile.enable) { \ 390 end_tick = dm_get_timestamp(dc->ctx); \ 391 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 392 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 393 if (watermark_tick) { \ 394 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 395 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 396 } \ 397 } 398 399 struct dc_debug_options { 400 enum visual_confirm visual_confirm; 401 bool sanity_checks; 402 bool max_disp_clk; 403 bool surface_trace; 404 bool timing_trace; 405 bool clock_trace; 406 bool validation_trace; 407 bool bandwidth_calcs_trace; 408 int max_downscale_src_width; 409 410 /* stutter efficiency related */ 411 bool disable_stutter; 412 bool use_max_lb; 413 enum dcc_option disable_dcc; 414 enum pipe_split_policy pipe_split_policy; 415 bool force_single_disp_pipe_split; 416 bool voltage_align_fclk; 417 418 bool disable_dfs_bypass; 419 bool disable_dpp_power_gate; 420 bool disable_hubp_power_gate; 421 bool disable_dsc_power_gate; 422 int dsc_min_slice_height_override; 423 int dsc_bpp_increment_div; 424 bool native422_support; 425 bool disable_pplib_wm_range; 426 enum wm_report_mode pplib_wm_report_mode; 427 unsigned int min_disp_clk_khz; 428 unsigned int min_dpp_clk_khz; 429 int sr_exit_time_dpm0_ns; 430 int sr_enter_plus_exit_time_dpm0_ns; 431 int sr_exit_time_ns; 432 int sr_enter_plus_exit_time_ns; 433 int urgent_latency_ns; 434 uint32_t underflow_assert_delay_us; 435 int percent_of_ideal_drambw; 436 int dram_clock_change_latency_ns; 437 bool optimized_watermark; 438 int always_scale; 439 bool disable_pplib_clock_request; 440 bool disable_clock_gate; 441 bool disable_mem_low_power; 442 bool disable_dmcu; 443 bool disable_psr; 444 bool force_abm_enable; 445 bool disable_stereo_support; 446 bool vsr_support; 447 bool performance_trace; 448 bool az_endpoint_mute_only; 449 bool always_use_regamma; 450 bool p010_mpo_support; 451 bool recovery_enabled; 452 bool avoid_vbios_exec_table; 453 bool scl_reset_length10; 454 bool hdmi20_disable; 455 bool skip_detection_link_training; 456 bool remove_disconnect_edp; 457 unsigned int force_odm_combine; //bit vector based on otg inst 458 unsigned int force_fclk_khz; 459 bool disable_tri_buf; 460 bool dmub_offload_enabled; 461 bool dmcub_emulation; 462 bool dmub_command_table; /* for testing only */ 463 struct dc_bw_validation_profile bw_val_profile; 464 bool disable_fec; 465 bool disable_48mhz_pwrdwn; 466 /* This forces a hard min on the DCFCLK requested to SMU/PP 467 * watermarks are not affected. 468 */ 469 unsigned int force_min_dcfclk_mhz; 470 bool disable_timing_sync; 471 bool cm_in_bypass; 472 int force_clock_mode;/*every mode change.*/ 473 474 bool nv12_iflip_vm_wa; 475 bool disable_dram_clock_change_vactive_support; 476 bool validate_dml_output; 477 bool enable_dmcub_surface_flip; 478 bool usbc_combo_phy_reset_wa; 479 bool disable_dsc; 480 bool enable_dram_clock_change_one_display_vactive; 481 }; 482 483 struct dc_debug_data { 484 uint32_t ltFailCount; 485 uint32_t i2cErrorCount; 486 uint32_t auxErrorCount; 487 }; 488 489 struct dc_phy_addr_space_config { 490 struct { 491 uint64_t start_addr; 492 uint64_t end_addr; 493 uint64_t fb_top; 494 uint64_t fb_offset; 495 uint64_t fb_base; 496 uint64_t agp_top; 497 uint64_t agp_bot; 498 uint64_t agp_base; 499 } system_aperture; 500 501 struct { 502 uint64_t page_table_start_addr; 503 uint64_t page_table_end_addr; 504 uint64_t page_table_base_addr; 505 } gart_config; 506 507 bool valid; 508 bool is_hvm_enabled; 509 uint64_t page_table_default_page_addr; 510 }; 511 512 struct dc_virtual_addr_space_config { 513 uint64_t page_table_base_addr; 514 uint64_t page_table_start_addr; 515 uint64_t page_table_end_addr; 516 uint32_t page_table_block_size_in_bytes; 517 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 518 }; 519 520 struct dc_bounding_box_overrides { 521 int sr_exit_time_ns; 522 int sr_enter_plus_exit_time_ns; 523 int urgent_latency_ns; 524 int percent_of_ideal_drambw; 525 int dram_clock_change_latency_ns; 526 int dummy_clock_change_latency_ns; 527 /* This forces a hard min on the DCFCLK we use 528 * for DML. Unlike the debug option for forcing 529 * DCFCLK, this override affects watermark calculations 530 */ 531 int min_dcfclk_mhz; 532 }; 533 534 struct dc_state; 535 struct resource_pool; 536 struct dce_hwseq; 537 struct gpu_info_soc_bounding_box_v1_0; 538 struct dc { 539 struct dc_versions versions; 540 struct dc_caps caps; 541 struct dc_cap_funcs cap_funcs; 542 struct dc_config config; 543 struct dc_debug_options debug; 544 struct dc_bounding_box_overrides bb_overrides; 545 struct dc_bug_wa work_arounds; 546 struct dc_context *ctx; 547 struct dc_phy_addr_space_config vm_pa_config; 548 549 uint8_t link_count; 550 struct dc_link *links[MAX_PIPES * 2]; 551 552 struct dc_state *current_state; 553 struct resource_pool *res_pool; 554 555 struct clk_mgr *clk_mgr; 556 557 /* Display Engine Clock levels */ 558 struct dm_pp_clock_levels sclk_lvls; 559 560 /* Inputs into BW and WM calculations. */ 561 struct bw_calcs_dceip *bw_dceip; 562 struct bw_calcs_vbios *bw_vbios; 563 #ifdef CONFIG_DRM_AMD_DC_DCN 564 struct dcn_soc_bounding_box *dcn_soc; 565 struct dcn_ip_params *dcn_ip; 566 struct display_mode_lib dml; 567 #endif 568 569 /* HW functions */ 570 struct hw_sequencer_funcs hwss; 571 struct dce_hwseq *hwseq; 572 573 /* Require to optimize clocks and bandwidth for added/removed planes */ 574 bool optimized_required; 575 bool wm_optimized_required; 576 577 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 578 int optimize_seamless_boot_streams; 579 580 /* FBC compressor */ 581 struct compressor *fbc_compressor; 582 583 struct dc_debug_data debug_data; 584 struct dpcd_vendor_signature vendor_signature; 585 586 const char *build_id; 587 struct vm_helper *vm_helper; 588 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 589 }; 590 591 enum frame_buffer_mode { 592 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 593 FRAME_BUFFER_MODE_ZFB_ONLY, 594 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 595 } ; 596 597 struct dchub_init_data { 598 int64_t zfb_phys_addr_base; 599 int64_t zfb_mc_base_addr; 600 uint64_t zfb_size_in_byte; 601 enum frame_buffer_mode fb_mode; 602 bool dchub_initialzied; 603 bool dchub_info_valid; 604 }; 605 606 struct dc_init_data { 607 struct hw_asic_id asic_id; 608 void *driver; /* ctx */ 609 struct cgs_device *cgs_device; 610 struct dc_bounding_box_overrides bb_overrides; 611 612 int num_virtual_links; 613 /* 614 * If 'vbios_override' not NULL, it will be called instead 615 * of the real VBIOS. Intended use is Diagnostics on FPGA. 616 */ 617 struct dc_bios *vbios_override; 618 enum dce_environment dce_environment; 619 620 struct dmub_offload_funcs *dmub_if; 621 struct dc_reg_helper_state *dmub_offload; 622 623 struct dc_config flags; 624 uint64_t log_mask; 625 626 /** 627 * gpu_info FW provided soc bounding box struct or 0 if not 628 * available in FW 629 */ 630 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 631 struct dpcd_vendor_signature vendor_signature; 632 }; 633 634 struct dc_callback_init { 635 #ifdef CONFIG_DRM_AMD_DC_HDCP 636 struct cp_psp cp_psp; 637 #else 638 uint8_t reserved; 639 #endif 640 }; 641 642 struct dc *dc_create(const struct dc_init_data *init_params); 643 void dc_hardware_init(struct dc *dc); 644 645 int dc_get_vmid_use_vector(struct dc *dc); 646 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 647 /* Returns the number of vmids supported */ 648 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 649 void dc_init_callbacks(struct dc *dc, 650 const struct dc_callback_init *init_params); 651 void dc_deinit_callbacks(struct dc *dc); 652 void dc_destroy(struct dc **dc); 653 654 /******************************************************************************* 655 * Surface Interfaces 656 ******************************************************************************/ 657 658 enum { 659 TRANSFER_FUNC_POINTS = 1025 660 }; 661 662 struct dc_hdr_static_metadata { 663 /* display chromaticities and white point in units of 0.00001 */ 664 unsigned int chromaticity_green_x; 665 unsigned int chromaticity_green_y; 666 unsigned int chromaticity_blue_x; 667 unsigned int chromaticity_blue_y; 668 unsigned int chromaticity_red_x; 669 unsigned int chromaticity_red_y; 670 unsigned int chromaticity_white_point_x; 671 unsigned int chromaticity_white_point_y; 672 673 uint32_t min_luminance; 674 uint32_t max_luminance; 675 uint32_t maximum_content_light_level; 676 uint32_t maximum_frame_average_light_level; 677 }; 678 679 enum dc_transfer_func_type { 680 TF_TYPE_PREDEFINED, 681 TF_TYPE_DISTRIBUTED_POINTS, 682 TF_TYPE_BYPASS, 683 TF_TYPE_HWPWL 684 }; 685 686 struct dc_transfer_func_distributed_points { 687 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 688 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 689 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 690 691 uint16_t end_exponent; 692 uint16_t x_point_at_y1_red; 693 uint16_t x_point_at_y1_green; 694 uint16_t x_point_at_y1_blue; 695 }; 696 697 enum dc_transfer_func_predefined { 698 TRANSFER_FUNCTION_SRGB, 699 TRANSFER_FUNCTION_BT709, 700 TRANSFER_FUNCTION_PQ, 701 TRANSFER_FUNCTION_LINEAR, 702 TRANSFER_FUNCTION_UNITY, 703 TRANSFER_FUNCTION_HLG, 704 TRANSFER_FUNCTION_HLG12, 705 TRANSFER_FUNCTION_GAMMA22, 706 TRANSFER_FUNCTION_GAMMA24, 707 TRANSFER_FUNCTION_GAMMA26 708 }; 709 710 711 struct dc_transfer_func { 712 struct kref refcount; 713 enum dc_transfer_func_type type; 714 enum dc_transfer_func_predefined tf; 715 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 716 uint32_t sdr_ref_white_level; 717 struct dc_context *ctx; 718 union { 719 struct pwl_params pwl; 720 struct dc_transfer_func_distributed_points tf_pts; 721 }; 722 }; 723 724 725 union dc_3dlut_state { 726 struct { 727 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 728 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 729 uint32_t rmu_mux_num:3; /*index of mux to use*/ 730 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 731 uint32_t mpc_rmu1_mux:4; 732 uint32_t mpc_rmu2_mux:4; 733 uint32_t reserved:15; 734 } bits; 735 uint32_t raw; 736 }; 737 738 739 struct dc_3dlut { 740 struct kref refcount; 741 struct tetrahedral_params lut_3d; 742 struct fixed31_32 hdr_multiplier; 743 union dc_3dlut_state state; 744 struct dc_context *ctx; 745 }; 746 /* 747 * This structure is filled in by dc_surface_get_status and contains 748 * the last requested address and the currently active address so the called 749 * can determine if there are any outstanding flips 750 */ 751 struct dc_plane_status { 752 struct dc_plane_address requested_address; 753 struct dc_plane_address current_address; 754 bool is_flip_pending; 755 bool is_right_eye; 756 }; 757 758 union surface_update_flags { 759 760 struct { 761 uint32_t addr_update:1; 762 /* Medium updates */ 763 uint32_t dcc_change:1; 764 uint32_t color_space_change:1; 765 uint32_t horizontal_mirror_change:1; 766 uint32_t per_pixel_alpha_change:1; 767 uint32_t global_alpha_change:1; 768 uint32_t hdr_mult:1; 769 uint32_t rotation_change:1; 770 uint32_t swizzle_change:1; 771 uint32_t scaling_change:1; 772 uint32_t position_change:1; 773 uint32_t in_transfer_func_change:1; 774 uint32_t input_csc_change:1; 775 uint32_t coeff_reduction_change:1; 776 uint32_t output_tf_change:1; 777 uint32_t pixel_format_change:1; 778 uint32_t plane_size_change:1; 779 uint32_t gamut_remap_change:1; 780 781 /* Full updates */ 782 uint32_t new_plane:1; 783 uint32_t bpp_change:1; 784 uint32_t gamma_change:1; 785 uint32_t bandwidth_change:1; 786 uint32_t clock_change:1; 787 uint32_t stereo_format_change:1; 788 uint32_t full_update:1; 789 } bits; 790 791 uint32_t raw; 792 }; 793 794 struct dc_plane_state { 795 struct dc_plane_address address; 796 struct dc_plane_flip_time time; 797 bool triplebuffer_flips; 798 struct scaling_taps scaling_quality; 799 struct rect src_rect; 800 struct rect dst_rect; 801 struct rect clip_rect; 802 803 struct plane_size plane_size; 804 union dc_tiling_info tiling_info; 805 806 struct dc_plane_dcc_param dcc; 807 808 struct dc_gamma *gamma_correction; 809 struct dc_transfer_func *in_transfer_func; 810 struct dc_bias_and_scale *bias_and_scale; 811 struct dc_csc_transform input_csc_color_matrix; 812 struct fixed31_32 coeff_reduction_factor; 813 struct fixed31_32 hdr_mult; 814 struct colorspace_transform gamut_remap_matrix; 815 816 // TODO: No longer used, remove 817 struct dc_hdr_static_metadata hdr_static_ctx; 818 819 enum dc_color_space color_space; 820 821 struct dc_3dlut *lut3d_func; 822 struct dc_transfer_func *in_shaper_func; 823 struct dc_transfer_func *blend_tf; 824 825 enum surface_pixel_format format; 826 enum dc_rotation_angle rotation; 827 enum plane_stereo_format stereo_format; 828 829 bool is_tiling_rotated; 830 bool per_pixel_alpha; 831 bool global_alpha; 832 int global_alpha_value; 833 bool visible; 834 bool flip_immediate; 835 bool horizontal_mirror; 836 int layer_index; 837 838 union surface_update_flags update_flags; 839 /* private to DC core */ 840 struct dc_plane_status status; 841 struct dc_context *ctx; 842 843 /* HACK: Workaround for forcing full reprogramming under some conditions */ 844 bool force_full_update; 845 846 /* private to dc_surface.c */ 847 enum dc_irq_source irq_source; 848 struct kref refcount; 849 }; 850 851 struct dc_plane_info { 852 struct plane_size plane_size; 853 union dc_tiling_info tiling_info; 854 struct dc_plane_dcc_param dcc; 855 enum surface_pixel_format format; 856 enum dc_rotation_angle rotation; 857 enum plane_stereo_format stereo_format; 858 enum dc_color_space color_space; 859 bool horizontal_mirror; 860 bool visible; 861 bool per_pixel_alpha; 862 bool global_alpha; 863 int global_alpha_value; 864 bool input_csc_enabled; 865 int layer_index; 866 }; 867 868 struct dc_scaling_info { 869 struct rect src_rect; 870 struct rect dst_rect; 871 struct rect clip_rect; 872 struct scaling_taps scaling_quality; 873 }; 874 875 struct dc_surface_update { 876 struct dc_plane_state *surface; 877 878 /* isr safe update parameters. null means no updates */ 879 const struct dc_flip_addrs *flip_addr; 880 const struct dc_plane_info *plane_info; 881 const struct dc_scaling_info *scaling_info; 882 struct fixed31_32 hdr_mult; 883 /* following updates require alloc/sleep/spin that is not isr safe, 884 * null means no updates 885 */ 886 const struct dc_gamma *gamma; 887 const struct dc_transfer_func *in_transfer_func; 888 889 const struct dc_csc_transform *input_csc_color_matrix; 890 const struct fixed31_32 *coeff_reduction_factor; 891 const struct dc_transfer_func *func_shaper; 892 const struct dc_3dlut *lut3d_func; 893 const struct dc_transfer_func *blend_tf; 894 const struct colorspace_transform *gamut_remap_matrix; 895 }; 896 897 /* 898 * Create a new surface with default parameters; 899 */ 900 struct dc_plane_state *dc_create_plane_state(struct dc *dc); 901 const struct dc_plane_status *dc_plane_get_status( 902 const struct dc_plane_state *plane_state); 903 904 void dc_plane_state_retain(struct dc_plane_state *plane_state); 905 void dc_plane_state_release(struct dc_plane_state *plane_state); 906 907 void dc_gamma_retain(struct dc_gamma *dc_gamma); 908 void dc_gamma_release(struct dc_gamma **dc_gamma); 909 struct dc_gamma *dc_create_gamma(void); 910 911 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 912 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 913 struct dc_transfer_func *dc_create_transfer_func(void); 914 915 struct dc_3dlut *dc_create_3dlut_func(void); 916 void dc_3dlut_func_release(struct dc_3dlut *lut); 917 void dc_3dlut_func_retain(struct dc_3dlut *lut); 918 /* 919 * This structure holds a surface address. There could be multiple addresses 920 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 921 * as frame durations and DCC format can also be set. 922 */ 923 struct dc_flip_addrs { 924 struct dc_plane_address address; 925 unsigned int flip_timestamp_in_us; 926 bool flip_immediate; 927 /* TODO: add flip duration for FreeSync */ 928 bool triplebuffer_flips; 929 }; 930 931 bool dc_post_update_surfaces_to_stream( 932 struct dc *dc); 933 934 #include "dc_stream.h" 935 936 /* 937 * Structure to store surface/stream associations for validation 938 */ 939 struct dc_validation_set { 940 struct dc_stream_state *stream; 941 struct dc_plane_state *plane_states[MAX_SURFACES]; 942 uint8_t plane_count; 943 }; 944 945 bool dc_validate_seamless_boot_timing(const struct dc *dc, 946 const struct dc_sink *sink, 947 struct dc_crtc_timing *crtc_timing); 948 949 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 950 951 void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 952 953 bool dc_set_generic_gpio_for_stereo(bool enable, 954 struct gpio_service *gpio_service); 955 956 /* 957 * fast_validate: we return after determining if we can support the new state, 958 * but before we populate the programming info 959 */ 960 enum dc_status dc_validate_global_state( 961 struct dc *dc, 962 struct dc_state *new_ctx, 963 bool fast_validate); 964 965 966 void dc_resource_state_construct( 967 const struct dc *dc, 968 struct dc_state *dst_ctx); 969 970 void dc_resource_state_copy_construct( 971 const struct dc_state *src_ctx, 972 struct dc_state *dst_ctx); 973 974 void dc_resource_state_copy_construct_current( 975 const struct dc *dc, 976 struct dc_state *dst_ctx); 977 978 void dc_resource_state_destruct(struct dc_state *context); 979 980 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 981 982 /* 983 * TODO update to make it about validation sets 984 * Set up streams and links associated to drive sinks 985 * The streams parameter is an absolute set of all active streams. 986 * 987 * After this call: 988 * Phy, Encoder, Timing Generator are programmed and enabled. 989 * New streams are enabled with blank stream; no memory read. 990 */ 991 bool dc_commit_state(struct dc *dc, struct dc_state *context); 992 993 994 struct dc_state *dc_create_state(struct dc *dc); 995 struct dc_state *dc_copy_state(struct dc_state *src_ctx); 996 void dc_retain_state(struct dc_state *context); 997 void dc_release_state(struct dc_state *context); 998 999 /******************************************************************************* 1000 * Link Interfaces 1001 ******************************************************************************/ 1002 1003 struct dpcd_caps { 1004 union dpcd_rev dpcd_rev; 1005 union max_lane_count max_ln_count; 1006 union max_down_spread max_down_spread; 1007 union dprx_feature dprx_feature; 1008 1009 /* valid only for eDP v1.4 or higher*/ 1010 uint8_t edp_supported_link_rates_count; 1011 enum dc_link_rate edp_supported_link_rates[8]; 1012 1013 /* dongle type (DP converter, CV smart dongle) */ 1014 enum display_dongle_type dongle_type; 1015 /* branch device or sink device */ 1016 bool is_branch_dev; 1017 /* Dongle's downstream count. */ 1018 union sink_count sink_count; 1019 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 1020 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 1021 struct dc_dongle_caps dongle_caps; 1022 1023 uint32_t sink_dev_id; 1024 int8_t sink_dev_id_str[6]; 1025 int8_t sink_hw_revision; 1026 int8_t sink_fw_revision[2]; 1027 1028 uint32_t branch_dev_id; 1029 int8_t branch_dev_name[6]; 1030 int8_t branch_hw_revision; 1031 int8_t branch_fw_revision[2]; 1032 1033 bool allow_invalid_MSA_timing_param; 1034 bool panel_mode_edp; 1035 bool dpcd_display_control_capable; 1036 bool ext_receiver_cap_field_present; 1037 union dpcd_fec_capability fec_cap; 1038 struct dpcd_dsc_capabilities dsc_caps; 1039 struct dc_lttpr_caps lttpr_caps; 1040 struct psr_caps psr_caps; 1041 1042 }; 1043 1044 union dpcd_sink_ext_caps { 1045 struct { 1046 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode 1047 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode. 1048 */ 1049 uint8_t sdr_aux_backlight_control : 1; 1050 uint8_t hdr_aux_backlight_control : 1; 1051 uint8_t reserved_1 : 2; 1052 uint8_t oled : 1; 1053 uint8_t reserved : 3; 1054 } bits; 1055 uint8_t raw; 1056 }; 1057 1058 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1059 union hdcp_rx_caps { 1060 struct { 1061 uint8_t version; 1062 uint8_t reserved; 1063 struct { 1064 uint8_t repeater : 1; 1065 uint8_t hdcp_capable : 1; 1066 uint8_t reserved : 6; 1067 } byte0; 1068 } fields; 1069 uint8_t raw[3]; 1070 }; 1071 1072 union hdcp_bcaps { 1073 struct { 1074 uint8_t HDCP_CAPABLE:1; 1075 uint8_t REPEATER:1; 1076 uint8_t RESERVED:6; 1077 } bits; 1078 uint8_t raw; 1079 }; 1080 1081 struct hdcp_caps { 1082 union hdcp_rx_caps rx_caps; 1083 union hdcp_bcaps bcaps; 1084 }; 1085 #endif 1086 1087 #include "dc_link.h" 1088 1089 /******************************************************************************* 1090 * Sink Interfaces - A sink corresponds to a display output device 1091 ******************************************************************************/ 1092 1093 struct dc_container_id { 1094 // 128bit GUID in binary form 1095 unsigned char guid[16]; 1096 // 8 byte port ID -> ELD.PortID 1097 unsigned int portId[2]; 1098 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 1099 unsigned short manufacturerName; 1100 // 2 byte product code -> ELD.ProductCode 1101 unsigned short productCode; 1102 }; 1103 1104 1105 struct dc_sink_dsc_caps { 1106 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1107 // 'false' if they are sink's DSC caps 1108 bool is_virtual_dpcd_dsc; 1109 struct dsc_dec_dpcd_caps dsc_dec_caps; 1110 }; 1111 1112 struct dc_sink_fec_caps { 1113 bool is_rx_fec_supported; 1114 bool is_topology_fec_supported; 1115 }; 1116 1117 /* 1118 * The sink structure contains EDID and other display device properties 1119 */ 1120 struct dc_sink { 1121 enum signal_type sink_signal; 1122 struct dc_edid dc_edid; /* raw edid */ 1123 struct dc_edid_caps edid_caps; /* parse display caps */ 1124 struct dc_container_id *dc_container_id; 1125 uint32_t dongle_max_pix_clk; 1126 void *priv; 1127 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1128 bool converter_disable_audio; 1129 bool is_mst_legacy; 1130 struct dc_sink_dsc_caps dsc_caps; 1131 struct dc_sink_fec_caps fec_caps; 1132 1133 bool is_vsc_sdp_colorimetry_supported; 1134 1135 /* private to DC core */ 1136 struct dc_link *link; 1137 struct dc_context *ctx; 1138 1139 uint32_t sink_id; 1140 1141 /* private to dc_sink.c */ 1142 // refcount must be the last member in dc_sink, since we want the 1143 // sink structure to be logically cloneable up to (but not including) 1144 // refcount 1145 struct kref refcount; 1146 }; 1147 1148 void dc_sink_retain(struct dc_sink *sink); 1149 void dc_sink_release(struct dc_sink *sink); 1150 1151 struct dc_sink_init_data { 1152 enum signal_type sink_signal; 1153 struct dc_link *link; 1154 uint32_t dongle_max_pix_clk; 1155 bool converter_disable_audio; 1156 bool sink_is_legacy; 1157 }; 1158 1159 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1160 1161 /* Newer interfaces */ 1162 struct dc_cursor { 1163 struct dc_plane_address address; 1164 struct dc_cursor_attributes attributes; 1165 }; 1166 1167 1168 /******************************************************************************* 1169 * Interrupt interfaces 1170 ******************************************************************************/ 1171 enum dc_irq_source dc_interrupt_to_irq_source( 1172 struct dc *dc, 1173 uint32_t src_id, 1174 uint32_t ext_id); 1175 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1176 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1177 enum dc_irq_source dc_get_hpd_irq_source_at_index( 1178 struct dc *dc, uint32_t link_index); 1179 1180 /******************************************************************************* 1181 * Power Interfaces 1182 ******************************************************************************/ 1183 1184 void dc_set_power_state( 1185 struct dc *dc, 1186 enum dc_acpi_cm_power_state power_state); 1187 void dc_resume(struct dc *dc); 1188 1189 #if defined(CONFIG_DRM_AMD_DC_HDCP) 1190 /* 1191 * HDCP Interfaces 1192 */ 1193 enum hdcp_message_status dc_process_hdcp_msg( 1194 enum signal_type signal, 1195 struct dc_link *link, 1196 struct hdcp_protection_message *message_info); 1197 #endif 1198 bool dc_is_dmcu_initialized(struct dc *dc); 1199 1200 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1201 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1202 /******************************************************************************* 1203 * DSC Interfaces 1204 ******************************************************************************/ 1205 #include "dc_dsc.h" 1206 #endif /* DC_INTERFACE_H_ */ 1207