1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/firmware.h> 24 #include <linux/module.h> 25 #include <linux/vmalloc.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_psp.h" 29 #include "amdgpu_ras.h" 30 #include "amdgpu_ucode.h" 31 #include "soc15_common.h" 32 #include "psp_v11_0.h" 33 34 #include "mp/mp_11_0_offset.h" 35 #include "mp/mp_11_0_sh_mask.h" 36 #include "gc/gc_9_0_offset.h" 37 #include "sdma0/sdma0_4_0_offset.h" 38 #include "nbio/nbio_7_4_offset.h" 39 40 #include "oss/osssys_4_0_offset.h" 41 #include "oss/osssys_4_0_sh_mask.h" 42 43 MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); 44 MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); 45 MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); 46 MODULE_FIRMWARE("amdgpu/navi10_sos.bin"); 47 MODULE_FIRMWARE("amdgpu/navi10_asd.bin"); 48 MODULE_FIRMWARE("amdgpu/navi10_ta.bin"); 49 MODULE_FIRMWARE("amdgpu/navi14_sos.bin"); 50 MODULE_FIRMWARE("amdgpu/navi14_asd.bin"); 51 MODULE_FIRMWARE("amdgpu/navi14_ta.bin"); 52 MODULE_FIRMWARE("amdgpu/navi12_sos.bin"); 53 MODULE_FIRMWARE("amdgpu/navi12_asd.bin"); 54 MODULE_FIRMWARE("amdgpu/navi12_ta.bin"); 55 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin"); 56 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin"); 57 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin"); 58 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin"); 59 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin"); 60 MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin"); 61 MODULE_FIRMWARE("amdgpu/navy_flounder_asd.bin"); 62 63 /* address block */ 64 #define smnMP1_FIRMWARE_FLAGS 0x3010024 65 /* navi10 reg offset define */ 66 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61 67 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62 68 #define mmSDMA0_UCODE_ADDR_NV10 0x5880 69 #define mmSDMA0_UCODE_DATA_NV10 0x5881 70 /* memory training timeout define */ 71 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 72 73 /* For large FW files the time to complete can be very long */ 74 #define USBC_PD_POLLING_LIMIT_S 240 75 76 static int psp_v11_0_init_microcode(struct psp_context *psp) 77 { 78 struct amdgpu_device *adev = psp->adev; 79 const char *chip_name; 80 char fw_name[30]; 81 int err = 0; 82 const struct ta_firmware_header_v1_0 *ta_hdr; 83 84 DRM_DEBUG("\n"); 85 86 switch (adev->asic_type) { 87 case CHIP_VEGA20: 88 chip_name = "vega20"; 89 break; 90 case CHIP_NAVI10: 91 chip_name = "navi10"; 92 break; 93 case CHIP_NAVI14: 94 chip_name = "navi14"; 95 break; 96 case CHIP_NAVI12: 97 chip_name = "navi12"; 98 break; 99 case CHIP_ARCTURUS: 100 chip_name = "arcturus"; 101 break; 102 case CHIP_SIENNA_CICHLID: 103 chip_name = "sienna_cichlid"; 104 break; 105 case CHIP_NAVY_FLOUNDER: 106 chip_name = "navy_flounder"; 107 break; 108 default: 109 BUG(); 110 } 111 112 err = psp_init_sos_microcode(psp, chip_name); 113 if (err) 114 return err; 115 116 if (adev->asic_type != CHIP_SIENNA_CICHLID && 117 adev->asic_type != CHIP_NAVY_FLOUNDER) { 118 err = psp_init_asd_microcode(psp, chip_name); 119 if (err) 120 return err; 121 } 122 123 switch (adev->asic_type) { 124 case CHIP_VEGA20: 125 case CHIP_ARCTURUS: 126 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 127 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 128 if (err) { 129 release_firmware(adev->psp.ta_fw); 130 adev->psp.ta_fw = NULL; 131 dev_info(adev->dev, 132 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 133 } else { 134 err = amdgpu_ucode_validate(adev->psp.ta_fw); 135 if (err) 136 goto out2; 137 138 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 139 adev->psp.ta_xgmi_ucode_version = le32_to_cpu(ta_hdr->ta_xgmi_ucode_version); 140 adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes); 141 adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr + 142 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 143 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 144 adev->psp.ta_ras_ucode_version = le32_to_cpu(ta_hdr->ta_ras_ucode_version); 145 adev->psp.ta_ras_ucode_size = le32_to_cpu(ta_hdr->ta_ras_size_bytes); 146 adev->psp.ta_ras_start_addr = (uint8_t *)adev->psp.ta_xgmi_start_addr + 147 le32_to_cpu(ta_hdr->ta_ras_offset_bytes); 148 } 149 break; 150 case CHIP_NAVI10: 151 case CHIP_NAVI14: 152 case CHIP_NAVI12: 153 if (amdgpu_sriov_vf(adev)) 154 break; 155 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); 156 err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); 157 if (err) { 158 release_firmware(adev->psp.ta_fw); 159 adev->psp.ta_fw = NULL; 160 dev_info(adev->dev, 161 "psp v11.0: Failed to load firmware \"%s\"\n", fw_name); 162 } else { 163 err = amdgpu_ucode_validate(adev->psp.ta_fw); 164 if (err) 165 goto out2; 166 167 ta_hdr = (const struct ta_firmware_header_v1_0 *)adev->psp.ta_fw->data; 168 adev->psp.ta_hdcp_ucode_version = le32_to_cpu(ta_hdr->ta_hdcp_ucode_version); 169 adev->psp.ta_hdcp_ucode_size = le32_to_cpu(ta_hdr->ta_hdcp_size_bytes); 170 adev->psp.ta_hdcp_start_addr = (uint8_t *)ta_hdr + 171 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); 172 173 adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); 174 175 adev->psp.ta_dtm_ucode_version = le32_to_cpu(ta_hdr->ta_dtm_ucode_version); 176 adev->psp.ta_dtm_ucode_size = le32_to_cpu(ta_hdr->ta_dtm_size_bytes); 177 adev->psp.ta_dtm_start_addr = (uint8_t *)adev->psp.ta_hdcp_start_addr + 178 le32_to_cpu(ta_hdr->ta_dtm_offset_bytes); 179 } 180 break; 181 case CHIP_SIENNA_CICHLID: 182 err = psp_init_ta_microcode(&adev->psp, chip_name); 183 if (err) 184 return err; 185 break; 186 case CHIP_NAVY_FLOUNDER: 187 break; 188 default: 189 BUG(); 190 } 191 192 return 0; 193 194 out2: 195 release_firmware(adev->psp.ta_fw); 196 adev->psp.ta_fw = NULL; 197 return err; 198 } 199 200 int psp_v11_0_wait_for_bootloader(struct psp_context *psp) 201 { 202 struct amdgpu_device *adev = psp->adev; 203 204 int ret; 205 int retry_loop; 206 207 for (retry_loop = 0; retry_loop < 10; retry_loop++) { 208 /* Wait for bootloader to signify that is 209 ready having bit 31 of C2PMSG_35 set to 1 */ 210 ret = psp_wait_for(psp, 211 SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 212 0x80000000, 213 0x80000000, 214 false); 215 216 if (ret == 0) 217 return 0; 218 } 219 220 return ret; 221 } 222 223 static bool psp_v11_0_is_sos_alive(struct psp_context *psp) 224 { 225 struct amdgpu_device *adev = psp->adev; 226 uint32_t sol_reg; 227 228 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); 229 230 return sol_reg != 0x0; 231 } 232 233 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp) 234 { 235 int ret; 236 uint32_t psp_gfxdrv_command_reg = 0; 237 struct amdgpu_device *adev = psp->adev; 238 239 /* Check tOS sign of life register to confirm sys driver and sOS 240 * are already been loaded. 241 */ 242 if (psp_v11_0_is_sos_alive(psp)) 243 return 0; 244 245 ret = psp_v11_0_wait_for_bootloader(psp); 246 if (ret) 247 return ret; 248 249 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 250 251 /* Copy PSP KDB binary to memory */ 252 memcpy(psp->fw_pri_buf, psp->kdb_start_addr, psp->kdb_bin_size); 253 254 /* Provide the PSP KDB to bootloader */ 255 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 256 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 257 psp_gfxdrv_command_reg = PSP_BL__LOAD_KEY_DATABASE; 258 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 259 psp_gfxdrv_command_reg); 260 261 ret = psp_v11_0_wait_for_bootloader(psp); 262 263 return ret; 264 } 265 266 static int psp_v11_0_bootloader_load_spl(struct psp_context *psp) 267 { 268 int ret; 269 uint32_t psp_gfxdrv_command_reg = 0; 270 struct amdgpu_device *adev = psp->adev; 271 272 /* Check tOS sign of life register to confirm sys driver and sOS 273 * are already been loaded. 274 */ 275 if (psp_v11_0_is_sos_alive(psp)) 276 return 0; 277 278 ret = psp_v11_0_wait_for_bootloader(psp); 279 if (ret) 280 return ret; 281 282 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 283 284 /* Copy PSP SPL binary to memory */ 285 memcpy(psp->fw_pri_buf, psp->spl_start_addr, psp->spl_bin_size); 286 287 /* Provide the PSP SPL to bootloader */ 288 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 289 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 290 psp_gfxdrv_command_reg = PSP_BL__LOAD_TOS_SPL_TABLE; 291 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 292 psp_gfxdrv_command_reg); 293 294 ret = psp_v11_0_wait_for_bootloader(psp); 295 296 return ret; 297 } 298 299 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp) 300 { 301 int ret; 302 uint32_t psp_gfxdrv_command_reg = 0; 303 struct amdgpu_device *adev = psp->adev; 304 305 /* Check sOS sign of life register to confirm sys driver and sOS 306 * are already been loaded. 307 */ 308 if (psp_v11_0_is_sos_alive(psp)) 309 return 0; 310 311 ret = psp_v11_0_wait_for_bootloader(psp); 312 if (ret) 313 return ret; 314 315 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 316 317 /* Copy PSP System Driver binary to memory */ 318 memcpy(psp->fw_pri_buf, psp->sys_start_addr, psp->sys_bin_size); 319 320 /* Provide the sys driver to bootloader */ 321 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 322 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 323 psp_gfxdrv_command_reg = PSP_BL__LOAD_SYSDRV; 324 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 325 psp_gfxdrv_command_reg); 326 327 /* there might be handshake issue with hardware which needs delay */ 328 mdelay(20); 329 330 ret = psp_v11_0_wait_for_bootloader(psp); 331 332 return ret; 333 } 334 335 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) 336 { 337 int ret; 338 unsigned int psp_gfxdrv_command_reg = 0; 339 struct amdgpu_device *adev = psp->adev; 340 341 /* Check sOS sign of life register to confirm sys driver and sOS 342 * are already been loaded. 343 */ 344 if (psp_v11_0_is_sos_alive(psp)) 345 return 0; 346 347 ret = psp_v11_0_wait_for_bootloader(psp); 348 if (ret) 349 return ret; 350 351 memset(psp->fw_pri_buf, 0, PSP_1_MEG); 352 353 /* Copy Secure OS binary to PSP memory */ 354 memcpy(psp->fw_pri_buf, psp->sos_start_addr, psp->sos_bin_size); 355 356 /* Provide the PSP secure OS to bootloader */ 357 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, 358 (uint32_t)(psp->fw_pri_mc_addr >> 20)); 359 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV; 360 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 361 psp_gfxdrv_command_reg); 362 363 /* there might be handshake issue with hardware which needs delay */ 364 mdelay(20); 365 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), 366 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 367 0, true); 368 369 return ret; 370 } 371 372 static void psp_v11_0_reroute_ih(struct psp_context *psp) 373 { 374 struct amdgpu_device *adev = psp->adev; 375 uint32_t tmp; 376 377 /* Change IH ring for VMC */ 378 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b); 379 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1); 380 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 381 382 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3); 383 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 384 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 385 386 mdelay(20); 387 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 388 0x80000000, 0x8000FFFF, false); 389 390 /* Change IH ring for UMC */ 391 tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b); 392 tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1); 393 394 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4); 395 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp); 396 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET); 397 398 mdelay(20); 399 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 400 0x80000000, 0x8000FFFF, false); 401 } 402 403 static int psp_v11_0_ring_init(struct psp_context *psp, 404 enum psp_ring_type ring_type) 405 { 406 int ret = 0; 407 struct psp_ring *ring; 408 struct amdgpu_device *adev = psp->adev; 409 410 if ((!amdgpu_sriov_vf(adev)) && 411 (adev->asic_type != CHIP_SIENNA_CICHLID) && 412 (adev->asic_type != CHIP_NAVY_FLOUNDER)) 413 psp_v11_0_reroute_ih(psp); 414 415 ring = &psp->km_ring; 416 417 ring->ring_type = ring_type; 418 419 /* allocate 4k Page of Local Frame Buffer memory for ring */ 420 ring->ring_size = 0x1000; 421 ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE, 422 AMDGPU_GEM_DOMAIN_VRAM, 423 &adev->firmware.rbuf, 424 &ring->ring_mem_mc_addr, 425 (void **)&ring->ring_mem); 426 if (ret) { 427 ring->ring_size = 0; 428 return ret; 429 } 430 431 return 0; 432 } 433 434 static int psp_v11_0_ring_stop(struct psp_context *psp, 435 enum psp_ring_type ring_type) 436 { 437 int ret = 0; 438 struct amdgpu_device *adev = psp->adev; 439 440 /* Write the ring destroy command*/ 441 if (amdgpu_sriov_vf(adev)) 442 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 443 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING); 444 else 445 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, 446 GFX_CTRL_CMD_ID_DESTROY_RINGS); 447 448 /* there might be handshake issue with hardware which needs delay */ 449 mdelay(20); 450 451 /* Wait for response flag (bit 31) */ 452 if (amdgpu_sriov_vf(adev)) 453 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 454 0x80000000, 0x80000000, false); 455 else 456 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 457 0x80000000, 0x80000000, false); 458 459 return ret; 460 } 461 462 static int psp_v11_0_ring_create(struct psp_context *psp, 463 enum psp_ring_type ring_type) 464 { 465 int ret = 0; 466 unsigned int psp_ring_reg = 0; 467 struct psp_ring *ring = &psp->km_ring; 468 struct amdgpu_device *adev = psp->adev; 469 470 if (amdgpu_sriov_vf(adev)) { 471 ret = psp_v11_0_ring_stop(psp, ring_type); 472 if (ret) { 473 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n"); 474 return ret; 475 } 476 477 /* Write low address of the ring to C2PMSG_102 */ 478 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 479 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg); 480 /* Write high address of the ring to C2PMSG_103 */ 481 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 482 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg); 483 484 /* Write the ring initialization command to C2PMSG_101 */ 485 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, 486 GFX_CTRL_CMD_ID_INIT_GPCOM_RING); 487 488 /* there might be handshake issue with hardware which needs delay */ 489 mdelay(20); 490 491 /* Wait for response flag (bit 31) in C2PMSG_101 */ 492 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), 493 0x80000000, 0x8000FFFF, false); 494 495 } else { 496 /* Wait for sOS ready for ring creation */ 497 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 498 0x80000000, 0x80000000, false); 499 if (ret) { 500 DRM_ERROR("Failed to wait for sOS ready for ring creation\n"); 501 return ret; 502 } 503 504 /* Write low address of the ring to C2PMSG_69 */ 505 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr); 506 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg); 507 /* Write high address of the ring to C2PMSG_70 */ 508 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr); 509 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg); 510 /* Write size of ring to C2PMSG_71 */ 511 psp_ring_reg = ring->ring_size; 512 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg); 513 /* Write the ring initialization command to C2PMSG_64 */ 514 psp_ring_reg = ring_type; 515 psp_ring_reg = psp_ring_reg << 16; 516 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg); 517 518 /* there might be handshake issue with hardware which needs delay */ 519 mdelay(20); 520 521 /* Wait for response flag (bit 31) in C2PMSG_64 */ 522 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), 523 0x80000000, 0x8000FFFF, false); 524 } 525 526 return ret; 527 } 528 529 530 static int psp_v11_0_ring_destroy(struct psp_context *psp, 531 enum psp_ring_type ring_type) 532 { 533 int ret = 0; 534 struct psp_ring *ring = &psp->km_ring; 535 struct amdgpu_device *adev = psp->adev; 536 537 ret = psp_v11_0_ring_stop(psp, ring_type); 538 if (ret) 539 DRM_ERROR("Fail to stop psp ring\n"); 540 541 amdgpu_bo_free_kernel(&adev->firmware.rbuf, 542 &ring->ring_mem_mc_addr, 543 (void **)&ring->ring_mem); 544 545 return ret; 546 } 547 548 static int psp_v11_0_mode1_reset(struct psp_context *psp) 549 { 550 int ret; 551 uint32_t offset; 552 struct amdgpu_device *adev = psp->adev; 553 554 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); 555 556 ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false); 557 558 if (ret) { 559 DRM_INFO("psp is not working correctly before mode1 reset!\n"); 560 return -EINVAL; 561 } 562 563 /*send the mode 1 reset command*/ 564 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST); 565 566 msleep(500); 567 568 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33); 569 570 ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false); 571 572 if (ret) { 573 DRM_INFO("psp mode 1 reset failed!\n"); 574 return -EINVAL; 575 } 576 577 DRM_INFO("psp mode1 reset succeed \n"); 578 579 return 0; 580 } 581 582 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg) 583 { 584 int ret; 585 int i; 586 uint32_t data_32; 587 int max_wait; 588 struct amdgpu_device *adev = psp->adev; 589 590 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20); 591 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32); 592 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg); 593 594 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout; 595 for (i = 0; i < max_wait; i++) { 596 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 597 0x80000000, 0x80000000, false); 598 if (ret == 0) 599 break; 600 } 601 if (i < max_wait) 602 ret = 0; 603 else 604 ret = -ETIME; 605 606 DRM_DEBUG("training %s %s, cost %d @ %d ms\n", 607 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long", 608 (ret == 0) ? "succeed" : "failed", 609 i, adev->usec_timeout/1000); 610 return ret; 611 } 612 613 /* 614 * save and restore proces 615 */ 616 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops) 617 { 618 struct psp_memory_training_context *ctx = &psp->mem_train_ctx; 619 uint32_t *pcache = (uint32_t*)ctx->sys_cache; 620 struct amdgpu_device *adev = psp->adev; 621 uint32_t p2c_header[4]; 622 uint32_t sz; 623 void *buf; 624 int ret; 625 626 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) { 627 DRM_DEBUG("Memory training is not supported.\n"); 628 return 0; 629 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) { 630 DRM_ERROR("Memory training initialization failure.\n"); 631 return -EINVAL; 632 } 633 634 if (psp_v11_0_is_sos_alive(psp)) { 635 DRM_DEBUG("SOS is alive, skip memory training.\n"); 636 return 0; 637 } 638 639 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false); 640 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n", 641 pcache[0], pcache[1], pcache[2], pcache[3], 642 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]); 643 644 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 645 DRM_DEBUG("Short training depends on restore.\n"); 646 ops |= PSP_MEM_TRAIN_RESTORE; 647 } 648 649 if ((ops & PSP_MEM_TRAIN_RESTORE) && 650 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 651 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n"); 652 ops |= PSP_MEM_TRAIN_SAVE; 653 } 654 655 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 656 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE && 657 pcache[3] == p2c_header[3])) { 658 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n"); 659 ops |= PSP_MEM_TRAIN_SAVE; 660 } 661 662 if ((ops & PSP_MEM_TRAIN_SAVE) && 663 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) { 664 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n"); 665 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG; 666 } 667 668 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 669 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG; 670 ops |= PSP_MEM_TRAIN_SAVE; 671 } 672 673 DRM_DEBUG("Memory training ops:%x.\n", ops); 674 675 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) { 676 /* 677 * Long traing will encroach certain mount of bottom VRAM, 678 * saving the content of this bottom VRAM to system memory 679 * before training, and restoring it after training to avoid 680 * VRAM corruption. 681 */ 682 sz = GDDR6_MEM_TRAINING_ENCROACHED_SIZE; 683 684 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) { 685 DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n", 686 adev->gmc.visible_vram_size, 687 adev->mman.aper_base_kaddr); 688 return -EINVAL; 689 } 690 691 buf = vmalloc(sz); 692 if (!buf) { 693 DRM_ERROR("failed to allocate system memory.\n"); 694 return -ENOMEM; 695 } 696 697 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz); 698 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN); 699 if (ret) { 700 DRM_ERROR("Send long training msg failed.\n"); 701 vfree(buf); 702 return ret; 703 } 704 705 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz); 706 adev->nbio.funcs->hdp_flush(adev, NULL); 707 vfree(buf); 708 } 709 710 if (ops & PSP_MEM_TRAIN_SAVE) { 711 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false); 712 } 713 714 if (ops & PSP_MEM_TRAIN_RESTORE) { 715 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true); 716 } 717 718 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) { 719 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ? 720 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN); 721 if (ret) { 722 DRM_ERROR("send training msg failed.\n"); 723 return ret; 724 } 725 } 726 ctx->training_cnt++; 727 return 0; 728 } 729 730 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp) 731 { 732 uint32_t data; 733 struct amdgpu_device *adev = psp->adev; 734 735 if (amdgpu_sriov_vf(adev)) 736 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102); 737 else 738 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67); 739 740 return data; 741 } 742 743 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value) 744 { 745 struct amdgpu_device *adev = psp->adev; 746 747 if (amdgpu_sriov_vf(adev)) { 748 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value); 749 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD); 750 } else 751 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value); 752 } 753 754 static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, dma_addr_t dma_addr) 755 { 756 struct amdgpu_device *adev = psp->adev; 757 uint32_t reg_status; 758 int ret, i = 0; 759 760 /* Write lower 32-bit address of the PD Controller FW */ 761 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, lower_32_bits(dma_addr)); 762 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 763 0x80000000, 0x80000000, false); 764 if (ret) 765 return ret; 766 767 /* Fireup interrupt so PSP can pick up the lower address */ 768 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 0x800000); 769 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 770 0x80000000, 0x80000000, false); 771 if (ret) 772 return ret; 773 774 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35); 775 776 if ((reg_status & 0xFFFF) != 0) { 777 DRM_ERROR("Lower address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %02x...\n", 778 reg_status & 0xFFFF); 779 return -EIO; 780 } 781 782 /* Write upper 32-bit address of the PD Controller FW */ 783 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, upper_32_bits(dma_addr)); 784 785 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 786 0x80000000, 0x80000000, false); 787 if (ret) 788 return ret; 789 790 /* Fireup interrupt so PSP can pick up the upper address */ 791 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, 0x4000000); 792 793 /* FW load takes very long time */ 794 do { 795 msleep(1000); 796 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35); 797 798 if (reg_status & 0x80000000) 799 goto done; 800 801 } while (++i < USBC_PD_POLLING_LIMIT_S); 802 803 return -ETIME; 804 done: 805 806 if ((reg_status & 0xFFFF) != 0) { 807 DRM_ERROR("Upper address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = x%04x\n", 808 reg_status & 0xFFFF); 809 return -EIO; 810 } 811 812 return 0; 813 } 814 815 static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver) 816 { 817 struct amdgpu_device *adev = psp->adev; 818 int ret; 819 820 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER); 821 822 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), 823 0x80000000, 0x80000000, false); 824 if (!ret) 825 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36); 826 827 return ret; 828 } 829 830 static const struct psp_funcs psp_v11_0_funcs = { 831 .init_microcode = psp_v11_0_init_microcode, 832 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb, 833 .bootloader_load_spl = psp_v11_0_bootloader_load_spl, 834 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv, 835 .bootloader_load_sos = psp_v11_0_bootloader_load_sos, 836 .ring_init = psp_v11_0_ring_init, 837 .ring_create = psp_v11_0_ring_create, 838 .ring_stop = psp_v11_0_ring_stop, 839 .ring_destroy = psp_v11_0_ring_destroy, 840 .mode1_reset = psp_v11_0_mode1_reset, 841 .mem_training = psp_v11_0_memory_training, 842 .ring_get_wptr = psp_v11_0_ring_get_wptr, 843 .ring_set_wptr = psp_v11_0_ring_set_wptr, 844 .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw, 845 .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw 846 }; 847 848 void psp_v11_0_set_psp_funcs(struct psp_context *psp) 849 { 850 psp->funcs = &psp_v11_0_funcs; 851 } 852