1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVIDIA Tegra xHCI host controller driver 4 * 5 * Copyright (C) 2014 NVIDIA Corporation 6 * Copyright (C) 2014 Google, Inc. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/firmware.h> 13 #include <linux/interrupt.h> 14 #include <linux/iopoll.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/of_device.h> 18 #include <linux/phy/phy.h> 19 #include <linux/phy/tegra/xusb.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm.h> 22 #include <linux/pm_domain.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/reset.h> 26 #include <linux/slab.h> 27 #include <linux/usb/otg.h> 28 #include <linux/usb/phy.h> 29 #include <linux/usb/role.h> 30 #include <soc/tegra/pmc.h> 31 32 #include "xhci.h" 33 34 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000 35 #define TEGRA_XHCI_SS_LOW_SPEED 12000000 36 37 /* FPCI CFG registers */ 38 #define XUSB_CFG_1 0x004 39 #define XUSB_IO_SPACE_EN BIT(0) 40 #define XUSB_MEM_SPACE_EN BIT(1) 41 #define XUSB_BUS_MASTER_EN BIT(2) 42 #define XUSB_CFG_4 0x010 43 #define XUSB_BASE_ADDR_SHIFT 15 44 #define XUSB_BASE_ADDR_MASK 0x1ffff 45 #define XUSB_CFG_16 0x040 46 #define XUSB_CFG_24 0x060 47 #define XUSB_CFG_AXI_CFG 0x0f8 48 #define XUSB_CFG_ARU_C11_CSBRANGE 0x41c 49 #define XUSB_CFG_ARU_CONTEXT 0x43c 50 #define XUSB_CFG_ARU_CONTEXT_HS_PLS 0x478 51 #define XUSB_CFG_ARU_CONTEXT_FS_PLS 0x47c 52 #define XUSB_CFG_ARU_CONTEXT_HSFS_SPEED 0x480 53 #define XUSB_CFG_ARU_CONTEXT_HSFS_PP 0x484 54 #define XUSB_CFG_CSB_BASE_ADDR 0x800 55 56 /* FPCI mailbox registers */ 57 /* XUSB_CFG_ARU_MBOX_CMD */ 58 #define MBOX_DEST_FALC BIT(27) 59 #define MBOX_DEST_PME BIT(28) 60 #define MBOX_DEST_SMI BIT(29) 61 #define MBOX_DEST_XHCI BIT(30) 62 #define MBOX_INT_EN BIT(31) 63 /* XUSB_CFG_ARU_MBOX_DATA_IN and XUSB_CFG_ARU_MBOX_DATA_OUT */ 64 #define CMD_DATA_SHIFT 0 65 #define CMD_DATA_MASK 0xffffff 66 #define CMD_TYPE_SHIFT 24 67 #define CMD_TYPE_MASK 0xff 68 /* XUSB_CFG_ARU_MBOX_OWNER */ 69 #define MBOX_OWNER_NONE 0 70 #define MBOX_OWNER_FW 1 71 #define MBOX_OWNER_SW 2 72 #define XUSB_CFG_ARU_SMI_INTR 0x428 73 #define MBOX_SMI_INTR_FW_HANG BIT(1) 74 #define MBOX_SMI_INTR_EN BIT(3) 75 76 /* IPFS registers */ 77 #define IPFS_XUSB_HOST_MSI_BAR_SZ_0 0x0c0 78 #define IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0 0x0c4 79 #define IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0 0x0c8 80 #define IPFS_XUSB_HOST_MSI_VEC0_0 0x100 81 #define IPFS_XUSB_HOST_MSI_EN_VEC0_0 0x140 82 #define IPFS_XUSB_HOST_CONFIGURATION_0 0x180 83 #define IPFS_EN_FPCI BIT(0) 84 #define IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0 0x184 85 #define IPFS_XUSB_HOST_INTR_MASK_0 0x188 86 #define IPFS_IP_INT_MASK BIT(16) 87 #define IPFS_XUSB_HOST_INTR_ENABLE_0 0x198 88 #define IPFS_XUSB_HOST_UFPCI_CONFIG_0 0x19c 89 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc 90 #define IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0 0x1dc 91 92 #define CSB_PAGE_SELECT_MASK 0x7fffff 93 #define CSB_PAGE_SELECT_SHIFT 9 94 #define CSB_PAGE_OFFSET_MASK 0x1ff 95 #define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \ 96 CSB_PAGE_SELECT_MASK) 97 #define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK) 98 99 /* Falcon CSB registers */ 100 #define XUSB_FALC_CPUCTL 0x100 101 #define CPUCTL_STARTCPU BIT(1) 102 #define CPUCTL_STATE_HALTED BIT(4) 103 #define CPUCTL_STATE_STOPPED BIT(5) 104 #define XUSB_FALC_BOOTVEC 0x104 105 #define XUSB_FALC_DMACTL 0x10c 106 #define XUSB_FALC_IMFILLRNG1 0x154 107 #define IMFILLRNG1_TAG_MASK 0xffff 108 #define IMFILLRNG1_TAG_LO_SHIFT 0 109 #define IMFILLRNG1_TAG_HI_SHIFT 16 110 #define XUSB_FALC_IMFILLCTL 0x158 111 112 /* MP CSB registers */ 113 #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00 114 #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04 115 #define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08 116 #define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10 117 #define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8 118 #define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff 119 #define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24 120 #define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff 121 #define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14 122 #define L2IMEMOP_ACTION_SHIFT 24 123 #define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT) 124 #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT) 125 #define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT 0x101a18 126 #define L2IMEMOP_RESULT_VLD BIT(31) 127 #define XUSB_CSB_MP_APMAP 0x10181c 128 #define APMAP_BOOTPATH BIT(31) 129 130 #define IMEM_BLOCK_SIZE 256 131 132 struct tegra_xusb_fw_header { 133 __le32 boot_loadaddr_in_imem; 134 __le32 boot_codedfi_offset; 135 __le32 boot_codetag; 136 __le32 boot_codesize; 137 __le32 phys_memaddr; 138 __le16 reqphys_memsize; 139 __le16 alloc_phys_memsize; 140 __le32 rodata_img_offset; 141 __le32 rodata_section_start; 142 __le32 rodata_section_end; 143 __le32 main_fnaddr; 144 __le32 fwimg_cksum; 145 __le32 fwimg_created_time; 146 __le32 imem_resident_start; 147 __le32 imem_resident_end; 148 __le32 idirect_start; 149 __le32 idirect_end; 150 __le32 l2_imem_start; 151 __le32 l2_imem_end; 152 __le32 version_id; 153 u8 init_ddirect; 154 u8 reserved[3]; 155 __le32 phys_addr_log_buffer; 156 __le32 total_log_entries; 157 __le32 dequeue_ptr; 158 __le32 dummy_var[2]; 159 __le32 fwimg_len; 160 u8 magic[8]; 161 __le32 ss_low_power_entry_timeout; 162 u8 num_hsic_port; 163 u8 padding[139]; /* Pad to 256 bytes */ 164 }; 165 166 struct tegra_xusb_phy_type { 167 const char *name; 168 unsigned int num; 169 }; 170 171 struct tegra_xusb_mbox_regs { 172 u16 cmd; 173 u16 data_in; 174 u16 data_out; 175 u16 owner; 176 }; 177 178 struct tegra_xusb_context_soc { 179 struct { 180 const unsigned int *offsets; 181 unsigned int num_offsets; 182 } ipfs; 183 184 struct { 185 const unsigned int *offsets; 186 unsigned int num_offsets; 187 } fpci; 188 }; 189 190 struct tegra_xusb_soc { 191 const char *firmware; 192 const char * const *supply_names; 193 unsigned int num_supplies; 194 const struct tegra_xusb_phy_type *phy_types; 195 unsigned int num_types; 196 const struct tegra_xusb_context_soc *context; 197 198 struct { 199 struct { 200 unsigned int offset; 201 unsigned int count; 202 } usb2, ulpi, hsic, usb3; 203 } ports; 204 205 struct tegra_xusb_mbox_regs mbox; 206 207 bool scale_ss_clock; 208 bool has_ipfs; 209 bool lpm_support; 210 bool otg_reset_sspi; 211 }; 212 213 struct tegra_xusb_context { 214 u32 *ipfs; 215 u32 *fpci; 216 }; 217 218 struct tegra_xusb { 219 struct device *dev; 220 void __iomem *regs; 221 struct usb_hcd *hcd; 222 223 struct mutex lock; 224 225 int xhci_irq; 226 int mbox_irq; 227 228 void __iomem *ipfs_base; 229 void __iomem *fpci_base; 230 231 const struct tegra_xusb_soc *soc; 232 233 struct regulator_bulk_data *supplies; 234 235 struct tegra_xusb_padctl *padctl; 236 237 struct clk *host_clk; 238 struct clk *falcon_clk; 239 struct clk *ss_clk; 240 struct clk *ss_src_clk; 241 struct clk *hs_src_clk; 242 struct clk *fs_src_clk; 243 struct clk *pll_u_480m; 244 struct clk *clk_m; 245 struct clk *pll_e; 246 247 struct reset_control *host_rst; 248 struct reset_control *ss_rst; 249 250 struct device *genpd_dev_host; 251 struct device *genpd_dev_ss; 252 struct device_link *genpd_dl_host; 253 struct device_link *genpd_dl_ss; 254 255 struct phy **phys; 256 unsigned int num_phys; 257 258 struct usb_phy **usbphy; 259 unsigned int num_usb_phys; 260 int otg_usb2_port; 261 int otg_usb3_port; 262 bool host_mode; 263 struct notifier_block id_nb; 264 struct work_struct id_work; 265 266 /* Firmware loading related */ 267 struct { 268 size_t size; 269 void *virt; 270 dma_addr_t phys; 271 } fw; 272 273 struct tegra_xusb_context context; 274 }; 275 276 static struct hc_driver __read_mostly tegra_xhci_hc_driver; 277 278 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset) 279 { 280 return readl(tegra->fpci_base + offset); 281 } 282 283 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value, 284 unsigned int offset) 285 { 286 writel(value, tegra->fpci_base + offset); 287 } 288 289 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset) 290 { 291 return readl(tegra->ipfs_base + offset); 292 } 293 294 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value, 295 unsigned int offset) 296 { 297 writel(value, tegra->ipfs_base + offset); 298 } 299 300 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset) 301 { 302 u32 page = CSB_PAGE_SELECT(offset); 303 u32 ofs = CSB_PAGE_OFFSET(offset); 304 305 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE); 306 307 return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs); 308 } 309 310 static void csb_writel(struct tegra_xusb *tegra, u32 value, 311 unsigned int offset) 312 { 313 u32 page = CSB_PAGE_SELECT(offset); 314 u32 ofs = CSB_PAGE_OFFSET(offset); 315 316 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE); 317 fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs); 318 } 319 320 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra, 321 unsigned long rate) 322 { 323 unsigned long new_parent_rate, old_parent_rate; 324 struct clk *clk = tegra->ss_src_clk; 325 unsigned int div; 326 int err; 327 328 if (clk_get_rate(clk) == rate) 329 return 0; 330 331 switch (rate) { 332 case TEGRA_XHCI_SS_HIGH_SPEED: 333 /* 334 * Reparent to PLLU_480M. Set divider first to avoid 335 * overclocking. 336 */ 337 old_parent_rate = clk_get_rate(clk_get_parent(clk)); 338 new_parent_rate = clk_get_rate(tegra->pll_u_480m); 339 div = new_parent_rate / rate; 340 341 err = clk_set_rate(clk, old_parent_rate / div); 342 if (err) 343 return err; 344 345 err = clk_set_parent(clk, tegra->pll_u_480m); 346 if (err) 347 return err; 348 349 /* 350 * The rate should already be correct, but set it again just 351 * to be sure. 352 */ 353 err = clk_set_rate(clk, rate); 354 if (err) 355 return err; 356 357 break; 358 359 case TEGRA_XHCI_SS_LOW_SPEED: 360 /* Reparent to CLK_M */ 361 err = clk_set_parent(clk, tegra->clk_m); 362 if (err) 363 return err; 364 365 err = clk_set_rate(clk, rate); 366 if (err) 367 return err; 368 369 break; 370 371 default: 372 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate); 373 return -EINVAL; 374 } 375 376 if (clk_get_rate(clk) != rate) { 377 dev_err(tegra->dev, "SS clock doesn't match requested rate\n"); 378 return -EINVAL; 379 } 380 381 return 0; 382 } 383 384 static unsigned long extract_field(u32 value, unsigned int start, 385 unsigned int count) 386 { 387 return (value >> start) & ((1 << count) - 1); 388 } 389 390 /* Command requests from the firmware */ 391 enum tegra_xusb_mbox_cmd { 392 MBOX_CMD_MSG_ENABLED = 1, 393 MBOX_CMD_INC_FALC_CLOCK, 394 MBOX_CMD_DEC_FALC_CLOCK, 395 MBOX_CMD_INC_SSPI_CLOCK, 396 MBOX_CMD_DEC_SSPI_CLOCK, 397 MBOX_CMD_SET_BW, /* no ACK/NAK required */ 398 MBOX_CMD_SET_SS_PWR_GATING, 399 MBOX_CMD_SET_SS_PWR_UNGATING, 400 MBOX_CMD_SAVE_DFE_CTLE_CTX, 401 MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */ 402 MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */ 403 MBOX_CMD_START_HSIC_IDLE, 404 MBOX_CMD_STOP_HSIC_IDLE, 405 MBOX_CMD_DBC_WAKE_STACK, /* unused */ 406 MBOX_CMD_HSIC_PRETEND_CONNECT, 407 MBOX_CMD_RESET_SSPI, 408 MBOX_CMD_DISABLE_SS_LFPS_DETECTION, 409 MBOX_CMD_ENABLE_SS_LFPS_DETECTION, 410 411 MBOX_CMD_MAX, 412 413 /* Response message to above commands */ 414 MBOX_CMD_ACK = 128, 415 MBOX_CMD_NAK 416 }; 417 418 struct tegra_xusb_mbox_msg { 419 u32 cmd; 420 u32 data; 421 }; 422 423 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg) 424 { 425 return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT | 426 (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT; 427 } 428 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg, 429 u32 value) 430 { 431 msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK; 432 msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK; 433 } 434 435 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd) 436 { 437 switch (cmd) { 438 case MBOX_CMD_SET_BW: 439 case MBOX_CMD_ACK: 440 case MBOX_CMD_NAK: 441 return false; 442 443 default: 444 return true; 445 } 446 } 447 448 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, 449 const struct tegra_xusb_mbox_msg *msg) 450 { 451 bool wait_for_idle = false; 452 u32 value; 453 454 /* 455 * Acquire the mailbox. The firmware still owns the mailbox for 456 * ACK/NAK messages. 457 */ 458 if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) { 459 value = fpci_readl(tegra, tegra->soc->mbox.owner); 460 if (value != MBOX_OWNER_NONE) { 461 dev_err(tegra->dev, "mailbox is busy\n"); 462 return -EBUSY; 463 } 464 465 fpci_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner); 466 467 value = fpci_readl(tegra, tegra->soc->mbox.owner); 468 if (value != MBOX_OWNER_SW) { 469 dev_err(tegra->dev, "failed to acquire mailbox\n"); 470 return -EBUSY; 471 } 472 473 wait_for_idle = true; 474 } 475 476 value = tegra_xusb_mbox_pack(msg); 477 fpci_writel(tegra, value, tegra->soc->mbox.data_in); 478 479 value = fpci_readl(tegra, tegra->soc->mbox.cmd); 480 value |= MBOX_INT_EN | MBOX_DEST_FALC; 481 fpci_writel(tegra, value, tegra->soc->mbox.cmd); 482 483 if (wait_for_idle) { 484 unsigned long timeout = jiffies + msecs_to_jiffies(250); 485 486 while (time_before(jiffies, timeout)) { 487 value = fpci_readl(tegra, tegra->soc->mbox.owner); 488 if (value == MBOX_OWNER_NONE) 489 break; 490 491 usleep_range(10, 20); 492 } 493 494 if (time_after(jiffies, timeout)) 495 value = fpci_readl(tegra, tegra->soc->mbox.owner); 496 497 if (value != MBOX_OWNER_NONE) 498 return -ETIMEDOUT; 499 } 500 501 return 0; 502 } 503 504 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data) 505 { 506 struct tegra_xusb *tegra = data; 507 u32 value; 508 509 /* clear mailbox interrupts */ 510 value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR); 511 fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR); 512 513 if (value & MBOX_SMI_INTR_FW_HANG) 514 dev_err(tegra->dev, "controller firmware hang\n"); 515 516 return IRQ_WAKE_THREAD; 517 } 518 519 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra, 520 const struct tegra_xusb_mbox_msg *msg) 521 { 522 struct tegra_xusb_padctl *padctl = tegra->padctl; 523 const struct tegra_xusb_soc *soc = tegra->soc; 524 struct device *dev = tegra->dev; 525 struct tegra_xusb_mbox_msg rsp; 526 unsigned long mask; 527 unsigned int port; 528 bool idle, enable; 529 int err = 0; 530 531 memset(&rsp, 0, sizeof(rsp)); 532 533 switch (msg->cmd) { 534 case MBOX_CMD_INC_FALC_CLOCK: 535 case MBOX_CMD_DEC_FALC_CLOCK: 536 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000; 537 if (rsp.data != msg->data) 538 rsp.cmd = MBOX_CMD_NAK; 539 else 540 rsp.cmd = MBOX_CMD_ACK; 541 542 break; 543 544 case MBOX_CMD_INC_SSPI_CLOCK: 545 case MBOX_CMD_DEC_SSPI_CLOCK: 546 if (tegra->soc->scale_ss_clock) { 547 err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000); 548 if (err < 0) 549 rsp.cmd = MBOX_CMD_NAK; 550 else 551 rsp.cmd = MBOX_CMD_ACK; 552 553 rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000; 554 } else { 555 rsp.cmd = MBOX_CMD_ACK; 556 rsp.data = msg->data; 557 } 558 559 break; 560 561 case MBOX_CMD_SET_BW: 562 /* 563 * TODO: Request bandwidth once EMC scaling is supported. 564 * Ignore for now since ACK/NAK is not required for SET_BW 565 * messages. 566 */ 567 break; 568 569 case MBOX_CMD_SAVE_DFE_CTLE_CTX: 570 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data); 571 if (err < 0) { 572 dev_err(dev, "failed to save context for USB3#%u: %d\n", 573 msg->data, err); 574 rsp.cmd = MBOX_CMD_NAK; 575 } else { 576 rsp.cmd = MBOX_CMD_ACK; 577 } 578 579 rsp.data = msg->data; 580 break; 581 582 case MBOX_CMD_START_HSIC_IDLE: 583 case MBOX_CMD_STOP_HSIC_IDLE: 584 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE) 585 idle = false; 586 else 587 idle = true; 588 589 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset, 590 soc->ports.hsic.count); 591 592 for_each_set_bit(port, &mask, 32) { 593 err = tegra_xusb_padctl_hsic_set_idle(padctl, port, 594 idle); 595 if (err < 0) 596 break; 597 } 598 599 if (err < 0) { 600 dev_err(dev, "failed to set HSIC#%u %s: %d\n", port, 601 idle ? "idle" : "busy", err); 602 rsp.cmd = MBOX_CMD_NAK; 603 } else { 604 rsp.cmd = MBOX_CMD_ACK; 605 } 606 607 rsp.data = msg->data; 608 break; 609 610 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION: 611 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION: 612 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION) 613 enable = false; 614 else 615 enable = true; 616 617 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset, 618 soc->ports.usb3.count); 619 620 for_each_set_bit(port, &mask, soc->ports.usb3.count) { 621 err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl, 622 port, 623 enable); 624 if (err < 0) 625 break; 626 } 627 628 if (err < 0) { 629 dev_err(dev, 630 "failed to %s LFPS detection on USB3#%u: %d\n", 631 enable ? "enable" : "disable", port, err); 632 rsp.cmd = MBOX_CMD_NAK; 633 } else { 634 rsp.cmd = MBOX_CMD_ACK; 635 } 636 637 rsp.data = msg->data; 638 break; 639 640 default: 641 dev_warn(dev, "unknown message: %#x\n", msg->cmd); 642 break; 643 } 644 645 if (rsp.cmd) { 646 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK"; 647 648 err = tegra_xusb_mbox_send(tegra, &rsp); 649 if (err < 0) 650 dev_err(dev, "failed to send %s: %d\n", cmd, err); 651 } 652 } 653 654 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data) 655 { 656 struct tegra_xusb *tegra = data; 657 struct tegra_xusb_mbox_msg msg; 658 u32 value; 659 660 mutex_lock(&tegra->lock); 661 662 value = fpci_readl(tegra, tegra->soc->mbox.data_out); 663 tegra_xusb_mbox_unpack(&msg, value); 664 665 value = fpci_readl(tegra, tegra->soc->mbox.cmd); 666 value &= ~MBOX_DEST_SMI; 667 fpci_writel(tegra, value, tegra->soc->mbox.cmd); 668 669 /* clear mailbox owner if no ACK/NAK is required */ 670 if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd)) 671 fpci_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner); 672 673 tegra_xusb_mbox_handle(tegra, &msg); 674 675 mutex_unlock(&tegra->lock); 676 return IRQ_HANDLED; 677 } 678 679 static void tegra_xusb_config(struct tegra_xusb *tegra) 680 { 681 u32 regs = tegra->hcd->rsrc_start; 682 u32 value; 683 684 if (tegra->soc->has_ipfs) { 685 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0); 686 value |= IPFS_EN_FPCI; 687 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0); 688 689 usleep_range(10, 20); 690 } 691 692 /* Program BAR0 space */ 693 value = fpci_readl(tegra, XUSB_CFG_4); 694 value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); 695 value |= regs & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); 696 fpci_writel(tegra, value, XUSB_CFG_4); 697 698 usleep_range(100, 200); 699 700 /* Enable bus master */ 701 value = fpci_readl(tegra, XUSB_CFG_1); 702 value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN; 703 fpci_writel(tegra, value, XUSB_CFG_1); 704 705 if (tegra->soc->has_ipfs) { 706 /* Enable interrupt assertion */ 707 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0); 708 value |= IPFS_IP_INT_MASK; 709 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0); 710 711 /* Set hysteresis */ 712 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0); 713 } 714 } 715 716 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra) 717 { 718 int err; 719 720 err = clk_prepare_enable(tegra->pll_e); 721 if (err < 0) 722 return err; 723 724 err = clk_prepare_enable(tegra->host_clk); 725 if (err < 0) 726 goto disable_plle; 727 728 err = clk_prepare_enable(tegra->ss_clk); 729 if (err < 0) 730 goto disable_host; 731 732 err = clk_prepare_enable(tegra->falcon_clk); 733 if (err < 0) 734 goto disable_ss; 735 736 err = clk_prepare_enable(tegra->fs_src_clk); 737 if (err < 0) 738 goto disable_falc; 739 740 err = clk_prepare_enable(tegra->hs_src_clk); 741 if (err < 0) 742 goto disable_fs_src; 743 744 if (tegra->soc->scale_ss_clock) { 745 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED); 746 if (err < 0) 747 goto disable_hs_src; 748 } 749 750 return 0; 751 752 disable_hs_src: 753 clk_disable_unprepare(tegra->hs_src_clk); 754 disable_fs_src: 755 clk_disable_unprepare(tegra->fs_src_clk); 756 disable_falc: 757 clk_disable_unprepare(tegra->falcon_clk); 758 disable_ss: 759 clk_disable_unprepare(tegra->ss_clk); 760 disable_host: 761 clk_disable_unprepare(tegra->host_clk); 762 disable_plle: 763 clk_disable_unprepare(tegra->pll_e); 764 return err; 765 } 766 767 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra) 768 { 769 clk_disable_unprepare(tegra->pll_e); 770 clk_disable_unprepare(tegra->host_clk); 771 clk_disable_unprepare(tegra->ss_clk); 772 clk_disable_unprepare(tegra->falcon_clk); 773 clk_disable_unprepare(tegra->fs_src_clk); 774 clk_disable_unprepare(tegra->hs_src_clk); 775 } 776 777 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra) 778 { 779 unsigned int i; 780 int err; 781 782 for (i = 0; i < tegra->num_phys; i++) { 783 err = phy_init(tegra->phys[i]); 784 if (err) 785 goto disable_phy; 786 787 err = phy_power_on(tegra->phys[i]); 788 if (err) { 789 phy_exit(tegra->phys[i]); 790 goto disable_phy; 791 } 792 } 793 794 return 0; 795 796 disable_phy: 797 while (i--) { 798 phy_power_off(tegra->phys[i]); 799 phy_exit(tegra->phys[i]); 800 } 801 802 return err; 803 } 804 805 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra) 806 { 807 unsigned int i; 808 809 for (i = 0; i < tegra->num_phys; i++) { 810 phy_power_off(tegra->phys[i]); 811 phy_exit(tegra->phys[i]); 812 } 813 } 814 815 static int tegra_xusb_runtime_suspend(struct device *dev) 816 { 817 struct tegra_xusb *tegra = dev_get_drvdata(dev); 818 819 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies); 820 tegra_xusb_clk_disable(tegra); 821 822 return 0; 823 } 824 825 static int tegra_xusb_runtime_resume(struct device *dev) 826 { 827 struct tegra_xusb *tegra = dev_get_drvdata(dev); 828 int err; 829 830 err = tegra_xusb_clk_enable(tegra); 831 if (err) { 832 dev_err(dev, "failed to enable clocks: %d\n", err); 833 return err; 834 } 835 836 err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies); 837 if (err) { 838 dev_err(dev, "failed to enable regulators: %d\n", err); 839 goto disable_clk; 840 } 841 842 return 0; 843 844 disable_clk: 845 tegra_xusb_clk_disable(tegra); 846 return err; 847 } 848 849 #ifdef CONFIG_PM_SLEEP 850 static int tegra_xusb_init_context(struct tegra_xusb *tegra) 851 { 852 const struct tegra_xusb_context_soc *soc = tegra->soc->context; 853 854 tegra->context.ipfs = devm_kcalloc(tegra->dev, soc->ipfs.num_offsets, 855 sizeof(u32), GFP_KERNEL); 856 if (!tegra->context.ipfs) 857 return -ENOMEM; 858 859 tegra->context.fpci = devm_kcalloc(tegra->dev, soc->fpci.num_offsets, 860 sizeof(u32), GFP_KERNEL); 861 if (!tegra->context.fpci) 862 return -ENOMEM; 863 864 return 0; 865 } 866 #else 867 static inline int tegra_xusb_init_context(struct tegra_xusb *tegra) 868 { 869 return 0; 870 } 871 #endif 872 873 static int tegra_xusb_request_firmware(struct tegra_xusb *tegra) 874 { 875 struct tegra_xusb_fw_header *header; 876 const struct firmware *fw; 877 int err; 878 879 err = request_firmware(&fw, tegra->soc->firmware, tegra->dev); 880 if (err < 0) { 881 dev_err(tegra->dev, "failed to request firmware: %d\n", err); 882 return err; 883 } 884 885 /* Load Falcon controller with its firmware. */ 886 header = (struct tegra_xusb_fw_header *)fw->data; 887 tegra->fw.size = le32_to_cpu(header->fwimg_len); 888 889 tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size, 890 &tegra->fw.phys, GFP_KERNEL); 891 if (!tegra->fw.virt) { 892 dev_err(tegra->dev, "failed to allocate memory for firmware\n"); 893 release_firmware(fw); 894 return -ENOMEM; 895 } 896 897 header = (struct tegra_xusb_fw_header *)tegra->fw.virt; 898 memcpy(tegra->fw.virt, fw->data, tegra->fw.size); 899 release_firmware(fw); 900 901 return 0; 902 } 903 904 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) 905 { 906 unsigned int code_tag_blocks, code_size_blocks, code_blocks; 907 struct xhci_cap_regs __iomem *cap = tegra->regs; 908 struct tegra_xusb_fw_header *header; 909 struct device *dev = tegra->dev; 910 struct xhci_op_regs __iomem *op; 911 unsigned long timeout; 912 time64_t timestamp; 913 struct tm time; 914 u64 address; 915 u32 value; 916 int err; 917 918 header = (struct tegra_xusb_fw_header *)tegra->fw.virt; 919 op = tegra->regs + HC_LENGTH(readl(&cap->hc_capbase)); 920 921 if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) { 922 dev_info(dev, "Firmware already loaded, Falcon state %#x\n", 923 csb_readl(tegra, XUSB_FALC_CPUCTL)); 924 return 0; 925 } 926 927 /* Program the size of DFI into ILOAD_ATTR. */ 928 csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR); 929 930 /* 931 * Boot code of the firmware reads the ILOAD_BASE registers 932 * to get to the start of the DFI in system memory. 933 */ 934 address = tegra->fw.phys + sizeof(*header); 935 csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI); 936 csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO); 937 938 /* Set BOOTPATH to 1 in APMAP. */ 939 csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP); 940 941 /* Invalidate L2IMEM. */ 942 csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG); 943 944 /* 945 * Initiate fetch of bootcode from system memory into L2IMEM. 946 * Program bootcode location and size in system memory. 947 */ 948 code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag), 949 IMEM_BLOCK_SIZE); 950 code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize), 951 IMEM_BLOCK_SIZE); 952 code_blocks = code_tag_blocks + code_size_blocks; 953 954 value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) << 955 L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) | 956 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) << 957 L2IMEMOP_SIZE_SRC_COUNT_SHIFT); 958 csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE); 959 960 /* Trigger L2IMEM load operation. */ 961 csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT, 962 XUSB_CSB_MP_L2IMEMOP_TRIG); 963 964 /* Setup Falcon auto-fill. */ 965 csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL); 966 967 value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) << 968 IMFILLRNG1_TAG_LO_SHIFT) | 969 ((code_blocks & IMFILLRNG1_TAG_MASK) << 970 IMFILLRNG1_TAG_HI_SHIFT); 971 csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1); 972 973 csb_writel(tegra, 0, XUSB_FALC_DMACTL); 974 975 /* wait for RESULT_VLD to get set */ 976 #define tegra_csb_readl(offset) csb_readl(tegra, offset) 977 err = readx_poll_timeout(tegra_csb_readl, 978 XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT, value, 979 value & L2IMEMOP_RESULT_VLD, 100, 10000); 980 if (err < 0) { 981 dev_err(dev, "DMA controller not ready %#010x\n", value); 982 return err; 983 } 984 #undef tegra_csb_readl 985 986 csb_writel(tegra, le32_to_cpu(header->boot_codetag), 987 XUSB_FALC_BOOTVEC); 988 989 /* Boot Falcon CPU and wait for USBSTS_CNR to get cleared. */ 990 csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL); 991 992 timeout = jiffies + msecs_to_jiffies(200); 993 994 do { 995 value = readl(&op->status); 996 if ((value & STS_CNR) == 0) 997 break; 998 999 usleep_range(1000, 2000); 1000 } while (time_is_after_jiffies(timeout)); 1001 1002 value = readl(&op->status); 1003 if (value & STS_CNR) { 1004 value = csb_readl(tegra, XUSB_FALC_CPUCTL); 1005 dev_err(dev, "XHCI controller not read: %#010x\n", value); 1006 return -EIO; 1007 } 1008 1009 timestamp = le32_to_cpu(header->fwimg_created_time); 1010 time64_to_tm(timestamp, 0, &time); 1011 1012 dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n", 1013 time.tm_year + 1900, time.tm_mon + 1, time.tm_mday, 1014 time.tm_hour, time.tm_min, time.tm_sec); 1015 1016 return 0; 1017 } 1018 1019 static void tegra_xusb_powerdomain_remove(struct device *dev, 1020 struct tegra_xusb *tegra) 1021 { 1022 if (tegra->genpd_dl_ss) 1023 device_link_del(tegra->genpd_dl_ss); 1024 if (tegra->genpd_dl_host) 1025 device_link_del(tegra->genpd_dl_host); 1026 if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss)) 1027 dev_pm_domain_detach(tegra->genpd_dev_ss, true); 1028 if (!IS_ERR_OR_NULL(tegra->genpd_dev_host)) 1029 dev_pm_domain_detach(tegra->genpd_dev_host, true); 1030 } 1031 1032 static int tegra_xusb_powerdomain_init(struct device *dev, 1033 struct tegra_xusb *tegra) 1034 { 1035 int err; 1036 1037 tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, "xusb_host"); 1038 if (IS_ERR(tegra->genpd_dev_host)) { 1039 err = PTR_ERR(tegra->genpd_dev_host); 1040 dev_err(dev, "failed to get host pm-domain: %d\n", err); 1041 return err; 1042 } 1043 1044 tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "xusb_ss"); 1045 if (IS_ERR(tegra->genpd_dev_ss)) { 1046 err = PTR_ERR(tegra->genpd_dev_ss); 1047 dev_err(dev, "failed to get superspeed pm-domain: %d\n", err); 1048 return err; 1049 } 1050 1051 tegra->genpd_dl_host = device_link_add(dev, tegra->genpd_dev_host, 1052 DL_FLAG_PM_RUNTIME | 1053 DL_FLAG_STATELESS); 1054 if (!tegra->genpd_dl_host) { 1055 dev_err(dev, "adding host device link failed!\n"); 1056 return -ENODEV; 1057 } 1058 1059 tegra->genpd_dl_ss = device_link_add(dev, tegra->genpd_dev_ss, 1060 DL_FLAG_PM_RUNTIME | 1061 DL_FLAG_STATELESS); 1062 if (!tegra->genpd_dl_ss) { 1063 dev_err(dev, "adding superspeed device link failed!\n"); 1064 return -ENODEV; 1065 } 1066 1067 return 0; 1068 } 1069 1070 static int __tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra) 1071 { 1072 struct tegra_xusb_mbox_msg msg; 1073 int err; 1074 1075 /* Enable firmware messages from controller. */ 1076 msg.cmd = MBOX_CMD_MSG_ENABLED; 1077 msg.data = 0; 1078 1079 err = tegra_xusb_mbox_send(tegra, &msg); 1080 if (err < 0) 1081 dev_err(tegra->dev, "failed to enable messages: %d\n", err); 1082 1083 return err; 1084 } 1085 1086 static int tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra) 1087 { 1088 int err; 1089 1090 mutex_lock(&tegra->lock); 1091 err = __tegra_xusb_enable_firmware_messages(tegra); 1092 mutex_unlock(&tegra->lock); 1093 1094 return err; 1095 } 1096 1097 static void tegra_xhci_set_port_power(struct tegra_xusb *tegra, bool main, 1098 bool set) 1099 { 1100 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1101 struct usb_hcd *hcd = main ? xhci->main_hcd : xhci->shared_hcd; 1102 unsigned int wait = (!main && !set) ? 1000 : 10; 1103 u16 typeReq = set ? SetPortFeature : ClearPortFeature; 1104 u16 wIndex = main ? tegra->otg_usb2_port + 1 : tegra->otg_usb3_port + 1; 1105 u32 status; 1106 u32 stat_power = main ? USB_PORT_STAT_POWER : USB_SS_PORT_STAT_POWER; 1107 u32 status_val = set ? stat_power : 0; 1108 1109 dev_dbg(tegra->dev, "%s():%s %s port power\n", __func__, 1110 set ? "set" : "clear", main ? "HS" : "SS"); 1111 1112 hcd->driver->hub_control(hcd, typeReq, USB_PORT_FEAT_POWER, wIndex, 1113 NULL, 0); 1114 1115 do { 1116 tegra_xhci_hc_driver.hub_control(hcd, GetPortStatus, 0, wIndex, 1117 (char *) &status, sizeof(status)); 1118 if (status_val == (status & stat_power)) 1119 break; 1120 1121 if (!main && !set) 1122 usleep_range(600, 700); 1123 else 1124 usleep_range(10, 20); 1125 } while (--wait > 0); 1126 1127 if (status_val != (status & stat_power)) 1128 dev_info(tegra->dev, "failed to %s %s PP %d\n", 1129 set ? "set" : "clear", 1130 main ? "HS" : "SS", status); 1131 } 1132 1133 static struct phy *tegra_xusb_get_phy(struct tegra_xusb *tegra, char *name, 1134 int port) 1135 { 1136 unsigned int i, phy_count = 0; 1137 1138 for (i = 0; i < tegra->soc->num_types; i++) { 1139 if (!strncmp(tegra->soc->phy_types[i].name, "usb2", 1140 strlen(name))) 1141 return tegra->phys[phy_count+port]; 1142 1143 phy_count += tegra->soc->phy_types[i].num; 1144 } 1145 1146 return NULL; 1147 } 1148 1149 static void tegra_xhci_id_work(struct work_struct *work) 1150 { 1151 struct tegra_xusb *tegra = container_of(work, struct tegra_xusb, 1152 id_work); 1153 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1154 struct tegra_xusb_mbox_msg msg; 1155 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", 1156 tegra->otg_usb2_port); 1157 u32 status; 1158 int ret; 1159 1160 dev_dbg(tegra->dev, "host mode %s\n", tegra->host_mode ? "on" : "off"); 1161 1162 mutex_lock(&tegra->lock); 1163 1164 if (tegra->host_mode) 1165 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_HOST); 1166 else 1167 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_NONE); 1168 1169 mutex_unlock(&tegra->lock); 1170 1171 if (tegra->host_mode) { 1172 /* switch to host mode */ 1173 if (tegra->otg_usb3_port >= 0) { 1174 if (tegra->soc->otg_reset_sspi) { 1175 /* set PP=0 */ 1176 tegra_xhci_hc_driver.hub_control( 1177 xhci->shared_hcd, GetPortStatus, 1178 0, tegra->otg_usb3_port+1, 1179 (char *) &status, sizeof(status)); 1180 if (status & USB_SS_PORT_STAT_POWER) 1181 tegra_xhci_set_port_power(tegra, false, 1182 false); 1183 1184 /* reset OTG port SSPI */ 1185 msg.cmd = MBOX_CMD_RESET_SSPI; 1186 msg.data = tegra->otg_usb3_port+1; 1187 1188 ret = tegra_xusb_mbox_send(tegra, &msg); 1189 if (ret < 0) { 1190 dev_info(tegra->dev, 1191 "failed to RESET_SSPI %d\n", 1192 ret); 1193 } 1194 } 1195 1196 tegra_xhci_set_port_power(tegra, false, true); 1197 } 1198 1199 tegra_xhci_set_port_power(tegra, true, true); 1200 1201 } else { 1202 if (tegra->otg_usb3_port >= 0) 1203 tegra_xhci_set_port_power(tegra, false, false); 1204 1205 tegra_xhci_set_port_power(tegra, true, false); 1206 } 1207 } 1208 1209 static int tegra_xusb_get_usb2_port(struct tegra_xusb *tegra, 1210 struct usb_phy *usbphy) 1211 { 1212 unsigned int i; 1213 1214 for (i = 0; i < tegra->num_usb_phys; i++) { 1215 if (tegra->usbphy[i] && usbphy == tegra->usbphy[i]) 1216 return i; 1217 } 1218 1219 return -1; 1220 } 1221 1222 static int tegra_xhci_id_notify(struct notifier_block *nb, 1223 unsigned long action, void *data) 1224 { 1225 struct tegra_xusb *tegra = container_of(nb, struct tegra_xusb, 1226 id_nb); 1227 struct usb_phy *usbphy = (struct usb_phy *)data; 1228 1229 dev_dbg(tegra->dev, "%s(): action is %d", __func__, usbphy->last_event); 1230 1231 if ((tegra->host_mode && usbphy->last_event == USB_EVENT_ID) || 1232 (!tegra->host_mode && usbphy->last_event != USB_EVENT_ID)) { 1233 dev_dbg(tegra->dev, "Same role(%d) received. Ignore", 1234 tegra->host_mode); 1235 return NOTIFY_OK; 1236 } 1237 1238 tegra->otg_usb2_port = tegra_xusb_get_usb2_port(tegra, usbphy); 1239 tegra->otg_usb3_port = tegra_xusb_padctl_get_usb3_companion( 1240 tegra->padctl, 1241 tegra->otg_usb2_port); 1242 1243 tegra->host_mode = (usbphy->last_event == USB_EVENT_ID) ? true : false; 1244 1245 schedule_work(&tegra->id_work); 1246 1247 return NOTIFY_OK; 1248 } 1249 1250 static int tegra_xusb_init_usb_phy(struct tegra_xusb *tegra) 1251 { 1252 unsigned int i; 1253 1254 tegra->usbphy = devm_kcalloc(tegra->dev, tegra->num_usb_phys, 1255 sizeof(*tegra->usbphy), GFP_KERNEL); 1256 if (!tegra->usbphy) 1257 return -ENOMEM; 1258 1259 INIT_WORK(&tegra->id_work, tegra_xhci_id_work); 1260 tegra->id_nb.notifier_call = tegra_xhci_id_notify; 1261 1262 for (i = 0; i < tegra->num_usb_phys; i++) { 1263 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", i); 1264 1265 if (!phy) 1266 continue; 1267 1268 tegra->usbphy[i] = devm_usb_get_phy_by_node(tegra->dev, 1269 phy->dev.of_node, 1270 &tegra->id_nb); 1271 if (!IS_ERR(tegra->usbphy[i])) { 1272 dev_dbg(tegra->dev, "usbphy-%d registered", i); 1273 otg_set_host(tegra->usbphy[i]->otg, &tegra->hcd->self); 1274 } else { 1275 /* 1276 * usb-phy is optional, continue if its not available. 1277 */ 1278 tegra->usbphy[i] = NULL; 1279 } 1280 } 1281 1282 return 0; 1283 } 1284 1285 static void tegra_xusb_deinit_usb_phy(struct tegra_xusb *tegra) 1286 { 1287 unsigned int i; 1288 1289 cancel_work_sync(&tegra->id_work); 1290 1291 for (i = 0; i < tegra->num_usb_phys; i++) 1292 if (tegra->usbphy[i]) 1293 otg_set_host(tegra->usbphy[i]->otg, NULL); 1294 } 1295 1296 static int tegra_xusb_probe(struct platform_device *pdev) 1297 { 1298 struct tegra_xusb *tegra; 1299 struct resource *regs; 1300 struct xhci_hcd *xhci; 1301 unsigned int i, j, k; 1302 struct phy *phy; 1303 int err; 1304 1305 BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256); 1306 1307 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); 1308 if (!tegra) 1309 return -ENOMEM; 1310 1311 tegra->soc = of_device_get_match_data(&pdev->dev); 1312 mutex_init(&tegra->lock); 1313 tegra->dev = &pdev->dev; 1314 1315 err = tegra_xusb_init_context(tegra); 1316 if (err < 0) 1317 return err; 1318 1319 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1320 tegra->regs = devm_ioremap_resource(&pdev->dev, regs); 1321 if (IS_ERR(tegra->regs)) 1322 return PTR_ERR(tegra->regs); 1323 1324 tegra->fpci_base = devm_platform_ioremap_resource(pdev, 1); 1325 if (IS_ERR(tegra->fpci_base)) 1326 return PTR_ERR(tegra->fpci_base); 1327 1328 if (tegra->soc->has_ipfs) { 1329 tegra->ipfs_base = devm_platform_ioremap_resource(pdev, 2); 1330 if (IS_ERR(tegra->ipfs_base)) 1331 return PTR_ERR(tegra->ipfs_base); 1332 } 1333 1334 tegra->xhci_irq = platform_get_irq(pdev, 0); 1335 if (tegra->xhci_irq < 0) 1336 return tegra->xhci_irq; 1337 1338 tegra->mbox_irq = platform_get_irq(pdev, 1); 1339 if (tegra->mbox_irq < 0) 1340 return tegra->mbox_irq; 1341 1342 tegra->padctl = tegra_xusb_padctl_get(&pdev->dev); 1343 if (IS_ERR(tegra->padctl)) 1344 return PTR_ERR(tegra->padctl); 1345 1346 tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host"); 1347 if (IS_ERR(tegra->host_clk)) { 1348 err = PTR_ERR(tegra->host_clk); 1349 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err); 1350 goto put_padctl; 1351 } 1352 1353 tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src"); 1354 if (IS_ERR(tegra->falcon_clk)) { 1355 err = PTR_ERR(tegra->falcon_clk); 1356 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err); 1357 goto put_padctl; 1358 } 1359 1360 tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss"); 1361 if (IS_ERR(tegra->ss_clk)) { 1362 err = PTR_ERR(tegra->ss_clk); 1363 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err); 1364 goto put_padctl; 1365 } 1366 1367 tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src"); 1368 if (IS_ERR(tegra->ss_src_clk)) { 1369 err = PTR_ERR(tegra->ss_src_clk); 1370 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err); 1371 goto put_padctl; 1372 } 1373 1374 tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src"); 1375 if (IS_ERR(tegra->hs_src_clk)) { 1376 err = PTR_ERR(tegra->hs_src_clk); 1377 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err); 1378 goto put_padctl; 1379 } 1380 1381 tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src"); 1382 if (IS_ERR(tegra->fs_src_clk)) { 1383 err = PTR_ERR(tegra->fs_src_clk); 1384 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err); 1385 goto put_padctl; 1386 } 1387 1388 tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m"); 1389 if (IS_ERR(tegra->pll_u_480m)) { 1390 err = PTR_ERR(tegra->pll_u_480m); 1391 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err); 1392 goto put_padctl; 1393 } 1394 1395 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m"); 1396 if (IS_ERR(tegra->clk_m)) { 1397 err = PTR_ERR(tegra->clk_m); 1398 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err); 1399 goto put_padctl; 1400 } 1401 1402 tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e"); 1403 if (IS_ERR(tegra->pll_e)) { 1404 err = PTR_ERR(tegra->pll_e); 1405 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err); 1406 goto put_padctl; 1407 } 1408 1409 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) { 1410 tegra->host_rst = devm_reset_control_get(&pdev->dev, 1411 "xusb_host"); 1412 if (IS_ERR(tegra->host_rst)) { 1413 err = PTR_ERR(tegra->host_rst); 1414 dev_err(&pdev->dev, 1415 "failed to get xusb_host reset: %d\n", err); 1416 goto put_padctl; 1417 } 1418 1419 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss"); 1420 if (IS_ERR(tegra->ss_rst)) { 1421 err = PTR_ERR(tegra->ss_rst); 1422 dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n", 1423 err); 1424 goto put_padctl; 1425 } 1426 1427 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA, 1428 tegra->ss_clk, 1429 tegra->ss_rst); 1430 if (err) { 1431 dev_err(&pdev->dev, 1432 "failed to enable XUSBA domain: %d\n", err); 1433 goto put_padctl; 1434 } 1435 1436 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC, 1437 tegra->host_clk, 1438 tegra->host_rst); 1439 if (err) { 1440 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); 1441 dev_err(&pdev->dev, 1442 "failed to enable XUSBC domain: %d\n", err); 1443 goto put_padctl; 1444 } 1445 } else { 1446 err = tegra_xusb_powerdomain_init(&pdev->dev, tegra); 1447 if (err) 1448 goto put_powerdomains; 1449 } 1450 1451 tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies, 1452 sizeof(*tegra->supplies), GFP_KERNEL); 1453 if (!tegra->supplies) { 1454 err = -ENOMEM; 1455 goto put_powerdomains; 1456 } 1457 1458 regulator_bulk_set_supply_names(tegra->supplies, 1459 tegra->soc->supply_names, 1460 tegra->soc->num_supplies); 1461 1462 err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies, 1463 tegra->supplies); 1464 if (err) { 1465 dev_err(&pdev->dev, "failed to get regulators: %d\n", err); 1466 goto put_powerdomains; 1467 } 1468 1469 for (i = 0; i < tegra->soc->num_types; i++) { 1470 if (!strncmp(tegra->soc->phy_types[i].name, "usb2", 4)) 1471 tegra->num_usb_phys = tegra->soc->phy_types[i].num; 1472 tegra->num_phys += tegra->soc->phy_types[i].num; 1473 } 1474 1475 tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys, 1476 sizeof(*tegra->phys), GFP_KERNEL); 1477 if (!tegra->phys) { 1478 err = -ENOMEM; 1479 goto put_powerdomains; 1480 } 1481 1482 for (i = 0, k = 0; i < tegra->soc->num_types; i++) { 1483 char prop[8]; 1484 1485 for (j = 0; j < tegra->soc->phy_types[i].num; j++) { 1486 snprintf(prop, sizeof(prop), "%s-%d", 1487 tegra->soc->phy_types[i].name, j); 1488 1489 phy = devm_phy_optional_get(&pdev->dev, prop); 1490 if (IS_ERR(phy)) { 1491 dev_err(&pdev->dev, 1492 "failed to get PHY %s: %ld\n", prop, 1493 PTR_ERR(phy)); 1494 err = PTR_ERR(phy); 1495 goto put_powerdomains; 1496 } 1497 1498 tegra->phys[k++] = phy; 1499 } 1500 } 1501 1502 tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev, 1503 dev_name(&pdev->dev)); 1504 if (!tegra->hcd) { 1505 err = -ENOMEM; 1506 goto put_powerdomains; 1507 } 1508 1509 tegra->hcd->regs = tegra->regs; 1510 tegra->hcd->rsrc_start = regs->start; 1511 tegra->hcd->rsrc_len = resource_size(regs); 1512 1513 /* 1514 * This must happen after usb_create_hcd(), because usb_create_hcd() 1515 * will overwrite the drvdata of the device with the hcd it creates. 1516 */ 1517 platform_set_drvdata(pdev, tegra); 1518 1519 err = tegra_xusb_phy_enable(tegra); 1520 if (err < 0) { 1521 dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err); 1522 goto put_hcd; 1523 } 1524 1525 /* 1526 * The XUSB Falcon microcontroller can only address 40 bits, so set 1527 * the DMA mask accordingly. 1528 */ 1529 err = dma_set_mask_and_coherent(tegra->dev, DMA_BIT_MASK(40)); 1530 if (err < 0) { 1531 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 1532 goto disable_phy; 1533 } 1534 1535 err = tegra_xusb_request_firmware(tegra); 1536 if (err < 0) { 1537 dev_err(&pdev->dev, "failed to request firmware: %d\n", err); 1538 goto disable_phy; 1539 } 1540 1541 pm_runtime_enable(&pdev->dev); 1542 1543 if (!pm_runtime_enabled(&pdev->dev)) 1544 err = tegra_xusb_runtime_resume(&pdev->dev); 1545 else 1546 err = pm_runtime_get_sync(&pdev->dev); 1547 1548 if (err < 0) { 1549 dev_err(&pdev->dev, "failed to enable device: %d\n", err); 1550 goto free_firmware; 1551 } 1552 1553 tegra_xusb_config(tegra); 1554 1555 err = tegra_xusb_load_firmware(tegra); 1556 if (err < 0) { 1557 dev_err(&pdev->dev, "failed to load firmware: %d\n", err); 1558 goto put_rpm; 1559 } 1560 1561 err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED); 1562 if (err < 0) { 1563 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err); 1564 goto put_rpm; 1565 } 1566 1567 device_wakeup_enable(tegra->hcd->self.controller); 1568 1569 xhci = hcd_to_xhci(tegra->hcd); 1570 1571 xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver, 1572 &pdev->dev, 1573 dev_name(&pdev->dev), 1574 tegra->hcd); 1575 if (!xhci->shared_hcd) { 1576 dev_err(&pdev->dev, "failed to create shared HCD\n"); 1577 err = -ENOMEM; 1578 goto remove_usb2; 1579 } 1580 1581 err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED); 1582 if (err < 0) { 1583 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err); 1584 goto put_usb3; 1585 } 1586 1587 err = tegra_xusb_enable_firmware_messages(tegra); 1588 if (err < 0) { 1589 dev_err(&pdev->dev, "failed to enable messages: %d\n", err); 1590 goto remove_usb3; 1591 } 1592 1593 err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq, 1594 tegra_xusb_mbox_irq, 1595 tegra_xusb_mbox_thread, 0, 1596 dev_name(&pdev->dev), tegra); 1597 if (err < 0) { 1598 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); 1599 goto remove_usb3; 1600 } 1601 1602 err = tegra_xusb_init_usb_phy(tegra); 1603 if (err < 0) { 1604 dev_err(&pdev->dev, "failed to init USB PHY: %d\n", err); 1605 goto remove_usb3; 1606 } 1607 1608 return 0; 1609 1610 remove_usb3: 1611 usb_remove_hcd(xhci->shared_hcd); 1612 put_usb3: 1613 usb_put_hcd(xhci->shared_hcd); 1614 remove_usb2: 1615 usb_remove_hcd(tegra->hcd); 1616 put_rpm: 1617 if (!pm_runtime_status_suspended(&pdev->dev)) 1618 tegra_xusb_runtime_suspend(&pdev->dev); 1619 put_hcd: 1620 usb_put_hcd(tegra->hcd); 1621 free_firmware: 1622 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt, 1623 tegra->fw.phys); 1624 disable_phy: 1625 tegra_xusb_phy_disable(tegra); 1626 pm_runtime_disable(&pdev->dev); 1627 put_powerdomains: 1628 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) { 1629 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC); 1630 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); 1631 } else { 1632 tegra_xusb_powerdomain_remove(&pdev->dev, tegra); 1633 } 1634 put_padctl: 1635 tegra_xusb_padctl_put(tegra->padctl); 1636 return err; 1637 } 1638 1639 static int tegra_xusb_remove(struct platform_device *pdev) 1640 { 1641 struct tegra_xusb *tegra = platform_get_drvdata(pdev); 1642 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1643 1644 tegra_xusb_deinit_usb_phy(tegra); 1645 1646 usb_remove_hcd(xhci->shared_hcd); 1647 usb_put_hcd(xhci->shared_hcd); 1648 xhci->shared_hcd = NULL; 1649 usb_remove_hcd(tegra->hcd); 1650 usb_put_hcd(tegra->hcd); 1651 1652 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt, 1653 tegra->fw.phys); 1654 1655 pm_runtime_put_sync(&pdev->dev); 1656 pm_runtime_disable(&pdev->dev); 1657 1658 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) { 1659 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC); 1660 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA); 1661 } else { 1662 tegra_xusb_powerdomain_remove(&pdev->dev, tegra); 1663 } 1664 1665 tegra_xusb_phy_disable(tegra); 1666 1667 tegra_xusb_padctl_put(tegra->padctl); 1668 1669 return 0; 1670 } 1671 1672 #ifdef CONFIG_PM_SLEEP 1673 static bool xhci_hub_ports_suspended(struct xhci_hub *hub) 1674 { 1675 struct device *dev = hub->hcd->self.controller; 1676 bool status = true; 1677 unsigned int i; 1678 u32 value; 1679 1680 for (i = 0; i < hub->num_ports; i++) { 1681 value = readl(hub->ports[i]->addr); 1682 if ((value & PORT_PE) == 0) 1683 continue; 1684 1685 if ((value & PORT_PLS_MASK) != XDEV_U3) { 1686 dev_info(dev, "%u-%u isn't suspended: %#010x\n", 1687 hub->hcd->self.busnum, i + 1, value); 1688 status = false; 1689 } 1690 } 1691 1692 return status; 1693 } 1694 1695 static int tegra_xusb_check_ports(struct tegra_xusb *tegra) 1696 { 1697 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1698 unsigned long flags; 1699 int err = 0; 1700 1701 spin_lock_irqsave(&xhci->lock, flags); 1702 1703 if (!xhci_hub_ports_suspended(&xhci->usb2_rhub) || 1704 !xhci_hub_ports_suspended(&xhci->usb3_rhub)) 1705 err = -EBUSY; 1706 1707 spin_unlock_irqrestore(&xhci->lock, flags); 1708 1709 return err; 1710 } 1711 1712 static void tegra_xusb_save_context(struct tegra_xusb *tegra) 1713 { 1714 const struct tegra_xusb_context_soc *soc = tegra->soc->context; 1715 struct tegra_xusb_context *ctx = &tegra->context; 1716 unsigned int i; 1717 1718 if (soc->ipfs.num_offsets > 0) { 1719 for (i = 0; i < soc->ipfs.num_offsets; i++) 1720 ctx->ipfs[i] = ipfs_readl(tegra, soc->ipfs.offsets[i]); 1721 } 1722 1723 if (soc->fpci.num_offsets > 0) { 1724 for (i = 0; i < soc->fpci.num_offsets; i++) 1725 ctx->fpci[i] = fpci_readl(tegra, soc->fpci.offsets[i]); 1726 } 1727 } 1728 1729 static void tegra_xusb_restore_context(struct tegra_xusb *tegra) 1730 { 1731 const struct tegra_xusb_context_soc *soc = tegra->soc->context; 1732 struct tegra_xusb_context *ctx = &tegra->context; 1733 unsigned int i; 1734 1735 if (soc->fpci.num_offsets > 0) { 1736 for (i = 0; i < soc->fpci.num_offsets; i++) 1737 fpci_writel(tegra, ctx->fpci[i], soc->fpci.offsets[i]); 1738 } 1739 1740 if (soc->ipfs.num_offsets > 0) { 1741 for (i = 0; i < soc->ipfs.num_offsets; i++) 1742 ipfs_writel(tegra, ctx->ipfs[i], soc->ipfs.offsets[i]); 1743 } 1744 } 1745 1746 static int tegra_xusb_enter_elpg(struct tegra_xusb *tegra, bool wakeup) 1747 { 1748 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1749 int err; 1750 1751 err = tegra_xusb_check_ports(tegra); 1752 if (err < 0) { 1753 dev_err(tegra->dev, "not all ports suspended: %d\n", err); 1754 return err; 1755 } 1756 1757 err = xhci_suspend(xhci, wakeup); 1758 if (err < 0) { 1759 dev_err(tegra->dev, "failed to suspend XHCI: %d\n", err); 1760 return err; 1761 } 1762 1763 tegra_xusb_save_context(tegra); 1764 tegra_xusb_phy_disable(tegra); 1765 tegra_xusb_clk_disable(tegra); 1766 1767 return 0; 1768 } 1769 1770 static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool wakeup) 1771 { 1772 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd); 1773 int err; 1774 1775 err = tegra_xusb_clk_enable(tegra); 1776 if (err < 0) { 1777 dev_err(tegra->dev, "failed to enable clocks: %d\n", err); 1778 return err; 1779 } 1780 1781 err = tegra_xusb_phy_enable(tegra); 1782 if (err < 0) { 1783 dev_err(tegra->dev, "failed to enable PHYs: %d\n", err); 1784 goto disable_clk; 1785 } 1786 1787 tegra_xusb_config(tegra); 1788 tegra_xusb_restore_context(tegra); 1789 1790 err = tegra_xusb_load_firmware(tegra); 1791 if (err < 0) { 1792 dev_err(tegra->dev, "failed to load firmware: %d\n", err); 1793 goto disable_phy; 1794 } 1795 1796 err = __tegra_xusb_enable_firmware_messages(tegra); 1797 if (err < 0) { 1798 dev_err(tegra->dev, "failed to enable messages: %d\n", err); 1799 goto disable_phy; 1800 } 1801 1802 err = xhci_resume(xhci, true); 1803 if (err < 0) { 1804 dev_err(tegra->dev, "failed to resume XHCI: %d\n", err); 1805 goto disable_phy; 1806 } 1807 1808 return 0; 1809 1810 disable_phy: 1811 tegra_xusb_phy_disable(tegra); 1812 disable_clk: 1813 tegra_xusb_clk_disable(tegra); 1814 return err; 1815 } 1816 1817 static int tegra_xusb_suspend(struct device *dev) 1818 { 1819 struct tegra_xusb *tegra = dev_get_drvdata(dev); 1820 bool wakeup = device_may_wakeup(dev); 1821 int err; 1822 1823 synchronize_irq(tegra->mbox_irq); 1824 1825 mutex_lock(&tegra->lock); 1826 err = tegra_xusb_enter_elpg(tegra, wakeup); 1827 mutex_unlock(&tegra->lock); 1828 1829 return err; 1830 } 1831 1832 static int tegra_xusb_resume(struct device *dev) 1833 { 1834 struct tegra_xusb *tegra = dev_get_drvdata(dev); 1835 bool wakeup = device_may_wakeup(dev); 1836 int err; 1837 1838 mutex_lock(&tegra->lock); 1839 err = tegra_xusb_exit_elpg(tegra, wakeup); 1840 mutex_unlock(&tegra->lock); 1841 1842 return err; 1843 } 1844 #endif 1845 1846 static const struct dev_pm_ops tegra_xusb_pm_ops = { 1847 SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend, 1848 tegra_xusb_runtime_resume, NULL) 1849 SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume) 1850 }; 1851 1852 static const char * const tegra124_supply_names[] = { 1853 "avddio-pex", 1854 "dvddio-pex", 1855 "avdd-usb", 1856 "hvdd-usb-ss", 1857 }; 1858 1859 static const struct tegra_xusb_phy_type tegra124_phy_types[] = { 1860 { .name = "usb3", .num = 2, }, 1861 { .name = "usb2", .num = 3, }, 1862 { .name = "hsic", .num = 2, }, 1863 }; 1864 1865 static const unsigned int tegra124_xusb_context_ipfs[] = { 1866 IPFS_XUSB_HOST_MSI_BAR_SZ_0, 1867 IPFS_XUSB_HOST_MSI_BAR_SZ_0, 1868 IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0, 1869 IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0, 1870 IPFS_XUSB_HOST_MSI_VEC0_0, 1871 IPFS_XUSB_HOST_MSI_EN_VEC0_0, 1872 IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0, 1873 IPFS_XUSB_HOST_INTR_MASK_0, 1874 IPFS_XUSB_HOST_INTR_ENABLE_0, 1875 IPFS_XUSB_HOST_UFPCI_CONFIG_0, 1876 IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0, 1877 IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0, 1878 }; 1879 1880 static const unsigned int tegra124_xusb_context_fpci[] = { 1881 XUSB_CFG_ARU_CONTEXT_HS_PLS, 1882 XUSB_CFG_ARU_CONTEXT_FS_PLS, 1883 XUSB_CFG_ARU_CONTEXT_HSFS_SPEED, 1884 XUSB_CFG_ARU_CONTEXT_HSFS_PP, 1885 XUSB_CFG_ARU_CONTEXT, 1886 XUSB_CFG_AXI_CFG, 1887 XUSB_CFG_24, 1888 XUSB_CFG_16, 1889 }; 1890 1891 static const struct tegra_xusb_context_soc tegra124_xusb_context = { 1892 .ipfs = { 1893 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_ipfs), 1894 .offsets = tegra124_xusb_context_ipfs, 1895 }, 1896 .fpci = { 1897 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci), 1898 .offsets = tegra124_xusb_context_fpci, 1899 }, 1900 }; 1901 1902 static const struct tegra_xusb_soc tegra124_soc = { 1903 .firmware = "nvidia/tegra124/xusb.bin", 1904 .supply_names = tegra124_supply_names, 1905 .num_supplies = ARRAY_SIZE(tegra124_supply_names), 1906 .phy_types = tegra124_phy_types, 1907 .num_types = ARRAY_SIZE(tegra124_phy_types), 1908 .context = &tegra124_xusb_context, 1909 .ports = { 1910 .usb2 = { .offset = 4, .count = 4, }, 1911 .hsic = { .offset = 6, .count = 2, }, 1912 .usb3 = { .offset = 0, .count = 2, }, 1913 }, 1914 .scale_ss_clock = true, 1915 .has_ipfs = true, 1916 .otg_reset_sspi = false, 1917 .mbox = { 1918 .cmd = 0xe4, 1919 .data_in = 0xe8, 1920 .data_out = 0xec, 1921 .owner = 0xf0, 1922 }, 1923 }; 1924 MODULE_FIRMWARE("nvidia/tegra124/xusb.bin"); 1925 1926 static const char * const tegra210_supply_names[] = { 1927 "dvddio-pex", 1928 "hvddio-pex", 1929 "avdd-usb", 1930 }; 1931 1932 static const struct tegra_xusb_phy_type tegra210_phy_types[] = { 1933 { .name = "usb3", .num = 4, }, 1934 { .name = "usb2", .num = 4, }, 1935 { .name = "hsic", .num = 1, }, 1936 }; 1937 1938 static const struct tegra_xusb_soc tegra210_soc = { 1939 .firmware = "nvidia/tegra210/xusb.bin", 1940 .supply_names = tegra210_supply_names, 1941 .num_supplies = ARRAY_SIZE(tegra210_supply_names), 1942 .phy_types = tegra210_phy_types, 1943 .num_types = ARRAY_SIZE(tegra210_phy_types), 1944 .context = &tegra124_xusb_context, 1945 .ports = { 1946 .usb2 = { .offset = 4, .count = 4, }, 1947 .hsic = { .offset = 8, .count = 1, }, 1948 .usb3 = { .offset = 0, .count = 4, }, 1949 }, 1950 .scale_ss_clock = false, 1951 .has_ipfs = true, 1952 .otg_reset_sspi = true, 1953 .mbox = { 1954 .cmd = 0xe4, 1955 .data_in = 0xe8, 1956 .data_out = 0xec, 1957 .owner = 0xf0, 1958 }, 1959 }; 1960 MODULE_FIRMWARE("nvidia/tegra210/xusb.bin"); 1961 1962 static const char * const tegra186_supply_names[] = { 1963 }; 1964 MODULE_FIRMWARE("nvidia/tegra186/xusb.bin"); 1965 1966 static const struct tegra_xusb_phy_type tegra186_phy_types[] = { 1967 { .name = "usb3", .num = 3, }, 1968 { .name = "usb2", .num = 3, }, 1969 { .name = "hsic", .num = 1, }, 1970 }; 1971 1972 static const struct tegra_xusb_context_soc tegra186_xusb_context = { 1973 .fpci = { 1974 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci), 1975 .offsets = tegra124_xusb_context_fpci, 1976 }, 1977 }; 1978 1979 static const struct tegra_xusb_soc tegra186_soc = { 1980 .firmware = "nvidia/tegra186/xusb.bin", 1981 .supply_names = tegra186_supply_names, 1982 .num_supplies = ARRAY_SIZE(tegra186_supply_names), 1983 .phy_types = tegra186_phy_types, 1984 .num_types = ARRAY_SIZE(tegra186_phy_types), 1985 .context = &tegra186_xusb_context, 1986 .ports = { 1987 .usb3 = { .offset = 0, .count = 3, }, 1988 .usb2 = { .offset = 3, .count = 3, }, 1989 .hsic = { .offset = 6, .count = 1, }, 1990 }, 1991 .scale_ss_clock = false, 1992 .has_ipfs = false, 1993 .otg_reset_sspi = false, 1994 .mbox = { 1995 .cmd = 0xe4, 1996 .data_in = 0xe8, 1997 .data_out = 0xec, 1998 .owner = 0xf0, 1999 }, 2000 .lpm_support = true, 2001 }; 2002 2003 static const char * const tegra194_supply_names[] = { 2004 }; 2005 2006 static const struct tegra_xusb_phy_type tegra194_phy_types[] = { 2007 { .name = "usb3", .num = 4, }, 2008 { .name = "usb2", .num = 4, }, 2009 }; 2010 2011 static const struct tegra_xusb_soc tegra194_soc = { 2012 .firmware = "nvidia/tegra194/xusb.bin", 2013 .supply_names = tegra194_supply_names, 2014 .num_supplies = ARRAY_SIZE(tegra194_supply_names), 2015 .phy_types = tegra194_phy_types, 2016 .num_types = ARRAY_SIZE(tegra194_phy_types), 2017 .context = &tegra186_xusb_context, 2018 .ports = { 2019 .usb3 = { .offset = 0, .count = 4, }, 2020 .usb2 = { .offset = 4, .count = 4, }, 2021 }, 2022 .scale_ss_clock = false, 2023 .has_ipfs = false, 2024 .otg_reset_sspi = false, 2025 .mbox = { 2026 .cmd = 0x68, 2027 .data_in = 0x6c, 2028 .data_out = 0x70, 2029 .owner = 0x74, 2030 }, 2031 .lpm_support = true, 2032 }; 2033 MODULE_FIRMWARE("nvidia/tegra194/xusb.bin"); 2034 2035 static const struct of_device_id tegra_xusb_of_match[] = { 2036 { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc }, 2037 { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc }, 2038 { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc }, 2039 { .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc }, 2040 { }, 2041 }; 2042 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match); 2043 2044 static struct platform_driver tegra_xusb_driver = { 2045 .probe = tegra_xusb_probe, 2046 .remove = tegra_xusb_remove, 2047 .driver = { 2048 .name = "tegra-xusb", 2049 .pm = &tegra_xusb_pm_ops, 2050 .of_match_table = tegra_xusb_of_match, 2051 }, 2052 }; 2053 2054 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci) 2055 { 2056 struct tegra_xusb *tegra = dev_get_drvdata(dev); 2057 2058 xhci->quirks |= XHCI_PLAT; 2059 if (tegra && tegra->soc->lpm_support) 2060 xhci->quirks |= XHCI_LPM_SUPPORT; 2061 } 2062 2063 static int tegra_xhci_setup(struct usb_hcd *hcd) 2064 { 2065 return xhci_gen_setup(hcd, tegra_xhci_quirks); 2066 } 2067 2068 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = { 2069 .reset = tegra_xhci_setup, 2070 }; 2071 2072 static int __init tegra_xusb_init(void) 2073 { 2074 xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides); 2075 2076 return platform_driver_register(&tegra_xusb_driver); 2077 } 2078 module_init(tegra_xusb_init); 2079 2080 static void __exit tegra_xusb_exit(void) 2081 { 2082 platform_driver_unregister(&tegra_xusb_driver); 2083 } 2084 module_exit(tegra_xusb_exit); 2085 2086 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>"); 2087 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver"); 2088 MODULE_LICENSE("GPL v2"); 2089