1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Aardvark PCIe controller, used on Marvell Armada 4 * 3700. 5 * 6 * Copyright (C) 2016 Marvell 7 * 8 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com> 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/gpio.h> 13 #include <linux/interrupt.h> 14 #include <linux/irq.h> 15 #include <linux/irqdomain.h> 16 #include <linux/kernel.h> 17 #include <linux/pci.h> 18 #include <linux/init.h> 19 #include <linux/phy/phy.h> 20 #include <linux/platform_device.h> 21 #include <linux/msi.h> 22 #include <linux/of_address.h> 23 #include <linux/of_gpio.h> 24 #include <linux/of_pci.h> 25 26 #include "../pci.h" 27 #include "../pci-bridge-emul.h" 28 29 /* PCIe core registers */ 30 #define PCIE_CORE_DEV_ID_REG 0x0 31 #define PCIE_CORE_CMD_STATUS_REG 0x4 32 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0) 33 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1) 34 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) 35 #define PCIE_CORE_DEV_REV_REG 0x8 36 #define PCIE_CORE_PCIEXP_CAP 0xc0 37 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 38 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) 39 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) 40 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7) 41 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8) 42 #define PCIE_CORE_INT_A_ASSERT_ENABLE 1 43 #define PCIE_CORE_INT_B_ASSERT_ENABLE 2 44 #define PCIE_CORE_INT_C_ASSERT_ENABLE 3 45 #define PCIE_CORE_INT_D_ASSERT_ENABLE 4 46 /* PIO registers base address and register offsets */ 47 #define PIO_BASE_ADDR 0x4000 48 #define PIO_CTRL (PIO_BASE_ADDR + 0x0) 49 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0) 50 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24) 51 #define PIO_STAT (PIO_BASE_ADDR + 0x4) 52 #define PIO_COMPLETION_STATUS_SHIFT 7 53 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7) 54 #define PIO_COMPLETION_STATUS_OK 0 55 #define PIO_COMPLETION_STATUS_UR 1 56 #define PIO_COMPLETION_STATUS_CRS 2 57 #define PIO_COMPLETION_STATUS_CA 4 58 #define PIO_NON_POSTED_REQ BIT(0) 59 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8) 60 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc) 61 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10) 62 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14) 63 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18) 64 #define PIO_START (PIO_BASE_ADDR + 0x1c) 65 #define PIO_ISR (PIO_BASE_ADDR + 0x20) 66 #define PIO_ISRM (PIO_BASE_ADDR + 0x24) 67 68 /* Aardvark Control registers */ 69 #define CONTROL_BASE_ADDR 0x4800 70 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0) 71 #define PCIE_GEN_SEL_MSK 0x3 72 #define PCIE_GEN_SEL_SHIFT 0x0 73 #define SPEED_GEN_1 0 74 #define SPEED_GEN_2 1 75 #define SPEED_GEN_3 2 76 #define IS_RC_MSK 1 77 #define IS_RC_SHIFT 2 78 #define LANE_CNT_MSK 0x18 79 #define LANE_CNT_SHIFT 0x3 80 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT) 81 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT) 82 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT) 83 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT) 84 #define LINK_TRAINING_EN BIT(6) 85 #define LEGACY_INTA BIT(28) 86 #define LEGACY_INTB BIT(29) 87 #define LEGACY_INTC BIT(30) 88 #define LEGACY_INTD BIT(31) 89 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4) 90 #define HOT_RESET_GEN BIT(0) 91 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8) 92 #define PCIE_CORE_CTRL2_RESERVED 0x7 93 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4) 94 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5) 95 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6) 96 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10) 97 #define PCIE_CORE_REF_CLK_REG (CONTROL_BASE_ADDR + 0x14) 98 #define PCIE_CORE_REF_CLK_TX_ENABLE BIT(1) 99 #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30) 100 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40) 101 #define PCIE_MSG_PM_PME_MASK BIT(7) 102 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) 103 #define PCIE_ISR0_MSI_INT_PENDING BIT(24) 104 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val)) 105 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val)) 106 #define PCIE_ISR0_ALL_MASK GENMASK(26, 0) 107 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48) 108 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C) 109 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4) 110 #define PCIE_ISR1_FLUSH BIT(5) 111 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val)) 112 #define PCIE_ISR1_ALL_MASK GENMASK(11, 4) 113 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50) 114 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54) 115 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58) 116 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C) 117 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C) 118 119 /* LMI registers base address and register offsets */ 120 #define LMI_BASE_ADDR 0x6000 121 #define CFG_REG (LMI_BASE_ADDR + 0x0) 122 #define LTSSM_SHIFT 24 123 #define LTSSM_MASK 0x3f 124 #define LTSSM_L0 0x10 125 #define RC_BAR_CONFIG 0x300 126 127 /* PCIe core controller registers */ 128 #define CTRL_CORE_BASE_ADDR 0x18000 129 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0) 130 #define CTRL_MODE_SHIFT 0x0 131 #define CTRL_MODE_MASK 0x1 132 #define PCIE_CORE_MODE_DIRECT 0x0 133 #define PCIE_CORE_MODE_COMMAND 0x1 134 135 /* PCIe Central Interrupts Registers */ 136 #define CENTRAL_INT_BASE_ADDR 0x1b000 137 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0) 138 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4) 139 #define PCIE_IRQ_CMDQ_INT BIT(0) 140 #define PCIE_IRQ_MSI_STATUS_INT BIT(1) 141 #define PCIE_IRQ_CMD_SENT_DONE BIT(3) 142 #define PCIE_IRQ_DMA_INT BIT(4) 143 #define PCIE_IRQ_IB_DXFERDONE BIT(5) 144 #define PCIE_IRQ_OB_DXFERDONE BIT(6) 145 #define PCIE_IRQ_OB_RXFERDONE BIT(7) 146 #define PCIE_IRQ_COMPQ_INT BIT(12) 147 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13) 148 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14) 149 #define PCIE_IRQ_CORE_INT BIT(16) 150 #define PCIE_IRQ_CORE_INT_PIO BIT(17) 151 #define PCIE_IRQ_DPMU_INT BIT(18) 152 #define PCIE_IRQ_PCIE_MIS_INT BIT(19) 153 #define PCIE_IRQ_MSI_INT1_DET BIT(20) 154 #define PCIE_IRQ_MSI_INT2_DET BIT(21) 155 #define PCIE_IRQ_RC_DBELL_DET BIT(22) 156 #define PCIE_IRQ_EP_STATUS BIT(23) 157 #define PCIE_IRQ_ALL_MASK 0xfff0fb 158 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT 159 160 /* Transaction types */ 161 #define PCIE_CONFIG_RD_TYPE0 0x8 162 #define PCIE_CONFIG_RD_TYPE1 0x9 163 #define PCIE_CONFIG_WR_TYPE0 0xa 164 #define PCIE_CONFIG_WR_TYPE1 0xb 165 166 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20) 167 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15) 168 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12) 169 #define PCIE_CONF_REG(reg) ((reg) & 0xffc) 170 #define PCIE_CONF_ADDR(bus, devfn, where) \ 171 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ 172 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where)) 173 174 #define PIO_RETRY_CNT 500 175 #define PIO_RETRY_DELAY 2 /* 2 us*/ 176 177 #define LINK_WAIT_MAX_RETRIES 10 178 #define LINK_WAIT_USLEEP_MIN 90000 179 #define LINK_WAIT_USLEEP_MAX 100000 180 #define RETRAIN_WAIT_MAX_RETRIES 10 181 #define RETRAIN_WAIT_USLEEP_US 2000 182 183 #define MSI_IRQ_NUM 32 184 185 struct advk_pcie { 186 struct platform_device *pdev; 187 void __iomem *base; 188 struct irq_domain *irq_domain; 189 struct irq_chip irq_chip; 190 struct irq_domain *msi_domain; 191 struct irq_domain *msi_inner_domain; 192 struct irq_chip msi_bottom_irq_chip; 193 struct irq_chip msi_irq_chip; 194 struct msi_domain_info msi_domain_info; 195 DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); 196 struct mutex msi_used_lock; 197 u16 msi_msg; 198 int root_bus_nr; 199 int link_gen; 200 struct pci_bridge_emul bridge; 201 struct gpio_desc *reset_gpio; 202 struct phy *phy; 203 }; 204 205 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) 206 { 207 writel(val, pcie->base + reg); 208 } 209 210 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) 211 { 212 return readl(pcie->base + reg); 213 } 214 215 static inline u16 advk_read16(struct advk_pcie *pcie, u64 reg) 216 { 217 return advk_readl(pcie, (reg & ~0x3)) >> ((reg & 0x3) * 8); 218 } 219 220 static int advk_pcie_link_up(struct advk_pcie *pcie) 221 { 222 u32 val, ltssm_state; 223 224 val = advk_readl(pcie, CFG_REG); 225 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK; 226 return ltssm_state >= LTSSM_L0; 227 } 228 229 static int advk_pcie_wait_for_link(struct advk_pcie *pcie) 230 { 231 int retries; 232 233 /* check if the link is up or not */ 234 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { 235 if (advk_pcie_link_up(pcie)) 236 return 0; 237 238 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); 239 } 240 241 return -ETIMEDOUT; 242 } 243 244 static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie) 245 { 246 size_t retries; 247 248 for (retries = 0; retries < RETRAIN_WAIT_MAX_RETRIES; ++retries) { 249 if (!advk_pcie_link_up(pcie)) 250 break; 251 udelay(RETRAIN_WAIT_USLEEP_US); 252 } 253 } 254 255 static int advk_pcie_train_at_gen(struct advk_pcie *pcie, int gen) 256 { 257 int ret, neg_gen; 258 u32 reg; 259 260 /* Setup link speed */ 261 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 262 reg &= ~PCIE_GEN_SEL_MSK; 263 if (gen == 3) 264 reg |= SPEED_GEN_3; 265 else if (gen == 2) 266 reg |= SPEED_GEN_2; 267 else 268 reg |= SPEED_GEN_1; 269 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 270 271 /* 272 * Enable link training. This is not needed in every call to this 273 * function, just once suffices, but it does not break anything either. 274 */ 275 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 276 reg |= LINK_TRAINING_EN; 277 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 278 279 /* 280 * Start link training immediately after enabling it. 281 * This solves problems for some buggy cards. 282 */ 283 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL); 284 reg |= PCI_EXP_LNKCTL_RL; 285 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL); 286 287 ret = advk_pcie_wait_for_link(pcie); 288 if (ret) 289 return ret; 290 291 reg = advk_read16(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKSTA); 292 neg_gen = reg & PCI_EXP_LNKSTA_CLS; 293 294 return neg_gen; 295 } 296 297 static void advk_pcie_train_link(struct advk_pcie *pcie) 298 { 299 struct device *dev = &pcie->pdev->dev; 300 int neg_gen = -1, gen; 301 302 /* 303 * Try link training at link gen specified by device tree property 304 * 'max-link-speed'. If this fails, iteratively train at lower gen. 305 */ 306 for (gen = pcie->link_gen; gen > 0; --gen) { 307 neg_gen = advk_pcie_train_at_gen(pcie, gen); 308 if (neg_gen > 0) 309 break; 310 } 311 312 if (neg_gen < 0) 313 goto err; 314 315 /* 316 * After successful training if negotiated gen is lower than requested, 317 * train again on negotiated gen. This solves some stability issues for 318 * some buggy gen1 cards. 319 */ 320 if (neg_gen < gen) { 321 gen = neg_gen; 322 neg_gen = advk_pcie_train_at_gen(pcie, gen); 323 } 324 325 if (neg_gen == gen) { 326 dev_info(dev, "link up at gen %i\n", gen); 327 return; 328 } 329 330 err: 331 dev_err(dev, "link never came up\n"); 332 } 333 334 static void advk_pcie_issue_perst(struct advk_pcie *pcie) 335 { 336 u32 reg; 337 338 if (!pcie->reset_gpio) 339 return; 340 341 /* PERST does not work for some cards when link training is enabled */ 342 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 343 reg &= ~LINK_TRAINING_EN; 344 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 345 346 /* 10ms delay is needed for some cards */ 347 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); 348 gpiod_set_value_cansleep(pcie->reset_gpio, 1); 349 usleep_range(10000, 11000); 350 gpiod_set_value_cansleep(pcie->reset_gpio, 0); 351 } 352 353 static void advk_pcie_setup_hw(struct advk_pcie *pcie) 354 { 355 u32 reg; 356 357 advk_pcie_issue_perst(pcie); 358 359 /* Enable TX */ 360 reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG); 361 reg |= PCIE_CORE_REF_CLK_TX_ENABLE; 362 advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG); 363 364 /* Set to Direct mode */ 365 reg = advk_readl(pcie, CTRL_CONFIG_REG); 366 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); 367 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT); 368 advk_writel(pcie, reg, CTRL_CONFIG_REG); 369 370 /* Set PCI global control register to RC mode */ 371 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 372 reg |= (IS_RC_MSK << IS_RC_SHIFT); 373 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 374 375 /* Set Advanced Error Capabilities and Control PF0 register */ 376 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | 377 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | 378 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK | 379 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV; 380 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); 381 382 /* Set PCIe Device Control register */ 383 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); 384 reg &= ~PCI_EXP_DEVCTL_RELAX_EN; 385 reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; 386 reg &= ~PCI_EXP_DEVCTL_READRQ; 387 reg |= PCI_EXP_DEVCTL_PAYLOAD; /* Set max payload size */ 388 reg |= PCI_EXP_DEVCTL_READRQ_512B; 389 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); 390 391 /* Program PCIe Control 2 to disable strict ordering */ 392 reg = PCIE_CORE_CTRL2_RESERVED | 393 PCIE_CORE_CTRL2_TD_ENABLE; 394 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 395 396 /* Set lane X1 */ 397 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 398 reg &= ~LANE_CNT_MSK; 399 reg |= LANE_COUNT_1; 400 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 401 402 /* Enable MSI */ 403 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 404 reg |= PCIE_CORE_CTRL2_MSI_ENABLE; 405 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 406 407 /* Clear all interrupts */ 408 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); 409 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); 410 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); 411 412 /* Disable All ISR0/1 Sources */ 413 reg = PCIE_ISR0_ALL_MASK; 414 reg &= ~PCIE_ISR0_MSI_INT_PENDING; 415 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); 416 417 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); 418 419 /* Unmask all MSIs */ 420 advk_writel(pcie, 0, PCIE_MSI_MASK_REG); 421 422 /* Enable summary interrupt for GIC SPI source */ 423 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); 424 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); 425 426 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 427 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE; 428 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 429 430 /* Bypass the address window mapping for PIO */ 431 reg = advk_readl(pcie, PIO_CTRL); 432 reg |= PIO_CTRL_ADDR_WIN_DISABLE; 433 advk_writel(pcie, reg, PIO_CTRL); 434 435 /* 436 * PERST# signal could have been asserted by pinctrl subsystem before 437 * probe() callback has been called or issued explicitly by reset gpio 438 * function advk_pcie_issue_perst(), making the endpoint going into 439 * fundamental reset. As required by PCI Express spec a delay for at 440 * least 100ms after such a reset before link training is needed. 441 */ 442 msleep(PCI_PM_D3COLD_WAIT); 443 444 advk_pcie_train_link(pcie); 445 446 /* 447 * FIXME: The following register update is suspicious. This register is 448 * applicable only when the PCI controller is configured for Endpoint 449 * mode, not as a Root Complex. But apparently when this code is 450 * removed, some cards stop working. This should be investigated and 451 * a comment explaining this should be put here. 452 */ 453 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); 454 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN | 455 PCIE_CORE_CMD_IO_ACCESS_EN | 456 PCIE_CORE_CMD_MEM_IO_REQ_EN; 457 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); 458 } 459 460 static void advk_pcie_check_pio_status(struct advk_pcie *pcie) 461 { 462 struct device *dev = &pcie->pdev->dev; 463 u32 reg; 464 unsigned int status; 465 char *strcomp_status, *str_posted; 466 467 reg = advk_readl(pcie, PIO_STAT); 468 status = (reg & PIO_COMPLETION_STATUS_MASK) >> 469 PIO_COMPLETION_STATUS_SHIFT; 470 471 if (!status) 472 return; 473 474 switch (status) { 475 case PIO_COMPLETION_STATUS_UR: 476 strcomp_status = "UR"; 477 break; 478 case PIO_COMPLETION_STATUS_CRS: 479 strcomp_status = "CRS"; 480 break; 481 case PIO_COMPLETION_STATUS_CA: 482 strcomp_status = "CA"; 483 break; 484 default: 485 strcomp_status = "Unknown"; 486 break; 487 } 488 489 if (reg & PIO_NON_POSTED_REQ) 490 str_posted = "Non-posted"; 491 else 492 str_posted = "Posted"; 493 494 dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n", 495 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); 496 } 497 498 static int advk_pcie_wait_pio(struct advk_pcie *pcie) 499 { 500 struct device *dev = &pcie->pdev->dev; 501 int i; 502 503 for (i = 0; i < PIO_RETRY_CNT; i++) { 504 u32 start, isr; 505 506 start = advk_readl(pcie, PIO_START); 507 isr = advk_readl(pcie, PIO_ISR); 508 if (!start && isr) 509 return 0; 510 udelay(PIO_RETRY_DELAY); 511 } 512 513 dev_err(dev, "config read/write timed out\n"); 514 return -ETIMEDOUT; 515 } 516 517 518 static pci_bridge_emul_read_status_t 519 advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, 520 int reg, u32 *value) 521 { 522 struct advk_pcie *pcie = bridge->data; 523 524 525 switch (reg) { 526 case PCI_EXP_SLTCTL: 527 *value = PCI_EXP_SLTSTA_PDS << 16; 528 return PCI_BRIDGE_EMUL_HANDLED; 529 530 case PCI_EXP_RTCTL: { 531 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); 532 *value = (val & PCIE_MSG_PM_PME_MASK) ? 0 : PCI_EXP_RTCTL_PMEIE; 533 return PCI_BRIDGE_EMUL_HANDLED; 534 } 535 536 case PCI_EXP_RTSTA: { 537 u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG); 538 u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG); 539 *value = (isr0 & PCIE_MSG_PM_PME_MASK) << 16 | (msglog >> 16); 540 return PCI_BRIDGE_EMUL_HANDLED; 541 } 542 543 case PCI_EXP_LNKCTL: { 544 /* u32 contains both PCI_EXP_LNKCTL and PCI_EXP_LNKSTA */ 545 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & 546 ~(PCI_EXP_LNKSTA_LT << 16); 547 if (!advk_pcie_link_up(pcie)) 548 val |= (PCI_EXP_LNKSTA_LT << 16); 549 *value = val; 550 return PCI_BRIDGE_EMUL_HANDLED; 551 } 552 553 case PCI_CAP_LIST_ID: 554 case PCI_EXP_DEVCAP: 555 case PCI_EXP_DEVCTL: 556 case PCI_EXP_LNKCAP: 557 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); 558 return PCI_BRIDGE_EMUL_HANDLED; 559 default: 560 return PCI_BRIDGE_EMUL_NOT_HANDLED; 561 } 562 563 } 564 565 static void 566 advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, 567 int reg, u32 old, u32 new, u32 mask) 568 { 569 struct advk_pcie *pcie = bridge->data; 570 571 switch (reg) { 572 case PCI_EXP_DEVCTL: 573 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); 574 break; 575 576 case PCI_EXP_LNKCTL: 577 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); 578 if (new & PCI_EXP_LNKCTL_RL) 579 advk_pcie_wait_for_retrain(pcie); 580 break; 581 582 case PCI_EXP_RTCTL: { 583 /* Only mask/unmask PME interrupt */ 584 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) & 585 ~PCIE_MSG_PM_PME_MASK; 586 if ((new & PCI_EXP_RTCTL_PMEIE) == 0) 587 val |= PCIE_MSG_PM_PME_MASK; 588 advk_writel(pcie, val, PCIE_ISR0_MASK_REG); 589 break; 590 } 591 592 case PCI_EXP_RTSTA: 593 new = (new & PCI_EXP_RTSTA_PME) >> 9; 594 advk_writel(pcie, new, PCIE_ISR0_REG); 595 break; 596 597 default: 598 break; 599 } 600 } 601 602 static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { 603 .read_pcie = advk_pci_bridge_emul_pcie_conf_read, 604 .write_pcie = advk_pci_bridge_emul_pcie_conf_write, 605 }; 606 607 /* 608 * Initialize the configuration space of the PCI-to-PCI bridge 609 * associated with the given PCIe interface. 610 */ 611 static void advk_sw_pci_bridge_init(struct advk_pcie *pcie) 612 { 613 struct pci_bridge_emul *bridge = &pcie->bridge; 614 615 bridge->conf.vendor = 616 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); 617 bridge->conf.device = 618 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16); 619 bridge->conf.class_revision = 620 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff); 621 622 /* Support 32 bits I/O addressing */ 623 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; 624 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; 625 626 /* Support 64 bits memory pref */ 627 bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); 628 bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); 629 630 /* Support interrupt A for MSI feature */ 631 bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE; 632 633 bridge->has_pcie = true; 634 bridge->data = pcie; 635 bridge->ops = &advk_pci_bridge_emul_ops; 636 637 pci_bridge_emul_init(bridge, 0); 638 639 } 640 641 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus, 642 int devfn) 643 { 644 if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0) 645 return false; 646 647 return true; 648 } 649 650 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, 651 int where, int size, u32 *val) 652 { 653 struct advk_pcie *pcie = bus->sysdata; 654 u32 reg; 655 int ret; 656 657 if (!advk_pcie_valid_device(pcie, bus, devfn)) { 658 *val = 0xffffffff; 659 return PCIBIOS_DEVICE_NOT_FOUND; 660 } 661 662 if (bus->number == pcie->root_bus_nr) 663 return pci_bridge_emul_conf_read(&pcie->bridge, where, 664 size, val); 665 666 /* Start PIO */ 667 advk_writel(pcie, 0, PIO_START); 668 advk_writel(pcie, 1, PIO_ISR); 669 670 /* Program the control register */ 671 reg = advk_readl(pcie, PIO_CTRL); 672 reg &= ~PIO_CTRL_TYPE_MASK; 673 if (bus->primary == pcie->root_bus_nr) 674 reg |= PCIE_CONFIG_RD_TYPE0; 675 else 676 reg |= PCIE_CONFIG_RD_TYPE1; 677 advk_writel(pcie, reg, PIO_CTRL); 678 679 /* Program the address registers */ 680 reg = PCIE_CONF_ADDR(bus->number, devfn, where); 681 advk_writel(pcie, reg, PIO_ADDR_LS); 682 advk_writel(pcie, 0, PIO_ADDR_MS); 683 684 /* Program the data strobe */ 685 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); 686 687 /* Start the transfer */ 688 advk_writel(pcie, 1, PIO_START); 689 690 ret = advk_pcie_wait_pio(pcie); 691 if (ret < 0) 692 return PCIBIOS_SET_FAILED; 693 694 advk_pcie_check_pio_status(pcie); 695 696 /* Get the read result */ 697 *val = advk_readl(pcie, PIO_RD_DATA); 698 if (size == 1) 699 *val = (*val >> (8 * (where & 3))) & 0xff; 700 else if (size == 2) 701 *val = (*val >> (8 * (where & 3))) & 0xffff; 702 703 return PCIBIOS_SUCCESSFUL; 704 } 705 706 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 707 int where, int size, u32 val) 708 { 709 struct advk_pcie *pcie = bus->sysdata; 710 u32 reg; 711 u32 data_strobe = 0x0; 712 int offset; 713 int ret; 714 715 if (!advk_pcie_valid_device(pcie, bus, devfn)) 716 return PCIBIOS_DEVICE_NOT_FOUND; 717 718 if (bus->number == pcie->root_bus_nr) 719 return pci_bridge_emul_conf_write(&pcie->bridge, where, 720 size, val); 721 722 if (where % size) 723 return PCIBIOS_SET_FAILED; 724 725 /* Start PIO */ 726 advk_writel(pcie, 0, PIO_START); 727 advk_writel(pcie, 1, PIO_ISR); 728 729 /* Program the control register */ 730 reg = advk_readl(pcie, PIO_CTRL); 731 reg &= ~PIO_CTRL_TYPE_MASK; 732 if (bus->primary == pcie->root_bus_nr) 733 reg |= PCIE_CONFIG_WR_TYPE0; 734 else 735 reg |= PCIE_CONFIG_WR_TYPE1; 736 advk_writel(pcie, reg, PIO_CTRL); 737 738 /* Program the address registers */ 739 reg = PCIE_CONF_ADDR(bus->number, devfn, where); 740 advk_writel(pcie, reg, PIO_ADDR_LS); 741 advk_writel(pcie, 0, PIO_ADDR_MS); 742 743 /* Calculate the write strobe */ 744 offset = where & 0x3; 745 reg = val << (8 * offset); 746 data_strobe = GENMASK(size - 1, 0) << offset; 747 748 /* Program the data register */ 749 advk_writel(pcie, reg, PIO_WR_DATA); 750 751 /* Program the data strobe */ 752 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); 753 754 /* Start the transfer */ 755 advk_writel(pcie, 1, PIO_START); 756 757 ret = advk_pcie_wait_pio(pcie); 758 if (ret < 0) 759 return PCIBIOS_SET_FAILED; 760 761 advk_pcie_check_pio_status(pcie); 762 763 return PCIBIOS_SUCCESSFUL; 764 } 765 766 static struct pci_ops advk_pcie_ops = { 767 .read = advk_pcie_rd_conf, 768 .write = advk_pcie_wr_conf, 769 }; 770 771 static void advk_msi_irq_compose_msi_msg(struct irq_data *data, 772 struct msi_msg *msg) 773 { 774 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); 775 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); 776 777 msg->address_lo = lower_32_bits(msi_msg); 778 msg->address_hi = upper_32_bits(msi_msg); 779 msg->data = data->irq; 780 } 781 782 static int advk_msi_set_affinity(struct irq_data *irq_data, 783 const struct cpumask *mask, bool force) 784 { 785 return -EINVAL; 786 } 787 788 static int advk_msi_irq_domain_alloc(struct irq_domain *domain, 789 unsigned int virq, 790 unsigned int nr_irqs, void *args) 791 { 792 struct advk_pcie *pcie = domain->host_data; 793 int hwirq, i; 794 795 mutex_lock(&pcie->msi_used_lock); 796 hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM, 797 0, nr_irqs, 0); 798 if (hwirq >= MSI_IRQ_NUM) { 799 mutex_unlock(&pcie->msi_used_lock); 800 return -ENOSPC; 801 } 802 803 bitmap_set(pcie->msi_used, hwirq, nr_irqs); 804 mutex_unlock(&pcie->msi_used_lock); 805 806 for (i = 0; i < nr_irqs; i++) 807 irq_domain_set_info(domain, virq + i, hwirq + i, 808 &pcie->msi_bottom_irq_chip, 809 domain->host_data, handle_simple_irq, 810 NULL, NULL); 811 812 return hwirq; 813 } 814 815 static void advk_msi_irq_domain_free(struct irq_domain *domain, 816 unsigned int virq, unsigned int nr_irqs) 817 { 818 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 819 struct advk_pcie *pcie = domain->host_data; 820 821 mutex_lock(&pcie->msi_used_lock); 822 bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs); 823 mutex_unlock(&pcie->msi_used_lock); 824 } 825 826 static const struct irq_domain_ops advk_msi_domain_ops = { 827 .alloc = advk_msi_irq_domain_alloc, 828 .free = advk_msi_irq_domain_free, 829 }; 830 831 static void advk_pcie_irq_mask(struct irq_data *d) 832 { 833 struct advk_pcie *pcie = d->domain->host_data; 834 irq_hw_number_t hwirq = irqd_to_hwirq(d); 835 u32 mask; 836 837 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 838 mask |= PCIE_ISR1_INTX_ASSERT(hwirq); 839 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); 840 } 841 842 static void advk_pcie_irq_unmask(struct irq_data *d) 843 { 844 struct advk_pcie *pcie = d->domain->host_data; 845 irq_hw_number_t hwirq = irqd_to_hwirq(d); 846 u32 mask; 847 848 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 849 mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq); 850 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); 851 } 852 853 static int advk_pcie_irq_map(struct irq_domain *h, 854 unsigned int virq, irq_hw_number_t hwirq) 855 { 856 struct advk_pcie *pcie = h->host_data; 857 858 advk_pcie_irq_mask(irq_get_irq_data(virq)); 859 irq_set_status_flags(virq, IRQ_LEVEL); 860 irq_set_chip_and_handler(virq, &pcie->irq_chip, 861 handle_level_irq); 862 irq_set_chip_data(virq, pcie); 863 864 return 0; 865 } 866 867 static const struct irq_domain_ops advk_pcie_irq_domain_ops = { 868 .map = advk_pcie_irq_map, 869 .xlate = irq_domain_xlate_onecell, 870 }; 871 872 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) 873 { 874 struct device *dev = &pcie->pdev->dev; 875 struct device_node *node = dev->of_node; 876 struct irq_chip *bottom_ic, *msi_ic; 877 struct msi_domain_info *msi_di; 878 phys_addr_t msi_msg_phys; 879 880 mutex_init(&pcie->msi_used_lock); 881 882 bottom_ic = &pcie->msi_bottom_irq_chip; 883 884 bottom_ic->name = "MSI"; 885 bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg; 886 bottom_ic->irq_set_affinity = advk_msi_set_affinity; 887 888 msi_ic = &pcie->msi_irq_chip; 889 msi_ic->name = "advk-MSI"; 890 891 msi_di = &pcie->msi_domain_info; 892 msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 893 MSI_FLAG_MULTI_PCI_MSI; 894 msi_di->chip = msi_ic; 895 896 msi_msg_phys = virt_to_phys(&pcie->msi_msg); 897 898 advk_writel(pcie, lower_32_bits(msi_msg_phys), 899 PCIE_MSI_ADDR_LOW_REG); 900 advk_writel(pcie, upper_32_bits(msi_msg_phys), 901 PCIE_MSI_ADDR_HIGH_REG); 902 903 pcie->msi_inner_domain = 904 irq_domain_add_linear(NULL, MSI_IRQ_NUM, 905 &advk_msi_domain_ops, pcie); 906 if (!pcie->msi_inner_domain) 907 return -ENOMEM; 908 909 pcie->msi_domain = 910 pci_msi_create_irq_domain(of_node_to_fwnode(node), 911 msi_di, pcie->msi_inner_domain); 912 if (!pcie->msi_domain) { 913 irq_domain_remove(pcie->msi_inner_domain); 914 return -ENOMEM; 915 } 916 917 return 0; 918 } 919 920 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie) 921 { 922 irq_domain_remove(pcie->msi_domain); 923 irq_domain_remove(pcie->msi_inner_domain); 924 } 925 926 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) 927 { 928 struct device *dev = &pcie->pdev->dev; 929 struct device_node *node = dev->of_node; 930 struct device_node *pcie_intc_node; 931 struct irq_chip *irq_chip; 932 int ret = 0; 933 934 pcie_intc_node = of_get_next_child(node, NULL); 935 if (!pcie_intc_node) { 936 dev_err(dev, "No PCIe Intc node found\n"); 937 return -ENODEV; 938 } 939 940 irq_chip = &pcie->irq_chip; 941 942 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq", 943 dev_name(dev)); 944 if (!irq_chip->name) { 945 ret = -ENOMEM; 946 goto out_put_node; 947 } 948 949 irq_chip->irq_mask = advk_pcie_irq_mask; 950 irq_chip->irq_mask_ack = advk_pcie_irq_mask; 951 irq_chip->irq_unmask = advk_pcie_irq_unmask; 952 953 pcie->irq_domain = 954 irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 955 &advk_pcie_irq_domain_ops, pcie); 956 if (!pcie->irq_domain) { 957 dev_err(dev, "Failed to get a INTx IRQ domain\n"); 958 ret = -ENOMEM; 959 goto out_put_node; 960 } 961 962 out_put_node: 963 of_node_put(pcie_intc_node); 964 return ret; 965 } 966 967 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) 968 { 969 irq_domain_remove(pcie->irq_domain); 970 } 971 972 static void advk_pcie_handle_msi(struct advk_pcie *pcie) 973 { 974 u32 msi_val, msi_mask, msi_status, msi_idx; 975 u16 msi_data; 976 977 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); 978 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); 979 msi_status = msi_val & ~msi_mask; 980 981 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) { 982 if (!(BIT(msi_idx) & msi_status)) 983 continue; 984 985 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); 986 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF; 987 generic_handle_irq(msi_data); 988 } 989 990 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, 991 PCIE_ISR0_REG); 992 } 993 994 static void advk_pcie_handle_int(struct advk_pcie *pcie) 995 { 996 u32 isr0_val, isr0_mask, isr0_status; 997 u32 isr1_val, isr1_mask, isr1_status; 998 int i, virq; 999 1000 isr0_val = advk_readl(pcie, PCIE_ISR0_REG); 1001 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); 1002 isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK); 1003 1004 isr1_val = advk_readl(pcie, PCIE_ISR1_REG); 1005 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 1006 isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK); 1007 1008 if (!isr0_status && !isr1_status) { 1009 advk_writel(pcie, isr0_val, PCIE_ISR0_REG); 1010 advk_writel(pcie, isr1_val, PCIE_ISR1_REG); 1011 return; 1012 } 1013 1014 /* Process MSI interrupts */ 1015 if (isr0_status & PCIE_ISR0_MSI_INT_PENDING) 1016 advk_pcie_handle_msi(pcie); 1017 1018 /* Process legacy interrupts */ 1019 for (i = 0; i < PCI_NUM_INTX; i++) { 1020 if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i))) 1021 continue; 1022 1023 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i), 1024 PCIE_ISR1_REG); 1025 1026 virq = irq_find_mapping(pcie->irq_domain, i); 1027 generic_handle_irq(virq); 1028 } 1029 } 1030 1031 static irqreturn_t advk_pcie_irq_handler(int irq, void *arg) 1032 { 1033 struct advk_pcie *pcie = arg; 1034 u32 status; 1035 1036 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); 1037 if (!(status & PCIE_IRQ_CORE_INT)) 1038 return IRQ_NONE; 1039 1040 advk_pcie_handle_int(pcie); 1041 1042 /* Clear interrupt */ 1043 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); 1044 1045 return IRQ_HANDLED; 1046 } 1047 1048 static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie) 1049 { 1050 phy_power_off(pcie->phy); 1051 phy_exit(pcie->phy); 1052 } 1053 1054 static int advk_pcie_enable_phy(struct advk_pcie *pcie) 1055 { 1056 int ret; 1057 1058 if (!pcie->phy) 1059 return 0; 1060 1061 ret = phy_init(pcie->phy); 1062 if (ret) 1063 return ret; 1064 1065 ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); 1066 if (ret) { 1067 phy_exit(pcie->phy); 1068 return ret; 1069 } 1070 1071 ret = phy_power_on(pcie->phy); 1072 if (ret) { 1073 phy_exit(pcie->phy); 1074 return ret; 1075 } 1076 1077 return 0; 1078 } 1079 1080 static int advk_pcie_setup_phy(struct advk_pcie *pcie) 1081 { 1082 struct device *dev = &pcie->pdev->dev; 1083 struct device_node *node = dev->of_node; 1084 int ret = 0; 1085 1086 pcie->phy = devm_of_phy_get(dev, node, NULL); 1087 if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER)) 1088 return PTR_ERR(pcie->phy); 1089 1090 /* Old bindings miss the PHY handle */ 1091 if (IS_ERR(pcie->phy)) { 1092 dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy)); 1093 pcie->phy = NULL; 1094 return 0; 1095 } 1096 1097 ret = advk_pcie_enable_phy(pcie); 1098 if (ret) 1099 dev_err(dev, "Failed to initialize PHY (%d)\n", ret); 1100 1101 return ret; 1102 } 1103 1104 static int advk_pcie_probe(struct platform_device *pdev) 1105 { 1106 struct device *dev = &pdev->dev; 1107 struct advk_pcie *pcie; 1108 struct resource *res, *bus; 1109 struct pci_host_bridge *bridge; 1110 int ret, irq; 1111 1112 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie)); 1113 if (!bridge) 1114 return -ENOMEM; 1115 1116 pcie = pci_host_bridge_priv(bridge); 1117 pcie->pdev = pdev; 1118 1119 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1120 pcie->base = devm_ioremap_resource(dev, res); 1121 if (IS_ERR(pcie->base)) 1122 return PTR_ERR(pcie->base); 1123 1124 irq = platform_get_irq(pdev, 0); 1125 if (irq < 0) 1126 return irq; 1127 1128 ret = devm_request_irq(dev, irq, advk_pcie_irq_handler, 1129 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", 1130 pcie); 1131 if (ret) { 1132 dev_err(dev, "Failed to register interrupt\n"); 1133 return ret; 1134 } 1135 1136 ret = pci_parse_request_of_pci_ranges(dev, &bridge->windows, 1137 &bridge->dma_ranges, &bus); 1138 if (ret) { 1139 dev_err(dev, "Failed to parse resources\n"); 1140 return ret; 1141 } 1142 pcie->root_bus_nr = bus->start; 1143 1144 pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node, 1145 "reset-gpios", 0, 1146 GPIOD_OUT_LOW, 1147 "pcie1-reset"); 1148 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio); 1149 if (ret) { 1150 if (ret == -ENOENT) { 1151 pcie->reset_gpio = NULL; 1152 } else { 1153 if (ret != -EPROBE_DEFER) 1154 dev_err(dev, "Failed to get reset-gpio: %i\n", 1155 ret); 1156 return ret; 1157 } 1158 } 1159 1160 ret = of_pci_get_max_link_speed(dev->of_node); 1161 if (ret <= 0 || ret > 3) 1162 pcie->link_gen = 3; 1163 else 1164 pcie->link_gen = ret; 1165 1166 ret = advk_pcie_setup_phy(pcie); 1167 if (ret) 1168 return ret; 1169 1170 advk_pcie_setup_hw(pcie); 1171 1172 advk_sw_pci_bridge_init(pcie); 1173 1174 ret = advk_pcie_init_irq_domain(pcie); 1175 if (ret) { 1176 dev_err(dev, "Failed to initialize irq\n"); 1177 return ret; 1178 } 1179 1180 ret = advk_pcie_init_msi_irq_domain(pcie); 1181 if (ret) { 1182 dev_err(dev, "Failed to initialize irq\n"); 1183 advk_pcie_remove_irq_domain(pcie); 1184 return ret; 1185 } 1186 1187 bridge->dev.parent = dev; 1188 bridge->sysdata = pcie; 1189 bridge->busnr = 0; 1190 bridge->ops = &advk_pcie_ops; 1191 bridge->map_irq = of_irq_parse_and_map_pci; 1192 bridge->swizzle_irq = pci_common_swizzle; 1193 1194 ret = pci_host_probe(bridge); 1195 if (ret < 0) { 1196 advk_pcie_remove_msi_irq_domain(pcie); 1197 advk_pcie_remove_irq_domain(pcie); 1198 return ret; 1199 } 1200 1201 return 0; 1202 } 1203 1204 static const struct of_device_id advk_pcie_of_match_table[] = { 1205 { .compatible = "marvell,armada-3700-pcie", }, 1206 {}, 1207 }; 1208 1209 static struct platform_driver advk_pcie_driver = { 1210 .driver = { 1211 .name = "advk-pcie", 1212 .of_match_table = advk_pcie_of_match_table, 1213 /* Driver unloading/unbinding currently not supported */ 1214 .suppress_bind_attrs = true, 1215 }, 1216 .probe = advk_pcie_probe, 1217 }; 1218 builtin_platform_driver(advk_pcie_driver); 1219