xref: /openbmc/linux/arch/arm64/mm/proc.S (revision dc6a81c3) 
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Based on arch/arm/mm/proc.S
4 *
5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * Copyright (C) 2012 ARM Ltd.
7 * Author: Catalin Marinas <catalin.marinas@arm.com>
8 */
9
10#include <linux/init.h>
11#include <linux/linkage.h>
12#include <asm/assembler.h>
13#include <asm/asm-offsets.h>
14#include <asm/hwcap.h>
15#include <asm/pgtable.h>
16#include <asm/pgtable-hwdef.h>
17#include <asm/cpufeature.h>
18#include <asm/alternative.h>
19
20#ifdef CONFIG_ARM64_64K_PAGES
21#define TCR_TG_FLAGS	TCR_TG0_64K | TCR_TG1_64K
22#elif defined(CONFIG_ARM64_16K_PAGES)
23#define TCR_TG_FLAGS	TCR_TG0_16K | TCR_TG1_16K
24#else /* CONFIG_ARM64_4K_PAGES */
25#define TCR_TG_FLAGS	TCR_TG0_4K | TCR_TG1_4K
26#endif
27
28#ifdef CONFIG_RANDOMIZE_BASE
29#define TCR_KASLR_FLAGS	TCR_NFD1
30#else
31#define TCR_KASLR_FLAGS	0
32#endif
33
34#define TCR_SMP_FLAGS	TCR_SHARED
35
36/* PTWs cacheable, inner/outer WBWA */
37#define TCR_CACHE_FLAGS	TCR_IRGN_WBWA | TCR_ORGN_WBWA
38
39#ifdef CONFIG_KASAN_SW_TAGS
40#define TCR_KASAN_FLAGS TCR_TBI1
41#else
42#define TCR_KASAN_FLAGS 0
43#endif
44
45/* Default MAIR_EL1 */
46#define MAIR_EL1_SET							\
47	(MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) |	\
48	 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) |	\
49	 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) |		\
50	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) |		\
51	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) |			\
52	 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT))
53
54#ifdef CONFIG_CPU_PM
55/**
56 * cpu_do_suspend - save CPU registers context
57 *
58 * x0: virtual address of context pointer
59 */
60SYM_FUNC_START(cpu_do_suspend)
61	mrs	x2, tpidr_el0
62	mrs	x3, tpidrro_el0
63	mrs	x4, contextidr_el1
64	mrs	x5, osdlr_el1
65	mrs	x6, cpacr_el1
66	mrs	x7, tcr_el1
67	mrs	x8, vbar_el1
68	mrs	x9, mdscr_el1
69	mrs	x10, oslsr_el1
70	mrs	x11, sctlr_el1
71alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
72	mrs	x12, tpidr_el1
73alternative_else
74	mrs	x12, tpidr_el2
75alternative_endif
76	mrs	x13, sp_el0
77	stp	x2, x3, [x0]
78	stp	x4, x5, [x0, #16]
79	stp	x6, x7, [x0, #32]
80	stp	x8, x9, [x0, #48]
81	stp	x10, x11, [x0, #64]
82	stp	x12, x13, [x0, #80]
83	ret
84SYM_FUNC_END(cpu_do_suspend)
85
86/**
87 * cpu_do_resume - restore CPU register context
88 *
89 * x0: Address of context pointer
90 */
91	.pushsection ".idmap.text", "awx"
92SYM_FUNC_START(cpu_do_resume)
93	ldp	x2, x3, [x0]
94	ldp	x4, x5, [x0, #16]
95	ldp	x6, x8, [x0, #32]
96	ldp	x9, x10, [x0, #48]
97	ldp	x11, x12, [x0, #64]
98	ldp	x13, x14, [x0, #80]
99	msr	tpidr_el0, x2
100	msr	tpidrro_el0, x3
101	msr	contextidr_el1, x4
102	msr	cpacr_el1, x6
103
104	/* Don't change t0sz here, mask those bits when restoring */
105	mrs	x7, tcr_el1
106	bfi	x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
107
108	msr	tcr_el1, x8
109	msr	vbar_el1, x9
110
111	/*
112	 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
113	 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
114	 * exception. Mask them until local_daif_restore() in cpu_suspend()
115	 * resets them.
116	 */
117	disable_daif
118	msr	mdscr_el1, x10
119
120	msr	sctlr_el1, x12
121alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
122	msr	tpidr_el1, x13
123alternative_else
124	msr	tpidr_el2, x13
125alternative_endif
126	msr	sp_el0, x14
127	/*
128	 * Restore oslsr_el1 by writing oslar_el1
129	 */
130	msr	osdlr_el1, x5
131	ubfx	x11, x11, #1, #1
132	msr	oslar_el1, x11
133	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
134
135alternative_if ARM64_HAS_RAS_EXTN
136	msr_s	SYS_DISR_EL1, xzr
137alternative_else_nop_endif
138
139	isb
140	ret
141SYM_FUNC_END(cpu_do_resume)
142	.popsection
143#endif
144
145/*
146 *	cpu_do_switch_mm(pgd_phys, tsk)
147 *
148 *	Set the translation table base pointer to be pgd_phys.
149 *
150 *	- pgd_phys - physical address of new TTB
151 */
152SYM_FUNC_START(cpu_do_switch_mm)
153	mrs	x2, ttbr1_el1
154	mmid	x1, x1				// get mm->context.id
155	phys_to_ttbr x3, x0
156
157alternative_if ARM64_HAS_CNP
158	cbz     x1, 1f                          // skip CNP for reserved ASID
159	orr     x3, x3, #TTBR_CNP_BIT
1601:
161alternative_else_nop_endif
162#ifdef CONFIG_ARM64_SW_TTBR0_PAN
163	bfi	x3, x1, #48, #16		// set the ASID field in TTBR0
164#endif
165	bfi	x2, x1, #48, #16		// set the ASID
166	msr	ttbr1_el1, x2			// in TTBR1 (since TCR.A1 is set)
167	isb
168	msr	ttbr0_el1, x3			// now update TTBR0
169	isb
170	b	post_ttbr_update_workaround	// Back to C code...
171SYM_FUNC_END(cpu_do_switch_mm)
172
173	.pushsection ".idmap.text", "awx"
174
175.macro	__idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
176	adrp	\tmp1, empty_zero_page
177	phys_to_ttbr \tmp2, \tmp1
178	offset_ttbr1 \tmp2, \tmp1
179	msr	ttbr1_el1, \tmp2
180	isb
181	tlbi	vmalle1
182	dsb	nsh
183	isb
184.endm
185
186/*
187 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
188 *
189 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
190 * called by anything else. It can only be executed from a TTBR0 mapping.
191 */
192SYM_FUNC_START(idmap_cpu_replace_ttbr1)
193	save_and_disable_daif flags=x2
194
195	__idmap_cpu_set_reserved_ttbr1 x1, x3
196
197	offset_ttbr1 x0, x3
198	msr	ttbr1_el1, x0
199	isb
200
201	restore_daif x2
202
203	ret
204SYM_FUNC_END(idmap_cpu_replace_ttbr1)
205	.popsection
206
207#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
208	.pushsection ".idmap.text", "awx"
209
210	.macro	__idmap_kpti_get_pgtable_ent, type
211	dc	cvac, cur_\()\type\()p		// Ensure any existing dirty
212	dmb	sy				// lines are written back before
213	ldr	\type, [cur_\()\type\()p]	// loading the entry
214	tbz	\type, #0, skip_\()\type	// Skip invalid and
215	tbnz	\type, #11, skip_\()\type	// non-global entries
216	.endm
217
218	.macro __idmap_kpti_put_pgtable_ent_ng, type
219	orr	\type, \type, #PTE_NG		// Same bit for blocks and pages
220	str	\type, [cur_\()\type\()p]	// Update the entry and ensure
221	dmb	sy				// that it is visible to all
222	dc	civac, cur_\()\type\()p		// CPUs.
223	.endm
224
225/*
226 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
227 *
228 * Called exactly once from stop_machine context by each CPU found during boot.
229 */
230__idmap_kpti_flag:
231	.long	1
232SYM_FUNC_START(idmap_kpti_install_ng_mappings)
233	cpu		.req	w0
234	num_cpus	.req	w1
235	swapper_pa	.req	x2
236	swapper_ttb	.req	x3
237	flag_ptr	.req	x4
238	cur_pgdp	.req	x5
239	end_pgdp	.req	x6
240	pgd		.req	x7
241	cur_pudp	.req	x8
242	end_pudp	.req	x9
243	pud		.req	x10
244	cur_pmdp	.req	x11
245	end_pmdp	.req	x12
246	pmd		.req	x13
247	cur_ptep	.req	x14
248	end_ptep	.req	x15
249	pte		.req	x16
250
251	mrs	swapper_ttb, ttbr1_el1
252	restore_ttbr1	swapper_ttb
253	adr	flag_ptr, __idmap_kpti_flag
254
255	cbnz	cpu, __idmap_kpti_secondary
256
257	/* We're the boot CPU. Wait for the others to catch up */
258	sevl
2591:	wfe
260	ldaxr	w17, [flag_ptr]
261	eor	w17, w17, num_cpus
262	cbnz	w17, 1b
263
264	/* We need to walk swapper, so turn off the MMU. */
265	pre_disable_mmu_workaround
266	mrs	x17, sctlr_el1
267	bic	x17, x17, #SCTLR_ELx_M
268	msr	sctlr_el1, x17
269	isb
270
271	/* Everybody is enjoying the idmap, so we can rewrite swapper. */
272	/* PGD */
273	mov	cur_pgdp, swapper_pa
274	add	end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
275do_pgd:	__idmap_kpti_get_pgtable_ent	pgd
276	tbnz	pgd, #1, walk_puds
277next_pgd:
278	__idmap_kpti_put_pgtable_ent_ng	pgd
279skip_pgd:
280	add	cur_pgdp, cur_pgdp, #8
281	cmp	cur_pgdp, end_pgdp
282	b.ne	do_pgd
283
284	/* Publish the updated tables and nuke all the TLBs */
285	dsb	sy
286	tlbi	vmalle1is
287	dsb	ish
288	isb
289
290	/* We're done: fire up the MMU again */
291	mrs	x17, sctlr_el1
292	orr	x17, x17, #SCTLR_ELx_M
293	msr	sctlr_el1, x17
294	isb
295
296	/*
297	 * Invalidate the local I-cache so that any instructions fetched
298	 * speculatively from the PoC are discarded, since they may have
299	 * been dynamically patched at the PoU.
300	 */
301	ic	iallu
302	dsb	nsh
303	isb
304
305	/* Set the flag to zero to indicate that we're all done */
306	str	wzr, [flag_ptr]
307	ret
308
309	/* PUD */
310walk_puds:
311	.if CONFIG_PGTABLE_LEVELS > 3
312	pte_to_phys	cur_pudp, pgd
313	add	end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
314do_pud:	__idmap_kpti_get_pgtable_ent	pud
315	tbnz	pud, #1, walk_pmds
316next_pud:
317	__idmap_kpti_put_pgtable_ent_ng	pud
318skip_pud:
319	add	cur_pudp, cur_pudp, 8
320	cmp	cur_pudp, end_pudp
321	b.ne	do_pud
322	b	next_pgd
323	.else /* CONFIG_PGTABLE_LEVELS <= 3 */
324	mov	pud, pgd
325	b	walk_pmds
326next_pud:
327	b	next_pgd
328	.endif
329
330	/* PMD */
331walk_pmds:
332	.if CONFIG_PGTABLE_LEVELS > 2
333	pte_to_phys	cur_pmdp, pud
334	add	end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
335do_pmd:	__idmap_kpti_get_pgtable_ent	pmd
336	tbnz	pmd, #1, walk_ptes
337next_pmd:
338	__idmap_kpti_put_pgtable_ent_ng	pmd
339skip_pmd:
340	add	cur_pmdp, cur_pmdp, #8
341	cmp	cur_pmdp, end_pmdp
342	b.ne	do_pmd
343	b	next_pud
344	.else /* CONFIG_PGTABLE_LEVELS <= 2 */
345	mov	pmd, pud
346	b	walk_ptes
347next_pmd:
348	b	next_pud
349	.endif
350
351	/* PTE */
352walk_ptes:
353	pte_to_phys	cur_ptep, pmd
354	add	end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
355do_pte:	__idmap_kpti_get_pgtable_ent	pte
356	__idmap_kpti_put_pgtable_ent_ng	pte
357skip_pte:
358	add	cur_ptep, cur_ptep, #8
359	cmp	cur_ptep, end_ptep
360	b.ne	do_pte
361	b	next_pmd
362
363	.unreq	cpu
364	.unreq	num_cpus
365	.unreq	swapper_pa
366	.unreq	cur_pgdp
367	.unreq	end_pgdp
368	.unreq	pgd
369	.unreq	cur_pudp
370	.unreq	end_pudp
371	.unreq	pud
372	.unreq	cur_pmdp
373	.unreq	end_pmdp
374	.unreq	pmd
375	.unreq	cur_ptep
376	.unreq	end_ptep
377	.unreq	pte
378
379	/* Secondary CPUs end up here */
380__idmap_kpti_secondary:
381	/* Uninstall swapper before surgery begins */
382	__idmap_cpu_set_reserved_ttbr1 x16, x17
383
384	/* Increment the flag to let the boot CPU we're ready */
3851:	ldxr	w16, [flag_ptr]
386	add	w16, w16, #1
387	stxr	w17, w16, [flag_ptr]
388	cbnz	w17, 1b
389
390	/* Wait for the boot CPU to finish messing around with swapper */
391	sevl
3921:	wfe
393	ldxr	w16, [flag_ptr]
394	cbnz	w16, 1b
395
396	/* All done, act like nothing happened */
397	offset_ttbr1 swapper_ttb, x16
398	msr	ttbr1_el1, swapper_ttb
399	isb
400	ret
401
402	.unreq	swapper_ttb
403	.unreq	flag_ptr
404SYM_FUNC_END(idmap_kpti_install_ng_mappings)
405	.popsection
406#endif
407
408/*
409 *	__cpu_setup
410 *
411 *	Initialise the processor for turning the MMU on.  Return in x0 the
412 *	value of the SCTLR_EL1 register.
413 */
414	.pushsection ".idmap.text", "awx"
415SYM_FUNC_START(__cpu_setup)
416	tlbi	vmalle1				// Invalidate local TLB
417	dsb	nsh
418
419	mov	x0, #3 << 20
420	msr	cpacr_el1, x0			// Enable FP/ASIMD
421	mov	x0, #1 << 12			// Reset mdscr_el1 and disable
422	msr	mdscr_el1, x0			// access to the DCC from EL0
423	isb					// Unmask debug exceptions now,
424	enable_dbg				// since this is per-cpu
425	reset_pmuserenr_el0 x0			// Disable PMU access from EL0
426	/*
427	 * Memory region attributes
428	 */
429	mov_q	x5, MAIR_EL1_SET
430	msr	mair_el1, x5
431	/*
432	 * Prepare SCTLR
433	 */
434	mov_q	x0, SCTLR_EL1_SET
435	/*
436	 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
437	 * both user and kernel.
438	 */
439	ldr	x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
440			TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
441			TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS
442	tcr_clear_errata_bits x10, x9, x5
443
444#ifdef CONFIG_ARM64_VA_BITS_52
445	ldr_l		x9, vabits_actual
446	sub		x9, xzr, x9
447	add		x9, x9, #64
448	tcr_set_t1sz	x10, x9
449#else
450	ldr_l		x9, idmap_t0sz
451#endif
452	tcr_set_t0sz	x10, x9
453
454	/*
455	 * Set the IPS bits in TCR_EL1.
456	 */
457	tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
458#ifdef CONFIG_ARM64_HW_AFDBM
459	/*
460	 * Enable hardware update of the Access Flags bit.
461	 * Hardware dirty bit management is enabled later,
462	 * via capabilities.
463	 */
464	mrs	x9, ID_AA64MMFR1_EL1
465	and	x9, x9, #0xf
466	cbz	x9, 1f
467	orr	x10, x10, #TCR_HA		// hardware Access flag update
4681:
469#endif	/* CONFIG_ARM64_HW_AFDBM */
470	msr	tcr_el1, x10
471	ret					// return to head.S
472SYM_FUNC_END(__cpu_setup)
473