1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/clk-provider.h> 3 #include <linux/mfd/syscon.h> 4 #include <linux/slab.h> 5 6 #include <dt-bindings/clock/at91.h> 7 8 #include "pmc.h" 9 10 static const struct clk_master_characteristics mck_characteristics = { 11 .output = { .min = 0, .max = 166000000 }, 12 .divisors = { 1, 2, 4, 3 }, 13 }; 14 15 static u8 plla_out[] = { 0 }; 16 17 static u16 plla_icpll[] = { 0 }; 18 19 static const struct clk_range plla_outputs[] = { 20 { .min = 400000000, .max = 1000000000 }, 21 }; 22 23 static const struct clk_pll_characteristics plla_characteristics = { 24 .input = { .min = 8000000, .max = 50000000 }, 25 .num_output = ARRAY_SIZE(plla_outputs), 26 .output = plla_outputs, 27 .icpll = plla_icpll, 28 .out = plla_out, 29 }; 30 31 static const struct clk_pcr_layout sama5d3_pcr_layout = { 32 .offset = 0x10c, 33 .cmd = BIT(12), 34 .pid_mask = GENMASK(6, 0), 35 .div_mask = GENMASK(17, 16), 36 }; 37 38 static const struct { 39 char *n; 40 char *p; 41 u8 id; 42 } sama5d3_systemck[] = { 43 { .n = "ddrck", .p = "masterck", .id = 2 }, 44 { .n = "lcdck", .p = "masterck", .id = 3 }, 45 { .n = "smdck", .p = "smdclk", .id = 4 }, 46 { .n = "uhpck", .p = "usbck", .id = 6 }, 47 { .n = "udpck", .p = "usbck", .id = 7 }, 48 { .n = "pck0", .p = "prog0", .id = 8 }, 49 { .n = "pck1", .p = "prog1", .id = 9 }, 50 { .n = "pck2", .p = "prog2", .id = 10 }, 51 }; 52 53 static const struct { 54 char *n; 55 u8 id; 56 struct clk_range r; 57 } sama5d3_periphck[] = { 58 { .n = "dbgu_clk", .id = 2, }, 59 { .n = "hsmc_clk", .id = 5, }, 60 { .n = "pioA_clk", .id = 6, }, 61 { .n = "pioB_clk", .id = 7, }, 62 { .n = "pioC_clk", .id = 8, }, 63 { .n = "pioD_clk", .id = 9, }, 64 { .n = "pioE_clk", .id = 10, }, 65 { .n = "usart0_clk", .id = 12, .r = { .min = 0, .max = 83000000 }, }, 66 { .n = "usart1_clk", .id = 13, .r = { .min = 0, .max = 83000000 }, }, 67 { .n = "usart2_clk", .id = 14, .r = { .min = 0, .max = 83000000 }, }, 68 { .n = "usart3_clk", .id = 15, .r = { .min = 0, .max = 83000000 }, }, 69 { .n = "uart0_clk", .id = 16, .r = { .min = 0, .max = 83000000 }, }, 70 { .n = "uart1_clk", .id = 17, .r = { .min = 0, .max = 83000000 }, }, 71 { .n = "twi0_clk", .id = 18, .r = { .min = 0, .max = 41500000 }, }, 72 { .n = "twi1_clk", .id = 19, .r = { .min = 0, .max = 41500000 }, }, 73 { .n = "twi2_clk", .id = 20, .r = { .min = 0, .max = 41500000 }, }, 74 { .n = "mci0_clk", .id = 21, }, 75 { .n = "mci1_clk", .id = 22, }, 76 { .n = "mci2_clk", .id = 23, }, 77 { .n = "spi0_clk", .id = 24, .r = { .min = 0, .max = 166000000 }, }, 78 { .n = "spi1_clk", .id = 25, .r = { .min = 0, .max = 166000000 }, }, 79 { .n = "tcb0_clk", .id = 26, .r = { .min = 0, .max = 166000000 }, }, 80 { .n = "tcb1_clk", .id = 27, .r = { .min = 0, .max = 166000000 }, }, 81 { .n = "pwm_clk", .id = 28, }, 82 { .n = "adc_clk", .id = 29, .r = { .min = 0, .max = 83000000 }, }, 83 { .n = "dma0_clk", .id = 30, }, 84 { .n = "dma1_clk", .id = 31, }, 85 { .n = "uhphs_clk", .id = 32, }, 86 { .n = "udphs_clk", .id = 33, }, 87 { .n = "macb0_clk", .id = 34, }, 88 { .n = "macb1_clk", .id = 35, }, 89 { .n = "lcdc_clk", .id = 36, }, 90 { .n = "isi_clk", .id = 37, }, 91 { .n = "ssc0_clk", .id = 38, .r = { .min = 0, .max = 83000000 }, }, 92 { .n = "ssc1_clk", .id = 39, .r = { .min = 0, .max = 83000000 }, }, 93 { .n = "can0_clk", .id = 40, .r = { .min = 0, .max = 83000000 }, }, 94 { .n = "can1_clk", .id = 41, .r = { .min = 0, .max = 83000000 }, }, 95 { .n = "sha_clk", .id = 42, }, 96 { .n = "aes_clk", .id = 43, }, 97 { .n = "tdes_clk", .id = 44, }, 98 { .n = "trng_clk", .id = 45, }, 99 { .n = "fuse_clk", .id = 48, }, 100 { .n = "mpddr_clk", .id = 49, }, 101 }; 102 103 static void __init sama5d3_pmc_setup(struct device_node *np) 104 { 105 const char *slck_name, *mainxtal_name; 106 struct pmc_data *sama5d3_pmc; 107 const char *parent_names[5]; 108 struct regmap *regmap; 109 struct clk_hw *hw; 110 int i; 111 bool bypass; 112 113 i = of_property_match_string(np, "clock-names", "slow_clk"); 114 if (i < 0) 115 return; 116 117 slck_name = of_clk_get_parent_name(np, i); 118 119 i = of_property_match_string(np, "clock-names", "main_xtal"); 120 if (i < 0) 121 return; 122 mainxtal_name = of_clk_get_parent_name(np, i); 123 124 regmap = device_node_to_regmap(np); 125 if (IS_ERR(regmap)) 126 return; 127 128 sama5d3_pmc = pmc_data_allocate(PMC_PLLACK + 1, 129 nck(sama5d3_systemck), 130 nck(sama5d3_periphck), 0, 3); 131 if (!sama5d3_pmc) 132 return; 133 134 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, 135 50000000); 136 if (IS_ERR(hw)) 137 goto err_free; 138 139 bypass = of_property_read_bool(np, "atmel,osc-bypass"); 140 141 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, 142 bypass); 143 if (IS_ERR(hw)) 144 goto err_free; 145 146 parent_names[0] = "main_rc_osc"; 147 parent_names[1] = "main_osc"; 148 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2); 149 if (IS_ERR(hw)) 150 goto err_free; 151 152 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, 153 &sama5d3_pll_layout, &plla_characteristics); 154 if (IS_ERR(hw)) 155 goto err_free; 156 157 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack"); 158 if (IS_ERR(hw)) 159 goto err_free; 160 161 sama5d3_pmc->chws[PMC_PLLACK] = hw; 162 163 hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck"); 164 if (IS_ERR(hw)) 165 goto err_free; 166 167 sama5d3_pmc->chws[PMC_UTMI] = hw; 168 169 parent_names[0] = slck_name; 170 parent_names[1] = "mainck"; 171 parent_names[2] = "plladivck"; 172 parent_names[3] = "utmick"; 173 hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, 174 &at91sam9x5_master_layout, 175 &mck_characteristics); 176 if (IS_ERR(hw)) 177 goto err_free; 178 179 sama5d3_pmc->chws[PMC_MCK] = hw; 180 181 parent_names[0] = "plladivck"; 182 parent_names[1] = "utmick"; 183 hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); 184 if (IS_ERR(hw)) 185 goto err_free; 186 187 hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2); 188 if (IS_ERR(hw)) 189 goto err_free; 190 191 parent_names[0] = slck_name; 192 parent_names[1] = "mainck"; 193 parent_names[2] = "plladivck"; 194 parent_names[3] = "utmick"; 195 parent_names[4] = "masterck"; 196 for (i = 0; i < 3; i++) { 197 char name[6]; 198 199 snprintf(name, sizeof(name), "prog%d", i); 200 201 hw = at91_clk_register_programmable(regmap, name, 202 parent_names, 5, i, 203 &at91sam9x5_programmable_layout, 204 NULL); 205 if (IS_ERR(hw)) 206 goto err_free; 207 208 sama5d3_pmc->pchws[i] = hw; 209 } 210 211 for (i = 0; i < ARRAY_SIZE(sama5d3_systemck); i++) { 212 hw = at91_clk_register_system(regmap, sama5d3_systemck[i].n, 213 sama5d3_systemck[i].p, 214 sama5d3_systemck[i].id); 215 if (IS_ERR(hw)) 216 goto err_free; 217 218 sama5d3_pmc->shws[sama5d3_systemck[i].id] = hw; 219 } 220 221 for (i = 0; i < ARRAY_SIZE(sama5d3_periphck); i++) { 222 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, 223 &sama5d3_pcr_layout, 224 sama5d3_periphck[i].n, 225 "masterck", 226 sama5d3_periphck[i].id, 227 &sama5d3_periphck[i].r, 228 INT_MIN); 229 if (IS_ERR(hw)) 230 goto err_free; 231 232 sama5d3_pmc->phws[sama5d3_periphck[i].id] = hw; 233 } 234 235 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d3_pmc); 236 237 return; 238 239 err_free: 240 kfree(sama5d3_pmc); 241 } 242 /* 243 * The TCB is used as the clocksource so its clock is needed early. This means 244 * this can't be a platform driver. 245 */ 246 CLK_OF_DECLARE_DRIVER(sama5d3_pmc, "atmel,sama5d3-pmc", sama5d3_pmc_setup); 247