1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/pm_runtime.h> 8 #include <linux/soc/mediatek/mtk-cmdq.h> 9 10 #include <asm/barrier.h> 11 #include <soc/mediatek/smi.h> 12 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_plane_helper.h> 15 #include <drm/drm_probe_helper.h> 16 #include <drm/drm_vblank.h> 17 18 #include "mtk_drm_drv.h" 19 #include "mtk_drm_crtc.h" 20 #include "mtk_drm_ddp.h" 21 #include "mtk_drm_ddp_comp.h" 22 #include "mtk_drm_gem.h" 23 #include "mtk_drm_plane.h" 24 25 /** 26 * struct mtk_drm_crtc - MediaTek specific crtc structure. 27 * @base: crtc object. 28 * @enabled: records whether crtc_enable succeeded 29 * @planes: array of 4 drm_plane structures, one for each overlay plane 30 * @pending_planes: whether any plane has pending changes to be applied 31 * @config_regs: memory mapped mmsys configuration register space 32 * @mutex: handle to one of the ten disp_mutex streams 33 * @ddp_comp_nr: number of components in ddp_comp 34 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc 35 */ 36 struct mtk_drm_crtc { 37 struct drm_crtc base; 38 bool enabled; 39 40 bool pending_needs_vblank; 41 struct drm_pending_vblank_event *event; 42 43 struct drm_plane *planes; 44 unsigned int layer_nr; 45 bool pending_planes; 46 bool pending_async_planes; 47 48 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 49 struct cmdq_client *cmdq_client; 50 u32 cmdq_event; 51 #endif 52 53 void __iomem *config_regs; 54 struct mtk_disp_mutex *mutex; 55 unsigned int ddp_comp_nr; 56 struct mtk_ddp_comp **ddp_comp; 57 58 /* lock for display hardware access */ 59 struct mutex hw_lock; 60 }; 61 62 struct mtk_crtc_state { 63 struct drm_crtc_state base; 64 65 bool pending_config; 66 unsigned int pending_width; 67 unsigned int pending_height; 68 unsigned int pending_vrefresh; 69 }; 70 71 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) 72 { 73 return container_of(c, struct mtk_drm_crtc, base); 74 } 75 76 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) 77 { 78 return container_of(s, struct mtk_crtc_state, base); 79 } 80 81 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 82 { 83 struct drm_crtc *crtc = &mtk_crtc->base; 84 unsigned long flags; 85 86 spin_lock_irqsave(&crtc->dev->event_lock, flags); 87 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); 88 drm_crtc_vblank_put(crtc); 89 mtk_crtc->event = NULL; 90 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 91 } 92 93 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 94 { 95 drm_crtc_handle_vblank(&mtk_crtc->base); 96 if (mtk_crtc->pending_needs_vblank) { 97 mtk_drm_crtc_finish_page_flip(mtk_crtc); 98 mtk_crtc->pending_needs_vblank = false; 99 } 100 } 101 102 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) 103 { 104 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 105 106 mtk_disp_mutex_put(mtk_crtc->mutex); 107 108 drm_crtc_cleanup(crtc); 109 } 110 111 static void mtk_drm_crtc_reset(struct drm_crtc *crtc) 112 { 113 struct mtk_crtc_state *state; 114 115 if (crtc->state) { 116 __drm_atomic_helper_crtc_destroy_state(crtc->state); 117 118 state = to_mtk_crtc_state(crtc->state); 119 memset(state, 0, sizeof(*state)); 120 } else { 121 state = kzalloc(sizeof(*state), GFP_KERNEL); 122 if (!state) 123 return; 124 crtc->state = &state->base; 125 } 126 127 state->base.crtc = crtc; 128 } 129 130 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) 131 { 132 struct mtk_crtc_state *state; 133 134 state = kzalloc(sizeof(*state), GFP_KERNEL); 135 if (!state) 136 return NULL; 137 138 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 139 140 WARN_ON(state->base.crtc != crtc); 141 state->base.crtc = crtc; 142 143 return &state->base; 144 } 145 146 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, 147 struct drm_crtc_state *state) 148 { 149 __drm_atomic_helper_crtc_destroy_state(state); 150 kfree(to_mtk_crtc_state(state)); 151 } 152 153 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, 154 const struct drm_display_mode *mode, 155 struct drm_display_mode *adjusted_mode) 156 { 157 /* Nothing to do here, but this callback is mandatory. */ 158 return true; 159 } 160 161 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 162 { 163 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 164 165 state->pending_width = crtc->mode.hdisplay; 166 state->pending_height = crtc->mode.vdisplay; 167 state->pending_vrefresh = crtc->mode.vrefresh; 168 wmb(); /* Make sure the above parameters are set before update */ 169 state->pending_config = true; 170 } 171 172 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 173 { 174 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 175 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 176 177 mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base); 178 179 return 0; 180 } 181 182 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 183 { 184 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 185 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 186 187 mtk_ddp_comp_disable_vblank(comp); 188 } 189 190 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) 191 { 192 int ret; 193 int i; 194 195 DRM_DEBUG_DRIVER("%s\n", __func__); 196 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 197 ret = clk_prepare_enable(mtk_crtc->ddp_comp[i]->clk); 198 if (ret) { 199 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 200 goto err; 201 } 202 } 203 204 return 0; 205 err: 206 while (--i >= 0) 207 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 208 return ret; 209 } 210 211 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) 212 { 213 int i; 214 215 DRM_DEBUG_DRIVER("%s\n", __func__); 216 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 217 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 218 } 219 220 static 221 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, 222 struct drm_plane *plane, 223 unsigned int *local_layer) 224 { 225 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 226 struct mtk_ddp_comp *comp; 227 int i, count = 0; 228 unsigned int local_index = plane - mtk_crtc->planes; 229 230 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 231 comp = mtk_crtc->ddp_comp[i]; 232 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) { 233 *local_layer = local_index - count; 234 return comp; 235 } 236 count += mtk_ddp_comp_layer_nr(comp); 237 } 238 239 WARN(1, "Failed to find component for plane %d\n", plane->index); 240 return NULL; 241 } 242 243 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 244 static void ddp_cmdq_cb(struct cmdq_cb_data data) 245 { 246 cmdq_pkt_destroy(data.data); 247 } 248 #endif 249 250 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 251 { 252 struct drm_crtc *crtc = &mtk_crtc->base; 253 struct drm_connector *connector; 254 struct drm_encoder *encoder; 255 struct drm_connector_list_iter conn_iter; 256 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 257 int ret; 258 int i; 259 260 DRM_DEBUG_DRIVER("%s\n", __func__); 261 if (WARN_ON(!crtc->state)) 262 return -EINVAL; 263 264 width = crtc->state->adjusted_mode.hdisplay; 265 height = crtc->state->adjusted_mode.vdisplay; 266 vrefresh = crtc->state->adjusted_mode.vrefresh; 267 268 drm_for_each_encoder(encoder, crtc->dev) { 269 if (encoder->crtc != crtc) 270 continue; 271 272 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 273 drm_for_each_connector_iter(connector, &conn_iter) { 274 if (connector->encoder != encoder) 275 continue; 276 if (connector->display_info.bpc != 0 && 277 bpc > connector->display_info.bpc) 278 bpc = connector->display_info.bpc; 279 } 280 drm_connector_list_iter_end(&conn_iter); 281 } 282 283 ret = pm_runtime_get_sync(crtc->dev->dev); 284 if (ret < 0) { 285 DRM_ERROR("Failed to enable power domain: %d\n", ret); 286 return ret; 287 } 288 289 ret = mtk_disp_mutex_prepare(mtk_crtc->mutex); 290 if (ret < 0) { 291 DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 292 goto err_pm_runtime_put; 293 } 294 295 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 296 if (ret < 0) { 297 DRM_ERROR("Failed to enable component clocks: %d\n", ret); 298 goto err_mutex_unprepare; 299 } 300 301 DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n"); 302 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 303 mtk_ddp_add_comp_to_path(mtk_crtc->config_regs, 304 mtk_crtc->ddp_comp[i]->id, 305 mtk_crtc->ddp_comp[i + 1]->id); 306 mtk_disp_mutex_add_comp(mtk_crtc->mutex, 307 mtk_crtc->ddp_comp[i]->id); 308 } 309 mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 310 mtk_disp_mutex_enable(mtk_crtc->mutex); 311 312 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 313 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; 314 315 if (i == 1) 316 mtk_ddp_comp_bgclr_in_on(comp); 317 318 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL); 319 mtk_ddp_comp_start(comp); 320 } 321 322 /* Initially configure all planes */ 323 for (i = 0; i < mtk_crtc->layer_nr; i++) { 324 struct drm_plane *plane = &mtk_crtc->planes[i]; 325 struct mtk_plane_state *plane_state; 326 struct mtk_ddp_comp *comp; 327 unsigned int local_layer; 328 329 plane_state = to_mtk_plane_state(plane->state); 330 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 331 if (comp) 332 mtk_ddp_comp_layer_config(comp, local_layer, 333 plane_state, NULL); 334 } 335 336 return 0; 337 338 err_mutex_unprepare: 339 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 340 err_pm_runtime_put: 341 pm_runtime_put(crtc->dev->dev); 342 return ret; 343 } 344 345 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 346 { 347 struct drm_device *drm = mtk_crtc->base.dev; 348 struct drm_crtc *crtc = &mtk_crtc->base; 349 int i; 350 351 DRM_DEBUG_DRIVER("%s\n", __func__); 352 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 353 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); 354 if (i == 1) 355 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]); 356 } 357 358 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 359 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 360 mtk_crtc->ddp_comp[i]->id); 361 mtk_disp_mutex_disable(mtk_crtc->mutex); 362 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 363 mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs, 364 mtk_crtc->ddp_comp[i]->id, 365 mtk_crtc->ddp_comp[i + 1]->id); 366 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 367 mtk_crtc->ddp_comp[i]->id); 368 } 369 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 370 mtk_crtc_ddp_clk_disable(mtk_crtc); 371 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 372 373 pm_runtime_put(drm->dev); 374 375 if (crtc->state->event && !crtc->state->active) { 376 spin_lock_irq(&crtc->dev->event_lock); 377 drm_crtc_send_vblank_event(crtc, crtc->state->event); 378 crtc->state->event = NULL; 379 spin_unlock_irq(&crtc->dev->event_lock); 380 } 381 } 382 383 static void mtk_crtc_ddp_config(struct drm_crtc *crtc, 384 struct cmdq_pkt *cmdq_handle) 385 { 386 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 387 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 388 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 389 unsigned int i; 390 unsigned int local_layer; 391 392 /* 393 * TODO: instead of updating the registers here, we should prepare 394 * working registers in atomic_commit and let the hardware command 395 * queue update module registers on vblank. 396 */ 397 if (state->pending_config) { 398 mtk_ddp_comp_config(comp, state->pending_width, 399 state->pending_height, 400 state->pending_vrefresh, 0, 401 cmdq_handle); 402 403 state->pending_config = false; 404 } 405 406 if (mtk_crtc->pending_planes) { 407 for (i = 0; i < mtk_crtc->layer_nr; i++) { 408 struct drm_plane *plane = &mtk_crtc->planes[i]; 409 struct mtk_plane_state *plane_state; 410 411 plane_state = to_mtk_plane_state(plane->state); 412 413 if (!plane_state->pending.config) 414 continue; 415 416 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 417 &local_layer); 418 419 if (comp) 420 mtk_ddp_comp_layer_config(comp, local_layer, 421 plane_state, 422 cmdq_handle); 423 plane_state->pending.config = false; 424 } 425 mtk_crtc->pending_planes = false; 426 } 427 428 if (mtk_crtc->pending_async_planes) { 429 for (i = 0; i < mtk_crtc->layer_nr; i++) { 430 struct drm_plane *plane = &mtk_crtc->planes[i]; 431 struct mtk_plane_state *plane_state; 432 433 plane_state = to_mtk_plane_state(plane->state); 434 435 if (!plane_state->pending.async_config) 436 continue; 437 438 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 439 &local_layer); 440 441 if (comp) 442 mtk_ddp_comp_layer_config(comp, local_layer, 443 plane_state, 444 cmdq_handle); 445 plane_state->pending.async_config = false; 446 } 447 mtk_crtc->pending_async_planes = false; 448 } 449 } 450 451 static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) 452 { 453 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 454 struct cmdq_pkt *cmdq_handle; 455 #endif 456 struct drm_crtc *crtc = &mtk_crtc->base; 457 struct mtk_drm_private *priv = crtc->dev->dev_private; 458 unsigned int pending_planes = 0, pending_async_planes = 0; 459 int i; 460 461 mutex_lock(&mtk_crtc->hw_lock); 462 for (i = 0; i < mtk_crtc->layer_nr; i++) { 463 struct drm_plane *plane = &mtk_crtc->planes[i]; 464 struct mtk_plane_state *plane_state; 465 466 plane_state = to_mtk_plane_state(plane->state); 467 if (plane_state->pending.dirty) { 468 plane_state->pending.config = true; 469 plane_state->pending.dirty = false; 470 pending_planes |= BIT(i); 471 } else if (plane_state->pending.async_dirty) { 472 plane_state->pending.async_config = true; 473 plane_state->pending.async_dirty = false; 474 pending_async_planes |= BIT(i); 475 } 476 } 477 if (pending_planes) 478 mtk_crtc->pending_planes = true; 479 if (pending_async_planes) 480 mtk_crtc->pending_async_planes = true; 481 482 if (priv->data->shadow_register) { 483 mtk_disp_mutex_acquire(mtk_crtc->mutex); 484 mtk_crtc_ddp_config(crtc, NULL); 485 mtk_disp_mutex_release(mtk_crtc->mutex); 486 } 487 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 488 if (mtk_crtc->cmdq_client) { 489 cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE); 490 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); 491 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event); 492 mtk_crtc_ddp_config(crtc, cmdq_handle); 493 cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle); 494 } 495 #endif 496 mutex_unlock(&mtk_crtc->hw_lock); 497 } 498 499 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, 500 struct mtk_plane_state *state) 501 { 502 unsigned int local_layer; 503 struct mtk_ddp_comp *comp; 504 505 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 506 if (comp) 507 return mtk_ddp_comp_layer_check(comp, local_layer, state); 508 return 0; 509 } 510 511 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, 512 struct drm_plane_state *new_state) 513 { 514 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 515 const struct drm_plane_helper_funcs *plane_helper_funcs = 516 plane->helper_private; 517 518 if (!mtk_crtc->enabled) 519 return; 520 521 plane_helper_funcs->atomic_update(plane, new_state); 522 mtk_drm_crtc_hw_config(mtk_crtc); 523 } 524 525 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 526 struct drm_crtc_state *old_state) 527 { 528 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 529 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 530 int ret; 531 532 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 533 534 ret = mtk_smi_larb_get(comp->larb_dev); 535 if (ret) { 536 DRM_ERROR("Failed to get larb: %d\n", ret); 537 return; 538 } 539 540 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 541 if (ret) { 542 mtk_smi_larb_put(comp->larb_dev); 543 return; 544 } 545 546 drm_crtc_vblank_on(crtc); 547 mtk_crtc->enabled = true; 548 } 549 550 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 551 struct drm_crtc_state *old_state) 552 { 553 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 554 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 555 int i; 556 557 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 558 if (!mtk_crtc->enabled) 559 return; 560 561 /* Set all pending plane state to disabled */ 562 for (i = 0; i < mtk_crtc->layer_nr; i++) { 563 struct drm_plane *plane = &mtk_crtc->planes[i]; 564 struct mtk_plane_state *plane_state; 565 566 plane_state = to_mtk_plane_state(plane->state); 567 plane_state->pending.enable = false; 568 plane_state->pending.config = true; 569 } 570 mtk_crtc->pending_planes = true; 571 572 mtk_drm_crtc_hw_config(mtk_crtc); 573 /* Wait for planes to be disabled */ 574 drm_crtc_wait_one_vblank(crtc); 575 576 drm_crtc_vblank_off(crtc); 577 mtk_crtc_ddp_hw_fini(mtk_crtc); 578 mtk_smi_larb_put(comp->larb_dev); 579 580 mtk_crtc->enabled = false; 581 } 582 583 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, 584 struct drm_crtc_state *old_crtc_state) 585 { 586 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 587 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 588 589 if (mtk_crtc->event && state->base.event) 590 DRM_ERROR("new event while there is still a pending event\n"); 591 592 if (state->base.event) { 593 state->base.event->pipe = drm_crtc_index(crtc); 594 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 595 mtk_crtc->event = state->base.event; 596 state->base.event = NULL; 597 } 598 } 599 600 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 601 struct drm_crtc_state *old_crtc_state) 602 { 603 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 604 int i; 605 606 if (mtk_crtc->event) 607 mtk_crtc->pending_needs_vblank = true; 608 if (crtc->state->color_mgmt_changed) 609 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 610 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); 611 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); 612 } 613 mtk_drm_crtc_hw_config(mtk_crtc); 614 } 615 616 static const struct drm_crtc_funcs mtk_crtc_funcs = { 617 .set_config = drm_atomic_helper_set_config, 618 .page_flip = drm_atomic_helper_page_flip, 619 .destroy = mtk_drm_crtc_destroy, 620 .reset = mtk_drm_crtc_reset, 621 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, 622 .atomic_destroy_state = mtk_drm_crtc_destroy_state, 623 .gamma_set = drm_atomic_helper_legacy_gamma_set, 624 .enable_vblank = mtk_drm_crtc_enable_vblank, 625 .disable_vblank = mtk_drm_crtc_disable_vblank, 626 }; 627 628 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { 629 .mode_fixup = mtk_drm_crtc_mode_fixup, 630 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, 631 .atomic_begin = mtk_drm_crtc_atomic_begin, 632 .atomic_flush = mtk_drm_crtc_atomic_flush, 633 .atomic_enable = mtk_drm_crtc_atomic_enable, 634 .atomic_disable = mtk_drm_crtc_atomic_disable, 635 }; 636 637 static int mtk_drm_crtc_init(struct drm_device *drm, 638 struct mtk_drm_crtc *mtk_crtc, 639 struct drm_plane *primary, 640 struct drm_plane *cursor, unsigned int pipe) 641 { 642 int ret; 643 644 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, 645 &mtk_crtc_funcs, NULL); 646 if (ret) 647 goto err_cleanup_crtc; 648 649 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); 650 651 return 0; 652 653 err_cleanup_crtc: 654 drm_crtc_cleanup(&mtk_crtc->base); 655 return ret; 656 } 657 658 void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) 659 { 660 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 661 struct mtk_drm_private *priv = crtc->dev->dev_private; 662 663 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 664 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client) 665 #else 666 if (!priv->data->shadow_register) 667 #endif 668 mtk_crtc_ddp_config(crtc, NULL); 669 670 mtk_drm_finish_page_flip(mtk_crtc); 671 } 672 673 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc, 674 int comp_idx) 675 { 676 struct mtk_ddp_comp *comp; 677 678 if (comp_idx > 1) 679 return 0; 680 681 comp = mtk_crtc->ddp_comp[comp_idx]; 682 if (!comp->funcs) 683 return 0; 684 685 if (comp_idx == 1 && !comp->funcs->bgclr_in_on) 686 return 0; 687 688 return mtk_ddp_comp_layer_nr(comp); 689 } 690 691 static inline 692 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx) 693 { 694 if (plane_idx == 0) 695 return DRM_PLANE_TYPE_PRIMARY; 696 else if (plane_idx == 1) 697 return DRM_PLANE_TYPE_CURSOR; 698 else 699 return DRM_PLANE_TYPE_OVERLAY; 700 701 } 702 703 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, 704 struct mtk_drm_crtc *mtk_crtc, 705 int comp_idx, int pipe) 706 { 707 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx); 708 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx]; 709 int i, ret; 710 711 for (i = 0; i < num_planes; i++) { 712 ret = mtk_plane_init(drm_dev, 713 &mtk_crtc->planes[mtk_crtc->layer_nr], 714 BIT(pipe), 715 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr), 716 mtk_ddp_comp_supported_rotations(comp)); 717 if (ret) 718 return ret; 719 720 mtk_crtc->layer_nr++; 721 } 722 return 0; 723 } 724 725 int mtk_drm_crtc_create(struct drm_device *drm_dev, 726 const enum mtk_ddp_comp_id *path, unsigned int path_len) 727 { 728 struct mtk_drm_private *priv = drm_dev->dev_private; 729 struct device *dev = drm_dev->dev; 730 struct mtk_drm_crtc *mtk_crtc; 731 unsigned int num_comp_planes = 0; 732 int pipe = priv->num_pipes; 733 int ret; 734 int i; 735 bool has_ctm = false; 736 uint gamma_lut_size = 0; 737 738 if (!path) 739 return 0; 740 741 for (i = 0; i < path_len; i++) { 742 enum mtk_ddp_comp_id comp_id = path[i]; 743 struct device_node *node; 744 745 node = priv->comp_node[comp_id]; 746 if (!node) { 747 dev_info(dev, 748 "Not creating crtc %d because component %d is disabled or missing\n", 749 pipe, comp_id); 750 return 0; 751 } 752 } 753 754 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); 755 if (!mtk_crtc) 756 return -ENOMEM; 757 758 mtk_crtc->config_regs = priv->config_regs; 759 mtk_crtc->ddp_comp_nr = path_len; 760 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, 761 sizeof(*mtk_crtc->ddp_comp), 762 GFP_KERNEL); 763 if (!mtk_crtc->ddp_comp) 764 return -ENOMEM; 765 766 mtk_crtc->mutex = mtk_disp_mutex_get(priv->mutex_dev, pipe); 767 if (IS_ERR(mtk_crtc->mutex)) { 768 ret = PTR_ERR(mtk_crtc->mutex); 769 dev_err(dev, "Failed to get mutex: %d\n", ret); 770 return ret; 771 } 772 773 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 774 enum mtk_ddp_comp_id comp_id = path[i]; 775 struct mtk_ddp_comp *comp; 776 struct device_node *node; 777 778 node = priv->comp_node[comp_id]; 779 comp = priv->ddp_comp[comp_id]; 780 if (!comp) { 781 dev_err(dev, "Component %pOF not initialized\n", node); 782 ret = -ENODEV; 783 return ret; 784 } 785 786 mtk_crtc->ddp_comp[i] = comp; 787 788 if (comp->funcs) { 789 if (comp->funcs->gamma_set) 790 gamma_lut_size = MTK_LUT_SIZE; 791 792 if (comp->funcs->ctm_set) 793 has_ctm = true; 794 } 795 } 796 797 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 798 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i); 799 800 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes, 801 sizeof(struct drm_plane), GFP_KERNEL); 802 803 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 804 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i, 805 pipe); 806 if (ret) 807 return ret; 808 } 809 810 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0], 811 mtk_crtc->layer_nr > 1 ? &mtk_crtc->planes[1] : 812 NULL, pipe); 813 if (ret < 0) 814 return ret; 815 816 if (gamma_lut_size) 817 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size); 818 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); 819 priv->num_pipes++; 820 mutex_init(&mtk_crtc->hw_lock); 821 822 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 823 mtk_crtc->cmdq_client = 824 cmdq_mbox_create(dev, drm_crtc_index(&mtk_crtc->base), 825 2000); 826 if (IS_ERR(mtk_crtc->cmdq_client)) { 827 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", 828 drm_crtc_index(&mtk_crtc->base)); 829 mtk_crtc->cmdq_client = NULL; 830 } 831 ret = of_property_read_u32_index(dev->of_node, "mediatek,gce-events", 832 drm_crtc_index(&mtk_crtc->base), 833 &mtk_crtc->cmdq_event); 834 if (ret) 835 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n", 836 drm_crtc_index(&mtk_crtc->base)); 837 #endif 838 return 0; 839 } 840