1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: "http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#" 5$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 7title: Bindings for the TI wrapper module for the Cadence USBSS-DRD controller 8 9maintainers: 10 - Roger Quadros <rogerq@ti.com> 11 12properties: 13 compatible: 14 items: 15 - const: ti,j721e-usb 16 17 reg: 18 description: module registers 19 20 power-domains: 21 description: 22 PM domain provider node and an args specifier containing 23 the USB device id value. See, 24 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt 25 26 clocks: 27 description: Clock phandles to usb2_refclk and lpm_clk 28 minItems: 2 29 maxItems: 2 30 31 clock-names: 32 items: 33 - const: ref 34 - const: lpm 35 36 ti,usb2-only: 37 description: 38 If present, it restricts the controller to USB2.0 mode of 39 operation. Must be present if USB3 PHY is not available 40 for USB. 41 type: boolean 42 43 ti,vbus-divider: 44 description: 45 Should be present if USB VBUS line is connected to the 46 VBUS pin of the SoC via a 1/3 voltage divider. 47 type: boolean 48 49required: 50 - compatible 51 - reg 52 - power-domains 53 - clocks 54 - clock-names 55 56examples: 57 - | 58 #include <dt-bindings/soc/ti,sci_pm_domain.h> 59 #include <dt-bindings/interrupt-controller/arm-gic.h> 60 61 bus { 62 #address-cells = <2>; 63 #size-cells = <2>; 64 65 cdns_usb@4104000 { 66 compatible = "ti,j721e-usb"; 67 reg = <0x00 0x4104000 0x00 0x100>; 68 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 69 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; 70 clock-names = "ref", "lpm"; 71 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ 72 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ 73 #address-cells = <2>; 74 #size-cells = <2>; 75 76 usb@6000000 { 77 compatible = "cdns,usb3"; 78 reg = <0x00 0x6000000 0x00 0x10000>, 79 <0x00 0x6010000 0x00 0x10000>, 80 <0x00 0x6020000 0x00 0x10000>; 81 reg-names = "otg", "xhci", "dev"; 82 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 83 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 84 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 85 interrupt-names = "host", 86 "peripheral", 87 "otg"; 88 maximum-speed = "super-speed"; 89 dr_mode = "otg"; 90 }; 91 }; 92 }; 93