1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Google Cheza device tree source (common between revisions) 4 * 5 * Copyright 2018 Google LLC. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 11#include "sdm845.dtsi" 12 13/* PMICs depend on spmi_bus label and so must come after SoC */ 14#include "pm8005.dtsi" 15#include "pm8998.dtsi" 16 17/ { 18 aliases { 19 bluetooth0 = &bluetooth; 20 hsuart0 = &uart6; 21 serial0 = &uart9; 22 wifi0 = &wifi; 23 }; 24 25 chosen { 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 backlight: backlight { 30 compatible = "pwm-backlight"; 31 pwms = <&cros_ec_pwm 0>; 32 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; 33 power-supply = <&ppvar_sys>; 34 pinctrl-names = "default"; 35 pinctrl-0 = <&ap_edp_bklten>; 36 }; 37 38 /* FIXED REGULATORS - parents above children */ 39 40 /* This is the top level supply and variable voltage */ 41 ppvar_sys: ppvar-sys-regulator { 42 compatible = "regulator-fixed"; 43 regulator-name = "ppvar_sys"; 44 regulator-always-on; 45 regulator-boot-on; 46 }; 47 48 /* This divides ppvar_sys by 2, so voltage is variable */ 49 src_vph_pwr: src-vph-pwr-regulator { 50 compatible = "regulator-fixed"; 51 regulator-name = "src_vph_pwr"; 52 53 /* EC turns on with switchcap_on_l; always on for AP */ 54 regulator-always-on; 55 regulator-boot-on; 56 57 vin-supply = <&ppvar_sys>; 58 }; 59 60 pp5000_a: pp5000-a-regulator { 61 compatible = "regulator-fixed"; 62 regulator-name = "pp5000_a"; 63 64 /* EC turns on with en_pp5000_a; always on for AP */ 65 regulator-always-on; 66 regulator-boot-on; 67 regulator-min-microvolt = <5000000>; 68 regulator-max-microvolt = <5000000>; 69 70 vin-supply = <&ppvar_sys>; 71 }; 72 73 src_vreg_bob: src-vreg-bob-regulator { 74 compatible = "regulator-fixed"; 75 regulator-name = "src_vreg_bob"; 76 77 /* EC turns on with vbob_en; always on for AP */ 78 regulator-always-on; 79 regulator-boot-on; 80 regulator-min-microvolt = <3600000>; 81 regulator-max-microvolt = <3600000>; 82 83 vin-supply = <&ppvar_sys>; 84 }; 85 86 pp3300_dx_edp: pp3300-dx-edp-regulator { 87 compatible = "regulator-fixed"; 88 regulator-name = "pp3300_dx_edp"; 89 90 regulator-min-microvolt = <3300000>; 91 regulator-max-microvolt = <3300000>; 92 93 gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>; 94 enable-active-high; 95 pinctrl-names = "default"; 96 pinctrl-0 = <&en_pp3300_dx_edp>; 97 }; 98 99 /* 100 * Apparently RPMh does not provide support for PM8998 S4 because it 101 * is always-on; model it as a fixed regulator. 102 */ 103 src_pp1800_s4a: pm8998-smps4 { 104 compatible = "regulator-fixed"; 105 regulator-name = "src_pp1800_s4a"; 106 107 regulator-min-microvolt = <1800000>; 108 regulator-max-microvolt = <1800000>; 109 110 regulator-always-on; 111 regulator-boot-on; 112 113 vin-supply = <&src_vph_pwr>; 114 }; 115 116 /* BOARD-SPECIFIC TOP LEVEL NODES */ 117 118 gpio-keys { 119 compatible = "gpio-keys"; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pen_eject_odl>; 122 123 pen-insert { 124 label = "Pen Insert"; 125 /* Insert = low, eject = high */ 126 gpios = <&tlmm 119 GPIO_ACTIVE_LOW>; 127 linux,code = <SW_PEN_INSERTED>; 128 linux,input-type = <EV_SW>; 129 wakeup-source; 130 }; 131 }; 132 133 panel: panel { 134 compatible ="innolux,p120zdg-bf1"; 135 power-supply = <&pp3300_dx_edp>; 136 backlight = <&backlight>; 137 no-hpd; 138 139 ports { 140 panel_in: port { 141 panel_in_edp: endpoint { 142 remote-endpoint = <&sn65dsi86_out>; 143 }; 144 }; 145 }; 146 }; 147}; 148 149/* 150 * Reserved memory changes 151 * 152 * Putting this all together (out of order with the rest of the file) to keep 153 * all modifications to the memory map (from sdm845.dtsi) in one place. 154 */ 155 156/* 157 * Our mpss_region is 8MB bigger than the default one and that conflicts 158 * with venus_mem and cdsp_mem. 159 * 160 * For venus_mem we'll delete and re-create at a different address. 161 * 162 * cdsp_mem isn't used on cheza right now so we won't bother re-creating it; but 163 * that also means we need to delete cdsp_pas. 164 */ 165/delete-node/ &venus_mem; 166/delete-node/ &cdsp_mem; 167/delete-node/ &cdsp_pas; 168/delete-node/ &gpu_mem; 169 170/* Increase the size from 120 MB to 128 MB */ 171&mpss_region { 172 reg = <0 0x8e000000 0 0x8000000>; 173}; 174 175/* Increase the size from 2MB to 8MB */ 176&rmtfs_mem { 177 reg = <0 0x88f00000 0 0x800000>; 178}; 179 180/ { 181 reserved-memory { 182 venus_mem: memory@96000000 { 183 reg = <0 0x96000000 0 0x500000>; 184 no-map; 185 }; 186 }; 187}; 188 189&qspi { 190 status = "okay"; 191 pinctrl-names = "default"; 192 pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; 193 194 flash@0 { 195 compatible = "jedec,spi-nor"; 196 reg = <0>; 197 198 /* 199 * In theory chip supports up to 104 MHz and controller up 200 * to 80 MHz, but above 25 MHz wasn't reliable so we'll use 201 * that for now. b:117440651 202 */ 203 spi-max-frequency = <25000000>; 204 spi-tx-bus-width = <2>; 205 spi-rx-bus-width = <2>; 206 }; 207}; 208 209 210&apps_rsc { 211 pm8998-rpmh-regulators { 212 compatible = "qcom,pm8998-rpmh-regulators"; 213 qcom,pmic-id = "a"; 214 215 vdd-s1-supply = <&src_vph_pwr>; 216 vdd-s2-supply = <&src_vph_pwr>; 217 vdd-s3-supply = <&src_vph_pwr>; 218 vdd-s4-supply = <&src_vph_pwr>; 219 vdd-s5-supply = <&src_vph_pwr>; 220 vdd-s6-supply = <&src_vph_pwr>; 221 vdd-s7-supply = <&src_vph_pwr>; 222 vdd-s8-supply = <&src_vph_pwr>; 223 vdd-s9-supply = <&src_vph_pwr>; 224 vdd-s10-supply = <&src_vph_pwr>; 225 vdd-s11-supply = <&src_vph_pwr>; 226 vdd-s12-supply = <&src_vph_pwr>; 227 vdd-s13-supply = <&src_vph_pwr>; 228 vdd-l1-l27-supply = <&src_pp1025_s7a>; 229 vdd-l2-l8-l17-supply = <&src_pp1350_s3a>; 230 vdd-l3-l11-supply = <&src_pp1025_s7a>; 231 vdd-l4-l5-supply = <&src_pp1025_s7a>; 232 vdd-l6-supply = <&src_vph_pwr>; 233 vdd-l7-l12-l14-l15-supply = <&src_pp2040_s5a>; 234 vdd-l9-supply = <&src_pp2040_s5a>; 235 vdd-l10-l23-l25-supply = <&src_vreg_bob>; 236 vdd-l13-l19-l21-supply = <&src_vreg_bob>; 237 vdd-l16-l28-supply = <&src_vreg_bob>; 238 vdd-l18-l22-supply = <&src_vreg_bob>; 239 vdd-l20-l24-supply = <&src_vreg_bob>; 240 vdd-l26-supply = <&src_pp1350_s3a>; 241 vin-lvs-1-2-supply = <&src_pp1800_s4a>; 242 243 src_pp1125_s2a: smps2 { 244 regulator-min-microvolt = <1100000>; 245 regulator-max-microvolt = <1100000>; 246 }; 247 248 src_pp1350_s3a: smps3 { 249 regulator-min-microvolt = <1352000>; 250 regulator-max-microvolt = <1352000>; 251 }; 252 253 src_pp2040_s5a: smps5 { 254 regulator-min-microvolt = <1904000>; 255 regulator-max-microvolt = <2040000>; 256 }; 257 258 src_pp1025_s7a: smps7 { 259 regulator-min-microvolt = <900000>; 260 regulator-max-microvolt = <1028000>; 261 }; 262 263 vdd_qusb_hs0: 264 vdda_hp_pcie_core: 265 vdda_mipi_csi0_0p9: 266 vdda_mipi_csi1_0p9: 267 vdda_mipi_csi2_0p9: 268 vdda_mipi_dsi0_pll: 269 vdda_mipi_dsi1_pll: 270 vdda_qlink_lv: 271 vdda_qlink_lv_ck: 272 vdda_qrefs_0p875: 273 vdda_pcie_core: 274 vdda_pll_cc_ebi01: 275 vdda_pll_cc_ebi23: 276 vdda_sp_sensor: 277 vdda_ufs1_core: 278 vdda_ufs2_core: 279 vdda_usb1_ss_core: 280 vdda_usb2_ss_core: 281 src_pp875_l1a: ldo1 { 282 regulator-min-microvolt = <880000>; 283 regulator-max-microvolt = <880000>; 284 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 285 }; 286 287 vddpx_10: 288 src_pp1200_l2a: ldo2 { 289 regulator-min-microvolt = <1200000>; 290 regulator-max-microvolt = <1200000>; 291 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 292 293 /* TODO: why??? */ 294 regulator-always-on; 295 }; 296 297 pp1000_l3a_sdr845: ldo3 { 298 regulator-min-microvolt = <1000000>; 299 regulator-max-microvolt = <1000000>; 300 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 301 }; 302 303 vdd_wcss_cx: 304 vdd_wcss_mx: 305 vdda_wcss_pll: 306 src_pp800_l5a: ldo5 { 307 regulator-min-microvolt = <800000>; 308 regulator-max-microvolt = <800000>; 309 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 310 }; 311 312 vddpx_13: 313 src_pp1800_l6a: ldo6 { 314 regulator-min-microvolt = <1856000>; 315 regulator-max-microvolt = <1856000>; 316 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 317 }; 318 319 pp1800_l7a_wcn3990: ldo7 { 320 regulator-min-microvolt = <1800000>; 321 regulator-max-microvolt = <1800000>; 322 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 323 }; 324 325 src_pp1200_l8a: ldo8 { 326 regulator-min-microvolt = <1200000>; 327 regulator-max-microvolt = <1248000>; 328 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 329 }; 330 331 pp1800_dx_pen: 332 src_pp1800_l9a: ldo9 { 333 regulator-min-microvolt = <1800000>; 334 regulator-max-microvolt = <1800000>; 335 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 336 }; 337 338 src_pp1800_l10a: ldo10 { 339 regulator-min-microvolt = <1800000>; 340 regulator-max-microvolt = <1800000>; 341 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 342 }; 343 344 pp1000_l11a_sdr845: ldo11 { 345 regulator-min-microvolt = <1000000>; 346 regulator-max-microvolt = <1048000>; 347 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 348 }; 349 350 vdd_qfprom: 351 vdd_qfprom_sp: 352 vdda_apc1_cs_1p8: 353 vdda_gfx_cs_1p8: 354 vdda_qrefs_1p8: 355 vdda_qusb_hs0_1p8: 356 vddpx_11: 357 src_pp1800_l12a: ldo12 { 358 regulator-min-microvolt = <1800000>; 359 regulator-max-microvolt = <1800000>; 360 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 361 }; 362 363 vddpx_2: 364 src_pp2950_l13a: ldo13 { 365 regulator-min-microvolt = <1800000>; 366 regulator-max-microvolt = <2960000>; 367 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 368 }; 369 370 src_pp1800_l14a: ldo14 { 371 regulator-min-microvolt = <1800000>; 372 regulator-max-microvolt = <1800000>; 373 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 374 }; 375 376 src_pp1800_l15a: ldo15 { 377 regulator-min-microvolt = <1800000>; 378 regulator-max-microvolt = <1800000>; 379 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 380 }; 381 382 pp2700_l16a: ldo16 { 383 regulator-min-microvolt = <2704000>; 384 regulator-max-microvolt = <2704000>; 385 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 386 }; 387 388 src_pp1300_l17a: ldo17 { 389 regulator-min-microvolt = <1304000>; 390 regulator-max-microvolt = <1304000>; 391 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 392 }; 393 394 pp2700_l18a: ldo18 { 395 regulator-min-microvolt = <2704000>; 396 regulator-max-microvolt = <2960000>; 397 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 398 }; 399 400 /* 401 * NOTE: this rail should have been called 402 * src_pp3300_l19a in the schematic 403 */ 404 src_pp3000_l19a: ldo19 { 405 regulator-min-microvolt = <3304000>; 406 regulator-max-microvolt = <3304000>; 407 408 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 409 }; 410 411 src_pp2950_l20a: ldo20 { 412 regulator-min-microvolt = <2704000>; 413 regulator-max-microvolt = <2960000>; 414 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 415 }; 416 417 src_pp2950_l21a: ldo21 { 418 regulator-min-microvolt = <2704000>; 419 regulator-max-microvolt = <2960000>; 420 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 421 }; 422 423 pp3300_hub: 424 src_pp3300_l22a: ldo22 { 425 regulator-min-microvolt = <3304000>; 426 regulator-max-microvolt = <3304000>; 427 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 428 /* 429 * HACK: Should add a usb hub node and driver 430 * to turn this on and off at suspend/resume time 431 */ 432 regulator-boot-on; 433 regulator-always-on; 434 }; 435 436 pp3300_l23a_ch1_wcn3990: ldo23 { 437 regulator-min-microvolt = <3000000>; 438 regulator-max-microvolt = <3312000>; 439 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 440 }; 441 442 vdda_qusb_hs0_3p1: 443 src_pp3075_l24a: ldo24 { 444 regulator-min-microvolt = <3088000>; 445 regulator-max-microvolt = <3088000>; 446 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 447 }; 448 449 pp3300_l25a_ch0_wcn3990: ldo25 { 450 regulator-min-microvolt = <3304000>; 451 regulator-max-microvolt = <3304000>; 452 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 453 }; 454 455 pp1200_hub: 456 vdda_hp_pcie_1p2: 457 vdda_hv_ebi0: 458 vdda_hv_ebi1: 459 vdda_hv_ebi2: 460 vdda_hv_ebi3: 461 vdda_mipi_csi_1p25: 462 vdda_mipi_dsi0_1p2: 463 vdda_mipi_dsi1_1p2: 464 vdda_pcie_1p2: 465 vdda_ufs1_1p2: 466 vdda_ufs2_1p2: 467 vdda_usb1_ss_1p2: 468 vdda_usb2_ss_1p2: 469 src_pp1200_l26a: ldo26 { 470 regulator-min-microvolt = <1200000>; 471 regulator-max-microvolt = <1200000>; 472 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 473 }; 474 475 pp3300_dx_pen: 476 src_pp3300_l28a: ldo28 { 477 regulator-min-microvolt = <3304000>; 478 regulator-max-microvolt = <3304000>; 479 regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; 480 }; 481 482 src_pp1800_lvs1: lvs1 { 483 regulator-min-microvolt = <1800000>; 484 regulator-max-microvolt = <1800000>; 485 }; 486 487 src_pp1800_lvs2: lvs2 { 488 regulator-min-microvolt = <1800000>; 489 regulator-max-microvolt = <1800000>; 490 }; 491 }; 492 493 pm8005-rpmh-regulators { 494 compatible = "qcom,pm8005-rpmh-regulators"; 495 qcom,pmic-id = "c"; 496 497 vdd-s1-supply = <&src_vph_pwr>; 498 vdd-s2-supply = <&src_vph_pwr>; 499 vdd-s3-supply = <&src_vph_pwr>; 500 vdd-s4-supply = <&src_vph_pwr>; 501 502 src_pp600_s3c: smps3 { 503 regulator-min-microvolt = <600000>; 504 regulator-max-microvolt = <600000>; 505 }; 506 }; 507}; 508 509&dsi0 { 510 status = "okay"; 511 vdda-supply = <&vdda_mipi_dsi0_1p2>; 512 513 ports { 514 port@1 { 515 endpoint { 516 remote-endpoint = <&sn65dsi86_in>; 517 data-lanes = <0 1 2 3>; 518 }; 519 }; 520 }; 521}; 522 523&dsi0_phy { 524 status = "okay"; 525 vdds-supply = <&vdda_mipi_dsi0_pll>; 526}; 527 528edp_brij_i2c: &i2c3 { 529 status = "okay"; 530 clock-frequency = <400000>; 531 532 sn65dsi86_bridge: bridge@2d { 533 compatible = "ti,sn65dsi86"; 534 reg = <0x2d>; 535 pinctrl-names = "default"; 536 pinctrl-0 = <&edp_brij_en &edp_brij_irq>; 537 538 interrupt-parent = <&tlmm>; 539 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 540 541 enable-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; 542 543 vpll-supply = <&src_pp1800_s4a>; 544 vccio-supply = <&src_pp1800_s4a>; 545 vcca-supply = <&src_pp1200_l2a>; 546 vcc-supply = <&src_pp1200_l2a>; 547 548 clocks = <&rpmhcc RPMH_LN_BB_CLK2>; 549 clock-names = "refclk"; 550 551 ports { 552 #address-cells = <1>; 553 #size-cells = <0>; 554 555 port@0 { 556 reg = <0>; 557 sn65dsi86_in: endpoint { 558 remote-endpoint = <&dsi0_out>; 559 }; 560 }; 561 562 port@1 { 563 reg = <1>; 564 sn65dsi86_out: endpoint { 565 remote-endpoint = <&panel_in_edp>; 566 }; 567 }; 568 }; 569 }; 570}; 571 572ap_pen_1v8: &i2c11 { 573 status = "okay"; 574 clock-frequency = <400000>; 575 576 digitizer@9 { 577 compatible = "wacom,w9013", "hid-over-i2c"; 578 reg = <0x9>; 579 pinctrl-names = "default"; 580 pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>; 581 582 vdd-supply = <&pp3300_dx_pen>; 583 vddl-supply = <&pp1800_dx_pen>; 584 post-power-on-delay-ms = <100>; 585 586 interrupt-parent = <&tlmm>; 587 interrupts = <24 IRQ_TYPE_LEVEL_LOW>; 588 589 hid-descr-addr = <0x1>; 590 }; 591}; 592 593amp_i2c: &i2c12 { 594 status = "okay"; 595 clock-frequency = <400000>; 596}; 597 598ap_ts_i2c: &i2c14 { 599 status = "okay"; 600 clock-frequency = <400000>; 601 602 touchscreen@10 { 603 compatible = "elan,ekth3500"; 604 reg = <0x10>; 605 pinctrl-names = "default"; 606 pinctrl-0 = <&ts_int_l &ts_reset_l>; 607 608 interrupt-parent = <&tlmm>; 609 interrupts = <125 IRQ_TYPE_LEVEL_LOW>; 610 611 vcc33-supply = <&src_pp3300_l28a>; 612 613 reset-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>; 614 }; 615}; 616 617&ipa { 618 status = "okay"; 619 modem-init; 620}; 621 622&lpasscc { 623 status = "okay"; 624}; 625 626&mdss { 627 status = "okay"; 628}; 629 630&mdss_mdp { 631 status = "okay"; 632}; 633 634&pm8998_pwrkey { 635 status = "disabled"; 636}; 637 638&qupv3_id_0 { 639 status = "okay"; 640}; 641 642&qupv3_id_1 { 643 status = "okay"; 644}; 645 646&sdhc_2 { 647 status = "okay"; 648 649 pinctrl-names = "default"; 650 pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data &sd_cd_odl>; 651 652 vmmc-supply = <&src_pp2950_l21a>; 653 vqmmc-supply = <&vddpx_2>; 654 655 cd-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; 656}; 657 658&spi0 { 659 status = "okay"; 660}; 661 662&spi5 { 663 status = "okay"; 664 665 tpm@0 { 666 compatible = "google,cr50"; 667 reg = <0>; 668 pinctrl-names = "default"; 669 pinctrl-0 = <&h1_ap_int_odl>; 670 spi-max-frequency = <800000>; 671 interrupt-parent = <&tlmm>; 672 interrupts = <129 IRQ_TYPE_EDGE_RISING>; 673 }; 674}; 675 676&spi10 { 677 status = "okay"; 678 679 cros_ec: ec@0 { 680 compatible = "google,cros-ec-spi"; 681 reg = <0>; 682 interrupt-parent = <&tlmm>; 683 interrupts = <122 IRQ_TYPE_LEVEL_LOW>; 684 pinctrl-names = "default"; 685 pinctrl-0 = <&ec_ap_int_l>; 686 spi-max-frequency = <3000000>; 687 688 cros_ec_pwm: ec-pwm { 689 compatible = "google,cros-ec-pwm"; 690 #pwm-cells = <1>; 691 }; 692 693 i2c_tunnel: i2c-tunnel { 694 compatible = "google,cros-ec-i2c-tunnel"; 695 google,remote-bus = <0>; 696 #address-cells = <1>; 697 #size-cells = <0>; 698 }; 699 700 pdupdate { 701 compatible = "google,cros-ec-pd-update"; 702 }; 703 }; 704}; 705 706#include <arm/cros-ec-keyboard.dtsi> 707#include <arm/cros-ec-sbs.dtsi> 708 709&uart6 { 710 status = "okay"; 711 712 bluetooth: wcn3990-bt { 713 compatible = "qcom,wcn3990-bt"; 714 vddio-supply = <&src_pp1800_s4a>; 715 vddxo-supply = <&pp1800_l7a_wcn3990>; 716 vddrf-supply = <&src_pp1300_l17a>; 717 vddch0-supply = <&pp3300_l25a_ch0_wcn3990>; 718 max-speed = <3200000>; 719 }; 720}; 721 722&uart9 { 723 status = "okay"; 724}; 725 726&ufs_mem_hc { 727 status = "okay"; 728 729 reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>; 730 731 vcc-supply = <&src_pp2950_l20a>; 732 vcc-max-microamp = <600000>; 733}; 734 735&ufs_mem_phy { 736 status = "okay"; 737 738 vdda-phy-supply = <&vdda_ufs1_core>; 739 vdda-pll-supply = <&vdda_ufs1_1p2>; 740}; 741 742&usb_1 { 743 status = "okay"; 744 745 /* We'll use this as USB 2.0 only */ 746 qcom,select-utmi-as-pipe-clk; 747}; 748 749&usb_1_dwc3 { 750 /* 751 * The hardware design intends this port to be hooked up in peripheral 752 * mode, so we'll hardcode it here. Some details: 753 * - SDM845 expects only a single Type C connector so it has only one 754 * native Type C port but cheza has two Type C connectors. 755 * - The only source of DP is the single native Type C port. 756 * - On cheza we want to be able to hook DP up to _either_ of the 757 * two Type C connectors and want to be able to achieve 4 lanes of DP. 758 * - When you configure a Type C port for 4 lanes of DP you lose USB3. 759 * - In order to make everything work, the native Type C port is always 760 * configured as 4-lanes DP so it's always available. 761 * - The extra USB3 port on SDM845 goes to a USB 3 hub which is then 762 * sent to the two Type C connectors. 763 * - The extra USB2 lines from the native Type C port are always 764 * setup as "peripheral" so that we can mux them over to one connector 765 * or the other if someone needs the connector configured as a gadget 766 * (but they only get USB2 speeds). 767 * 768 * All the hardware muxes would allow us to hook things up in different 769 * ways to some potential benefit for static configurations (you could 770 * achieve extra USB2 bandwidth by using two different ports for the 771 * two connectors or possibly even get USB3 peripheral mode), but in 772 * each case you end up forcing to disconnect/reconnect an in-use 773 * USB session in some cases depending on what you hotplug into the 774 * other connector. Thus hardcoding this as peripheral makes sense. 775 */ 776 dr_mode = "peripheral"; 777 778 /* 779 * We always need the high speed pins as 4-lanes DP in case someone 780 * hotplugs a DP peripheral. Thus limit this port to a max of high 781 * speed. 782 */ 783 maximum-speed = "high-speed"; 784 785 /* 786 * We don't need the usb3-phy since we run in highspeed mode always, so 787 * re-define these properties removing the superspeed USB PHY reference. 788 */ 789 phys = <&usb_1_hsphy>; 790 phy-names = "usb2-phy"; 791}; 792 793&usb_1_hsphy { 794 status = "okay"; 795 796 vdd-supply = <&vdda_usb1_ss_core>; 797 vdda-pll-supply = <&vdda_qusb_hs0_1p8>; 798 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; 799 800 qcom,imp-res-offset-value = <8>; 801 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; 802 qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; 803 qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; 804}; 805 806&usb_2 { 807 status = "okay"; 808}; 809 810&usb_2_dwc3 { 811 /* We have this hooked up to a hub and we always use in host mode */ 812 dr_mode = "host"; 813}; 814 815&usb_2_hsphy { 816 status = "okay"; 817 818 vdd-supply = <&vdda_usb2_ss_core>; 819 vdda-pll-supply = <&vdda_qusb_hs0_1p8>; 820 vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; 821 822 qcom,imp-res-offset-value = <8>; 823 qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>; 824}; 825 826&usb_2_qmpphy { 827 status = "okay"; 828 829 vdda-phy-supply = <&vdda_usb2_ss_1p2>; 830 vdda-pll-supply = <&vdda_usb2_ss_core>; 831}; 832 833&wifi { 834 status = "okay"; 835 836 vdd-0.8-cx-mx-supply = <&src_pp800_l5a >; 837 vdd-1.8-xo-supply = <&pp1800_l7a_wcn3990>; 838 vdd-1.3-rfa-supply = <&src_pp1300_l17a>; 839 vdd-3.3-ch0-supply = <&pp3300_l25a_ch0_wcn3990>; 840}; 841 842/* PINCTRL - additions to nodes defined in sdm845.dtsi */ 843 844&qspi_cs0 { 845 pinconf { 846 pins = "gpio90"; 847 bias-disable; 848 }; 849}; 850 851&qspi_clk { 852 pinconf { 853 pins = "gpio95"; 854 bias-disable; 855 }; 856}; 857 858&qspi_data01 { 859 pinconf { 860 pins = "gpio91", "gpio92"; 861 862 /* High-Z when no transfers; nice to park the lines */ 863 bias-pull-up; 864 }; 865}; 866 867&qup_i2c3_default { 868 pinconf { 869 pins = "gpio41", "gpio42"; 870 drive-strength = <2>; 871 872 /* Has external pullup */ 873 bias-disable; 874 }; 875}; 876 877&qup_i2c11_default { 878 pinconf { 879 pins = "gpio31", "gpio32"; 880 drive-strength = <2>; 881 882 /* Has external pullup */ 883 bias-disable; 884 }; 885}; 886 887&qup_i2c12_default { 888 pinconf { 889 pins = "gpio49", "gpio50"; 890 drive-strength = <2>; 891 892 /* Has external pullup */ 893 bias-disable; 894 }; 895}; 896 897&qup_i2c14_default { 898 pinconf { 899 pins = "gpio33", "gpio34"; 900 drive-strength = <2>; 901 902 /* Has external pullup */ 903 bias-disable; 904 }; 905}; 906 907&qup_spi0_default { 908 pinconf { 909 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 910 drive-strength = <2>; 911 bias-disable; 912 }; 913}; 914 915&qup_spi5_default { 916 pinconf { 917 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 918 drive-strength = <2>; 919 bias-disable; 920 }; 921}; 922 923&qup_spi10_default { 924 pinconf { 925 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 926 drive-strength = <2>; 927 bias-disable; 928 }; 929}; 930 931&qup_uart6_default { 932 /* Change pinmux to all 4 pins since CTS and RTS are connected */ 933 pinmux { 934 pins = "gpio45", "gpio46", 935 "gpio47", "gpio48"; 936 }; 937 938 pinconf-cts { 939 /* 940 * Configure a pull-down on 45 (CTS) to match the pull of 941 * the Bluetooth module. 942 */ 943 pins = "gpio45"; 944 bias-pull-down; 945 }; 946 947 pinconf-rts-tx { 948 /* We'll drive 46 (RTS) and 47 (TX), so no pull */ 949 pins = "gpio46", "gpio47"; 950 drive-strength = <2>; 951 bias-disable; 952 }; 953 954 pinconf-rx { 955 /* 956 * Configure a pull-up on 48 (RX). This is needed to avoid 957 * garbage data when the TX pin of the Bluetooth module is 958 * in tri-state (module powered off or not driving the 959 * signal yet). 960 */ 961 pins = "gpio48"; 962 bias-pull-up; 963 }; 964}; 965 966&qup_uart9_default { 967 pinconf-tx { 968 pins = "gpio4"; 969 drive-strength = <2>; 970 bias-disable; 971 }; 972 973 pinconf-rx { 974 pins = "gpio5"; 975 drive-strength = <2>; 976 bias-pull-up; 977 }; 978}; 979 980/* PINCTRL - board-specific pinctrl */ 981&pm8005_gpio { 982 gpio-line-names = "", 983 "", 984 "SLB", 985 ""; 986}; 987 988&pm8998_adc { 989 adc-chan@4d { 990 reg = <ADC5_AMUX_THM1_100K_PU>; 991 label = "sdm_temp"; 992 }; 993 994 adc-chan@4e { 995 reg = <ADC5_AMUX_THM2_100K_PU>; 996 label = "quiet_temp"; 997 }; 998 999 adc-chan@4f { 1000 reg = <ADC5_AMUX_THM3_100K_PU>; 1001 label = "lte_temp_1"; 1002 }; 1003 1004 adc-chan@50 { 1005 reg = <ADC5_AMUX_THM4_100K_PU>; 1006 label = "lte_temp_2"; 1007 }; 1008 1009 adc-chan@51 { 1010 reg = <ADC5_AMUX_THM5_100K_PU>; 1011 label = "charger_temp"; 1012 }; 1013}; 1014 1015&pm8998_gpio { 1016 gpio-line-names = "", 1017 "", 1018 "SW_CTRL", 1019 "", 1020 "", 1021 "", 1022 "", 1023 "", 1024 "", 1025 "", 1026 "", 1027 "", 1028 "", 1029 "", 1030 "", 1031 "", 1032 "", 1033 "", 1034 "", 1035 "", 1036 "", 1037 "CFG_OPT1", 1038 "WCSS_PWR_REQ", 1039 "", 1040 "CFG_OPT2", 1041 "SLB"; 1042}; 1043 1044&tlmm { 1045 /* 1046 * pinctrl settings for pins that have no real owners. 1047 */ 1048 pinctrl-names = "default", "sleep"; 1049 pinctrl-0 = <&bios_flash_wp_r_l>, 1050 <&ap_suspend_l_deassert>; 1051 1052 pinctrl-1 = <&bios_flash_wp_r_l>, 1053 <&ap_suspend_l_assert>; 1054 1055 /* 1056 * Hogs prevent usermode from changing the value. A GPIO can be both 1057 * here and in the pinctrl section. 1058 */ 1059 ap-suspend-l-hog { 1060 gpio-hog; 1061 gpios = <126 GPIO_ACTIVE_LOW>; 1062 output-low; 1063 }; 1064 1065 ap_edp_bklten: ap-edp-bklten { 1066 pinmux { 1067 pins = "gpio37"; 1068 function = "gpio"; 1069 }; 1070 1071 pinconf { 1072 pins = "gpio37"; 1073 drive-strength = <2>; 1074 bias-disable; 1075 }; 1076 }; 1077 1078 bios_flash_wp_r_l: bios-flash-wp-r-l { 1079 pinmux { 1080 pins = "gpio128"; 1081 function = "gpio"; 1082 input-enable; 1083 }; 1084 1085 pinconf { 1086 pins = "gpio128"; 1087 bias-disable; 1088 }; 1089 }; 1090 1091 ec_ap_int_l: ec-ap-int-l { 1092 pinmux { 1093 pins = "gpio122"; 1094 function = "gpio"; 1095 input-enable; 1096 }; 1097 1098 pinconf { 1099 pins = "gpio122"; 1100 bias-pull-up; 1101 }; 1102 }; 1103 1104 edp_brij_en: edp-brij-en { 1105 pinmux { 1106 pins = "gpio102"; 1107 function = "gpio"; 1108 }; 1109 1110 pinconf { 1111 pins = "gpio102"; 1112 drive-strength = <2>; 1113 bias-disable; 1114 }; 1115 }; 1116 1117 edp_brij_irq: edp-brij-irq { 1118 pinmux { 1119 pins = "gpio10"; 1120 function = "gpio"; 1121 }; 1122 1123 pinconf { 1124 pins = "gpio10"; 1125 drive-strength = <2>; 1126 bias-pull-down; 1127 }; 1128 }; 1129 1130 en_pp3300_dx_edp: en-pp3300-dx-edp { 1131 pinmux { 1132 pins = "gpio43"; 1133 function = "gpio"; 1134 }; 1135 1136 pinconf { 1137 pins = "gpio43"; 1138 drive-strength = <2>; 1139 bias-disable; 1140 }; 1141 }; 1142 1143 h1_ap_int_odl: h1-ap-int-odl { 1144 pinmux { 1145 pins = "gpio129"; 1146 function = "gpio"; 1147 input-enable; 1148 }; 1149 1150 pinconf { 1151 pins = "gpio129"; 1152 bias-pull-up; 1153 }; 1154 }; 1155 1156 pen_eject_odl: pen-eject-odl { 1157 pinmux { 1158 pins = "gpio119"; 1159 function = "gpio"; 1160 bias-pull-up; 1161 }; 1162 }; 1163 1164 pen_irq_l: pen-irq-l { 1165 pinmux { 1166 pins = "gpio24"; 1167 function = "gpio"; 1168 }; 1169 1170 pinconf { 1171 pins = "gpio24"; 1172 1173 /* Has external pullup */ 1174 bias-disable; 1175 }; 1176 }; 1177 1178 pen_pdct_l: pen-pdct-l { 1179 pinmux { 1180 pins = "gpio63"; 1181 function = "gpio"; 1182 }; 1183 1184 pinconf { 1185 pins = "gpio63"; 1186 1187 /* Has external pullup */ 1188 bias-disable; 1189 }; 1190 }; 1191 1192 pen_rst_l: pen-rst-l { 1193 pinmux { 1194 pins = "gpio23"; 1195 function = "gpio"; 1196 }; 1197 1198 pinconf { 1199 pins = "gpio23"; 1200 bias-disable; 1201 drive-strength = <2>; 1202 1203 /* 1204 * The pen driver doesn't currently support 1205 * driving this reset line. By specifying 1206 * output-high here we're relying on the fact 1207 * that this pin has a default pulldown at boot 1208 * (which makes sure the pen was in reset if it 1209 * was powered) and then we set it high here to 1210 * take it out of reset. Better would be if the 1211 * pen driver could control this and we could 1212 * remove "output-high" here. 1213 */ 1214 output-high; 1215 }; 1216 }; 1217 1218 sdc2_clk: sdc2-clk { 1219 pinconf { 1220 pins = "sdc2_clk"; 1221 bias-disable; 1222 1223 /* 1224 * It seems that mmc_test reports errors if drive 1225 * strength is not 16. 1226 */ 1227 drive-strength = <16>; 1228 }; 1229 }; 1230 1231 sdc2_cmd: sdc2-cmd { 1232 pinconf { 1233 pins = "sdc2_cmd"; 1234 bias-pull-up; 1235 drive-strength = <16>; 1236 }; 1237 }; 1238 1239 sdc2_data: sdc2-data { 1240 pinconf { 1241 pins = "sdc2_data"; 1242 bias-pull-up; 1243 drive-strength = <16>; 1244 }; 1245 }; 1246 1247 sd_cd_odl: sd-cd-odl { 1248 pinmux { 1249 pins = "gpio44"; 1250 function = "gpio"; 1251 }; 1252 1253 pinconf { 1254 pins = "gpio44"; 1255 bias-pull-up; 1256 }; 1257 }; 1258 1259 ts_int_l: ts-int-l { 1260 pinmux { 1261 pins = "gpio125"; 1262 function = "gpio"; 1263 }; 1264 1265 pinconf { 1266 pins = "gpio125"; 1267 bias-pull-up; 1268 }; 1269 }; 1270 1271 ts_reset_l: ts-reset-l { 1272 pinmux { 1273 pins = "gpio118"; 1274 function = "gpio"; 1275 }; 1276 1277 pinconf { 1278 pins = "gpio118"; 1279 bias-disable; 1280 drive-strength = <2>; 1281 }; 1282 }; 1283 1284 ap_suspend_l_assert: ap_suspend_l_assert { 1285 config { 1286 pins = "gpio126"; 1287 function = "gpio"; 1288 bias-no-pull; 1289 drive-strength = <2>; 1290 output-low; 1291 }; 1292 }; 1293 1294 ap_suspend_l_deassert: ap_suspend_l_deassert { 1295 config { 1296 pins = "gpio126"; 1297 function = "gpio"; 1298 bias-no-pull; 1299 drive-strength = <2>; 1300 output-high; 1301 }; 1302 }; 1303}; 1304 1305&venus { 1306 video-firmware { 1307 iommus = <&apps_smmu 0x10b2 0x0>; 1308 }; 1309}; 1310