1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __CXGB4_ULD_H 36 #define __CXGB4_ULD_H 37 38 #include <linux/cache.h> 39 #include <linux/spinlock.h> 40 #include <linux/skbuff.h> 41 #include <linux/inetdevice.h> 42 #include <linux/atomic.h> 43 #include "cxgb4.h" 44 45 #define MAX_ULD_QSETS 16 46 47 /* CPL message priority levels */ 48 enum { 49 CPL_PRIORITY_DATA = 0, /* data messages */ 50 CPL_PRIORITY_SETUP = 1, /* connection setup messages */ 51 CPL_PRIORITY_TEARDOWN = 0, /* connection teardown messages */ 52 CPL_PRIORITY_LISTEN = 1, /* listen start/stop messages */ 53 CPL_PRIORITY_ACK = 1, /* RX ACK messages */ 54 CPL_PRIORITY_CONTROL = 1 /* control messages */ 55 }; 56 57 #define INIT_TP_WR(w, tid) do { \ 58 (w)->wr.wr_hi = htonl(FW_WR_OP_V(FW_TP_WR) | \ 59 FW_WR_IMMDLEN_V(sizeof(*w) - sizeof(w->wr))); \ 60 (w)->wr.wr_mid = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*w), 16)) | \ 61 FW_WR_FLOWID_V(tid)); \ 62 (w)->wr.wr_lo = cpu_to_be64(0); \ 63 } while (0) 64 65 #define INIT_TP_WR_CPL(w, cpl, tid) do { \ 66 INIT_TP_WR(w, tid); \ 67 OPCODE_TID(w) = htonl(MK_OPCODE_TID(cpl, tid)); \ 68 } while (0) 69 70 #define INIT_ULPTX_WR(w, wrlen, atomic, tid) do { \ 71 (w)->wr.wr_hi = htonl(FW_WR_OP_V(FW_ULPTX_WR) | \ 72 FW_WR_ATOMIC_V(atomic)); \ 73 (w)->wr.wr_mid = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(wrlen, 16)) | \ 74 FW_WR_FLOWID_V(tid)); \ 75 (w)->wr.wr_lo = cpu_to_be64(0); \ 76 } while (0) 77 78 /* Special asynchronous notification message */ 79 #define CXGB4_MSG_AN ((void *)1) 80 #define TX_ULD(uld)(((uld) != CXGB4_ULD_CRYPTO) ? CXGB4_TX_OFLD :\ 81 CXGB4_TX_CRYPTO) 82 83 struct serv_entry { 84 void *data; 85 }; 86 87 union aopen_entry { 88 void *data; 89 union aopen_entry *next; 90 }; 91 92 struct eotid_entry { 93 void *data; 94 }; 95 96 /* 97 * Holds the size, base address, free list start, etc of the TID, server TID, 98 * and active-open TID tables. The tables themselves are allocated dynamically. 99 */ 100 struct tid_info { 101 void **tid_tab; 102 unsigned int tid_base; 103 unsigned int ntids; 104 105 struct serv_entry *stid_tab; 106 unsigned long *stid_bmap; 107 unsigned int nstids; 108 unsigned int stid_base; 109 unsigned int hash_base; 110 111 union aopen_entry *atid_tab; 112 unsigned int natids; 113 unsigned int atid_base; 114 115 struct filter_entry *hpftid_tab; 116 unsigned long *hpftid_bmap; 117 unsigned int nhpftids; 118 unsigned int hpftid_base; 119 120 struct filter_entry *ftid_tab; 121 unsigned long *ftid_bmap; 122 unsigned int nftids; 123 unsigned int ftid_base; 124 unsigned int aftid_base; 125 unsigned int aftid_end; 126 /* Server filter region */ 127 unsigned int sftid_base; 128 unsigned int nsftids; 129 130 spinlock_t atid_lock ____cacheline_aligned_in_smp; 131 union aopen_entry *afree; 132 unsigned int atids_in_use; 133 134 spinlock_t stid_lock; 135 unsigned int stids_in_use; 136 unsigned int v6_stids_in_use; 137 unsigned int sftids_in_use; 138 139 /* ETHOFLD range */ 140 struct eotid_entry *eotid_tab; 141 unsigned long *eotid_bmap; 142 unsigned int eotid_base; 143 unsigned int neotids; 144 145 /* TIDs in the TCAM */ 146 atomic_t tids_in_use; 147 /* TIDs in the HASH */ 148 atomic_t hash_tids_in_use; 149 atomic_t conns_in_use; 150 /* lock for setting/clearing filter bitmap */ 151 spinlock_t ftid_lock; 152 }; 153 154 static inline void *lookup_tid(const struct tid_info *t, unsigned int tid) 155 { 156 tid -= t->tid_base; 157 return tid < t->ntids ? t->tid_tab[tid] : NULL; 158 } 159 160 static inline bool tid_out_of_range(const struct tid_info *t, unsigned int tid) 161 { 162 return ((tid - t->tid_base) >= t->ntids); 163 } 164 165 static inline void *lookup_atid(const struct tid_info *t, unsigned int atid) 166 { 167 return atid < t->natids ? t->atid_tab[atid].data : NULL; 168 } 169 170 static inline void *lookup_stid(const struct tid_info *t, unsigned int stid) 171 { 172 /* Is it a server filter TID? */ 173 if (t->nsftids && (stid >= t->sftid_base)) { 174 stid -= t->sftid_base; 175 stid += t->nstids; 176 } else { 177 stid -= t->stid_base; 178 } 179 180 return stid < (t->nstids + t->nsftids) ? t->stid_tab[stid].data : NULL; 181 } 182 183 static inline void cxgb4_insert_tid(struct tid_info *t, void *data, 184 unsigned int tid, unsigned short family) 185 { 186 t->tid_tab[tid - t->tid_base] = data; 187 if (t->hash_base && (tid >= t->hash_base)) { 188 if (family == AF_INET6) 189 atomic_add(2, &t->hash_tids_in_use); 190 else 191 atomic_inc(&t->hash_tids_in_use); 192 } else { 193 if (family == AF_INET6) 194 atomic_add(2, &t->tids_in_use); 195 else 196 atomic_inc(&t->tids_in_use); 197 } 198 atomic_inc(&t->conns_in_use); 199 } 200 201 static inline struct eotid_entry *cxgb4_lookup_eotid(struct tid_info *t, 202 u32 eotid) 203 { 204 return eotid < t->neotids ? &t->eotid_tab[eotid] : NULL; 205 } 206 207 static inline int cxgb4_get_free_eotid(struct tid_info *t) 208 { 209 int eotid; 210 211 eotid = find_first_zero_bit(t->eotid_bmap, t->neotids); 212 if (eotid >= t->neotids) 213 eotid = -1; 214 215 return eotid; 216 } 217 218 static inline void cxgb4_alloc_eotid(struct tid_info *t, u32 eotid, void *data) 219 { 220 set_bit(eotid, t->eotid_bmap); 221 t->eotid_tab[eotid].data = data; 222 } 223 224 static inline void cxgb4_free_eotid(struct tid_info *t, u32 eotid) 225 { 226 clear_bit(eotid, t->eotid_bmap); 227 t->eotid_tab[eotid].data = NULL; 228 } 229 230 int cxgb4_alloc_atid(struct tid_info *t, void *data); 231 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data); 232 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data); 233 void cxgb4_free_atid(struct tid_info *t, unsigned int atid); 234 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family); 235 void cxgb4_remove_tid(struct tid_info *t, unsigned int qid, unsigned int tid, 236 unsigned short family); 237 struct in6_addr; 238 239 int cxgb4_create_server(const struct net_device *dev, unsigned int stid, 240 __be32 sip, __be16 sport, __be16 vlan, 241 unsigned int queue); 242 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid, 243 const struct in6_addr *sip, __be16 sport, 244 unsigned int queue); 245 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid, 246 unsigned int queue, bool ipv6); 247 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid, 248 __be32 sip, __be16 sport, __be16 vlan, 249 unsigned int queue, 250 unsigned char port, unsigned char mask); 251 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid, 252 unsigned int queue, bool ipv6); 253 254 /* Filter operation context to allow callers of cxgb4_set_filter() and 255 * cxgb4_del_filter() to wait for an asynchronous completion. 256 */ 257 struct filter_ctx { 258 struct completion completion; /* completion rendezvous */ 259 void *closure; /* caller's opaque information */ 260 int result; /* result of operation */ 261 u32 tid; /* to store tid */ 262 }; 263 264 struct ch_filter_specification; 265 266 int cxgb4_get_free_ftid(struct net_device *dev, int family); 267 int __cxgb4_set_filter(struct net_device *dev, int filter_id, 268 struct ch_filter_specification *fs, 269 struct filter_ctx *ctx); 270 int __cxgb4_del_filter(struct net_device *dev, int filter_id, 271 struct ch_filter_specification *fs, 272 struct filter_ctx *ctx); 273 int cxgb4_set_filter(struct net_device *dev, int filter_id, 274 struct ch_filter_specification *fs); 275 int cxgb4_del_filter(struct net_device *dev, int filter_id, 276 struct ch_filter_specification *fs); 277 int cxgb4_get_filter_counters(struct net_device *dev, unsigned int fidx, 278 u64 *hitcnt, u64 *bytecnt, bool hash); 279 280 static inline void set_wr_txq(struct sk_buff *skb, int prio, int queue) 281 { 282 skb_set_queue_mapping(skb, (queue << 1) | prio); 283 } 284 285 enum cxgb4_uld { 286 CXGB4_ULD_INIT, 287 CXGB4_ULD_RDMA, 288 CXGB4_ULD_ISCSI, 289 CXGB4_ULD_ISCSIT, 290 CXGB4_ULD_CRYPTO, 291 CXGB4_ULD_TLS, 292 CXGB4_ULD_MAX 293 }; 294 295 enum cxgb4_tx_uld { 296 CXGB4_TX_OFLD, 297 CXGB4_TX_CRYPTO, 298 CXGB4_TX_MAX 299 }; 300 301 enum cxgb4_txq_type { 302 CXGB4_TXQ_ETH, 303 CXGB4_TXQ_ULD, 304 CXGB4_TXQ_CTRL, 305 CXGB4_TXQ_MAX 306 }; 307 308 enum cxgb4_state { 309 CXGB4_STATE_UP, 310 CXGB4_STATE_START_RECOVERY, 311 CXGB4_STATE_DOWN, 312 CXGB4_STATE_DETACH, 313 CXGB4_STATE_FATAL_ERROR 314 }; 315 316 enum cxgb4_control { 317 CXGB4_CONTROL_DB_FULL, 318 CXGB4_CONTROL_DB_EMPTY, 319 CXGB4_CONTROL_DB_DROP, 320 }; 321 322 struct pci_dev; 323 struct l2t_data; 324 struct net_device; 325 struct pkt_gl; 326 struct tp_tcp_stats; 327 struct t4_lro_mgr; 328 329 struct cxgb4_range { 330 unsigned int start; 331 unsigned int size; 332 }; 333 334 struct cxgb4_virt_res { /* virtualized HW resources */ 335 struct cxgb4_range ddp; 336 struct cxgb4_range iscsi; 337 struct cxgb4_range stag; 338 struct cxgb4_range rq; 339 struct cxgb4_range srq; 340 struct cxgb4_range pbl; 341 struct cxgb4_range qp; 342 struct cxgb4_range cq; 343 struct cxgb4_range ocq; 344 struct cxgb4_range key; 345 unsigned int ncrypto_fc; 346 struct cxgb4_range ppod_edram; 347 }; 348 349 struct chcr_stats_debug { 350 atomic_t cipher_rqst; 351 atomic_t digest_rqst; 352 atomic_t aead_rqst; 353 atomic_t complete; 354 atomic_t error; 355 atomic_t fallback; 356 atomic_t ipsec_cnt; 357 atomic_t tls_pdu_tx; 358 atomic_t tls_pdu_rx; 359 atomic_t tls_key; 360 }; 361 362 #define OCQ_WIN_OFFSET(pdev, vres) \ 363 (pci_resource_len((pdev), 2) - roundup_pow_of_two((vres)->ocq.size)) 364 365 /* 366 * Block of information the LLD provides to ULDs attaching to a device. 367 */ 368 struct cxgb4_lld_info { 369 struct pci_dev *pdev; /* associated PCI device */ 370 struct l2t_data *l2t; /* L2 table */ 371 struct tid_info *tids; /* TID table */ 372 struct net_device **ports; /* device ports */ 373 const struct cxgb4_virt_res *vr; /* assorted HW resources */ 374 const unsigned short *mtus; /* MTU table */ 375 const unsigned short *rxq_ids; /* the ULD's Rx queue ids */ 376 const unsigned short *ciq_ids; /* the ULD's concentrator IQ ids */ 377 unsigned short nrxq; /* # of Rx queues */ 378 unsigned short ntxq; /* # of Tx queues */ 379 unsigned short nciq; /* # of concentrator IQ */ 380 unsigned char nchan:4; /* # of channels */ 381 unsigned char nports:4; /* # of ports */ 382 unsigned char wr_cred; /* WR 16-byte credits */ 383 unsigned char adapter_type; /* type of adapter */ 384 unsigned char fw_api_ver; /* FW API version */ 385 unsigned char crypto; /* crypto support */ 386 unsigned int fw_vers; /* FW version */ 387 unsigned int iscsi_iolen; /* iSCSI max I/O length */ 388 unsigned int cclk_ps; /* Core clock period in psec */ 389 unsigned short udb_density; /* # of user DB/page */ 390 unsigned short ucq_density; /* # of user CQs/page */ 391 unsigned int sge_host_page_size; /* SGE host page size */ 392 unsigned short filt_mode; /* filter optional components */ 393 unsigned short tx_modq[NCHAN]; /* maps each tx channel to a */ 394 /* scheduler queue */ 395 void __iomem *gts_reg; /* address of GTS register */ 396 void __iomem *db_reg; /* address of kernel doorbell */ 397 int dbfifo_int_thresh; /* doorbell fifo int threshold */ 398 unsigned int sge_ingpadboundary; /* SGE ingress padding boundary */ 399 unsigned int sge_egrstatuspagesize; /* SGE egress status page size */ 400 unsigned int sge_pktshift; /* Padding between CPL and */ 401 /* packet data */ 402 unsigned int pf; /* Physical Function we're using */ 403 bool enable_fw_ofld_conn; /* Enable connection through fw */ 404 /* WR */ 405 unsigned int max_ordird_qp; /* Max ORD/IRD depth per RDMA QP */ 406 unsigned int max_ird_adapter; /* Max IRD memory per adapter */ 407 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 408 unsigned int iscsi_tagmask; /* iscsi ddp tag mask */ 409 unsigned int iscsi_pgsz_order; /* iscsi ddp page size orders */ 410 unsigned int iscsi_llimit; /* chip's iscsi region llimit */ 411 unsigned int ulp_crypto; /* crypto lookaside support */ 412 void **iscsi_ppm; /* iscsi page pod manager */ 413 int nodeid; /* device numa node id */ 414 bool fr_nsmr_tpte_wr_support; /* FW supports FR_NSMR_TPTE_WR */ 415 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */ 416 bool write_cmpl_support; /* FW supports WRITE_CMPL WR */ 417 }; 418 419 struct cxgb4_uld_info { 420 char name[IFNAMSIZ]; 421 void *handle; 422 unsigned int nrxq; 423 unsigned int rxq_size; 424 unsigned int ntxq; 425 bool ciq; 426 bool lro; 427 void *(*add)(const struct cxgb4_lld_info *p); 428 int (*rx_handler)(void *handle, const __be64 *rsp, 429 const struct pkt_gl *gl); 430 int (*state_change)(void *handle, enum cxgb4_state new_state); 431 int (*control)(void *handle, enum cxgb4_control control, ...); 432 int (*lro_rx_handler)(void *handle, const __be64 *rsp, 433 const struct pkt_gl *gl, 434 struct t4_lro_mgr *lro_mgr, 435 struct napi_struct *napi); 436 void (*lro_flush)(struct t4_lro_mgr *); 437 int (*tx_handler)(struct sk_buff *skb, struct net_device *dev); 438 }; 439 440 void cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p); 441 int cxgb4_unregister_uld(enum cxgb4_uld type); 442 int cxgb4_ofld_send(struct net_device *dev, struct sk_buff *skb); 443 int cxgb4_immdata_send(struct net_device *dev, unsigned int idx, 444 const void *src, unsigned int len); 445 int cxgb4_crypto_send(struct net_device *dev, struct sk_buff *skb); 446 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo); 447 unsigned int cxgb4_port_chan(const struct net_device *dev); 448 unsigned int cxgb4_port_e2cchan(const struct net_device *dev); 449 unsigned int cxgb4_port_viid(const struct net_device *dev); 450 unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid); 451 unsigned int cxgb4_port_idx(const struct net_device *dev); 452 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu, 453 unsigned int *idx); 454 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus, 455 unsigned short header_size, 456 unsigned short data_size_max, 457 unsigned short data_size_align, 458 unsigned int *mtu_idxp); 459 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4, 460 struct tp_tcp_stats *v6); 461 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask, 462 const unsigned int *pgsz_order); 463 struct sk_buff *cxgb4_pktgl_to_skb(const struct pkt_gl *gl, 464 unsigned int skb_len, unsigned int pull_len); 465 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, u16 size); 466 int cxgb4_flush_eq_cache(struct net_device *dev); 467 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte); 468 u64 cxgb4_read_sge_timestamp(struct net_device *dev); 469 470 enum cxgb4_bar2_qtype { CXGB4_BAR2_QTYPE_EGRESS, CXGB4_BAR2_QTYPE_INGRESS }; 471 int cxgb4_bar2_sge_qregs(struct net_device *dev, 472 unsigned int qid, 473 enum cxgb4_bar2_qtype qtype, 474 int user, 475 u64 *pbar2_qoffset, 476 unsigned int *pbar2_qid); 477 478 #endif /* !__CXGB4_ULD_H */ 479