1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mmc/mmc-controller.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MMC Controller Generic Binding 8 9maintainers: 10 - Ulf Hansson <ulf.hansson@linaro.org> 11 12description: | 13 These properties are common to multiple MMC host controllers. Any host 14 that requires the respective functionality should implement them using 15 these definitions. 16 17properties: 18 $nodename: 19 pattern: "^mmc(@.*)?$" 20 21 "#address-cells": 22 const: 1 23 description: | 24 The cell is the slot ID if a function subnode is used. 25 26 "#size-cells": 27 const: 0 28 29 # Card Detection. 30 # If none of these properties are supplied, the host native card 31 # detect will be used. Only one of them should be provided. 32 33 broken-cd: 34 $ref: /schemas/types.yaml#/definitions/flag 35 description: 36 There is no card detection available; polling must be used. 37 38 cd-gpios: 39 description: 40 The card detection will be done using the GPIO provided. 41 42 non-removable: 43 $ref: /schemas/types.yaml#/definitions/flag 44 description: 45 Non-removable slot (like eMMC); assume always present. 46 47 # *NOTE* on CD and WP polarity. To use common for all SD/MMC host 48 # controllers line polarity properties, we have to fix the meaning 49 # of the "normal" and "inverted" line levels. We choose to follow 50 # the SDHCI standard, which specifies both those lines as "active 51 # low." Therefore, using the "cd-inverted" property means, that the 52 # CD line is active high, i.e. it is high, when a card is 53 # inserted. Similar logic applies to the "wp-inverted" property. 54 # 55 # CD and WP lines can be implemented on the hardware in one of two 56 # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or 57 # as dedicated pins. Polarity of dedicated pins can be specified, 58 # using *-inverted properties. GPIO polarity can also be specified 59 # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the 60 # latter case. We choose to use the XOR logic for GPIO CD and WP 61 # lines. This means, the two properties are "superimposed," for 62 # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the 63 # respective *-inverted property property results in a 64 # double-inversion and actually means the "normal" line polarity is 65 # in effect. 66 wp-inverted: 67 $ref: /schemas/types.yaml#/definitions/flag 68 description: 69 The Write Protect line polarity is inverted. 70 71 cd-inverted: 72 $ref: /schemas/types.yaml#/definitions/flag 73 description: 74 The CD line polarity is inverted. 75 76 # Other properties 77 78 bus-width: 79 description: 80 Number of data lines. 81 $ref: /schemas/types.yaml#/definitions/uint32 82 enum: [1, 4, 8] 83 default: 1 84 85 max-frequency: 86 description: 87 Maximum operating frequency of the bus. 88 $ref: /schemas/types.yaml#/definitions/uint32 89 minimum: 400000 90 maximum: 200000000 91 92 disable-wp: 93 $ref: /schemas/types.yaml#/definitions/flag 94 description: 95 When set, no physical write-protect line is present. This 96 property should only be specified when the controller has a 97 dedicated write-protect detection logic. If a GPIO is always used 98 for the write-protect detection logic, it is sufficient to not 99 specify the wp-gpios property in the absence of a write-protect 100 line. Not used in combination with eMMC or SDIO. 101 102 wp-gpios: 103 description: 104 GPIO to use for the write-protect detection. 105 106 cd-debounce-delay-ms: 107 description: 108 Set delay time before detecting card after card insert 109 interrupt. 110 111 no-1-8-v: 112 $ref: /schemas/types.yaml#/definitions/flag 113 description: 114 When specified, denotes that 1.8V card voltage is not supported 115 on this system, even if the controller claims it. 116 117 cap-sd-highspeed: 118 $ref: /schemas/types.yaml#/definitions/flag 119 description: 120 SD high-speed timing is supported. 121 122 cap-mmc-highspeed: 123 $ref: /schemas/types.yaml#/definitions/flag 124 description: 125 MMC high-speed timing is supported. 126 127 sd-uhs-sdr12: 128 $ref: /schemas/types.yaml#/definitions/flag 129 description: 130 SD UHS SDR12 speed is supported. 131 132 sd-uhs-sdr25: 133 $ref: /schemas/types.yaml#/definitions/flag 134 description: 135 SD UHS SDR25 speed is supported. 136 137 sd-uhs-sdr50: 138 $ref: /schemas/types.yaml#/definitions/flag 139 description: 140 SD UHS SDR50 speed is supported. 141 142 sd-uhs-sdr104: 143 $ref: /schemas/types.yaml#/definitions/flag 144 description: 145 SD UHS SDR104 speed is supported. 146 147 sd-uhs-ddr50: 148 $ref: /schemas/types.yaml#/definitions/flag 149 description: 150 SD UHS DDR50 speed is supported. 151 152 cap-power-off-card: 153 $ref: /schemas/types.yaml#/definitions/flag 154 description: 155 Powering off the card is safe. 156 157 cap-mmc-hw-reset: 158 $ref: /schemas/types.yaml#/definitions/flag 159 description: 160 eMMC hardware reset is supported 161 162 cap-sdio-irq: 163 $ref: /schemas/types.yaml#/definitions/flag 164 description: 165 enable SDIO IRQ signalling on this interface 166 167 full-pwr-cycle: 168 $ref: /schemas/types.yaml#/definitions/flag 169 description: 170 Full power cycle of the card is supported. 171 172 mmc-ddr-1_2v: 173 $ref: /schemas/types.yaml#/definitions/flag 174 description: 175 eMMC high-speed DDR mode (1.2V I/O) is supported. 176 177 mmc-ddr-1_8v: 178 $ref: /schemas/types.yaml#/definitions/flag 179 description: 180 eMMC high-speed DDR mode (1.8V I/O) is supported. 181 182 mmc-ddr-3_3v: 183 $ref: /schemas/types.yaml#/definitions/flag 184 description: 185 eMMC high-speed DDR mode (3.3V I/O) is supported. 186 187 mmc-hs200-1_2v: 188 $ref: /schemas/types.yaml#/definitions/flag 189 description: 190 eMMC HS200 mode (1.2V I/O) is supported. 191 192 mmc-hs200-1_8v: 193 $ref: /schemas/types.yaml#/definitions/flag 194 description: 195 eMMC HS200 mode (1.8V I/O) is supported. 196 197 mmc-hs400-1_2v: 198 $ref: /schemas/types.yaml#/definitions/flag 199 description: 200 eMMC HS400 mode (1.2V I/O) is supported. 201 202 mmc-hs400-1_8v: 203 $ref: /schemas/types.yaml#/definitions/flag 204 description: 205 eMMC HS400 mode (1.8V I/O) is supported. 206 207 mmc-hs400-enhanced-strobe: 208 $ref: /schemas/types.yaml#/definitions/flag 209 description: 210 eMMC HS400 enhanced strobe mode is supported 211 212 dsr: 213 description: 214 Value the card Driver Stage Register (DSR) should be programmed 215 with. 216 $ref: /schemas/types.yaml#/definitions/uint32 217 minimum: 0 218 maximum: 0xffff 219 220 no-sdio: 221 $ref: /schemas/types.yaml#/definitions/flag 222 description: 223 Controller is limited to send SDIO commands during 224 initialization. 225 226 no-sd: 227 $ref: /schemas/types.yaml#/definitions/flag 228 description: 229 Controller is limited to send SD commands during initialization. 230 231 no-mmc: 232 $ref: /schemas/types.yaml#/definitions/flag 233 description: 234 Controller is limited to send MMC commands during 235 initialization. 236 237 fixed-emmc-driver-type: 238 description: 239 For non-removable eMMC, enforce this driver type. The value is 240 the driver type as specified in the eMMC specification (table 241 206 in spec version 5.1) 242 $ref: /schemas/types.yaml#/definitions/uint32 243 minimum: 0 244 maximum: 4 245 246 post-power-on-delay-ms: 247 description: 248 It was invented for MMC pwrseq-simple which could be referred to 249 mmc-pwrseq-simple.txt. But now it\'s reused as a tunable delay 250 waiting for I/O signalling and card power supply to be stable, 251 regardless of whether pwrseq-simple is used. Default to 10ms if 252 no available. 253 $ref: /schemas/types.yaml#/definitions/uint32 254 default: 10 255 256 supports-cqe: 257 $ref: /schemas/types.yaml#/definitions/flag 258 description: 259 The presence of this property indicates that the corresponding 260 MMC host controller supports HW command queue feature. 261 262 disable-cqe-dcmd: 263 $ref: /schemas/types.yaml#/definitions/flag 264 description: 265 The presence of this property indicates that the MMC 266 controller\'s command queue engine (CQE) does not support direct 267 commands (DCMDs). 268 269 keep-power-in-suspend: 270 $ref: /schemas/types.yaml#/definitions/flag 271 description: 272 SDIO only. Preserves card power during a suspend/resume cycle. 273 274 # Deprecated: enable-sdio-wakeup 275 wakeup-source: 276 $ref: /schemas/types.yaml#/definitions/flag 277 description: 278 SDIO only. Enables wake up of host system on SDIO IRQ assertion. 279 280 vmmc-supply: 281 description: 282 Supply for the card power 283 284 vqmmc-supply: 285 description: 286 Supply for the bus IO line power 287 288 mmc-pwrseq: 289 $ref: /schemas/types.yaml#/definitions/phandle 290 description: 291 System-on-Chip designs may specify a specific MMC power 292 sequence. To successfully detect an (e)MMC/SD/SDIO card, that 293 power sequence must be maintained while initializing the card. 294 295patternProperties: 296 "^.*@[0-9]+$": 297 type: object 298 description: | 299 On embedded systems the cards connected to a host may need 300 additional properties. These can be specified in subnodes to the 301 host controller node. The subnodes are identified by the 302 standard \'reg\' property. Which information exactly can be 303 specified depends on the bindings for the SDIO function driver 304 for the subnode, as specified by the compatible string. 305 306 properties: 307 compatible: 308 description: | 309 Name of SDIO function following generic names recommended 310 practice 311 312 reg: 313 items: 314 - minimum: 0 315 maximum: 7 316 description: 317 Must contain the SDIO function number of the function this 318 subnode describes. A value of 0 denotes the memory SD 319 function, values from 1 to 7 denote the SDIO functions. 320 321 broken-hpi: 322 $ref: /schemas/types.yaml#/definitions/flag 323 description: 324 Use this to indicate that the mmc-card has a broken hpi 325 implementation, and that hpi should not be used. 326 327 required: 328 - reg 329 330 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$": 331 $ref: /schemas/types.yaml#/definitions/uint32-array 332 333 minItems: 2 334 maxItems: 2 335 items: 336 minimum: 0 337 maximum: 359 338 description: 339 Set the clock (phase) delays which are to be configured in the 340 controller while switching to particular speed mode. These values 341 are in pair of degrees. 342 343dependencies: 344 cd-debounce-delay-ms: [ cd-gpios ] 345 fixed-emmc-driver-type: [ non-removable ] 346 347examples: 348 - | 349 mmc@ab000000 { 350 compatible = "sdhci"; 351 reg = <0xab000000 0x200>; 352 interrupts = <23>; 353 bus-width = <4>; 354 cd-gpios = <&gpio 69 0>; 355 cd-inverted; 356 wp-gpios = <&gpio 70 0>; 357 max-frequency = <50000000>; 358 keep-power-in-suspend; 359 wakeup-source; 360 mmc-pwrseq = <&sdhci0_pwrseq>; 361 clk-phase-sd-hs = <63>, <72>; 362 }; 363 364 - | 365 mmc3: mmc@1c12000 { 366 #address-cells = <1>; 367 #size-cells = <0>; 368 reg = <0x1c12000 0x200>; 369 pinctrl-names = "default"; 370 pinctrl-0 = <&mmc3_pins_a>; 371 vmmc-supply = <®_vmmc3>; 372 bus-width = <4>; 373 non-removable; 374 mmc-pwrseq = <&sdhci0_pwrseq>; 375 376 brcmf: bcrmf@1 { 377 reg = <1>; 378 compatible = "brcm,bcm43xx-fmac"; 379 interrupt-parent = <&pio>; 380 interrupts = <10 8>; 381 interrupt-names = "host-wake"; 382 }; 383 }; 384