1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * i.MX8 NWL MIPI DSI host driver 4 * 5 * Copyright (C) 2017 NXP 6 * Copyright (C) 2020 Purism SPC 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/irq.h> 12 #include <linux/math64.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/mux/consumer.h> 16 #include <linux/of.h> 17 #include <linux/of_platform.h> 18 #include <linux/phy/phy.h> 19 #include <linux/regmap.h> 20 #include <linux/reset.h> 21 #include <linux/sys_soc.h> 22 #include <linux/time64.h> 23 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_mipi_dsi.h> 26 #include <drm/drm_of.h> 27 #include <drm/drm_panel.h> 28 #include <drm/drm_print.h> 29 30 #include <video/mipi_display.h> 31 32 #include "nwl-dsi.h" 33 34 #define DRV_NAME "nwl-dsi" 35 36 /* i.MX8 NWL quirks */ 37 /* i.MX8MQ errata E11418 */ 38 #define E11418_HS_MODE_QUIRK BIT(0) 39 40 #define NWL_DSI_MIPI_FIFO_TIMEOUT msecs_to_jiffies(500) 41 42 enum transfer_direction { 43 DSI_PACKET_SEND, 44 DSI_PACKET_RECEIVE, 45 }; 46 47 #define NWL_DSI_ENDPOINT_LCDIF 0 48 #define NWL_DSI_ENDPOINT_DCSS 1 49 50 struct nwl_dsi_plat_clk_config { 51 const char *id; 52 struct clk *clk; 53 bool present; 54 }; 55 56 struct nwl_dsi_transfer { 57 const struct mipi_dsi_msg *msg; 58 struct mipi_dsi_packet packet; 59 struct completion completed; 60 61 int status; /* status of transmission */ 62 enum transfer_direction direction; 63 bool need_bta; 64 u8 cmd; 65 u16 rx_word_count; 66 size_t tx_len; /* in bytes */ 67 size_t rx_len; /* in bytes */ 68 }; 69 70 struct nwl_dsi { 71 struct drm_bridge bridge; 72 struct mipi_dsi_host dsi_host; 73 struct drm_bridge *panel_bridge; 74 struct device *dev; 75 struct phy *phy; 76 union phy_configure_opts phy_cfg; 77 unsigned int quirks; 78 79 struct regmap *regmap; 80 int irq; 81 /* 82 * The DSI host controller needs this reset sequence according to NWL: 83 * 1. Deassert pclk reset to get access to DSI regs 84 * 2. Configure DSI Host and DPHY and enable DPHY 85 * 3. Deassert ESC and BYTE resets to allow host TX operations) 86 * 4. Send DSI cmds to configure peripheral (handled by panel drv) 87 * 5. Deassert DPI reset so DPI receives pixels and starts sending 88 * DSI data 89 * 90 * TODO: Since panel_bridges do their DSI setup in enable we 91 * currently have 4. and 5. swapped. 92 */ 93 struct reset_control *rst_byte; 94 struct reset_control *rst_esc; 95 struct reset_control *rst_dpi; 96 struct reset_control *rst_pclk; 97 struct mux_control *mux; 98 99 /* DSI clocks */ 100 struct clk *phy_ref_clk; 101 struct clk *rx_esc_clk; 102 struct clk *tx_esc_clk; 103 struct clk *core_clk; 104 /* 105 * hardware bug: the i.MX8MQ needs this clock on during reset 106 * even when not using LCDIF. 107 */ 108 struct clk *lcdif_clk; 109 110 /* dsi lanes */ 111 u32 lanes; 112 enum mipi_dsi_pixel_format format; 113 struct drm_display_mode mode; 114 unsigned long dsi_mode_flags; 115 int error; 116 117 struct nwl_dsi_transfer *xfer; 118 }; 119 120 static const struct regmap_config nwl_dsi_regmap_config = { 121 .reg_bits = 16, 122 .val_bits = 32, 123 .reg_stride = 4, 124 .max_register = NWL_DSI_IRQ_MASK2, 125 .name = DRV_NAME, 126 }; 127 128 static inline struct nwl_dsi *bridge_to_dsi(struct drm_bridge *bridge) 129 { 130 return container_of(bridge, struct nwl_dsi, bridge); 131 } 132 133 static int nwl_dsi_clear_error(struct nwl_dsi *dsi) 134 { 135 int ret = dsi->error; 136 137 dsi->error = 0; 138 return ret; 139 } 140 141 static void nwl_dsi_write(struct nwl_dsi *dsi, unsigned int reg, u32 val) 142 { 143 int ret; 144 145 if (dsi->error) 146 return; 147 148 ret = regmap_write(dsi->regmap, reg, val); 149 if (ret < 0) { 150 DRM_DEV_ERROR(dsi->dev, 151 "Failed to write NWL DSI reg 0x%x: %d\n", reg, 152 ret); 153 dsi->error = ret; 154 } 155 } 156 157 static u32 nwl_dsi_read(struct nwl_dsi *dsi, u32 reg) 158 { 159 unsigned int val; 160 int ret; 161 162 if (dsi->error) 163 return 0; 164 165 ret = regmap_read(dsi->regmap, reg, &val); 166 if (ret < 0) { 167 DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n", 168 reg, ret); 169 dsi->error = ret; 170 } 171 return val; 172 } 173 174 static int nwl_dsi_get_dpi_pixel_format(enum mipi_dsi_pixel_format format) 175 { 176 switch (format) { 177 case MIPI_DSI_FMT_RGB565: 178 return NWL_DSI_PIXEL_FORMAT_16; 179 case MIPI_DSI_FMT_RGB666: 180 return NWL_DSI_PIXEL_FORMAT_18L; 181 case MIPI_DSI_FMT_RGB666_PACKED: 182 return NWL_DSI_PIXEL_FORMAT_18; 183 case MIPI_DSI_FMT_RGB888: 184 return NWL_DSI_PIXEL_FORMAT_24; 185 default: 186 return -EINVAL; 187 } 188 } 189 190 /* 191 * ps2bc - Picoseconds to byte clock cycles 192 */ 193 static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps) 194 { 195 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 196 197 return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp, 198 dsi->lanes * 8 * NSEC_PER_SEC); 199 } 200 201 /* 202 * ui2bc - UI time periods to byte clock cycles 203 */ 204 static u32 ui2bc(struct nwl_dsi *dsi, unsigned long long ui) 205 { 206 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 207 208 return DIV64_U64_ROUND_UP(ui * dsi->lanes, 209 dsi->mode.clock * 1000 * bpp); 210 } 211 212 /* 213 * us2bc - micro seconds to lp clock cycles 214 */ 215 static u32 us2lp(u32 lp_clk_rate, unsigned long us) 216 { 217 return DIV_ROUND_UP(us * lp_clk_rate, USEC_PER_SEC); 218 } 219 220 static int nwl_dsi_config_host(struct nwl_dsi *dsi) 221 { 222 u32 cycles; 223 struct phy_configure_opts_mipi_dphy *cfg = &dsi->phy_cfg.mipi_dphy; 224 225 if (dsi->lanes < 1 || dsi->lanes > 4) 226 return -EINVAL; 227 228 DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes); 229 nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1); 230 231 if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 232 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x01); 233 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01); 234 } else { 235 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x00); 236 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x00); 237 } 238 239 /* values in byte clock cycles */ 240 cycles = ui2bc(dsi, cfg->clk_pre); 241 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles); 242 nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles); 243 cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero); 244 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles); 245 cycles += ui2bc(dsi, cfg->clk_pre); 246 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles); 247 nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles); 248 cycles = ps2bc(dsi, cfg->hs_exit); 249 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles); 250 nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles); 251 252 nwl_dsi_write(dsi, NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP, 0x01); 253 nwl_dsi_write(dsi, NWL_DSI_CFG_HTX_TO_COUNT, 0x00); 254 nwl_dsi_write(dsi, NWL_DSI_CFG_LRX_H_TO_COUNT, 0x00); 255 nwl_dsi_write(dsi, NWL_DSI_CFG_BTA_H_TO_COUNT, 0x00); 256 /* In LP clock cycles */ 257 cycles = us2lp(cfg->lp_clk_rate, cfg->wakeup); 258 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_twakeup: 0x%x\n", cycles); 259 nwl_dsi_write(dsi, NWL_DSI_CFG_TWAKEUP, cycles); 260 261 return nwl_dsi_clear_error(dsi); 262 } 263 264 static int nwl_dsi_config_dpi(struct nwl_dsi *dsi) 265 { 266 u32 mode; 267 int color_format; 268 bool burst_mode; 269 int hfront_porch, hback_porch, vfront_porch, vback_porch; 270 int hsync_len, vsync_len; 271 272 hfront_porch = dsi->mode.hsync_start - dsi->mode.hdisplay; 273 hsync_len = dsi->mode.hsync_end - dsi->mode.hsync_start; 274 hback_porch = dsi->mode.htotal - dsi->mode.hsync_end; 275 276 vfront_porch = dsi->mode.vsync_start - dsi->mode.vdisplay; 277 vsync_len = dsi->mode.vsync_end - dsi->mode.vsync_start; 278 vback_porch = dsi->mode.vtotal - dsi->mode.vsync_end; 279 280 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hfront_porch = %d\n", hfront_porch); 281 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hback_porch = %d\n", hback_porch); 282 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hsync_len = %d\n", hsync_len); 283 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hdisplay = %d\n", dsi->mode.hdisplay); 284 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vfront_porch = %d\n", vfront_porch); 285 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vback_porch = %d\n", vback_porch); 286 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vsync_len = %d\n", vsync_len); 287 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vactive = %d\n", dsi->mode.vdisplay); 288 DRM_DEV_DEBUG_DRIVER(dsi->dev, "clock = %d kHz\n", dsi->mode.clock); 289 290 color_format = nwl_dsi_get_dpi_pixel_format(dsi->format); 291 if (color_format < 0) { 292 DRM_DEV_ERROR(dsi->dev, "Invalid color format 0x%x\n", 293 dsi->format); 294 return color_format; 295 } 296 DRM_DEV_DEBUG_DRIVER(dsi->dev, "pixel fmt = %d\n", dsi->format); 297 298 nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT); 299 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format); 300 /* 301 * Adjusting input polarity based on the video mode results in 302 * a black screen so always pick active low: 303 */ 304 nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY, 305 NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW); 306 nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY, 307 NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW); 308 309 burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) && 310 !(dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE); 311 312 if (burst_mode) { 313 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, NWL_DSI_VM_BURST_MODE); 314 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 256); 315 } else { 316 mode = ((dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) ? 317 NWL_DSI_VM_BURST_MODE_WITH_SYNC_PULSES : 318 NWL_DSI_VM_NON_BURST_MODE_WITH_SYNC_EVENTS); 319 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, mode); 320 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 321 dsi->mode.hdisplay); 322 } 323 324 nwl_dsi_write(dsi, NWL_DSI_HFP, hfront_porch); 325 nwl_dsi_write(dsi, NWL_DSI_HBP, hback_porch); 326 nwl_dsi_write(dsi, NWL_DSI_HSA, hsync_len); 327 328 nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0); 329 nwl_dsi_write(dsi, NWL_DSI_BLLP_MODE, 0x1); 330 nwl_dsi_write(dsi, NWL_DSI_USE_NULL_PKT_BLLP, 0x0); 331 nwl_dsi_write(dsi, NWL_DSI_VC, 0x0); 332 333 nwl_dsi_write(dsi, NWL_DSI_PIXEL_PAYLOAD_SIZE, dsi->mode.hdisplay); 334 nwl_dsi_write(dsi, NWL_DSI_VACTIVE, dsi->mode.vdisplay - 1); 335 nwl_dsi_write(dsi, NWL_DSI_VBP, vback_porch); 336 nwl_dsi_write(dsi, NWL_DSI_VFP, vfront_porch); 337 338 return nwl_dsi_clear_error(dsi); 339 } 340 341 static int nwl_dsi_init_interrupts(struct nwl_dsi *dsi) 342 { 343 u32 irq_enable; 344 345 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, 0xffffffff); 346 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK2, 0x7); 347 348 irq_enable = ~(u32)(NWL_DSI_TX_PKT_DONE_MASK | 349 NWL_DSI_RX_PKT_HDR_RCVD_MASK | 350 NWL_DSI_TX_FIFO_OVFLW_MASK | 351 NWL_DSI_HS_TX_TIMEOUT_MASK); 352 353 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, irq_enable); 354 355 return nwl_dsi_clear_error(dsi); 356 } 357 358 static int nwl_dsi_host_attach(struct mipi_dsi_host *dsi_host, 359 struct mipi_dsi_device *device) 360 { 361 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host); 362 struct device *dev = dsi->dev; 363 364 DRM_DEV_INFO(dev, "lanes=%u, format=0x%x flags=0x%lx\n", device->lanes, 365 device->format, device->mode_flags); 366 367 if (device->lanes < 1 || device->lanes > 4) 368 return -EINVAL; 369 370 dsi->lanes = device->lanes; 371 dsi->format = device->format; 372 dsi->dsi_mode_flags = device->mode_flags; 373 374 return 0; 375 } 376 377 static bool nwl_dsi_read_packet(struct nwl_dsi *dsi, u32 status) 378 { 379 struct device *dev = dsi->dev; 380 struct nwl_dsi_transfer *xfer = dsi->xfer; 381 int err; 382 u8 *payload = xfer->msg->rx_buf; 383 u32 val; 384 u16 word_count; 385 u8 channel; 386 u8 data_type; 387 388 xfer->status = 0; 389 390 if (xfer->rx_word_count == 0) { 391 if (!(status & NWL_DSI_RX_PKT_HDR_RCVD)) 392 return false; 393 /* Get the RX header and parse it */ 394 val = nwl_dsi_read(dsi, NWL_DSI_RX_PKT_HEADER); 395 err = nwl_dsi_clear_error(dsi); 396 if (err) 397 xfer->status = err; 398 word_count = NWL_DSI_WC(val); 399 channel = NWL_DSI_RX_VC(val); 400 data_type = NWL_DSI_RX_DT(val); 401 402 if (channel != xfer->msg->channel) { 403 DRM_DEV_ERROR(dev, 404 "[%02X] Channel mismatch (%u != %u)\n", 405 xfer->cmd, channel, xfer->msg->channel); 406 xfer->status = -EINVAL; 407 return true; 408 } 409 410 switch (data_type) { 411 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 412 fallthrough; 413 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 414 if (xfer->msg->rx_len > 1) { 415 /* read second byte */ 416 payload[1] = word_count >> 8; 417 ++xfer->rx_len; 418 } 419 fallthrough; 420 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 421 fallthrough; 422 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 423 if (xfer->msg->rx_len > 0) { 424 /* read first byte */ 425 payload[0] = word_count & 0xff; 426 ++xfer->rx_len; 427 } 428 xfer->status = xfer->rx_len; 429 return true; 430 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 431 word_count &= 0xff; 432 DRM_DEV_ERROR(dev, "[%02X] DSI error report: 0x%02x\n", 433 xfer->cmd, word_count); 434 xfer->status = -EPROTO; 435 return true; 436 } 437 438 if (word_count > xfer->msg->rx_len) { 439 DRM_DEV_ERROR(dev, 440 "[%02X] Receive buffer too small: %zu (< %u)\n", 441 xfer->cmd, xfer->msg->rx_len, word_count); 442 xfer->status = -EINVAL; 443 return true; 444 } 445 446 xfer->rx_word_count = word_count; 447 } else { 448 /* Set word_count from previous header read */ 449 word_count = xfer->rx_word_count; 450 } 451 452 /* If RX payload is not yet received, wait for it */ 453 if (!(status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)) 454 return false; 455 456 /* Read the RX payload */ 457 while (word_count >= 4) { 458 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD); 459 payload[0] = (val >> 0) & 0xff; 460 payload[1] = (val >> 8) & 0xff; 461 payload[2] = (val >> 16) & 0xff; 462 payload[3] = (val >> 24) & 0xff; 463 payload += 4; 464 xfer->rx_len += 4; 465 word_count -= 4; 466 } 467 468 if (word_count > 0) { 469 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD); 470 switch (word_count) { 471 case 3: 472 payload[2] = (val >> 16) & 0xff; 473 ++xfer->rx_len; 474 fallthrough; 475 case 2: 476 payload[1] = (val >> 8) & 0xff; 477 ++xfer->rx_len; 478 fallthrough; 479 case 1: 480 payload[0] = (val >> 0) & 0xff; 481 ++xfer->rx_len; 482 break; 483 } 484 } 485 486 xfer->status = xfer->rx_len; 487 err = nwl_dsi_clear_error(dsi); 488 if (err) 489 xfer->status = err; 490 491 return true; 492 } 493 494 static void nwl_dsi_finish_transmission(struct nwl_dsi *dsi, u32 status) 495 { 496 struct nwl_dsi_transfer *xfer = dsi->xfer; 497 bool end_packet = false; 498 499 if (!xfer) 500 return; 501 502 if (xfer->direction == DSI_PACKET_SEND && 503 status & NWL_DSI_TX_PKT_DONE) { 504 xfer->status = xfer->tx_len; 505 end_packet = true; 506 } else if (status & NWL_DSI_DPHY_DIRECTION && 507 ((status & (NWL_DSI_RX_PKT_HDR_RCVD | 508 NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)))) { 509 end_packet = nwl_dsi_read_packet(dsi, status); 510 } 511 512 if (end_packet) 513 complete(&xfer->completed); 514 } 515 516 static void nwl_dsi_begin_transmission(struct nwl_dsi *dsi) 517 { 518 struct nwl_dsi_transfer *xfer = dsi->xfer; 519 struct mipi_dsi_packet *pkt = &xfer->packet; 520 const u8 *payload; 521 size_t length; 522 u16 word_count; 523 u8 hs_mode; 524 u32 val; 525 u32 hs_workaround = 0; 526 527 /* Send the payload, if any */ 528 length = pkt->payload_length; 529 payload = pkt->payload; 530 531 while (length >= 4) { 532 val = *(u32 *)payload; 533 hs_workaround |= !(val & 0xFFFF00); 534 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val); 535 payload += 4; 536 length -= 4; 537 } 538 /* Send the rest of the payload */ 539 val = 0; 540 switch (length) { 541 case 3: 542 val |= payload[2] << 16; 543 fallthrough; 544 case 2: 545 val |= payload[1] << 8; 546 hs_workaround |= !(val & 0xFFFF00); 547 fallthrough; 548 case 1: 549 val |= payload[0]; 550 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val); 551 break; 552 } 553 xfer->tx_len = pkt->payload_length; 554 555 /* 556 * Send the header 557 * header[0] = Virtual Channel + Data Type 558 * header[1] = Word Count LSB (LP) or first param (SP) 559 * header[2] = Word Count MSB (LP) or second param (SP) 560 */ 561 word_count = pkt->header[1] | (pkt->header[2] << 8); 562 if (hs_workaround && (dsi->quirks & E11418_HS_MODE_QUIRK)) { 563 DRM_DEV_DEBUG_DRIVER(dsi->dev, 564 "Using hs mode workaround for cmd 0x%x\n", 565 xfer->cmd); 566 hs_mode = 1; 567 } else { 568 hs_mode = (xfer->msg->flags & MIPI_DSI_MSG_USE_LPM) ? 0 : 1; 569 } 570 val = NWL_DSI_WC(word_count) | NWL_DSI_TX_VC(xfer->msg->channel) | 571 NWL_DSI_TX_DT(xfer->msg->type) | NWL_DSI_HS_SEL(hs_mode) | 572 NWL_DSI_BTA_TX(xfer->need_bta); 573 nwl_dsi_write(dsi, NWL_DSI_PKT_CONTROL, val); 574 575 /* Send packet command */ 576 nwl_dsi_write(dsi, NWL_DSI_SEND_PACKET, 0x1); 577 } 578 579 static ssize_t nwl_dsi_host_transfer(struct mipi_dsi_host *dsi_host, 580 const struct mipi_dsi_msg *msg) 581 { 582 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host); 583 struct nwl_dsi_transfer xfer; 584 ssize_t ret = 0; 585 586 /* Create packet to be sent */ 587 dsi->xfer = &xfer; 588 ret = mipi_dsi_create_packet(&xfer.packet, msg); 589 if (ret < 0) { 590 dsi->xfer = NULL; 591 return ret; 592 } 593 594 if ((msg->type & MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM || 595 msg->type & MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM || 596 msg->type & MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM || 597 msg->type & MIPI_DSI_DCS_READ) && 598 msg->rx_len > 0 && msg->rx_buf) 599 xfer.direction = DSI_PACKET_RECEIVE; 600 else 601 xfer.direction = DSI_PACKET_SEND; 602 603 xfer.need_bta = (xfer.direction == DSI_PACKET_RECEIVE); 604 xfer.need_bta |= (msg->flags & MIPI_DSI_MSG_REQ_ACK) ? 1 : 0; 605 xfer.msg = msg; 606 xfer.status = -ETIMEDOUT; 607 xfer.rx_word_count = 0; 608 xfer.rx_len = 0; 609 xfer.cmd = 0x00; 610 if (msg->tx_len > 0) 611 xfer.cmd = ((u8 *)(msg->tx_buf))[0]; 612 init_completion(&xfer.completed); 613 614 ret = clk_prepare_enable(dsi->rx_esc_clk); 615 if (ret < 0) { 616 DRM_DEV_ERROR(dsi->dev, "Failed to enable rx_esc clk: %zd\n", 617 ret); 618 return ret; 619 } 620 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled rx_esc clk @%lu Hz\n", 621 clk_get_rate(dsi->rx_esc_clk)); 622 623 /* Initiate the DSI packet transmision */ 624 nwl_dsi_begin_transmission(dsi); 625 626 if (!wait_for_completion_timeout(&xfer.completed, 627 NWL_DSI_MIPI_FIFO_TIMEOUT)) { 628 DRM_DEV_ERROR(dsi_host->dev, "[%02X] DSI transfer timed out\n", 629 xfer.cmd); 630 ret = -ETIMEDOUT; 631 } else { 632 ret = xfer.status; 633 } 634 635 clk_disable_unprepare(dsi->rx_esc_clk); 636 637 return ret; 638 } 639 640 static const struct mipi_dsi_host_ops nwl_dsi_host_ops = { 641 .attach = nwl_dsi_host_attach, 642 .transfer = nwl_dsi_host_transfer, 643 }; 644 645 static irqreturn_t nwl_dsi_irq_handler(int irq, void *data) 646 { 647 u32 irq_status; 648 struct nwl_dsi *dsi = data; 649 650 irq_status = nwl_dsi_read(dsi, NWL_DSI_IRQ_STATUS); 651 652 if (irq_status & NWL_DSI_TX_FIFO_OVFLW) 653 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "tx fifo overflow\n"); 654 655 if (irq_status & NWL_DSI_HS_TX_TIMEOUT) 656 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "HS tx timeout\n"); 657 658 if (irq_status & NWL_DSI_TX_PKT_DONE || 659 irq_status & NWL_DSI_RX_PKT_HDR_RCVD || 660 irq_status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD) 661 nwl_dsi_finish_transmission(dsi, irq_status); 662 663 return IRQ_HANDLED; 664 } 665 666 static int nwl_dsi_enable(struct nwl_dsi *dsi) 667 { 668 struct device *dev = dsi->dev; 669 union phy_configure_opts *phy_cfg = &dsi->phy_cfg; 670 int ret; 671 672 if (!dsi->lanes) { 673 DRM_DEV_ERROR(dev, "Need DSI lanes: %d\n", dsi->lanes); 674 return -EINVAL; 675 } 676 677 ret = phy_init(dsi->phy); 678 if (ret < 0) { 679 DRM_DEV_ERROR(dev, "Failed to init DSI phy: %d\n", ret); 680 return ret; 681 } 682 683 ret = phy_configure(dsi->phy, phy_cfg); 684 if (ret < 0) { 685 DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", ret); 686 goto uninit_phy; 687 } 688 689 ret = clk_prepare_enable(dsi->tx_esc_clk); 690 if (ret < 0) { 691 DRM_DEV_ERROR(dsi->dev, "Failed to enable tx_esc clk: %d\n", 692 ret); 693 goto uninit_phy; 694 } 695 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled tx_esc clk @%lu Hz\n", 696 clk_get_rate(dsi->tx_esc_clk)); 697 698 ret = nwl_dsi_config_host(dsi); 699 if (ret < 0) { 700 DRM_DEV_ERROR(dev, "Failed to set up DSI: %d", ret); 701 goto disable_clock; 702 } 703 704 ret = nwl_dsi_config_dpi(dsi); 705 if (ret < 0) { 706 DRM_DEV_ERROR(dev, "Failed to set up DPI: %d", ret); 707 goto disable_clock; 708 } 709 710 ret = phy_power_on(dsi->phy); 711 if (ret < 0) { 712 DRM_DEV_ERROR(dev, "Failed to power on DPHY (%d)\n", ret); 713 goto disable_clock; 714 } 715 716 ret = nwl_dsi_init_interrupts(dsi); 717 if (ret < 0) 718 goto power_off_phy; 719 720 return ret; 721 722 power_off_phy: 723 phy_power_off(dsi->phy); 724 disable_clock: 725 clk_disable_unprepare(dsi->tx_esc_clk); 726 uninit_phy: 727 phy_exit(dsi->phy); 728 729 return ret; 730 } 731 732 static int nwl_dsi_disable(struct nwl_dsi *dsi) 733 { 734 struct device *dev = dsi->dev; 735 736 DRM_DEV_DEBUG_DRIVER(dev, "Disabling clocks and phy\n"); 737 738 phy_power_off(dsi->phy); 739 phy_exit(dsi->phy); 740 741 /* Disabling the clock before the phy breaks enabling dsi again */ 742 clk_disable_unprepare(dsi->tx_esc_clk); 743 744 return 0; 745 } 746 747 static void nwl_dsi_bridge_disable(struct drm_bridge *bridge) 748 { 749 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 750 int ret; 751 752 nwl_dsi_disable(dsi); 753 754 ret = reset_control_assert(dsi->rst_dpi); 755 if (ret < 0) { 756 DRM_DEV_ERROR(dsi->dev, "Failed to assert DPI: %d\n", ret); 757 return; 758 } 759 ret = reset_control_assert(dsi->rst_byte); 760 if (ret < 0) { 761 DRM_DEV_ERROR(dsi->dev, "Failed to assert ESC: %d\n", ret); 762 return; 763 } 764 ret = reset_control_assert(dsi->rst_esc); 765 if (ret < 0) { 766 DRM_DEV_ERROR(dsi->dev, "Failed to assert BYTE: %d\n", ret); 767 return; 768 } 769 ret = reset_control_assert(dsi->rst_pclk); 770 if (ret < 0) { 771 DRM_DEV_ERROR(dsi->dev, "Failed to assert PCLK: %d\n", ret); 772 return; 773 } 774 775 clk_disable_unprepare(dsi->core_clk); 776 clk_disable_unprepare(dsi->lcdif_clk); 777 778 pm_runtime_put(dsi->dev); 779 } 780 781 static int nwl_dsi_get_dphy_params(struct nwl_dsi *dsi, 782 const struct drm_display_mode *mode, 783 union phy_configure_opts *phy_opts) 784 { 785 unsigned long rate; 786 int ret; 787 788 if (dsi->lanes < 1 || dsi->lanes > 4) 789 return -EINVAL; 790 791 /* 792 * So far the DPHY spec minimal timings work for both mixel 793 * dphy and nwl dsi host 794 */ 795 ret = phy_mipi_dphy_get_default_config(mode->clock * 1000, 796 mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes, 797 &phy_opts->mipi_dphy); 798 if (ret < 0) 799 return ret; 800 801 rate = clk_get_rate(dsi->tx_esc_clk); 802 DRM_DEV_DEBUG_DRIVER(dsi->dev, "LP clk is @%lu Hz\n", rate); 803 phy_opts->mipi_dphy.lp_clk_rate = rate; 804 805 return 0; 806 } 807 808 static bool nwl_dsi_bridge_mode_fixup(struct drm_bridge *bridge, 809 const struct drm_display_mode *mode, 810 struct drm_display_mode *adjusted_mode) 811 { 812 /* At least LCDIF + NWL needs active high sync */ 813 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 814 adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 815 816 return true; 817 } 818 819 static enum drm_mode_status 820 nwl_dsi_bridge_mode_valid(struct drm_bridge *bridge, 821 const struct drm_display_mode *mode) 822 { 823 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 824 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 825 826 if (mode->clock * bpp > 15000000 * dsi->lanes) 827 return MODE_CLOCK_HIGH; 828 829 if (mode->clock * bpp < 80000 * dsi->lanes) 830 return MODE_CLOCK_LOW; 831 832 return MODE_OK; 833 } 834 835 static void 836 nwl_dsi_bridge_mode_set(struct drm_bridge *bridge, 837 const struct drm_display_mode *mode, 838 const struct drm_display_mode *adjusted_mode) 839 { 840 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 841 struct device *dev = dsi->dev; 842 union phy_configure_opts new_cfg; 843 unsigned long phy_ref_rate; 844 int ret; 845 846 ret = nwl_dsi_get_dphy_params(dsi, adjusted_mode, &new_cfg); 847 if (ret < 0) 848 return; 849 850 /* 851 * If hs clock is unchanged, we're all good - all parameters are 852 * derived from it atm. 853 */ 854 if (new_cfg.mipi_dphy.hs_clk_rate == dsi->phy_cfg.mipi_dphy.hs_clk_rate) 855 return; 856 857 phy_ref_rate = clk_get_rate(dsi->phy_ref_clk); 858 DRM_DEV_DEBUG_DRIVER(dev, "PHY at ref rate: %lu\n", phy_ref_rate); 859 /* Save the new desired phy config */ 860 memcpy(&dsi->phy_cfg, &new_cfg, sizeof(new_cfg)); 861 862 memcpy(&dsi->mode, adjusted_mode, sizeof(dsi->mode)); 863 drm_mode_debug_printmodeline(adjusted_mode); 864 } 865 866 static void nwl_dsi_bridge_pre_enable(struct drm_bridge *bridge) 867 { 868 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 869 int ret; 870 871 pm_runtime_get_sync(dsi->dev); 872 873 if (clk_prepare_enable(dsi->lcdif_clk) < 0) 874 return; 875 if (clk_prepare_enable(dsi->core_clk) < 0) 876 return; 877 878 /* Step 1 from DSI reset-out instructions */ 879 ret = reset_control_deassert(dsi->rst_pclk); 880 if (ret < 0) { 881 DRM_DEV_ERROR(dsi->dev, "Failed to deassert PCLK: %d\n", ret); 882 return; 883 } 884 885 /* Step 2 from DSI reset-out instructions */ 886 nwl_dsi_enable(dsi); 887 888 /* Step 3 from DSI reset-out instructions */ 889 ret = reset_control_deassert(dsi->rst_esc); 890 if (ret < 0) { 891 DRM_DEV_ERROR(dsi->dev, "Failed to deassert ESC: %d\n", ret); 892 return; 893 } 894 ret = reset_control_deassert(dsi->rst_byte); 895 if (ret < 0) { 896 DRM_DEV_ERROR(dsi->dev, "Failed to deassert BYTE: %d\n", ret); 897 return; 898 } 899 } 900 901 static void nwl_dsi_bridge_enable(struct drm_bridge *bridge) 902 { 903 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 904 int ret; 905 906 /* Step 5 from DSI reset-out instructions */ 907 ret = reset_control_deassert(dsi->rst_dpi); 908 if (ret < 0) 909 DRM_DEV_ERROR(dsi->dev, "Failed to deassert DPI: %d\n", ret); 910 } 911 912 static int nwl_dsi_bridge_attach(struct drm_bridge *bridge, 913 enum drm_bridge_attach_flags flags) 914 { 915 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 916 struct drm_bridge *panel_bridge; 917 struct drm_panel *panel; 918 int ret; 919 920 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) { 921 DRM_ERROR("Fix bridge driver to make connector optional!"); 922 return -EINVAL; 923 } 924 925 ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0, &panel, 926 &panel_bridge); 927 if (ret) 928 return ret; 929 930 if (panel) { 931 panel_bridge = drm_panel_bridge_add(panel); 932 if (IS_ERR(panel_bridge)) 933 return PTR_ERR(panel_bridge); 934 } 935 dsi->panel_bridge = panel_bridge; 936 937 if (!dsi->panel_bridge) 938 return -EPROBE_DEFER; 939 940 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge, 941 flags); 942 } 943 944 static void nwl_dsi_bridge_detach(struct drm_bridge *bridge) 945 { struct nwl_dsi *dsi = bridge_to_dsi(bridge); 946 947 drm_of_panel_bridge_remove(dsi->dev->of_node, 1, 0); 948 } 949 950 static const struct drm_bridge_funcs nwl_dsi_bridge_funcs = { 951 .pre_enable = nwl_dsi_bridge_pre_enable, 952 .enable = nwl_dsi_bridge_enable, 953 .disable = nwl_dsi_bridge_disable, 954 .mode_fixup = nwl_dsi_bridge_mode_fixup, 955 .mode_set = nwl_dsi_bridge_mode_set, 956 .mode_valid = nwl_dsi_bridge_mode_valid, 957 .attach = nwl_dsi_bridge_attach, 958 .detach = nwl_dsi_bridge_detach, 959 }; 960 961 static int nwl_dsi_parse_dt(struct nwl_dsi *dsi) 962 { 963 struct platform_device *pdev = to_platform_device(dsi->dev); 964 struct clk *clk; 965 void __iomem *base; 966 int ret; 967 968 dsi->phy = devm_phy_get(dsi->dev, "dphy"); 969 if (IS_ERR(dsi->phy)) { 970 ret = PTR_ERR(dsi->phy); 971 if (ret != -EPROBE_DEFER) 972 DRM_DEV_ERROR(dsi->dev, "Could not get PHY: %d\n", ret); 973 return ret; 974 } 975 976 clk = devm_clk_get(dsi->dev, "lcdif"); 977 if (IS_ERR(clk)) { 978 ret = PTR_ERR(clk); 979 DRM_DEV_ERROR(dsi->dev, "Failed to get lcdif clock: %d\n", 980 ret); 981 return ret; 982 } 983 dsi->lcdif_clk = clk; 984 985 clk = devm_clk_get(dsi->dev, "core"); 986 if (IS_ERR(clk)) { 987 ret = PTR_ERR(clk); 988 DRM_DEV_ERROR(dsi->dev, "Failed to get core clock: %d\n", 989 ret); 990 return ret; 991 } 992 dsi->core_clk = clk; 993 994 clk = devm_clk_get(dsi->dev, "phy_ref"); 995 if (IS_ERR(clk)) { 996 ret = PTR_ERR(clk); 997 DRM_DEV_ERROR(dsi->dev, "Failed to get phy_ref clock: %d\n", 998 ret); 999 return ret; 1000 } 1001 dsi->phy_ref_clk = clk; 1002 1003 clk = devm_clk_get(dsi->dev, "rx_esc"); 1004 if (IS_ERR(clk)) { 1005 ret = PTR_ERR(clk); 1006 DRM_DEV_ERROR(dsi->dev, "Failed to get rx_esc clock: %d\n", 1007 ret); 1008 return ret; 1009 } 1010 dsi->rx_esc_clk = clk; 1011 1012 clk = devm_clk_get(dsi->dev, "tx_esc"); 1013 if (IS_ERR(clk)) { 1014 ret = PTR_ERR(clk); 1015 DRM_DEV_ERROR(dsi->dev, "Failed to get tx_esc clock: %d\n", 1016 ret); 1017 return ret; 1018 } 1019 dsi->tx_esc_clk = clk; 1020 1021 dsi->mux = devm_mux_control_get(dsi->dev, NULL); 1022 if (IS_ERR(dsi->mux)) { 1023 ret = PTR_ERR(dsi->mux); 1024 if (ret != -EPROBE_DEFER) 1025 DRM_DEV_ERROR(dsi->dev, "Failed to get mux: %d\n", ret); 1026 return ret; 1027 } 1028 1029 base = devm_platform_ioremap_resource(pdev, 0); 1030 if (IS_ERR(base)) 1031 return PTR_ERR(base); 1032 1033 dsi->regmap = 1034 devm_regmap_init_mmio(dsi->dev, base, &nwl_dsi_regmap_config); 1035 if (IS_ERR(dsi->regmap)) { 1036 ret = PTR_ERR(dsi->regmap); 1037 DRM_DEV_ERROR(dsi->dev, "Failed to create NWL DSI regmap: %d\n", 1038 ret); 1039 return ret; 1040 } 1041 1042 dsi->irq = platform_get_irq(pdev, 0); 1043 if (dsi->irq < 0) { 1044 DRM_DEV_ERROR(dsi->dev, "Failed to get device IRQ: %d\n", 1045 dsi->irq); 1046 return dsi->irq; 1047 } 1048 1049 dsi->rst_pclk = devm_reset_control_get_exclusive(dsi->dev, "pclk"); 1050 if (IS_ERR(dsi->rst_pclk)) { 1051 DRM_DEV_ERROR(dsi->dev, "Failed to get pclk reset: %ld\n", 1052 PTR_ERR(dsi->rst_pclk)); 1053 return PTR_ERR(dsi->rst_pclk); 1054 } 1055 dsi->rst_byte = devm_reset_control_get_exclusive(dsi->dev, "byte"); 1056 if (IS_ERR(dsi->rst_byte)) { 1057 DRM_DEV_ERROR(dsi->dev, "Failed to get byte reset: %ld\n", 1058 PTR_ERR(dsi->rst_byte)); 1059 return PTR_ERR(dsi->rst_byte); 1060 } 1061 dsi->rst_esc = devm_reset_control_get_exclusive(dsi->dev, "esc"); 1062 if (IS_ERR(dsi->rst_esc)) { 1063 DRM_DEV_ERROR(dsi->dev, "Failed to get esc reset: %ld\n", 1064 PTR_ERR(dsi->rst_esc)); 1065 return PTR_ERR(dsi->rst_esc); 1066 } 1067 dsi->rst_dpi = devm_reset_control_get_exclusive(dsi->dev, "dpi"); 1068 if (IS_ERR(dsi->rst_dpi)) { 1069 DRM_DEV_ERROR(dsi->dev, "Failed to get dpi reset: %ld\n", 1070 PTR_ERR(dsi->rst_dpi)); 1071 return PTR_ERR(dsi->rst_dpi); 1072 } 1073 return 0; 1074 } 1075 1076 static int nwl_dsi_select_input(struct nwl_dsi *dsi) 1077 { 1078 struct device_node *remote; 1079 u32 use_dcss = 1; 1080 int ret; 1081 1082 remote = of_graph_get_remote_node(dsi->dev->of_node, 0, 1083 NWL_DSI_ENDPOINT_LCDIF); 1084 if (remote) { 1085 use_dcss = 0; 1086 } else { 1087 remote = of_graph_get_remote_node(dsi->dev->of_node, 0, 1088 NWL_DSI_ENDPOINT_DCSS); 1089 if (!remote) { 1090 DRM_DEV_ERROR(dsi->dev, 1091 "No valid input endpoint found\n"); 1092 return -EINVAL; 1093 } 1094 } 1095 1096 DRM_DEV_INFO(dsi->dev, "Using %s as input source\n", 1097 (use_dcss) ? "DCSS" : "LCDIF"); 1098 ret = mux_control_try_select(dsi->mux, use_dcss); 1099 if (ret < 0) 1100 DRM_DEV_ERROR(dsi->dev, "Failed to select input: %d\n", ret); 1101 1102 of_node_put(remote); 1103 return ret; 1104 } 1105 1106 static int nwl_dsi_deselect_input(struct nwl_dsi *dsi) 1107 { 1108 int ret; 1109 1110 ret = mux_control_deselect(dsi->mux); 1111 if (ret < 0) 1112 DRM_DEV_ERROR(dsi->dev, "Failed to deselect input: %d\n", ret); 1113 1114 return ret; 1115 } 1116 1117 static const struct drm_bridge_timings nwl_dsi_timings = { 1118 .input_bus_flags = DRM_BUS_FLAG_DE_LOW, 1119 }; 1120 1121 static const struct of_device_id nwl_dsi_dt_ids[] = { 1122 { .compatible = "fsl,imx8mq-nwl-dsi", }, 1123 { /* sentinel */ } 1124 }; 1125 MODULE_DEVICE_TABLE(of, nwl_dsi_dt_ids); 1126 1127 static const struct soc_device_attribute nwl_dsi_quirks_match[] = { 1128 { .soc_id = "i.MX8MQ", .revision = "2.0", 1129 .data = (void *)E11418_HS_MODE_QUIRK }, 1130 { /* sentinel. */ }, 1131 }; 1132 1133 static int nwl_dsi_probe(struct platform_device *pdev) 1134 { 1135 struct device *dev = &pdev->dev; 1136 const struct soc_device_attribute *attr; 1137 struct nwl_dsi *dsi; 1138 int ret; 1139 1140 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1141 if (!dsi) 1142 return -ENOMEM; 1143 1144 dsi->dev = dev; 1145 1146 ret = nwl_dsi_parse_dt(dsi); 1147 if (ret) 1148 return ret; 1149 1150 ret = devm_request_irq(dev, dsi->irq, nwl_dsi_irq_handler, 0, 1151 dev_name(dev), dsi); 1152 if (ret < 0) { 1153 DRM_DEV_ERROR(dev, "Failed to request IRQ %d: %d\n", dsi->irq, 1154 ret); 1155 return ret; 1156 } 1157 1158 dsi->dsi_host.ops = &nwl_dsi_host_ops; 1159 dsi->dsi_host.dev = dev; 1160 ret = mipi_dsi_host_register(&dsi->dsi_host); 1161 if (ret) { 1162 DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret); 1163 return ret; 1164 } 1165 1166 attr = soc_device_match(nwl_dsi_quirks_match); 1167 if (attr) 1168 dsi->quirks = (uintptr_t)attr->data; 1169 1170 dsi->bridge.driver_private = dsi; 1171 dsi->bridge.funcs = &nwl_dsi_bridge_funcs; 1172 dsi->bridge.of_node = dev->of_node; 1173 dsi->bridge.timings = &nwl_dsi_timings; 1174 1175 dev_set_drvdata(dev, dsi); 1176 pm_runtime_enable(dev); 1177 1178 ret = nwl_dsi_select_input(dsi); 1179 if (ret < 0) { 1180 mipi_dsi_host_unregister(&dsi->dsi_host); 1181 return ret; 1182 } 1183 1184 drm_bridge_add(&dsi->bridge); 1185 return 0; 1186 } 1187 1188 static int nwl_dsi_remove(struct platform_device *pdev) 1189 { 1190 struct nwl_dsi *dsi = platform_get_drvdata(pdev); 1191 1192 nwl_dsi_deselect_input(dsi); 1193 mipi_dsi_host_unregister(&dsi->dsi_host); 1194 drm_bridge_remove(&dsi->bridge); 1195 pm_runtime_disable(&pdev->dev); 1196 return 0; 1197 } 1198 1199 static struct platform_driver nwl_dsi_driver = { 1200 .probe = nwl_dsi_probe, 1201 .remove = nwl_dsi_remove, 1202 .driver = { 1203 .of_match_table = nwl_dsi_dt_ids, 1204 .name = DRV_NAME, 1205 }, 1206 }; 1207 1208 module_platform_driver(nwl_dsi_driver); 1209 1210 MODULE_AUTHOR("NXP Semiconductor"); 1211 MODULE_AUTHOR("Purism SPC"); 1212 MODULE_DESCRIPTION("Northwest Logic MIPI-DSI driver"); 1213 MODULE_LICENSE("GPL"); /* GPLv2 or later */ 1214