1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Qualcomm QUSB2 phy controller
9
10maintainers:
11  - Manu Gautam <mgautam@codeaurora.org>
12
13description:
14  QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
15
16properties:
17  compatible:
18    oneOf:
19      - items:
20        - enum:
21          - qcom,msm8996-qusb2-phy
22          - qcom,msm8998-qusb2-phy
23      - items:
24        - enum:
25          - qcom,sc7180-qusb2-phy
26          - qcom,sdm845-qusb2-phy
27        - const: qcom,qusb2-v2-phy
28  reg:
29    maxItems: 1
30
31  "#phy-cells":
32    const: 0
33
34  clocks:
35    minItems: 2
36    maxItems: 3
37    items:
38      - description: phy config clock
39      - description: 19.2 MHz ref clk
40      - description: phy interface clock (Optional)
41
42  clock-names:
43    minItems: 2
44    maxItems: 3
45    items:
46      - const: cfg_ahb
47      - const: ref
48      - const: iface
49
50  vdda-pll-supply:
51     description:
52       Phandle to 1.8V regulator supply to PHY refclk pll block.
53
54  vdda-phy-dpdm-supply:
55     description:
56       Phandle to 3.1V regulator supply to Dp/Dm port signals.
57
58  resets:
59    maxItems: 1
60    description:
61      Phandle to reset to phy block.
62
63  nvmem-cells:
64    maxItems: 1
65    description:
66        Phandle to nvmem cell that contains 'HS Tx trim'
67        tuning parameter value for qusb2 phy.
68
69  qcom,tcsr-syscon:
70    description:
71        Phandle to TCSR syscon register region.
72    $ref: /schemas/types.yaml#/definitions/phandle
73
74if:
75  properties:
76    compatible:
77      contains:
78        const: qcom,qusb2-v2-phy
79then:
80  properties:
81    qcom,imp-res-offset-value:
82      description:
83        It is a 6 bit value that specifies offset to be
84        added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
85        tuning parameter that may vary for different boards of same SOC.
86      $ref: /schemas/types.yaml#/definitions/uint32
87      minimum: 0
88      maximum: 63
89      default: 0
90
91    qcom,bias-ctrl-value:
92      description:
93        It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
94        tuning parameter that may vary for different boards of same SOC.
95      $ref: /schemas/types.yaml#/definitions/uint32
96      minimum: 0
97      maximum: 63
98      default: 32
99
100    qcom,charge-ctrl-value:
101      description:
102        It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
103        tuning parameter that may vary for different boards of same SOC.
104      $ref: /schemas/types.yaml#/definitions/uint32
105      minimum: 0
106      maximum: 3
107      default: 0
108
109    qcom,hstx-trim-value:
110      description:
111        It is a 4 bit value that specifies tuning for HSTX
112        output current.
113        Possible range is - 15mA to 24mA (stepsize of 600 uA).
114        See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
115      $ref: /schemas/types.yaml#/definitions/uint32
116      minimum: 0
117      maximum: 15
118      default: 3
119
120    qcom,preemphasis-level:
121      description:
122        It is a 2 bit value that specifies pre-emphasis level.
123        Possible range is 0 to 15% (stepsize of 5%).
124        See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
125      $ref: /schemas/types.yaml#/definitions/uint32
126      minimum: 0
127      maximum: 3
128      default: 2
129
130    qcom,preemphasis-width:
131      description:
132        It is a 1 bit value that specifies how long the HSTX
133        pre-emphasis (specified using qcom,preemphasis-level) must be in
134        effect. Duration could be half-bit of full-bit.
135        See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
136      $ref: /schemas/types.yaml#/definitions/uint32
137      minimum: 0
138      maximum: 1
139      default: 0
140
141    qcom,hsdisc-trim-value:
142      description:
143        It is a 2 bit value tuning parameter that control disconnect
144        threshold and may vary for different boards of same SOC.
145      $ref: /schemas/types.yaml#/definitions/uint32
146      minimum: 0
147      maximum: 3
148      default: 0
149
150required:
151  - compatible
152  - reg
153  - "#phy-cells"
154  - clocks
155  - clock-names
156  - vdda-pll-supply
157  - vdda-phy-dpdm-supply
158  - resets
159
160
161examples:
162  - |
163    #include <dt-bindings/clock/qcom,gcc-msm8996.h>
164    hsusb_phy: phy@7411000 {
165        compatible = "qcom,msm8996-qusb2-phy";
166        reg = <0x7411000 0x180>;
167        #phy-cells = <0>;
168
169        clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
170                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
171        clock-names = "cfg_ahb", "ref";
172
173        vdda-pll-supply = <&pm8994_l12>;
174        vdda-phy-dpdm-supply = <&pm8994_l24>;
175
176        resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
177        nvmem-cells = <&qusb2p_hstx_trim>;
178    };
179