1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _ASM_X86_MWAIT_H 3 #define _ASM_X86_MWAIT_H 4 5 #include <linux/sched.h> 6 #include <linux/sched/idle.h> 7 8 #include <asm/cpufeature.h> 9 #include <asm/nospec-branch.h> 10 11 #define MWAIT_SUBSTATE_MASK 0xf 12 #define MWAIT_CSTATE_MASK 0xf 13 #define MWAIT_SUBSTATE_SIZE 4 14 #define MWAIT_HINT2CSTATE(hint) (((hint) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) 15 #define MWAIT_HINT2SUBSTATE(hint) ((hint) & MWAIT_CSTATE_MASK) 16 17 #define CPUID_MWAIT_LEAF 5 18 #define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1 19 #define CPUID5_ECX_INTERRUPT_BREAK 0x2 20 21 #define MWAIT_ECX_INTERRUPT_BREAK 0x1 22 #define MWAITX_ECX_TIMER_ENABLE BIT(1) 23 #define MWAITX_MAX_WAIT_CYCLES UINT_MAX 24 #define MWAITX_DISABLE_CSTATES 0xf0 25 #define TPAUSE_C01_STATE 1 26 #define TPAUSE_C02_STATE 0 27 28 u32 get_umwait_control_msr(void); 29 30 static inline void __monitor(const void *eax, unsigned long ecx, 31 unsigned long edx) 32 { 33 /* "monitor %eax, %ecx, %edx;" */ 34 asm volatile(".byte 0x0f, 0x01, 0xc8;" 35 :: "a" (eax), "c" (ecx), "d"(edx)); 36 } 37 38 static inline void __monitorx(const void *eax, unsigned long ecx, 39 unsigned long edx) 40 { 41 /* "monitorx %eax, %ecx, %edx;" */ 42 asm volatile(".byte 0x0f, 0x01, 0xfa;" 43 :: "a" (eax), "c" (ecx), "d"(edx)); 44 } 45 46 static inline void __mwait(unsigned long eax, unsigned long ecx) 47 { 48 mds_idle_clear_cpu_buffers(); 49 50 /* "mwait %eax, %ecx;" */ 51 asm volatile(".byte 0x0f, 0x01, 0xc9;" 52 :: "a" (eax), "c" (ecx)); 53 } 54 55 /* 56 * MWAITX allows for a timer expiration to get the core out a wait state in 57 * addition to the default MWAIT exit condition of a store appearing at a 58 * monitored virtual address. 59 * 60 * Registers: 61 * 62 * MWAITX ECX[1]: enable timer if set 63 * MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks. The software P0 64 * frequency is the same as the TSC frequency. 65 * 66 * Below is a comparison between MWAIT and MWAITX on AMD processors: 67 * 68 * MWAIT MWAITX 69 * opcode 0f 01 c9 | 0f 01 fb 70 * ECX[0] value of RFLAGS.IF seen by instruction 71 * ECX[1] unused/#GP if set | enable timer if set 72 * ECX[31:2] unused/#GP if set 73 * EAX unused (reserve for hint) 74 * EBX[31:0] unused | max wait time (P0 clocks) 75 * 76 * MONITOR MONITORX 77 * opcode 0f 01 c8 | 0f 01 fa 78 * EAX (logical) address to monitor 79 * ECX #GP if not zero 80 */ 81 static inline void __mwaitx(unsigned long eax, unsigned long ebx, 82 unsigned long ecx) 83 { 84 /* No MDS buffer clear as this is AMD/HYGON only */ 85 86 /* "mwaitx %eax, %ebx, %ecx;" */ 87 asm volatile(".byte 0x0f, 0x01, 0xfb;" 88 :: "a" (eax), "b" (ebx), "c" (ecx)); 89 } 90 91 static inline void __sti_mwait(unsigned long eax, unsigned long ecx) 92 { 93 trace_hardirqs_on(); 94 95 mds_idle_clear_cpu_buffers(); 96 /* "mwait %eax, %ecx;" */ 97 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;" 98 :: "a" (eax), "c" (ecx)); 99 } 100 101 /* 102 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI, 103 * which can obviate IPI to trigger checking of need_resched. 104 * We execute MONITOR against need_resched and enter optimized wait state 105 * through MWAIT. Whenever someone changes need_resched, we would be woken 106 * up from MWAIT (without an IPI). 107 * 108 * New with Core Duo processors, MWAIT can take some hints based on CPU 109 * capability. 110 */ 111 static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx) 112 { 113 if (static_cpu_has_bug(X86_BUG_MONITOR) || !current_set_polling_and_test()) { 114 if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR)) { 115 mb(); 116 clflush((void *)¤t_thread_info()->flags); 117 mb(); 118 } 119 120 __monitor((void *)¤t_thread_info()->flags, 0, 0); 121 if (!need_resched()) 122 __mwait(eax, ecx); 123 } 124 current_clr_polling(); 125 } 126 127 /* 128 * Caller can specify whether to enter C0.1 (low latency, less 129 * power saving) or C0.2 state (saves more power, but longer wakeup 130 * latency). This may be overridden by the IA32_UMWAIT_CONTROL MSR 131 * which can force requests for C0.2 to be downgraded to C0.1. 132 */ 133 static inline void __tpause(u32 ecx, u32 edx, u32 eax) 134 { 135 /* "tpause %ecx, %edx, %eax;" */ 136 #ifdef CONFIG_AS_TPAUSE 137 asm volatile("tpause %%ecx\n" 138 : 139 : "c"(ecx), "d"(edx), "a"(eax)); 140 #else 141 asm volatile(".byte 0x66, 0x0f, 0xae, 0xf1\t\n" 142 : 143 : "c"(ecx), "d"(edx), "a"(eax)); 144 #endif 145 } 146 147 #endif /* _ASM_X86_MWAIT_H */ 148