1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * drivers/i2c/busses/i2c-tegra.c 4 * 5 * Copyright (C) 2010 Google, Inc. 6 * Author: Colin Cross <ccross@android.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dmaengine.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/err.h> 14 #include <linux/i2c.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/irq.h> 20 #include <linux/kernel.h> 21 #include <linux/ktime.h> 22 #include <linux/module.h> 23 #include <linux/of_device.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/reset.h> 28 29 #define BYTES_PER_FIFO_WORD 4 30 31 #define I2C_CNFG 0x000 32 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12 33 #define I2C_CNFG_PACKET_MODE_EN BIT(10) 34 #define I2C_CNFG_NEW_MASTER_FSM BIT(11) 35 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17) 36 #define I2C_STATUS 0x01C 37 #define I2C_SL_CNFG 0x020 38 #define I2C_SL_CNFG_NACK BIT(1) 39 #define I2C_SL_CNFG_NEWSL BIT(2) 40 #define I2C_SL_ADDR1 0x02c 41 #define I2C_SL_ADDR2 0x030 42 #define I2C_TX_FIFO 0x050 43 #define I2C_RX_FIFO 0x054 44 #define I2C_PACKET_TRANSFER_STATUS 0x058 45 #define I2C_FIFO_CONTROL 0x05c 46 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1) 47 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0) 48 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5) 49 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2) 50 #define I2C_FIFO_STATUS 0x060 51 #define I2C_FIFO_STATUS_TX_MASK 0xF0 52 #define I2C_FIFO_STATUS_TX_SHIFT 4 53 #define I2C_FIFO_STATUS_RX_MASK 0x0F 54 #define I2C_FIFO_STATUS_RX_SHIFT 0 55 #define I2C_INT_MASK 0x064 56 #define I2C_INT_STATUS 0x068 57 #define I2C_INT_BUS_CLR_DONE BIT(11) 58 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7) 59 #define I2C_INT_NO_ACK BIT(3) 60 #define I2C_INT_ARBITRATION_LOST BIT(2) 61 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1) 62 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0) 63 #define I2C_CLK_DIVISOR 0x06c 64 #define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16 65 66 #define DVC_CTRL_REG1 0x000 67 #define DVC_CTRL_REG1_INTR_EN BIT(10) 68 #define DVC_CTRL_REG3 0x008 69 #define DVC_CTRL_REG3_SW_PROG BIT(26) 70 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30) 71 #define DVC_STATUS 0x00c 72 #define DVC_STATUS_I2C_DONE_INTR BIT(30) 73 74 #define I2C_ERR_NONE 0x00 75 #define I2C_ERR_NO_ACK BIT(0) 76 #define I2C_ERR_ARBITRATION_LOST BIT(1) 77 #define I2C_ERR_UNKNOWN_INTERRUPT BIT(2) 78 #define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3) 79 80 #define PACKET_HEADER0_HEADER_SIZE_SHIFT 28 81 #define PACKET_HEADER0_PACKET_ID_SHIFT 16 82 #define PACKET_HEADER0_CONT_ID_SHIFT 12 83 #define PACKET_HEADER0_PROTOCOL_I2C BIT(4) 84 85 #define I2C_HEADER_CONT_ON_NAK BIT(21) 86 #define I2C_HEADER_READ BIT(19) 87 #define I2C_HEADER_10BIT_ADDR BIT(18) 88 #define I2C_HEADER_IE_ENABLE BIT(17) 89 #define I2C_HEADER_REPEAT_START BIT(16) 90 #define I2C_HEADER_CONTINUE_XFER BIT(15) 91 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1 92 93 #define I2C_BUS_CLEAR_CNFG 0x084 94 #define I2C_BC_SCLK_THRESHOLD 9 95 #define I2C_BC_SCLK_THRESHOLD_SHIFT 16 96 #define I2C_BC_STOP_COND BIT(2) 97 #define I2C_BC_TERMINATE BIT(1) 98 #define I2C_BC_ENABLE BIT(0) 99 #define I2C_BUS_CLEAR_STATUS 0x088 100 #define I2C_BC_STATUS BIT(0) 101 102 #define I2C_CONFIG_LOAD 0x08C 103 #define I2C_MSTR_CONFIG_LOAD BIT(0) 104 105 #define I2C_CLKEN_OVERRIDE 0x090 106 #define I2C_MST_CORE_CLKEN_OVR BIT(0) 107 108 #define I2C_CONFIG_LOAD_TIMEOUT 1000000 109 110 #define I2C_MST_FIFO_CONTROL 0x0b4 111 #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0) 112 #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1) 113 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4) 114 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16) 115 116 #define I2C_MST_FIFO_STATUS 0x0b8 117 #define I2C_MST_FIFO_STATUS_RX_MASK 0xff 118 #define I2C_MST_FIFO_STATUS_RX_SHIFT 0 119 #define I2C_MST_FIFO_STATUS_TX_MASK 0xff0000 120 #define I2C_MST_FIFO_STATUS_TX_SHIFT 16 121 122 #define I2C_INTERFACE_TIMING_0 0x94 123 #define I2C_THIGH_SHIFT 8 124 #define I2C_INTERFACE_TIMING_1 0x98 125 126 #define I2C_STANDARD_MODE 100000 127 #define I2C_FAST_MODE 400000 128 #define I2C_FAST_PLUS_MODE 1000000 129 130 /* Packet header size in bytes */ 131 #define I2C_PACKET_HEADER_SIZE 12 132 133 /* 134 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to 135 * avoid DMA overhead, otherwise external APB DMA controller will be used. 136 * Note that the actual MAX PIO length is 20 bytes because 32 bytes include 137 * I2C_PACKET_HEADER_SIZE. 138 */ 139 #define I2C_PIO_MODE_PREFERRED_LEN 32 140 141 /* 142 * msg_end_type: The bus control which need to be send at end of transfer. 143 * @MSG_END_STOP: Send stop pulse at end of transfer. 144 * @MSG_END_REPEAT_START: Send repeat start at end of transfer. 145 * @MSG_END_CONTINUE: The following on message is coming and so do not send 146 * stop or repeat start. 147 */ 148 enum msg_end_type { 149 MSG_END_STOP, 150 MSG_END_REPEAT_START, 151 MSG_END_CONTINUE, 152 }; 153 154 /** 155 * struct tegra_i2c_hw_feature : Different HW support on Tegra 156 * @has_continue_xfer_support: Continue transfer supports. 157 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer 158 * complete interrupt per packet basis. 159 * @has_single_clk_source: The I2C controller has single clock source. Tegra30 160 * and earlier SoCs have two clock sources i.e. div-clk and 161 * fast-clk. 162 * @has_config_load_reg: Has the config load register to load the new 163 * configuration. 164 * @clk_divisor_hs_mode: Clock divisor in HS mode. 165 * @clk_divisor_std_mode: Clock divisor in standard mode. It is 166 * applicable if there is no fast clock source i.e. single clock 167 * source. 168 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is 169 * applicable if there is no fast clock source i.e. single clock 170 * source. 171 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is 172 * applicable if there is no fast clock source (i.e. single 173 * clock source). 174 * @has_multi_master_mode: The I2C controller supports running in single-master 175 * or multi-master mode. 176 * @has_slcg_override_reg: The I2C controller supports a register that 177 * overrides the second level clock gating. 178 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that 179 * provides additional features and allows for longer messages to 180 * be transferred in one go. 181 * @quirks: i2c adapter quirks for limiting write/read transfer size and not 182 * allowing 0 length transfers. 183 * @supports_bus_clear: Bus Clear support to recover from bus hang during 184 * SDA stuck low from device for some unknown reasons. 185 * @has_apb_dma: Support of APBDMA on corresponding Tegra chip. 186 * @tlow_std_mode: Low period of the clock in standard mode. 187 * @thigh_std_mode: High period of the clock in standard mode. 188 * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes. 189 * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes. 190 * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions 191 * in standard mode. 192 * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop 193 * conditions in fast/fast-plus modes. 194 * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions 195 * in HS mode. 196 * @has_interface_timing_reg: Has interface timing register to program the tuned 197 * timing settings. 198 */ 199 struct tegra_i2c_hw_feature { 200 bool has_continue_xfer_support; 201 bool has_per_pkt_xfer_complete_irq; 202 bool has_single_clk_source; 203 bool has_config_load_reg; 204 int clk_divisor_hs_mode; 205 int clk_divisor_std_mode; 206 int clk_divisor_fast_mode; 207 u16 clk_divisor_fast_plus_mode; 208 bool has_multi_master_mode; 209 bool has_slcg_override_reg; 210 bool has_mst_fifo; 211 const struct i2c_adapter_quirks *quirks; 212 bool supports_bus_clear; 213 bool has_apb_dma; 214 u8 tlow_std_mode; 215 u8 thigh_std_mode; 216 u8 tlow_fast_fastplus_mode; 217 u8 thigh_fast_fastplus_mode; 218 u32 setup_hold_time_std_mode; 219 u32 setup_hold_time_fast_fast_plus_mode; 220 u32 setup_hold_time_hs_mode; 221 bool has_interface_timing_reg; 222 }; 223 224 /** 225 * struct tegra_i2c_dev - per device I2C context 226 * @dev: device reference for power management 227 * @hw: Tegra I2C HW feature 228 * @adapter: core I2C layer adapter information 229 * @div_clk: clock reference for div clock of I2C controller 230 * @fast_clk: clock reference for fast clock of I2C controller 231 * @rst: reset control for the I2C controller 232 * @base: ioremapped registers cookie 233 * @base_phys: physical base address of the I2C controller 234 * @cont_id: I2C controller ID, used for packet header 235 * @irq: IRQ number of transfer complete interrupt 236 * @is_dvc: identifies the DVC I2C controller, has a different register layout 237 * @msg_complete: transfer completion notifier 238 * @msg_err: error code for completed message 239 * @msg_buf: pointer to current message data 240 * @msg_buf_remaining: size of unsent data in the message buffer 241 * @msg_read: identifies read transfers 242 * @bus_clk_rate: current I2C bus clock rate 243 * @clk_divisor_non_hs_mode: clock divider for non-high-speed modes 244 * @is_multimaster_mode: track if I2C controller is in multi-master mode 245 * @tx_dma_chan: DMA transmit channel 246 * @rx_dma_chan: DMA receive channel 247 * @dma_phys: handle to DMA resources 248 * @dma_buf: pointer to allocated DMA buffer 249 * @dma_buf_size: DMA buffer size 250 * @is_curr_dma_xfer: indicates active DMA transfer 251 * @dma_complete: DMA completion notifier 252 * @is_curr_atomic_xfer: indicates active atomic transfer 253 */ 254 struct tegra_i2c_dev { 255 struct device *dev; 256 const struct tegra_i2c_hw_feature *hw; 257 struct i2c_adapter adapter; 258 struct clk *div_clk; 259 struct clk *fast_clk; 260 struct reset_control *rst; 261 void __iomem *base; 262 phys_addr_t base_phys; 263 int cont_id; 264 int irq; 265 int is_dvc; 266 struct completion msg_complete; 267 int msg_err; 268 u8 *msg_buf; 269 size_t msg_buf_remaining; 270 int msg_read; 271 u32 bus_clk_rate; 272 u16 clk_divisor_non_hs_mode; 273 bool is_multimaster_mode; 274 struct dma_chan *tx_dma_chan; 275 struct dma_chan *rx_dma_chan; 276 dma_addr_t dma_phys; 277 u32 *dma_buf; 278 unsigned int dma_buf_size; 279 bool is_curr_dma_xfer; 280 struct completion dma_complete; 281 bool is_curr_atomic_xfer; 282 }; 283 284 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 285 unsigned long reg) 286 { 287 writel_relaxed(val, i2c_dev->base + reg); 288 } 289 290 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) 291 { 292 return readl_relaxed(i2c_dev->base + reg); 293 } 294 295 /* 296 * i2c_writel and i2c_readl will offset the register if necessary to talk 297 * to the I2C block inside the DVC block 298 */ 299 static unsigned long tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, 300 unsigned long reg) 301 { 302 if (i2c_dev->is_dvc) 303 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40; 304 return reg; 305 } 306 307 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, 308 unsigned long reg) 309 { 310 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 311 312 /* Read back register to make sure that register writes completed */ 313 if (reg != I2C_TX_FIFO) 314 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 315 } 316 317 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg) 318 { 319 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); 320 } 321 322 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data, 323 unsigned long reg, int len) 324 { 325 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 326 } 327 328 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data, 329 unsigned long reg, int len) 330 { 331 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); 332 } 333 334 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 335 { 336 u32 int_mask; 337 338 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask; 339 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 340 } 341 342 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) 343 { 344 u32 int_mask; 345 346 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask; 347 i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); 348 } 349 350 static void tegra_i2c_dma_complete(void *args) 351 { 352 struct tegra_i2c_dev *i2c_dev = args; 353 354 complete(&i2c_dev->dma_complete); 355 } 356 357 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len) 358 { 359 struct dma_async_tx_descriptor *dma_desc; 360 enum dma_transfer_direction dir; 361 struct dma_chan *chan; 362 363 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len); 364 reinit_completion(&i2c_dev->dma_complete); 365 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; 366 chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan; 367 dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys, 368 len, dir, DMA_PREP_INTERRUPT | 369 DMA_CTRL_ACK); 370 if (!dma_desc) { 371 dev_err(i2c_dev->dev, "failed to get DMA descriptor\n"); 372 return -EINVAL; 373 } 374 375 dma_desc->callback = tegra_i2c_dma_complete; 376 dma_desc->callback_param = i2c_dev; 377 dmaengine_submit(dma_desc); 378 dma_async_issue_pending(chan); 379 return 0; 380 } 381 382 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev) 383 { 384 if (i2c_dev->dma_buf) { 385 dma_free_coherent(i2c_dev->dev, i2c_dev->dma_buf_size, 386 i2c_dev->dma_buf, i2c_dev->dma_phys); 387 i2c_dev->dma_buf = NULL; 388 } 389 390 if (i2c_dev->tx_dma_chan) { 391 dma_release_channel(i2c_dev->tx_dma_chan); 392 i2c_dev->tx_dma_chan = NULL; 393 } 394 395 if (i2c_dev->rx_dma_chan) { 396 dma_release_channel(i2c_dev->rx_dma_chan); 397 i2c_dev->rx_dma_chan = NULL; 398 } 399 } 400 401 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev) 402 { 403 struct dma_chan *chan; 404 u32 *dma_buf; 405 dma_addr_t dma_phys; 406 int err; 407 408 if (!i2c_dev->hw->has_apb_dma) 409 return 0; 410 411 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) { 412 dev_dbg(i2c_dev->dev, "Support for APB DMA not enabled!\n"); 413 return 0; 414 } 415 416 chan = dma_request_chan(i2c_dev->dev, "rx"); 417 if (IS_ERR(chan)) { 418 err = PTR_ERR(chan); 419 goto err_out; 420 } 421 422 i2c_dev->rx_dma_chan = chan; 423 424 chan = dma_request_chan(i2c_dev->dev, "tx"); 425 if (IS_ERR(chan)) { 426 err = PTR_ERR(chan); 427 goto err_out; 428 } 429 430 i2c_dev->tx_dma_chan = chan; 431 432 dma_buf = dma_alloc_coherent(i2c_dev->dev, i2c_dev->dma_buf_size, 433 &dma_phys, GFP_KERNEL | __GFP_NOWARN); 434 if (!dma_buf) { 435 dev_err(i2c_dev->dev, "failed to allocate the DMA buffer\n"); 436 err = -ENOMEM; 437 goto err_out; 438 } 439 440 i2c_dev->dma_buf = dma_buf; 441 i2c_dev->dma_phys = dma_phys; 442 return 0; 443 444 err_out: 445 tegra_i2c_release_dma(i2c_dev); 446 if (err != -EPROBE_DEFER) { 447 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err); 448 dev_err(i2c_dev->dev, "falling back to PIO\n"); 449 return 0; 450 } 451 452 return err; 453 } 454 455 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) 456 { 457 unsigned long timeout = jiffies + HZ; 458 unsigned int offset; 459 u32 mask, val; 460 461 if (i2c_dev->hw->has_mst_fifo) { 462 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH | 463 I2C_MST_FIFO_CONTROL_RX_FLUSH; 464 offset = I2C_MST_FIFO_CONTROL; 465 } else { 466 mask = I2C_FIFO_CONTROL_TX_FLUSH | 467 I2C_FIFO_CONTROL_RX_FLUSH; 468 offset = I2C_FIFO_CONTROL; 469 } 470 471 val = i2c_readl(i2c_dev, offset); 472 val |= mask; 473 i2c_writel(i2c_dev, val, offset); 474 475 while (i2c_readl(i2c_dev, offset) & mask) { 476 if (time_after(jiffies, timeout)) { 477 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n"); 478 return -ETIMEDOUT; 479 } 480 usleep_range(1000, 2000); 481 } 482 return 0; 483 } 484 485 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev) 486 { 487 u32 val; 488 int rx_fifo_avail; 489 u8 *buf = i2c_dev->msg_buf; 490 size_t buf_remaining = i2c_dev->msg_buf_remaining; 491 int words_to_transfer; 492 493 /* 494 * Catch overflow due to message fully sent 495 * before the check for RX FIFO availability. 496 */ 497 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining))) 498 return -EINVAL; 499 500 if (i2c_dev->hw->has_mst_fifo) { 501 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 502 rx_fifo_avail = (val & I2C_MST_FIFO_STATUS_RX_MASK) >> 503 I2C_MST_FIFO_STATUS_RX_SHIFT; 504 } else { 505 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 506 rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >> 507 I2C_FIFO_STATUS_RX_SHIFT; 508 } 509 510 /* Rounds down to not include partial word at the end of buf */ 511 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 512 if (words_to_transfer > rx_fifo_avail) 513 words_to_transfer = rx_fifo_avail; 514 515 i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer); 516 517 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 518 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 519 rx_fifo_avail -= words_to_transfer; 520 521 /* 522 * If there is a partial word at the end of buf, handle it manually to 523 * prevent overwriting past the end of buf 524 */ 525 if (rx_fifo_avail > 0 && buf_remaining > 0) { 526 /* 527 * buf_remaining > 3 check not needed as rx_fifo_avail == 0 528 * when (words_to_transfer was > rx_fifo_avail) earlier 529 * in this function. 530 */ 531 val = i2c_readl(i2c_dev, I2C_RX_FIFO); 532 val = cpu_to_le32(val); 533 memcpy(buf, &val, buf_remaining); 534 buf_remaining = 0; 535 rx_fifo_avail--; 536 } 537 538 /* RX FIFO must be drained, otherwise it's an Overflow case. */ 539 if (WARN_ON_ONCE(rx_fifo_avail)) 540 return -EINVAL; 541 542 i2c_dev->msg_buf_remaining = buf_remaining; 543 i2c_dev->msg_buf = buf; 544 545 return 0; 546 } 547 548 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev) 549 { 550 u32 val; 551 int tx_fifo_avail; 552 u8 *buf = i2c_dev->msg_buf; 553 size_t buf_remaining = i2c_dev->msg_buf_remaining; 554 int words_to_transfer; 555 556 if (i2c_dev->hw->has_mst_fifo) { 557 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS); 558 tx_fifo_avail = (val & I2C_MST_FIFO_STATUS_TX_MASK) >> 559 I2C_MST_FIFO_STATUS_TX_SHIFT; 560 } else { 561 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS); 562 tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >> 563 I2C_FIFO_STATUS_TX_SHIFT; 564 } 565 566 /* Rounds down to not include partial word at the end of buf */ 567 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD; 568 569 /* It's very common to have < 4 bytes, so optimize that case. */ 570 if (words_to_transfer) { 571 if (words_to_transfer > tx_fifo_avail) 572 words_to_transfer = tx_fifo_avail; 573 574 /* 575 * Update state before writing to FIFO. If this casues us 576 * to finish writing all bytes (AKA buf_remaining goes to 0) we 577 * have a potential for an interrupt (PACKET_XFER_COMPLETE is 578 * not maskable). We need to make sure that the isr sees 579 * buf_remaining as 0 and doesn't call us back re-entrantly. 580 */ 581 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; 582 tx_fifo_avail -= words_to_transfer; 583 i2c_dev->msg_buf_remaining = buf_remaining; 584 i2c_dev->msg_buf = buf + 585 words_to_transfer * BYTES_PER_FIFO_WORD; 586 barrier(); 587 588 i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer); 589 590 buf += words_to_transfer * BYTES_PER_FIFO_WORD; 591 } 592 593 /* 594 * If there is a partial word at the end of buf, handle it manually to 595 * prevent reading past the end of buf, which could cross a page 596 * boundary and fault. 597 */ 598 if (tx_fifo_avail > 0 && buf_remaining > 0) { 599 /* 600 * buf_remaining > 3 check not needed as tx_fifo_avail == 0 601 * when (words_to_transfer was > tx_fifo_avail) earlier 602 * in this function for non-zero words_to_transfer. 603 */ 604 memcpy(&val, buf, buf_remaining); 605 val = le32_to_cpu(val); 606 607 /* Again update before writing to FIFO to make sure isr sees. */ 608 i2c_dev->msg_buf_remaining = 0; 609 i2c_dev->msg_buf = NULL; 610 barrier(); 611 612 i2c_writel(i2c_dev, val, I2C_TX_FIFO); 613 } 614 615 return 0; 616 } 617 618 /* 619 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller) 620 * block. This block is identical to the rest of the I2C blocks, except that 621 * it only supports master mode, it has registers moved around, and it needs 622 * some extra init to get it into I2C mode. The register moves are handled 623 * by i2c_readl and i2c_writel 624 */ 625 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev) 626 { 627 u32 val; 628 629 val = dvc_readl(i2c_dev, DVC_CTRL_REG3); 630 val |= DVC_CTRL_REG3_SW_PROG; 631 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN; 632 dvc_writel(i2c_dev, val, DVC_CTRL_REG3); 633 634 val = dvc_readl(i2c_dev, DVC_CTRL_REG1); 635 val |= DVC_CTRL_REG1_INTR_EN; 636 dvc_writel(i2c_dev, val, DVC_CTRL_REG1); 637 } 638 639 static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev) 640 { 641 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 642 int ret; 643 644 ret = pinctrl_pm_select_default_state(i2c_dev->dev); 645 if (ret) 646 return ret; 647 648 if (!i2c_dev->hw->has_single_clk_source) { 649 ret = clk_enable(i2c_dev->fast_clk); 650 if (ret < 0) { 651 dev_err(i2c_dev->dev, 652 "Enabling fast clk failed, err %d\n", ret); 653 return ret; 654 } 655 } 656 657 ret = clk_enable(i2c_dev->div_clk); 658 if (ret < 0) { 659 dev_err(i2c_dev->dev, 660 "Enabling div clk failed, err %d\n", ret); 661 clk_disable(i2c_dev->fast_clk); 662 return ret; 663 } 664 665 return 0; 666 } 667 668 static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev) 669 { 670 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 671 672 clk_disable(i2c_dev->div_clk); 673 if (!i2c_dev->hw->has_single_clk_source) 674 clk_disable(i2c_dev->fast_clk); 675 676 return pinctrl_pm_select_idle_state(i2c_dev->dev); 677 } 678 679 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) 680 { 681 unsigned long reg_offset; 682 void __iomem *addr; 683 u32 val; 684 int err; 685 686 if (i2c_dev->hw->has_config_load_reg) { 687 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD); 688 addr = i2c_dev->base + reg_offset; 689 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); 690 691 if (i2c_dev->is_curr_atomic_xfer) 692 err = readl_relaxed_poll_timeout_atomic( 693 addr, val, val == 0, 1000, 694 I2C_CONFIG_LOAD_TIMEOUT); 695 else 696 err = readl_relaxed_poll_timeout( 697 addr, val, val == 0, 1000, 698 I2C_CONFIG_LOAD_TIMEOUT); 699 700 if (err) { 701 dev_warn(i2c_dev->dev, 702 "timeout waiting for config load\n"); 703 return err; 704 } 705 } 706 707 return 0; 708 } 709 710 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev, bool clk_reinit) 711 { 712 u32 val; 713 int err; 714 u32 clk_divisor, clk_multiplier; 715 u32 tsu_thd; 716 u8 tlow, thigh; 717 718 reset_control_assert(i2c_dev->rst); 719 udelay(2); 720 reset_control_deassert(i2c_dev->rst); 721 722 if (i2c_dev->is_dvc) 723 tegra_dvc_init(i2c_dev); 724 725 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN | 726 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); 727 728 if (i2c_dev->hw->has_multi_master_mode) 729 val |= I2C_CNFG_MULTI_MASTER_MODE; 730 731 i2c_writel(i2c_dev, val, I2C_CNFG); 732 i2c_writel(i2c_dev, 0, I2C_INT_MASK); 733 734 /* Make sure clock divisor programmed correctly */ 735 clk_divisor = i2c_dev->hw->clk_divisor_hs_mode; 736 clk_divisor |= i2c_dev->clk_divisor_non_hs_mode << 737 I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT; 738 i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); 739 740 if (i2c_dev->bus_clk_rate > I2C_STANDARD_MODE && 741 i2c_dev->bus_clk_rate <= I2C_FAST_PLUS_MODE) { 742 tlow = i2c_dev->hw->tlow_fast_fastplus_mode; 743 thigh = i2c_dev->hw->thigh_fast_fastplus_mode; 744 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; 745 } else { 746 tlow = i2c_dev->hw->tlow_std_mode; 747 thigh = i2c_dev->hw->thigh_std_mode; 748 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; 749 } 750 751 if (i2c_dev->hw->has_interface_timing_reg) { 752 val = (thigh << I2C_THIGH_SHIFT) | tlow; 753 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0); 754 } 755 756 /* 757 * configure setup and hold times only when tsu_thd is non-zero. 758 * otherwise, preserve the chip default values 759 */ 760 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) 761 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); 762 763 if (!clk_reinit) { 764 clk_multiplier = (tlow + thigh + 2); 765 clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1); 766 err = clk_set_rate(i2c_dev->div_clk, 767 i2c_dev->bus_clk_rate * clk_multiplier); 768 if (err) { 769 dev_err(i2c_dev->dev, 770 "failed changing clock rate: %d\n", err); 771 return err; 772 } 773 } 774 775 if (!i2c_dev->is_dvc) { 776 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG); 777 778 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL; 779 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG); 780 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1); 781 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2); 782 } 783 784 err = tegra_i2c_flush_fifos(i2c_dev); 785 if (err) 786 return err; 787 788 if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg) 789 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE); 790 791 err = tegra_i2c_wait_for_config_load(i2c_dev); 792 if (err) 793 return err; 794 795 return 0; 796 } 797 798 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev) 799 { 800 u32 cnfg; 801 802 /* 803 * NACK interrupt is generated before the I2C controller generates 804 * the STOP condition on the bus. So wait for 2 clock periods 805 * before disabling the controller so that the STOP condition has 806 * been delivered properly. 807 */ 808 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); 809 810 cnfg = i2c_readl(i2c_dev, I2C_CNFG); 811 if (cnfg & I2C_CNFG_PACKET_MODE_EN) 812 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG); 813 814 return tegra_i2c_wait_for_config_load(i2c_dev); 815 } 816 817 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) 818 { 819 u32 status; 820 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 821 struct tegra_i2c_dev *i2c_dev = dev_id; 822 823 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 824 825 if (status == 0) { 826 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n", 827 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), 828 i2c_readl(i2c_dev, I2C_STATUS), 829 i2c_readl(i2c_dev, I2C_CNFG)); 830 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 831 goto err; 832 } 833 834 if (unlikely(status & status_err)) { 835 tegra_i2c_disable_packet_mode(i2c_dev); 836 if (status & I2C_INT_NO_ACK) 837 i2c_dev->msg_err |= I2C_ERR_NO_ACK; 838 if (status & I2C_INT_ARBITRATION_LOST) 839 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; 840 goto err; 841 } 842 843 /* 844 * I2C transfer is terminated during the bus clear so skip 845 * processing the other interrupts. 846 */ 847 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE)) 848 goto err; 849 850 if (!i2c_dev->is_curr_dma_xfer) { 851 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { 852 if (tegra_i2c_empty_rx_fifo(i2c_dev)) { 853 /* 854 * Overflow error condition: message fully sent, 855 * with no XFER_COMPLETE interrupt but hardware 856 * asks to transfer more. 857 */ 858 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW; 859 goto err; 860 } 861 } 862 863 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { 864 if (i2c_dev->msg_buf_remaining) 865 tegra_i2c_fill_tx_fifo(i2c_dev); 866 else 867 tegra_i2c_mask_irq(i2c_dev, 868 I2C_INT_TX_FIFO_DATA_REQ); 869 } 870 } 871 872 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 873 if (i2c_dev->is_dvc) 874 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 875 876 /* 877 * During message read XFER_COMPLETE interrupt is triggered prior to 878 * DMA completion and during message write XFER_COMPLETE interrupt is 879 * triggered after DMA completion. 880 * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer. 881 * so forcing msg_buf_remaining to 0 in DMA mode. 882 */ 883 if (status & I2C_INT_PACKET_XFER_COMPLETE) { 884 if (i2c_dev->is_curr_dma_xfer) 885 i2c_dev->msg_buf_remaining = 0; 886 /* 887 * Underflow error condition: XFER_COMPLETE before message 888 * fully sent. 889 */ 890 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) { 891 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; 892 goto err; 893 } 894 complete(&i2c_dev->msg_complete); 895 } 896 goto done; 897 err: 898 /* An error occurred, mask all interrupts */ 899 tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST | 900 I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ | 901 I2C_INT_RX_FIFO_DATA_REQ); 902 if (i2c_dev->hw->supports_bus_clear) 903 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 904 i2c_writel(i2c_dev, status, I2C_INT_STATUS); 905 if (i2c_dev->is_dvc) 906 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); 907 908 if (i2c_dev->is_curr_dma_xfer) { 909 if (i2c_dev->msg_read) 910 dmaengine_terminate_async(i2c_dev->rx_dma_chan); 911 else 912 dmaengine_terminate_async(i2c_dev->tx_dma_chan); 913 914 complete(&i2c_dev->dma_complete); 915 } 916 917 complete(&i2c_dev->msg_complete); 918 done: 919 return IRQ_HANDLED; 920 } 921 922 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev, 923 size_t len) 924 { 925 u32 val, reg; 926 u8 dma_burst; 927 struct dma_slave_config slv_config = {0}; 928 struct dma_chan *chan; 929 int ret; 930 unsigned long reg_offset; 931 932 if (i2c_dev->hw->has_mst_fifo) 933 reg = I2C_MST_FIFO_CONTROL; 934 else 935 reg = I2C_FIFO_CONTROL; 936 937 if (i2c_dev->is_curr_dma_xfer) { 938 if (len & 0xF) 939 dma_burst = 1; 940 else if (len & 0x10) 941 dma_burst = 4; 942 else 943 dma_burst = 8; 944 945 if (i2c_dev->msg_read) { 946 chan = i2c_dev->rx_dma_chan; 947 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO); 948 slv_config.src_addr = i2c_dev->base_phys + reg_offset; 949 slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 950 slv_config.src_maxburst = dma_burst; 951 952 if (i2c_dev->hw->has_mst_fifo) 953 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst); 954 else 955 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst); 956 } else { 957 chan = i2c_dev->tx_dma_chan; 958 reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO); 959 slv_config.dst_addr = i2c_dev->base_phys + reg_offset; 960 slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 961 slv_config.dst_maxburst = dma_burst; 962 963 if (i2c_dev->hw->has_mst_fifo) 964 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst); 965 else 966 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst); 967 } 968 969 slv_config.device_fc = true; 970 ret = dmaengine_slave_config(chan, &slv_config); 971 if (ret < 0) { 972 dev_err(i2c_dev->dev, "DMA slave config failed: %d\n", 973 ret); 974 dev_err(i2c_dev->dev, "falling back to PIO\n"); 975 tegra_i2c_release_dma(i2c_dev); 976 i2c_dev->is_curr_dma_xfer = false; 977 } else { 978 goto out; 979 } 980 } 981 982 if (i2c_dev->hw->has_mst_fifo) 983 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) | 984 I2C_MST_FIFO_CONTROL_RX_TRIG(1); 985 else 986 val = I2C_FIFO_CONTROL_TX_TRIG(8) | 987 I2C_FIFO_CONTROL_RX_TRIG(1); 988 out: 989 i2c_writel(i2c_dev, val, reg); 990 } 991 992 static unsigned long 993 tegra_i2c_poll_completion_timeout(struct tegra_i2c_dev *i2c_dev, 994 struct completion *complete, 995 unsigned int timeout_ms) 996 { 997 ktime_t ktime = ktime_get(); 998 ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms); 999 1000 do { 1001 u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS); 1002 1003 if (status) { 1004 tegra_i2c_isr(i2c_dev->irq, i2c_dev); 1005 1006 if (completion_done(complete)) { 1007 s64 delta = ktime_ms_delta(ktimeout, ktime); 1008 1009 return msecs_to_jiffies(delta) ?: 1; 1010 } 1011 } 1012 1013 ktime = ktime_get(); 1014 1015 } while (ktime_before(ktime, ktimeout)); 1016 1017 return 0; 1018 } 1019 1020 static unsigned long 1021 tegra_i2c_wait_completion_timeout(struct tegra_i2c_dev *i2c_dev, 1022 struct completion *complete, 1023 unsigned int timeout_ms) 1024 { 1025 unsigned long ret; 1026 1027 if (i2c_dev->is_curr_atomic_xfer) { 1028 ret = tegra_i2c_poll_completion_timeout(i2c_dev, complete, 1029 timeout_ms); 1030 } else { 1031 enable_irq(i2c_dev->irq); 1032 ret = wait_for_completion_timeout(complete, 1033 msecs_to_jiffies(timeout_ms)); 1034 disable_irq(i2c_dev->irq); 1035 1036 /* 1037 * There is a chance that completion may happen after IRQ 1038 * synchronization, which is done by disable_irq(). 1039 */ 1040 if (ret == 0 && completion_done(complete)) { 1041 dev_warn(i2c_dev->dev, 1042 "completion done after timeout\n"); 1043 ret = 1; 1044 } 1045 } 1046 1047 return ret; 1048 } 1049 1050 static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap) 1051 { 1052 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1053 int err; 1054 unsigned long time_left; 1055 u32 reg; 1056 1057 reinit_completion(&i2c_dev->msg_complete); 1058 reg = (I2C_BC_SCLK_THRESHOLD << I2C_BC_SCLK_THRESHOLD_SHIFT) | 1059 I2C_BC_STOP_COND | I2C_BC_TERMINATE; 1060 i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG); 1061 if (i2c_dev->hw->has_config_load_reg) { 1062 err = tegra_i2c_wait_for_config_load(i2c_dev); 1063 if (err) 1064 return err; 1065 } 1066 1067 reg |= I2C_BC_ENABLE; 1068 i2c_writel(i2c_dev, reg, I2C_BUS_CLEAR_CNFG); 1069 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE); 1070 1071 time_left = tegra_i2c_wait_completion_timeout( 1072 i2c_dev, &i2c_dev->msg_complete, 50); 1073 if (time_left == 0) { 1074 dev_err(i2c_dev->dev, "timed out for bus clear\n"); 1075 return -ETIMEDOUT; 1076 } 1077 1078 reg = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS); 1079 if (!(reg & I2C_BC_STATUS)) { 1080 dev_err(i2c_dev->dev, 1081 "un-recovered arbitration lost\n"); 1082 return -EIO; 1083 } 1084 1085 return -EAGAIN; 1086 } 1087 1088 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev, 1089 struct i2c_msg *msg, 1090 enum msg_end_type end_state) 1091 { 1092 u32 packet_header; 1093 u32 int_mask; 1094 unsigned long time_left; 1095 size_t xfer_size; 1096 u32 *buffer = NULL; 1097 int err = 0; 1098 bool dma; 1099 u16 xfer_time = 100; 1100 1101 tegra_i2c_flush_fifos(i2c_dev); 1102 1103 i2c_dev->msg_buf = msg->buf; 1104 i2c_dev->msg_buf_remaining = msg->len; 1105 i2c_dev->msg_err = I2C_ERR_NONE; 1106 i2c_dev->msg_read = (msg->flags & I2C_M_RD); 1107 reinit_completion(&i2c_dev->msg_complete); 1108 1109 if (i2c_dev->msg_read) 1110 xfer_size = msg->len; 1111 else 1112 xfer_size = msg->len + I2C_PACKET_HEADER_SIZE; 1113 1114 xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD); 1115 i2c_dev->is_curr_dma_xfer = (xfer_size > I2C_PIO_MODE_PREFERRED_LEN) && 1116 i2c_dev->dma_buf && 1117 !i2c_dev->is_curr_atomic_xfer; 1118 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size); 1119 dma = i2c_dev->is_curr_dma_xfer; 1120 /* 1121 * Transfer time in mSec = Total bits / transfer rate 1122 * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits 1123 */ 1124 xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC, 1125 i2c_dev->bus_clk_rate); 1126 1127 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST; 1128 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1129 if (dma) { 1130 if (i2c_dev->msg_read) { 1131 dma_sync_single_for_device(i2c_dev->dev, 1132 i2c_dev->dma_phys, 1133 xfer_size, 1134 DMA_FROM_DEVICE); 1135 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1136 if (err < 0) { 1137 dev_err(i2c_dev->dev, 1138 "starting RX DMA failed, err %d\n", 1139 err); 1140 return err; 1141 } 1142 1143 } else { 1144 dma_sync_single_for_cpu(i2c_dev->dev, 1145 i2c_dev->dma_phys, 1146 xfer_size, 1147 DMA_TO_DEVICE); 1148 buffer = i2c_dev->dma_buf; 1149 } 1150 } 1151 1152 packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) | 1153 PACKET_HEADER0_PROTOCOL_I2C | 1154 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) | 1155 (1 << PACKET_HEADER0_PACKET_ID_SHIFT); 1156 if (dma && !i2c_dev->msg_read) 1157 *buffer++ = packet_header; 1158 else 1159 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1160 1161 packet_header = msg->len - 1; 1162 if (dma && !i2c_dev->msg_read) 1163 *buffer++ = packet_header; 1164 else 1165 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1166 1167 packet_header = I2C_HEADER_IE_ENABLE; 1168 if (end_state == MSG_END_CONTINUE) 1169 packet_header |= I2C_HEADER_CONTINUE_XFER; 1170 else if (end_state == MSG_END_REPEAT_START) 1171 packet_header |= I2C_HEADER_REPEAT_START; 1172 if (msg->flags & I2C_M_TEN) { 1173 packet_header |= msg->addr; 1174 packet_header |= I2C_HEADER_10BIT_ADDR; 1175 } else { 1176 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; 1177 } 1178 if (msg->flags & I2C_M_IGNORE_NAK) 1179 packet_header |= I2C_HEADER_CONT_ON_NAK; 1180 if (msg->flags & I2C_M_RD) 1181 packet_header |= I2C_HEADER_READ; 1182 if (dma && !i2c_dev->msg_read) 1183 *buffer++ = packet_header; 1184 else 1185 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO); 1186 1187 if (!i2c_dev->msg_read) { 1188 if (dma) { 1189 memcpy(buffer, msg->buf, msg->len); 1190 dma_sync_single_for_device(i2c_dev->dev, 1191 i2c_dev->dma_phys, 1192 xfer_size, 1193 DMA_TO_DEVICE); 1194 err = tegra_i2c_dma_submit(i2c_dev, xfer_size); 1195 if (err < 0) { 1196 dev_err(i2c_dev->dev, 1197 "starting TX DMA failed, err %d\n", 1198 err); 1199 return err; 1200 } 1201 } else { 1202 tegra_i2c_fill_tx_fifo(i2c_dev); 1203 } 1204 } 1205 1206 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) 1207 int_mask |= I2C_INT_PACKET_XFER_COMPLETE; 1208 if (!dma) { 1209 if (msg->flags & I2C_M_RD) 1210 int_mask |= I2C_INT_RX_FIFO_DATA_REQ; 1211 else if (i2c_dev->msg_buf_remaining) 1212 int_mask |= I2C_INT_TX_FIFO_DATA_REQ; 1213 } 1214 1215 tegra_i2c_unmask_irq(i2c_dev, int_mask); 1216 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n", 1217 i2c_readl(i2c_dev, I2C_INT_MASK)); 1218 1219 if (dma) { 1220 time_left = tegra_i2c_wait_completion_timeout( 1221 i2c_dev, &i2c_dev->dma_complete, xfer_time); 1222 1223 dmaengine_terminate_sync(i2c_dev->msg_read ? 1224 i2c_dev->rx_dma_chan : 1225 i2c_dev->tx_dma_chan); 1226 1227 if (!time_left && !completion_done(&i2c_dev->dma_complete)) { 1228 dev_err(i2c_dev->dev, "DMA transfer timeout\n"); 1229 tegra_i2c_init(i2c_dev, true); 1230 return -ETIMEDOUT; 1231 } 1232 1233 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) { 1234 dma_sync_single_for_cpu(i2c_dev->dev, 1235 i2c_dev->dma_phys, 1236 xfer_size, 1237 DMA_FROM_DEVICE); 1238 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, 1239 msg->len); 1240 } 1241 } 1242 1243 time_left = tegra_i2c_wait_completion_timeout( 1244 i2c_dev, &i2c_dev->msg_complete, xfer_time); 1245 1246 tegra_i2c_mask_irq(i2c_dev, int_mask); 1247 1248 if (time_left == 0) { 1249 dev_err(i2c_dev->dev, "i2c transfer timed out\n"); 1250 tegra_i2c_init(i2c_dev, true); 1251 return -ETIMEDOUT; 1252 } 1253 1254 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", 1255 time_left, completion_done(&i2c_dev->msg_complete), 1256 i2c_dev->msg_err); 1257 1258 i2c_dev->is_curr_dma_xfer = false; 1259 if (likely(i2c_dev->msg_err == I2C_ERR_NONE)) 1260 return 0; 1261 1262 tegra_i2c_init(i2c_dev, true); 1263 /* start recovery upon arbitration loss in single master mode */ 1264 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) { 1265 if (!i2c_dev->is_multimaster_mode) 1266 return i2c_recover_bus(&i2c_dev->adapter); 1267 return -EAGAIN; 1268 } 1269 1270 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { 1271 if (msg->flags & I2C_M_IGNORE_NAK) 1272 return 0; 1273 return -EREMOTEIO; 1274 } 1275 1276 return -EIO; 1277 } 1278 1279 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], 1280 int num) 1281 { 1282 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1283 int i; 1284 int ret; 1285 1286 ret = pm_runtime_get_sync(i2c_dev->dev); 1287 if (ret < 0) { 1288 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); 1289 return ret; 1290 } 1291 1292 for (i = 0; i < num; i++) { 1293 enum msg_end_type end_type = MSG_END_STOP; 1294 1295 if (i < (num - 1)) { 1296 if (msgs[i + 1].flags & I2C_M_NOSTART) 1297 end_type = MSG_END_CONTINUE; 1298 else 1299 end_type = MSG_END_REPEAT_START; 1300 } 1301 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type); 1302 if (ret) 1303 break; 1304 } 1305 1306 pm_runtime_put(i2c_dev->dev); 1307 1308 return ret ?: i; 1309 } 1310 1311 static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap, 1312 struct i2c_msg msgs[], int num) 1313 { 1314 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1315 int ret; 1316 1317 i2c_dev->is_curr_atomic_xfer = true; 1318 ret = tegra_i2c_xfer(adap, msgs, num); 1319 i2c_dev->is_curr_atomic_xfer = false; 1320 1321 return ret; 1322 } 1323 1324 static u32 tegra_i2c_func(struct i2c_adapter *adap) 1325 { 1326 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 1327 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | 1328 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING; 1329 1330 if (i2c_dev->hw->has_continue_xfer_support) 1331 ret |= I2C_FUNC_NOSTART; 1332 return ret; 1333 } 1334 1335 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev) 1336 { 1337 struct device_node *np = i2c_dev->dev->of_node; 1338 int ret; 1339 bool multi_mode; 1340 1341 ret = of_property_read_u32(np, "clock-frequency", 1342 &i2c_dev->bus_clk_rate); 1343 if (ret) 1344 i2c_dev->bus_clk_rate = 100000; /* default clock rate */ 1345 1346 multi_mode = of_property_read_bool(np, "multi-master"); 1347 i2c_dev->is_multimaster_mode = multi_mode; 1348 } 1349 1350 static const struct i2c_algorithm tegra_i2c_algo = { 1351 .master_xfer = tegra_i2c_xfer, 1352 .master_xfer_atomic = tegra_i2c_xfer_atomic, 1353 .functionality = tegra_i2c_func, 1354 }; 1355 1356 /* payload size is only 12 bit */ 1357 static const struct i2c_adapter_quirks tegra_i2c_quirks = { 1358 .flags = I2C_AQ_NO_ZERO_LEN, 1359 .max_read_len = SZ_4K, 1360 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE, 1361 }; 1362 1363 static const struct i2c_adapter_quirks tegra194_i2c_quirks = { 1364 .flags = I2C_AQ_NO_ZERO_LEN, 1365 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE, 1366 }; 1367 1368 static struct i2c_bus_recovery_info tegra_i2c_recovery_info = { 1369 .recover_bus = tegra_i2c_issue_bus_clear, 1370 }; 1371 1372 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = { 1373 .has_continue_xfer_support = false, 1374 .has_per_pkt_xfer_complete_irq = false, 1375 .has_single_clk_source = false, 1376 .clk_divisor_hs_mode = 3, 1377 .clk_divisor_std_mode = 0, 1378 .clk_divisor_fast_mode = 0, 1379 .clk_divisor_fast_plus_mode = 0, 1380 .has_config_load_reg = false, 1381 .has_multi_master_mode = false, 1382 .has_slcg_override_reg = false, 1383 .has_mst_fifo = false, 1384 .quirks = &tegra_i2c_quirks, 1385 .supports_bus_clear = false, 1386 .has_apb_dma = true, 1387 .tlow_std_mode = 0x4, 1388 .thigh_std_mode = 0x2, 1389 .tlow_fast_fastplus_mode = 0x4, 1390 .thigh_fast_fastplus_mode = 0x2, 1391 .setup_hold_time_std_mode = 0x0, 1392 .setup_hold_time_fast_fast_plus_mode = 0x0, 1393 .setup_hold_time_hs_mode = 0x0, 1394 .has_interface_timing_reg = false, 1395 }; 1396 1397 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = { 1398 .has_continue_xfer_support = true, 1399 .has_per_pkt_xfer_complete_irq = false, 1400 .has_single_clk_source = false, 1401 .clk_divisor_hs_mode = 3, 1402 .clk_divisor_std_mode = 0, 1403 .clk_divisor_fast_mode = 0, 1404 .clk_divisor_fast_plus_mode = 0, 1405 .has_config_load_reg = false, 1406 .has_multi_master_mode = false, 1407 .has_slcg_override_reg = false, 1408 .has_mst_fifo = false, 1409 .quirks = &tegra_i2c_quirks, 1410 .supports_bus_clear = false, 1411 .has_apb_dma = true, 1412 .tlow_std_mode = 0x4, 1413 .thigh_std_mode = 0x2, 1414 .tlow_fast_fastplus_mode = 0x4, 1415 .thigh_fast_fastplus_mode = 0x2, 1416 .setup_hold_time_std_mode = 0x0, 1417 .setup_hold_time_fast_fast_plus_mode = 0x0, 1418 .setup_hold_time_hs_mode = 0x0, 1419 .has_interface_timing_reg = false, 1420 }; 1421 1422 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = { 1423 .has_continue_xfer_support = true, 1424 .has_per_pkt_xfer_complete_irq = true, 1425 .has_single_clk_source = true, 1426 .clk_divisor_hs_mode = 1, 1427 .clk_divisor_std_mode = 0x19, 1428 .clk_divisor_fast_mode = 0x19, 1429 .clk_divisor_fast_plus_mode = 0x10, 1430 .has_config_load_reg = false, 1431 .has_multi_master_mode = false, 1432 .has_slcg_override_reg = false, 1433 .has_mst_fifo = false, 1434 .quirks = &tegra_i2c_quirks, 1435 .supports_bus_clear = true, 1436 .has_apb_dma = true, 1437 .tlow_std_mode = 0x4, 1438 .thigh_std_mode = 0x2, 1439 .tlow_fast_fastplus_mode = 0x4, 1440 .thigh_fast_fastplus_mode = 0x2, 1441 .setup_hold_time_std_mode = 0x0, 1442 .setup_hold_time_fast_fast_plus_mode = 0x0, 1443 .setup_hold_time_hs_mode = 0x0, 1444 .has_interface_timing_reg = false, 1445 }; 1446 1447 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = { 1448 .has_continue_xfer_support = true, 1449 .has_per_pkt_xfer_complete_irq = true, 1450 .has_single_clk_source = true, 1451 .clk_divisor_hs_mode = 1, 1452 .clk_divisor_std_mode = 0x19, 1453 .clk_divisor_fast_mode = 0x19, 1454 .clk_divisor_fast_plus_mode = 0x10, 1455 .has_config_load_reg = true, 1456 .has_multi_master_mode = false, 1457 .has_slcg_override_reg = true, 1458 .has_mst_fifo = false, 1459 .quirks = &tegra_i2c_quirks, 1460 .supports_bus_clear = true, 1461 .has_apb_dma = true, 1462 .tlow_std_mode = 0x4, 1463 .thigh_std_mode = 0x2, 1464 .tlow_fast_fastplus_mode = 0x4, 1465 .thigh_fast_fastplus_mode = 0x2, 1466 .setup_hold_time_std_mode = 0x0, 1467 .setup_hold_time_fast_fast_plus_mode = 0x0, 1468 .setup_hold_time_hs_mode = 0x0, 1469 .has_interface_timing_reg = true, 1470 }; 1471 1472 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = { 1473 .has_continue_xfer_support = true, 1474 .has_per_pkt_xfer_complete_irq = true, 1475 .has_single_clk_source = true, 1476 .clk_divisor_hs_mode = 1, 1477 .clk_divisor_std_mode = 0x19, 1478 .clk_divisor_fast_mode = 0x19, 1479 .clk_divisor_fast_plus_mode = 0x10, 1480 .has_config_load_reg = true, 1481 .has_multi_master_mode = false, 1482 .has_slcg_override_reg = true, 1483 .has_mst_fifo = false, 1484 .quirks = &tegra_i2c_quirks, 1485 .supports_bus_clear = true, 1486 .has_apb_dma = true, 1487 .tlow_std_mode = 0x4, 1488 .thigh_std_mode = 0x2, 1489 .tlow_fast_fastplus_mode = 0x4, 1490 .thigh_fast_fastplus_mode = 0x2, 1491 .setup_hold_time_std_mode = 0, 1492 .setup_hold_time_fast_fast_plus_mode = 0, 1493 .setup_hold_time_hs_mode = 0, 1494 .has_interface_timing_reg = true, 1495 }; 1496 1497 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = { 1498 .has_continue_xfer_support = true, 1499 .has_per_pkt_xfer_complete_irq = true, 1500 .has_single_clk_source = true, 1501 .clk_divisor_hs_mode = 1, 1502 .clk_divisor_std_mode = 0x16, 1503 .clk_divisor_fast_mode = 0x19, 1504 .clk_divisor_fast_plus_mode = 0x10, 1505 .has_config_load_reg = true, 1506 .has_multi_master_mode = false, 1507 .has_slcg_override_reg = true, 1508 .has_mst_fifo = false, 1509 .quirks = &tegra_i2c_quirks, 1510 .supports_bus_clear = true, 1511 .has_apb_dma = false, 1512 .tlow_std_mode = 0x4, 1513 .thigh_std_mode = 0x3, 1514 .tlow_fast_fastplus_mode = 0x4, 1515 .thigh_fast_fastplus_mode = 0x2, 1516 .setup_hold_time_std_mode = 0, 1517 .setup_hold_time_fast_fast_plus_mode = 0, 1518 .setup_hold_time_hs_mode = 0, 1519 .has_interface_timing_reg = true, 1520 }; 1521 1522 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = { 1523 .has_continue_xfer_support = true, 1524 .has_per_pkt_xfer_complete_irq = true, 1525 .has_single_clk_source = true, 1526 .clk_divisor_hs_mode = 1, 1527 .clk_divisor_std_mode = 0x4f, 1528 .clk_divisor_fast_mode = 0x3c, 1529 .clk_divisor_fast_plus_mode = 0x16, 1530 .has_config_load_reg = true, 1531 .has_multi_master_mode = true, 1532 .has_slcg_override_reg = true, 1533 .has_mst_fifo = true, 1534 .quirks = &tegra194_i2c_quirks, 1535 .supports_bus_clear = true, 1536 .has_apb_dma = false, 1537 .tlow_std_mode = 0x8, 1538 .thigh_std_mode = 0x7, 1539 .tlow_fast_fastplus_mode = 0x2, 1540 .thigh_fast_fastplus_mode = 0x2, 1541 .setup_hold_time_std_mode = 0x08080808, 1542 .setup_hold_time_fast_fast_plus_mode = 0x02020202, 1543 .setup_hold_time_hs_mode = 0x090909, 1544 .has_interface_timing_reg = true, 1545 }; 1546 1547 /* Match table for of_platform binding */ 1548 static const struct of_device_id tegra_i2c_of_match[] = { 1549 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, }, 1550 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, }, 1551 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, }, 1552 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, }, 1553 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, }, 1554 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, }, 1555 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, }, 1556 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, }, 1557 {}, 1558 }; 1559 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match); 1560 1561 static int tegra_i2c_probe(struct platform_device *pdev) 1562 { 1563 struct tegra_i2c_dev *i2c_dev; 1564 struct resource *res; 1565 struct clk *div_clk; 1566 struct clk *fast_clk; 1567 void __iomem *base; 1568 phys_addr_t base_phys; 1569 int irq; 1570 int ret; 1571 1572 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1573 base_phys = res->start; 1574 base = devm_ioremap_resource(&pdev->dev, res); 1575 if (IS_ERR(base)) 1576 return PTR_ERR(base); 1577 1578 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1579 if (!res) { 1580 dev_err(&pdev->dev, "no irq resource\n"); 1581 return -EINVAL; 1582 } 1583 irq = res->start; 1584 1585 div_clk = devm_clk_get(&pdev->dev, "div-clk"); 1586 if (IS_ERR(div_clk)) { 1587 if (PTR_ERR(div_clk) != -EPROBE_DEFER) 1588 dev_err(&pdev->dev, "missing controller clock\n"); 1589 1590 return PTR_ERR(div_clk); 1591 } 1592 1593 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); 1594 if (!i2c_dev) 1595 return -ENOMEM; 1596 1597 i2c_dev->base = base; 1598 i2c_dev->base_phys = base_phys; 1599 i2c_dev->div_clk = div_clk; 1600 i2c_dev->adapter.algo = &tegra_i2c_algo; 1601 i2c_dev->adapter.retries = 1; 1602 i2c_dev->adapter.timeout = 6 * HZ; 1603 i2c_dev->irq = irq; 1604 i2c_dev->cont_id = pdev->id; 1605 i2c_dev->dev = &pdev->dev; 1606 1607 i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c"); 1608 if (IS_ERR(i2c_dev->rst)) { 1609 dev_err(&pdev->dev, "missing controller reset\n"); 1610 return PTR_ERR(i2c_dev->rst); 1611 } 1612 1613 tegra_i2c_parse_dt(i2c_dev); 1614 1615 i2c_dev->hw = of_device_get_match_data(&pdev->dev); 1616 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node, 1617 "nvidia,tegra20-i2c-dvc"); 1618 i2c_dev->adapter.quirks = i2c_dev->hw->quirks; 1619 i2c_dev->dma_buf_size = i2c_dev->adapter.quirks->max_write_len + 1620 I2C_PACKET_HEADER_SIZE; 1621 init_completion(&i2c_dev->msg_complete); 1622 init_completion(&i2c_dev->dma_complete); 1623 1624 if (!i2c_dev->hw->has_single_clk_source) { 1625 fast_clk = devm_clk_get(&pdev->dev, "fast-clk"); 1626 if (IS_ERR(fast_clk)) { 1627 dev_err(&pdev->dev, "missing fast clock\n"); 1628 return PTR_ERR(fast_clk); 1629 } 1630 i2c_dev->fast_clk = fast_clk; 1631 } 1632 1633 platform_set_drvdata(pdev, i2c_dev); 1634 1635 if (!i2c_dev->hw->has_single_clk_source) { 1636 ret = clk_prepare(i2c_dev->fast_clk); 1637 if (ret < 0) { 1638 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); 1639 return ret; 1640 } 1641 } 1642 1643 if (i2c_dev->bus_clk_rate > I2C_FAST_MODE && 1644 i2c_dev->bus_clk_rate <= I2C_FAST_PLUS_MODE) 1645 i2c_dev->clk_divisor_non_hs_mode = 1646 i2c_dev->hw->clk_divisor_fast_plus_mode; 1647 else if (i2c_dev->bus_clk_rate > I2C_STANDARD_MODE && 1648 i2c_dev->bus_clk_rate <= I2C_FAST_MODE) 1649 i2c_dev->clk_divisor_non_hs_mode = 1650 i2c_dev->hw->clk_divisor_fast_mode; 1651 else 1652 i2c_dev->clk_divisor_non_hs_mode = 1653 i2c_dev->hw->clk_divisor_std_mode; 1654 1655 ret = clk_prepare(i2c_dev->div_clk); 1656 if (ret < 0) { 1657 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); 1658 goto unprepare_fast_clk; 1659 } 1660 1661 pm_runtime_irq_safe(&pdev->dev); 1662 pm_runtime_enable(&pdev->dev); 1663 if (!pm_runtime_enabled(&pdev->dev)) { 1664 ret = tegra_i2c_runtime_resume(&pdev->dev); 1665 if (ret < 0) { 1666 dev_err(&pdev->dev, "runtime resume failed\n"); 1667 goto unprepare_div_clk; 1668 } 1669 } else { 1670 ret = pm_runtime_get_sync(i2c_dev->dev); 1671 if (ret < 0) { 1672 dev_err(&pdev->dev, "runtime resume failed\n"); 1673 goto disable_rpm; 1674 } 1675 } 1676 1677 if (i2c_dev->is_multimaster_mode) { 1678 ret = clk_enable(i2c_dev->div_clk); 1679 if (ret < 0) { 1680 dev_err(i2c_dev->dev, "div_clk enable failed %d\n", 1681 ret); 1682 goto put_rpm; 1683 } 1684 } 1685 1686 if (i2c_dev->hw->supports_bus_clear) 1687 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; 1688 1689 ret = tegra_i2c_init_dma(i2c_dev); 1690 if (ret < 0) 1691 goto disable_div_clk; 1692 1693 ret = tegra_i2c_init(i2c_dev, false); 1694 if (ret) { 1695 dev_err(&pdev->dev, "Failed to initialize i2c controller\n"); 1696 goto release_dma; 1697 } 1698 1699 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN); 1700 1701 ret = devm_request_irq(&pdev->dev, i2c_dev->irq, 1702 tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev); 1703 if (ret) { 1704 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); 1705 goto release_dma; 1706 } 1707 1708 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); 1709 i2c_dev->adapter.owner = THIS_MODULE; 1710 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; 1711 strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev), 1712 sizeof(i2c_dev->adapter.name)); 1713 i2c_dev->adapter.dev.parent = &pdev->dev; 1714 i2c_dev->adapter.nr = pdev->id; 1715 i2c_dev->adapter.dev.of_node = pdev->dev.of_node; 1716 1717 ret = i2c_add_numbered_adapter(&i2c_dev->adapter); 1718 if (ret) 1719 goto release_dma; 1720 1721 pm_runtime_put(&pdev->dev); 1722 1723 return 0; 1724 1725 release_dma: 1726 tegra_i2c_release_dma(i2c_dev); 1727 1728 disable_div_clk: 1729 if (i2c_dev->is_multimaster_mode) 1730 clk_disable(i2c_dev->div_clk); 1731 1732 put_rpm: 1733 if (pm_runtime_enabled(&pdev->dev)) 1734 pm_runtime_put_sync(&pdev->dev); 1735 else 1736 tegra_i2c_runtime_suspend(&pdev->dev); 1737 1738 disable_rpm: 1739 if (pm_runtime_enabled(&pdev->dev)) 1740 pm_runtime_disable(&pdev->dev); 1741 1742 unprepare_div_clk: 1743 clk_unprepare(i2c_dev->div_clk); 1744 1745 unprepare_fast_clk: 1746 if (!i2c_dev->hw->has_single_clk_source) 1747 clk_unprepare(i2c_dev->fast_clk); 1748 1749 return ret; 1750 } 1751 1752 static int tegra_i2c_remove(struct platform_device *pdev) 1753 { 1754 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev); 1755 1756 i2c_del_adapter(&i2c_dev->adapter); 1757 1758 if (i2c_dev->is_multimaster_mode) 1759 clk_disable(i2c_dev->div_clk); 1760 1761 pm_runtime_disable(&pdev->dev); 1762 if (!pm_runtime_status_suspended(&pdev->dev)) 1763 tegra_i2c_runtime_suspend(&pdev->dev); 1764 1765 clk_unprepare(i2c_dev->div_clk); 1766 if (!i2c_dev->hw->has_single_clk_source) 1767 clk_unprepare(i2c_dev->fast_clk); 1768 1769 tegra_i2c_release_dma(i2c_dev); 1770 return 0; 1771 } 1772 1773 static int __maybe_unused tegra_i2c_suspend(struct device *dev) 1774 { 1775 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1776 int err; 1777 1778 i2c_mark_adapter_suspended(&i2c_dev->adapter); 1779 1780 err = pm_runtime_force_suspend(dev); 1781 if (err < 0) 1782 return err; 1783 1784 return 0; 1785 } 1786 1787 static int __maybe_unused tegra_i2c_resume(struct device *dev) 1788 { 1789 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev); 1790 int err; 1791 1792 err = tegra_i2c_runtime_resume(dev); 1793 if (err) 1794 return err; 1795 1796 err = tegra_i2c_init(i2c_dev, false); 1797 if (err) 1798 return err; 1799 1800 err = tegra_i2c_runtime_suspend(dev); 1801 if (err) 1802 return err; 1803 1804 err = pm_runtime_force_resume(dev); 1805 if (err < 0) 1806 return err; 1807 1808 i2c_mark_adapter_resumed(&i2c_dev->adapter); 1809 1810 return 0; 1811 } 1812 1813 static const struct dev_pm_ops tegra_i2c_pm = { 1814 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume) 1815 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume, 1816 NULL) 1817 }; 1818 1819 static struct platform_driver tegra_i2c_driver = { 1820 .probe = tegra_i2c_probe, 1821 .remove = tegra_i2c_remove, 1822 .driver = { 1823 .name = "tegra-i2c", 1824 .of_match_table = tegra_i2c_of_match, 1825 .pm = &tegra_i2c_pm, 1826 }, 1827 }; 1828 1829 module_platform_driver(tegra_i2c_driver); 1830 1831 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver"); 1832 MODULE_AUTHOR("Colin Cross"); 1833 MODULE_LICENSE("GPL v2"); 1834