1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 /* 82562G 10/100 Network Connection 5 * 82562G-2 10/100 Network Connection 6 * 82562GT 10/100 Network Connection 7 * 82562GT-2 10/100 Network Connection 8 * 82562V 10/100 Network Connection 9 * 82562V-2 10/100 Network Connection 10 * 82566DC-2 Gigabit Network Connection 11 * 82566DC Gigabit Network Connection 12 * 82566DM-2 Gigabit Network Connection 13 * 82566DM Gigabit Network Connection 14 * 82566MC Gigabit Network Connection 15 * 82566MM Gigabit Network Connection 16 * 82567LM Gigabit Network Connection 17 * 82567LF Gigabit Network Connection 18 * 82567V Gigabit Network Connection 19 * 82567LM-2 Gigabit Network Connection 20 * 82567LF-2 Gigabit Network Connection 21 * 82567V-2 Gigabit Network Connection 22 * 82567LF-3 Gigabit Network Connection 23 * 82567LM-3 Gigabit Network Connection 24 * 82567LM-4 Gigabit Network Connection 25 * 82577LM Gigabit Network Connection 26 * 82577LC Gigabit Network Connection 27 * 82578DM Gigabit Network Connection 28 * 82578DC Gigabit Network Connection 29 * 82579LM Gigabit Network Connection 30 * 82579V Gigabit Network Connection 31 * Ethernet Connection I217-LM 32 * Ethernet Connection I217-V 33 * Ethernet Connection I218-V 34 * Ethernet Connection I218-LM 35 * Ethernet Connection (2) I218-LM 36 * Ethernet Connection (2) I218-V 37 * Ethernet Connection (3) I218-LM 38 * Ethernet Connection (3) I218-V 39 */ 40 41 #include "e1000.h" 42 43 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 44 /* Offset 04h HSFSTS */ 45 union ich8_hws_flash_status { 46 struct ich8_hsfsts { 47 u16 flcdone:1; /* bit 0 Flash Cycle Done */ 48 u16 flcerr:1; /* bit 1 Flash Cycle Error */ 49 u16 dael:1; /* bit 2 Direct Access error Log */ 50 u16 berasesz:2; /* bit 4:3 Sector Erase Size */ 51 u16 flcinprog:1; /* bit 5 flash cycle in Progress */ 52 u16 reserved1:2; /* bit 13:6 Reserved */ 53 u16 reserved2:6; /* bit 13:6 Reserved */ 54 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */ 55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */ 56 } hsf_status; 57 u16 regval; 58 }; 59 60 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 61 /* Offset 06h FLCTL */ 62 union ich8_hws_flash_ctrl { 63 struct ich8_hsflctl { 64 u16 flcgo:1; /* 0 Flash Cycle Go */ 65 u16 flcycle:2; /* 2:1 Flash Cycle */ 66 u16 reserved:5; /* 7:3 Reserved */ 67 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */ 68 u16 flockdn:6; /* 15:10 Reserved */ 69 } hsf_ctrl; 70 u16 regval; 71 }; 72 73 /* ICH Flash Region Access Permissions */ 74 union ich8_hws_flash_regacc { 75 struct ich8_flracc { 76 u32 grra:8; /* 0:7 GbE region Read Access */ 77 u32 grwa:8; /* 8:15 GbE region Write Access */ 78 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */ 79 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */ 80 } hsf_flregacc; 81 u16 regval; 82 }; 83 84 /* ICH Flash Protected Region */ 85 union ich8_flash_protected_range { 86 struct ich8_pr { 87 u32 base:13; /* 0:12 Protected Range Base */ 88 u32 reserved1:2; /* 13:14 Reserved */ 89 u32 rpe:1; /* 15 Read Protection Enable */ 90 u32 limit:13; /* 16:28 Protected Range Limit */ 91 u32 reserved2:2; /* 29:30 Reserved */ 92 u32 wpe:1; /* 31 Write Protection Enable */ 93 } range; 94 u32 regval; 95 }; 96 97 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); 98 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); 99 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); 100 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 101 u32 offset, u8 byte); 102 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 103 u8 *data); 104 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 105 u16 *data); 106 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 107 u8 size, u16 *data); 108 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 109 u32 *data); 110 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, 111 u32 offset, u32 *data); 112 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, 113 u32 offset, u32 data); 114 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 115 u32 offset, u32 dword); 116 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); 117 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); 118 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); 119 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); 120 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); 121 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); 122 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); 123 static s32 e1000_led_on_pchlan(struct e1000_hw *hw); 124 static s32 e1000_led_off_pchlan(struct e1000_hw *hw); 125 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); 126 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); 127 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); 128 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); 129 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); 130 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); 131 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); 132 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); 133 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); 134 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw); 135 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); 136 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); 137 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); 138 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw); 139 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state); 140 141 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) 142 { 143 return readw(hw->flash_address + reg); 144 } 145 146 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) 147 { 148 return readl(hw->flash_address + reg); 149 } 150 151 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) 152 { 153 writew(val, hw->flash_address + reg); 154 } 155 156 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) 157 { 158 writel(val, hw->flash_address + reg); 159 } 160 161 #define er16flash(reg) __er16flash(hw, (reg)) 162 #define er32flash(reg) __er32flash(hw, (reg)) 163 #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) 164 #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) 165 166 /** 167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers 168 * @hw: pointer to the HW structure 169 * 170 * Test access to the PHY registers by reading the PHY ID registers. If 171 * the PHY ID is already known (e.g. resume path) compare it with known ID, 172 * otherwise assume the read PHY ID is correct if it is valid. 173 * 174 * Assumes the sw/fw/hw semaphore is already acquired. 175 **/ 176 static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) 177 { 178 u16 phy_reg = 0; 179 u32 phy_id = 0; 180 s32 ret_val = 0; 181 u16 retry_count; 182 u32 mac_reg = 0; 183 184 for (retry_count = 0; retry_count < 2; retry_count++) { 185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg); 186 if (ret_val || (phy_reg == 0xFFFF)) 187 continue; 188 phy_id = (u32)(phy_reg << 16); 189 190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg); 191 if (ret_val || (phy_reg == 0xFFFF)) { 192 phy_id = 0; 193 continue; 194 } 195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); 196 break; 197 } 198 199 if (hw->phy.id) { 200 if (hw->phy.id == phy_id) 201 goto out; 202 } else if (phy_id) { 203 hw->phy.id = phy_id; 204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); 205 goto out; 206 } 207 208 /* In case the PHY needs to be in mdio slow mode, 209 * set slow mode and try to get the PHY id again. 210 */ 211 if (hw->mac.type < e1000_pch_lpt) { 212 hw->phy.ops.release(hw); 213 ret_val = e1000_set_mdio_slow_mode_hv(hw); 214 if (!ret_val) 215 ret_val = e1000e_get_phy_id(hw); 216 hw->phy.ops.acquire(hw); 217 } 218 219 if (ret_val) 220 return false; 221 out: 222 if (hw->mac.type >= e1000_pch_lpt) { 223 /* Only unforce SMBus if ME is not active */ 224 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 225 /* Unforce SMBus mode in PHY */ 226 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); 227 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 228 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); 229 230 /* Unforce SMBus mode in MAC */ 231 mac_reg = er32(CTRL_EXT); 232 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 233 ew32(CTRL_EXT, mac_reg); 234 } 235 } 236 237 return true; 238 } 239 240 /** 241 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value 242 * @hw: pointer to the HW structure 243 * 244 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is 245 * used to reset the PHY to a quiescent state when necessary. 246 **/ 247 static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw) 248 { 249 u32 mac_reg; 250 251 /* Set Phy Config Counter to 50msec */ 252 mac_reg = er32(FEXTNVM3); 253 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 254 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 255 ew32(FEXTNVM3, mac_reg); 256 257 /* Toggle LANPHYPC Value bit */ 258 mac_reg = er32(CTRL); 259 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; 260 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; 261 ew32(CTRL, mac_reg); 262 e1e_flush(); 263 usleep_range(10, 20); 264 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; 265 ew32(CTRL, mac_reg); 266 e1e_flush(); 267 268 if (hw->mac.type < e1000_pch_lpt) { 269 msleep(50); 270 } else { 271 u16 count = 20; 272 273 do { 274 usleep_range(5000, 6000); 275 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--); 276 277 msleep(30); 278 } 279 } 280 281 /** 282 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds 283 * @hw: pointer to the HW structure 284 * 285 * Workarounds/flow necessary for PHY initialization during driver load 286 * and resume paths. 287 **/ 288 static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) 289 { 290 struct e1000_adapter *adapter = hw->adapter; 291 u32 mac_reg, fwsm = er32(FWSM); 292 s32 ret_val; 293 294 /* Gate automatic PHY configuration by hardware on managed and 295 * non-managed 82579 and newer adapters. 296 */ 297 e1000_gate_hw_phy_config_ich8lan(hw, true); 298 299 /* It is not possible to be certain of the current state of ULP 300 * so forcibly disable it. 301 */ 302 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; 303 e1000_disable_ulp_lpt_lp(hw, true); 304 305 ret_val = hw->phy.ops.acquire(hw); 306 if (ret_val) { 307 e_dbg("Failed to initialize PHY flow\n"); 308 goto out; 309 } 310 311 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is 312 * inaccessible and resetting the PHY is not blocked, toggle the 313 * LANPHYPC Value bit to force the interconnect to PCIe mode. 314 */ 315 switch (hw->mac.type) { 316 case e1000_pch_lpt: 317 case e1000_pch_spt: 318 case e1000_pch_cnp: 319 case e1000_pch_tgp: 320 if (e1000_phy_is_accessible_pchlan(hw)) 321 break; 322 323 /* Before toggling LANPHYPC, see if PHY is accessible by 324 * forcing MAC to SMBus mode first. 325 */ 326 mac_reg = er32(CTRL_EXT); 327 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 328 ew32(CTRL_EXT, mac_reg); 329 330 /* Wait 50 milliseconds for MAC to finish any retries 331 * that it might be trying to perform from previous 332 * attempts to acknowledge any phy read requests. 333 */ 334 msleep(50); 335 336 /* fall-through */ 337 case e1000_pch2lan: 338 if (e1000_phy_is_accessible_pchlan(hw)) 339 break; 340 341 /* fall-through */ 342 case e1000_pchlan: 343 if ((hw->mac.type == e1000_pchlan) && 344 (fwsm & E1000_ICH_FWSM_FW_VALID)) 345 break; 346 347 if (hw->phy.ops.check_reset_block(hw)) { 348 e_dbg("Required LANPHYPC toggle blocked by ME\n"); 349 ret_val = -E1000_ERR_PHY; 350 break; 351 } 352 353 /* Toggle LANPHYPC Value bit */ 354 e1000_toggle_lanphypc_pch_lpt(hw); 355 if (hw->mac.type >= e1000_pch_lpt) { 356 if (e1000_phy_is_accessible_pchlan(hw)) 357 break; 358 359 /* Toggling LANPHYPC brings the PHY out of SMBus mode 360 * so ensure that the MAC is also out of SMBus mode 361 */ 362 mac_reg = er32(CTRL_EXT); 363 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 364 ew32(CTRL_EXT, mac_reg); 365 366 if (e1000_phy_is_accessible_pchlan(hw)) 367 break; 368 369 ret_val = -E1000_ERR_PHY; 370 } 371 break; 372 default: 373 break; 374 } 375 376 hw->phy.ops.release(hw); 377 if (!ret_val) { 378 379 /* Check to see if able to reset PHY. Print error if not */ 380 if (hw->phy.ops.check_reset_block(hw)) { 381 e_err("Reset blocked by ME\n"); 382 goto out; 383 } 384 385 /* Reset the PHY before any access to it. Doing so, ensures 386 * that the PHY is in a known good state before we read/write 387 * PHY registers. The generic reset is sufficient here, 388 * because we haven't determined the PHY type yet. 389 */ 390 ret_val = e1000e_phy_hw_reset_generic(hw); 391 if (ret_val) 392 goto out; 393 394 /* On a successful reset, possibly need to wait for the PHY 395 * to quiesce to an accessible state before returning control 396 * to the calling function. If the PHY does not quiesce, then 397 * return E1000E_BLK_PHY_RESET, as this is the condition that 398 * the PHY is in. 399 */ 400 ret_val = hw->phy.ops.check_reset_block(hw); 401 if (ret_val) 402 e_err("ME blocked access to PHY after reset\n"); 403 } 404 405 out: 406 /* Ungate automatic PHY configuration on non-managed 82579 */ 407 if ((hw->mac.type == e1000_pch2lan) && 408 !(fwsm & E1000_ICH_FWSM_FW_VALID)) { 409 usleep_range(10000, 11000); 410 e1000_gate_hw_phy_config_ich8lan(hw, false); 411 } 412 413 return ret_val; 414 } 415 416 /** 417 * e1000_init_phy_params_pchlan - Initialize PHY function pointers 418 * @hw: pointer to the HW structure 419 * 420 * Initialize family-specific PHY parameters and function pointers. 421 **/ 422 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) 423 { 424 struct e1000_phy_info *phy = &hw->phy; 425 s32 ret_val; 426 427 phy->addr = 1; 428 phy->reset_delay_us = 100; 429 430 phy->ops.set_page = e1000_set_page_igp; 431 phy->ops.read_reg = e1000_read_phy_reg_hv; 432 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; 433 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; 434 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; 435 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; 436 phy->ops.write_reg = e1000_write_phy_reg_hv; 437 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; 438 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; 439 phy->ops.power_up = e1000_power_up_phy_copper; 440 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 441 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 442 443 phy->id = e1000_phy_unknown; 444 445 ret_val = e1000_init_phy_workarounds_pchlan(hw); 446 if (ret_val) 447 return ret_val; 448 449 if (phy->id == e1000_phy_unknown) 450 switch (hw->mac.type) { 451 default: 452 ret_val = e1000e_get_phy_id(hw); 453 if (ret_val) 454 return ret_val; 455 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) 456 break; 457 /* fall-through */ 458 case e1000_pch2lan: 459 case e1000_pch_lpt: 460 case e1000_pch_spt: 461 case e1000_pch_cnp: 462 case e1000_pch_tgp: 463 /* In case the PHY needs to be in mdio slow mode, 464 * set slow mode and try to get the PHY id again. 465 */ 466 ret_val = e1000_set_mdio_slow_mode_hv(hw); 467 if (ret_val) 468 return ret_val; 469 ret_val = e1000e_get_phy_id(hw); 470 if (ret_val) 471 return ret_val; 472 break; 473 } 474 phy->type = e1000e_get_phy_type_from_id(phy->id); 475 476 switch (phy->type) { 477 case e1000_phy_82577: 478 case e1000_phy_82579: 479 case e1000_phy_i217: 480 phy->ops.check_polarity = e1000_check_polarity_82577; 481 phy->ops.force_speed_duplex = 482 e1000_phy_force_speed_duplex_82577; 483 phy->ops.get_cable_length = e1000_get_cable_length_82577; 484 phy->ops.get_info = e1000_get_phy_info_82577; 485 phy->ops.commit = e1000e_phy_sw_reset; 486 break; 487 case e1000_phy_82578: 488 phy->ops.check_polarity = e1000_check_polarity_m88; 489 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 490 phy->ops.get_cable_length = e1000e_get_cable_length_m88; 491 phy->ops.get_info = e1000e_get_phy_info_m88; 492 break; 493 default: 494 ret_val = -E1000_ERR_PHY; 495 break; 496 } 497 498 return ret_val; 499 } 500 501 /** 502 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers 503 * @hw: pointer to the HW structure 504 * 505 * Initialize family-specific PHY parameters and function pointers. 506 **/ 507 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) 508 { 509 struct e1000_phy_info *phy = &hw->phy; 510 s32 ret_val; 511 u16 i = 0; 512 513 phy->addr = 1; 514 phy->reset_delay_us = 100; 515 516 phy->ops.power_up = e1000_power_up_phy_copper; 517 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; 518 519 /* We may need to do this twice - once for IGP and if that fails, 520 * we'll set BM func pointers and try again 521 */ 522 ret_val = e1000e_determine_phy_address(hw); 523 if (ret_val) { 524 phy->ops.write_reg = e1000e_write_phy_reg_bm; 525 phy->ops.read_reg = e1000e_read_phy_reg_bm; 526 ret_val = e1000e_determine_phy_address(hw); 527 if (ret_val) { 528 e_dbg("Cannot determine PHY addr. Erroring out\n"); 529 return ret_val; 530 } 531 } 532 533 phy->id = 0; 534 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && 535 (i++ < 100)) { 536 usleep_range(1000, 1100); 537 ret_val = e1000e_get_phy_id(hw); 538 if (ret_val) 539 return ret_val; 540 } 541 542 /* Verify phy id */ 543 switch (phy->id) { 544 case IGP03E1000_E_PHY_ID: 545 phy->type = e1000_phy_igp_3; 546 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 547 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; 548 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; 549 phy->ops.get_info = e1000e_get_phy_info_igp; 550 phy->ops.check_polarity = e1000_check_polarity_igp; 551 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; 552 break; 553 case IFE_E_PHY_ID: 554 case IFE_PLUS_E_PHY_ID: 555 case IFE_C_E_PHY_ID: 556 phy->type = e1000_phy_ife; 557 phy->autoneg_mask = E1000_ALL_NOT_GIG; 558 phy->ops.get_info = e1000_get_phy_info_ife; 559 phy->ops.check_polarity = e1000_check_polarity_ife; 560 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; 561 break; 562 case BME1000_E_PHY_ID: 563 phy->type = e1000_phy_bm; 564 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 565 phy->ops.read_reg = e1000e_read_phy_reg_bm; 566 phy->ops.write_reg = e1000e_write_phy_reg_bm; 567 phy->ops.commit = e1000e_phy_sw_reset; 568 phy->ops.get_info = e1000e_get_phy_info_m88; 569 phy->ops.check_polarity = e1000_check_polarity_m88; 570 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 571 break; 572 default: 573 return -E1000_ERR_PHY; 574 } 575 576 return 0; 577 } 578 579 /** 580 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers 581 * @hw: pointer to the HW structure 582 * 583 * Initialize family-specific NVM parameters and function 584 * pointers. 585 **/ 586 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) 587 { 588 struct e1000_nvm_info *nvm = &hw->nvm; 589 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 590 u32 gfpreg, sector_base_addr, sector_end_addr; 591 u16 i; 592 u32 nvm_size; 593 594 nvm->type = e1000_nvm_flash_sw; 595 596 if (hw->mac.type >= e1000_pch_spt) { 597 /* in SPT, gfpreg doesn't exist. NVM size is taken from the 598 * STRAP register. This is because in SPT the GbE Flash region 599 * is no longer accessed through the flash registers. Instead, 600 * the mechanism has changed, and the Flash region access 601 * registers are now implemented in GbE memory space. 602 */ 603 nvm->flash_base_addr = 0; 604 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1) 605 * NVM_SIZE_MULTIPLIER; 606 nvm->flash_bank_size = nvm_size / 2; 607 /* Adjust to word count */ 608 nvm->flash_bank_size /= sizeof(u16); 609 /* Set the base address for flash register access */ 610 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR; 611 } else { 612 /* Can't read flash registers if register set isn't mapped. */ 613 if (!hw->flash_address) { 614 e_dbg("ERROR: Flash registers not mapped\n"); 615 return -E1000_ERR_CONFIG; 616 } 617 618 gfpreg = er32flash(ICH_FLASH_GFPREG); 619 620 /* sector_X_addr is a "sector"-aligned address (4096 bytes) 621 * Add 1 to sector_end_addr since this sector is included in 622 * the overall size. 623 */ 624 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 625 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 626 627 /* flash_base_addr is byte-aligned */ 628 nvm->flash_base_addr = sector_base_addr 629 << FLASH_SECTOR_ADDR_SHIFT; 630 631 /* find total size of the NVM, then cut in half since the total 632 * size represents two separate NVM banks. 633 */ 634 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr) 635 << FLASH_SECTOR_ADDR_SHIFT); 636 nvm->flash_bank_size /= 2; 637 /* Adjust to word count */ 638 nvm->flash_bank_size /= sizeof(u16); 639 } 640 641 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; 642 643 /* Clear shadow ram */ 644 for (i = 0; i < nvm->word_size; i++) { 645 dev_spec->shadow_ram[i].modified = false; 646 dev_spec->shadow_ram[i].value = 0xFFFF; 647 } 648 649 return 0; 650 } 651 652 /** 653 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers 654 * @hw: pointer to the HW structure 655 * 656 * Initialize family-specific MAC parameters and function 657 * pointers. 658 **/ 659 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) 660 { 661 struct e1000_mac_info *mac = &hw->mac; 662 663 /* Set media type function pointer */ 664 hw->phy.media_type = e1000_media_type_copper; 665 666 /* Set mta register count */ 667 mac->mta_reg_count = 32; 668 /* Set rar entry count */ 669 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 670 if (mac->type == e1000_ich8lan) 671 mac->rar_entry_count--; 672 /* FWSM register */ 673 mac->has_fwsm = true; 674 /* ARC subsystem not supported */ 675 mac->arc_subsystem_valid = false; 676 /* Adaptive IFS supported */ 677 mac->adaptive_ifs = true; 678 679 /* LED and other operations */ 680 switch (mac->type) { 681 case e1000_ich8lan: 682 case e1000_ich9lan: 683 case e1000_ich10lan: 684 /* check management mode */ 685 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; 686 /* ID LED init */ 687 mac->ops.id_led_init = e1000e_id_led_init_generic; 688 /* blink LED */ 689 mac->ops.blink_led = e1000e_blink_led_generic; 690 /* setup LED */ 691 mac->ops.setup_led = e1000e_setup_led_generic; 692 /* cleanup LED */ 693 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; 694 /* turn on/off LED */ 695 mac->ops.led_on = e1000_led_on_ich8lan; 696 mac->ops.led_off = e1000_led_off_ich8lan; 697 break; 698 case e1000_pch2lan: 699 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; 700 mac->ops.rar_set = e1000_rar_set_pch2lan; 701 /* fall-through */ 702 case e1000_pch_lpt: 703 case e1000_pch_spt: 704 case e1000_pch_cnp: 705 case e1000_pch_tgp: 706 case e1000_pchlan: 707 /* check management mode */ 708 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; 709 /* ID LED init */ 710 mac->ops.id_led_init = e1000_id_led_init_pchlan; 711 /* setup LED */ 712 mac->ops.setup_led = e1000_setup_led_pchlan; 713 /* cleanup LED */ 714 mac->ops.cleanup_led = e1000_cleanup_led_pchlan; 715 /* turn on/off LED */ 716 mac->ops.led_on = e1000_led_on_pchlan; 717 mac->ops.led_off = e1000_led_off_pchlan; 718 break; 719 default: 720 break; 721 } 722 723 if (mac->type >= e1000_pch_lpt) { 724 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; 725 mac->ops.rar_set = e1000_rar_set_pch_lpt; 726 mac->ops.setup_physical_interface = 727 e1000_setup_copper_link_pch_lpt; 728 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt; 729 } 730 731 /* Enable PCS Lock-loss workaround for ICH8 */ 732 if (mac->type == e1000_ich8lan) 733 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); 734 735 return 0; 736 } 737 738 /** 739 * __e1000_access_emi_reg_locked - Read/write EMI register 740 * @hw: pointer to the HW structure 741 * @addr: EMI address to program 742 * @data: pointer to value to read/write from/to the EMI address 743 * @read: boolean flag to indicate read or write 744 * 745 * This helper function assumes the SW/FW/HW Semaphore is already acquired. 746 **/ 747 static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, 748 u16 *data, bool read) 749 { 750 s32 ret_val; 751 752 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); 753 if (ret_val) 754 return ret_val; 755 756 if (read) 757 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); 758 else 759 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); 760 761 return ret_val; 762 } 763 764 /** 765 * e1000_read_emi_reg_locked - Read Extended Management Interface register 766 * @hw: pointer to the HW structure 767 * @addr: EMI address to program 768 * @data: value to be read from the EMI address 769 * 770 * Assumes the SW/FW/HW Semaphore is already acquired. 771 **/ 772 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) 773 { 774 return __e1000_access_emi_reg_locked(hw, addr, data, true); 775 } 776 777 /** 778 * e1000_write_emi_reg_locked - Write Extended Management Interface register 779 * @hw: pointer to the HW structure 780 * @addr: EMI address to program 781 * @data: value to be written to the EMI address 782 * 783 * Assumes the SW/FW/HW Semaphore is already acquired. 784 **/ 785 s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) 786 { 787 return __e1000_access_emi_reg_locked(hw, addr, &data, false); 788 } 789 790 /** 791 * e1000_set_eee_pchlan - Enable/disable EEE support 792 * @hw: pointer to the HW structure 793 * 794 * Enable/disable EEE based on setting in dev_spec structure, the duplex of 795 * the link and the EEE capabilities of the link partner. The LPI Control 796 * register bits will remain set only if/when link is up. 797 * 798 * EEE LPI must not be asserted earlier than one second after link is up. 799 * On 82579, EEE LPI should not be enabled until such time otherwise there 800 * can be link issues with some switches. Other devices can have EEE LPI 801 * enabled immediately upon link up since they have a timer in hardware which 802 * prevents LPI from being asserted too early. 803 **/ 804 s32 e1000_set_eee_pchlan(struct e1000_hw *hw) 805 { 806 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 807 s32 ret_val; 808 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data; 809 810 switch (hw->phy.type) { 811 case e1000_phy_82579: 812 lpa = I82579_EEE_LP_ABILITY; 813 pcs_status = I82579_EEE_PCS_STATUS; 814 adv_addr = I82579_EEE_ADVERTISEMENT; 815 break; 816 case e1000_phy_i217: 817 lpa = I217_EEE_LP_ABILITY; 818 pcs_status = I217_EEE_PCS_STATUS; 819 adv_addr = I217_EEE_ADVERTISEMENT; 820 break; 821 default: 822 return 0; 823 } 824 825 ret_val = hw->phy.ops.acquire(hw); 826 if (ret_val) 827 return ret_val; 828 829 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); 830 if (ret_val) 831 goto release; 832 833 /* Clear bits that enable EEE in various speeds */ 834 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; 835 836 /* Enable EEE if not disabled by user */ 837 if (!dev_spec->eee_disable) { 838 /* Save off link partner's EEE ability */ 839 ret_val = e1000_read_emi_reg_locked(hw, lpa, 840 &dev_spec->eee_lp_ability); 841 if (ret_val) 842 goto release; 843 844 /* Read EEE advertisement */ 845 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv); 846 if (ret_val) 847 goto release; 848 849 /* Enable EEE only for speeds in which the link partner is 850 * EEE capable and for which we advertise EEE. 851 */ 852 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) 853 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; 854 855 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { 856 e1e_rphy_locked(hw, MII_LPA, &data); 857 if (data & LPA_100FULL) 858 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; 859 else 860 /* EEE is not supported in 100Half, so ignore 861 * partner's EEE in 100 ability if full-duplex 862 * is not advertised. 863 */ 864 dev_spec->eee_lp_ability &= 865 ~I82579_EEE_100_SUPPORTED; 866 } 867 } 868 869 if (hw->phy.type == e1000_phy_82579) { 870 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 871 &data); 872 if (ret_val) 873 goto release; 874 875 data &= ~I82579_LPI_100_PLL_SHUT; 876 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT, 877 data); 878 } 879 880 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ 881 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); 882 if (ret_val) 883 goto release; 884 885 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); 886 release: 887 hw->phy.ops.release(hw); 888 889 return ret_val; 890 } 891 892 /** 893 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP 894 * @hw: pointer to the HW structure 895 * @link: link up bool flag 896 * 897 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications 898 * preventing further DMA write requests. Workaround the issue by disabling 899 * the de-assertion of the clock request when in 1Gpbs mode. 900 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link 901 * speeds in order to avoid Tx hangs. 902 **/ 903 static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) 904 { 905 u32 fextnvm6 = er32(FEXTNVM6); 906 u32 status = er32(STATUS); 907 s32 ret_val = 0; 908 u16 reg; 909 910 if (link && (status & E1000_STATUS_SPEED_1000)) { 911 ret_val = hw->phy.ops.acquire(hw); 912 if (ret_val) 913 return ret_val; 914 915 ret_val = 916 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 917 ®); 918 if (ret_val) 919 goto release; 920 921 ret_val = 922 e1000e_write_kmrn_reg_locked(hw, 923 E1000_KMRNCTRLSTA_K1_CONFIG, 924 reg & 925 ~E1000_KMRNCTRLSTA_K1_ENABLE); 926 if (ret_val) 927 goto release; 928 929 usleep_range(10, 20); 930 931 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK); 932 933 ret_val = 934 e1000e_write_kmrn_reg_locked(hw, 935 E1000_KMRNCTRLSTA_K1_CONFIG, 936 reg); 937 release: 938 hw->phy.ops.release(hw); 939 } else { 940 /* clear FEXTNVM6 bit 8 on link down or 10/100 */ 941 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK; 942 943 if ((hw->phy.revision > 5) || !link || 944 ((status & E1000_STATUS_SPEED_100) && 945 (status & E1000_STATUS_FD))) 946 goto update_fextnvm6; 947 948 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®); 949 if (ret_val) 950 return ret_val; 951 952 /* Clear link status transmit timeout */ 953 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK; 954 955 if (status & E1000_STATUS_SPEED_100) { 956 /* Set inband Tx timeout to 5x10us for 100Half */ 957 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 958 959 /* Do not extend the K1 entry latency for 100Half */ 960 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 961 } else { 962 /* Set inband Tx timeout to 50x10us for 10Full/Half */ 963 reg |= 50 << 964 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT; 965 966 /* Extend the K1 entry latency for 10 Mbps */ 967 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION; 968 } 969 970 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg); 971 if (ret_val) 972 return ret_val; 973 974 update_fextnvm6: 975 ew32(FEXTNVM6, fextnvm6); 976 } 977 978 return ret_val; 979 } 980 981 /** 982 * e1000_platform_pm_pch_lpt - Set platform power management values 983 * @hw: pointer to the HW structure 984 * @link: bool indicating link status 985 * 986 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like" 987 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed 988 * when link is up (which must not exceed the maximum latency supported 989 * by the platform), otherwise specify there is no LTR requirement. 990 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop 991 * latencies in the LTR Extended Capability Structure in the PCIe Extended 992 * Capability register set, on this device LTR is set by writing the 993 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and 994 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB) 995 * message to the PMC. 996 **/ 997 static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link) 998 { 999 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) | 1000 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND; 1001 u16 lat_enc = 0; /* latency encoded */ 1002 1003 if (link) { 1004 u16 speed, duplex, scale = 0; 1005 u16 max_snoop, max_nosnoop; 1006 u16 max_ltr_enc; /* max LTR latency encoded */ 1007 u64 value; 1008 u32 rxa; 1009 1010 if (!hw->adapter->max_frame_size) { 1011 e_dbg("max_frame_size not set.\n"); 1012 return -E1000_ERR_CONFIG; 1013 } 1014 1015 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 1016 if (!speed) { 1017 e_dbg("Speed not set.\n"); 1018 return -E1000_ERR_CONFIG; 1019 } 1020 1021 /* Rx Packet Buffer Allocation size (KB) */ 1022 rxa = er32(PBA) & E1000_PBA_RXA_MASK; 1023 1024 /* Determine the maximum latency tolerated by the device. 1025 * 1026 * Per the PCIe spec, the tolerated latencies are encoded as 1027 * a 3-bit encoded scale (only 0-5 are valid) multiplied by 1028 * a 10-bit value (0-1023) to provide a range from 1 ns to 1029 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns, 1030 * 1=2^5ns, 2=2^10ns,...5=2^25ns. 1031 */ 1032 rxa *= 512; 1033 value = (rxa > hw->adapter->max_frame_size) ? 1034 (rxa - hw->adapter->max_frame_size) * (16000 / speed) : 1035 0; 1036 1037 while (value > PCI_LTR_VALUE_MASK) { 1038 scale++; 1039 value = DIV_ROUND_UP(value, BIT(5)); 1040 } 1041 if (scale > E1000_LTRV_SCALE_MAX) { 1042 e_dbg("Invalid LTR latency scale %d\n", scale); 1043 return -E1000_ERR_CONFIG; 1044 } 1045 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value); 1046 1047 /* Determine the maximum latency tolerated by the platform */ 1048 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT, 1049 &max_snoop); 1050 pci_read_config_word(hw->adapter->pdev, 1051 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop); 1052 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop); 1053 1054 if (lat_enc > max_ltr_enc) 1055 lat_enc = max_ltr_enc; 1056 } 1057 1058 /* Set Snoop and No-Snoop latencies the same */ 1059 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT); 1060 ew32(LTRV, reg); 1061 1062 return 0; 1063 } 1064 1065 /** 1066 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP 1067 * @hw: pointer to the HW structure 1068 * @to_sx: boolean indicating a system power state transition to Sx 1069 * 1070 * When link is down, configure ULP mode to significantly reduce the power 1071 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the 1072 * ME firmware to start the ULP configuration. If not on an ME enabled 1073 * system, configure the ULP mode by software. 1074 */ 1075 s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) 1076 { 1077 u32 mac_reg; 1078 s32 ret_val = 0; 1079 u16 phy_reg; 1080 u16 oem_reg = 0; 1081 1082 if ((hw->mac.type < e1000_pch_lpt) || 1083 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1084 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1085 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1086 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1087 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on)) 1088 return 0; 1089 1090 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1091 /* Request ME configure ULP mode in the PHY */ 1092 mac_reg = er32(H2ME); 1093 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS; 1094 ew32(H2ME, mac_reg); 1095 1096 goto out; 1097 } 1098 1099 if (!to_sx) { 1100 int i = 0; 1101 1102 /* Poll up to 5 seconds for Cable Disconnected indication */ 1103 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) { 1104 /* Bail if link is re-acquired */ 1105 if (er32(STATUS) & E1000_STATUS_LU) 1106 return -E1000_ERR_PHY; 1107 1108 if (i++ == 100) 1109 break; 1110 1111 msleep(50); 1112 } 1113 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n", 1114 (er32(FEXT) & 1115 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50); 1116 } 1117 1118 ret_val = hw->phy.ops.acquire(hw); 1119 if (ret_val) 1120 goto out; 1121 1122 /* Force SMBus mode in PHY */ 1123 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1124 if (ret_val) 1125 goto release; 1126 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS; 1127 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1128 1129 /* Force SMBus mode in MAC */ 1130 mac_reg = er32(CTRL_EXT); 1131 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1132 ew32(CTRL_EXT, mac_reg); 1133 1134 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable 1135 * LPLU and disable Gig speed when entering ULP 1136 */ 1137 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) { 1138 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS, 1139 &oem_reg); 1140 if (ret_val) 1141 goto release; 1142 1143 phy_reg = oem_reg; 1144 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS; 1145 1146 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1147 phy_reg); 1148 1149 if (ret_val) 1150 goto release; 1151 } 1152 1153 /* Set Inband ULP Exit, Reset to SMBus mode and 1154 * Disable SMBus Release on PERST# in PHY 1155 */ 1156 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1157 if (ret_val) 1158 goto release; 1159 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS | 1160 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1161 if (to_sx) { 1162 if (er32(WUFC) & E1000_WUFC_LNKC) 1163 phy_reg |= I218_ULP_CONFIG1_WOL_HOST; 1164 else 1165 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1166 1167 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP; 1168 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT; 1169 } else { 1170 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT; 1171 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP; 1172 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST; 1173 } 1174 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1175 1176 /* Set Disable SMBus Release on PERST# in MAC */ 1177 mac_reg = er32(FEXTNVM7); 1178 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST; 1179 ew32(FEXTNVM7, mac_reg); 1180 1181 /* Commit ULP changes in PHY by starting auto ULP configuration */ 1182 phy_reg |= I218_ULP_CONFIG1_START; 1183 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1184 1185 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) && 1186 to_sx && (er32(STATUS) & E1000_STATUS_LU)) { 1187 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS, 1188 oem_reg); 1189 if (ret_val) 1190 goto release; 1191 } 1192 1193 release: 1194 hw->phy.ops.release(hw); 1195 out: 1196 if (ret_val) 1197 e_dbg("Error in ULP enable flow: %d\n", ret_val); 1198 else 1199 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on; 1200 1201 return ret_val; 1202 } 1203 1204 /** 1205 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP 1206 * @hw: pointer to the HW structure 1207 * @force: boolean indicating whether or not to force disabling ULP 1208 * 1209 * Un-configure ULP mode when link is up, the system is transitioned from 1210 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled 1211 * system, poll for an indication from ME that ULP has been un-configured. 1212 * If not on an ME enabled system, un-configure the ULP mode by software. 1213 * 1214 * During nominal operation, this function is called when link is acquired 1215 * to disable ULP mode (force=false); otherwise, for example when unloading 1216 * the driver or during Sx->S0 transitions, this is called with force=true 1217 * to forcibly disable ULP. 1218 */ 1219 static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) 1220 { 1221 s32 ret_val = 0; 1222 u32 mac_reg; 1223 u16 phy_reg; 1224 int i = 0; 1225 1226 if ((hw->mac.type < e1000_pch_lpt) || 1227 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) || 1228 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) || 1229 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) || 1230 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) || 1231 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off)) 1232 return 0; 1233 1234 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) { 1235 if (force) { 1236 /* Request ME un-configure ULP mode in the PHY */ 1237 mac_reg = er32(H2ME); 1238 mac_reg &= ~E1000_H2ME_ULP; 1239 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS; 1240 ew32(H2ME, mac_reg); 1241 } 1242 1243 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */ 1244 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) { 1245 if (i++ == 30) { 1246 ret_val = -E1000_ERR_PHY; 1247 goto out; 1248 } 1249 1250 usleep_range(10000, 11000); 1251 } 1252 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10); 1253 1254 if (force) { 1255 mac_reg = er32(H2ME); 1256 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS; 1257 ew32(H2ME, mac_reg); 1258 } else { 1259 /* Clear H2ME.ULP after ME ULP configuration */ 1260 mac_reg = er32(H2ME); 1261 mac_reg &= ~E1000_H2ME_ULP; 1262 ew32(H2ME, mac_reg); 1263 } 1264 1265 goto out; 1266 } 1267 1268 ret_val = hw->phy.ops.acquire(hw); 1269 if (ret_val) 1270 goto out; 1271 1272 if (force) 1273 /* Toggle LANPHYPC Value bit */ 1274 e1000_toggle_lanphypc_pch_lpt(hw); 1275 1276 /* Unforce SMBus mode in PHY */ 1277 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg); 1278 if (ret_val) { 1279 /* The MAC might be in PCIe mode, so temporarily force to 1280 * SMBus mode in order to access the PHY. 1281 */ 1282 mac_reg = er32(CTRL_EXT); 1283 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; 1284 ew32(CTRL_EXT, mac_reg); 1285 1286 msleep(50); 1287 1288 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, 1289 &phy_reg); 1290 if (ret_val) 1291 goto release; 1292 } 1293 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; 1294 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg); 1295 1296 /* Unforce SMBus mode in MAC */ 1297 mac_reg = er32(CTRL_EXT); 1298 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; 1299 ew32(CTRL_EXT, mac_reg); 1300 1301 /* When ULP mode was previously entered, K1 was disabled by the 1302 * hardware. Re-Enable K1 in the PHY when exiting ULP. 1303 */ 1304 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg); 1305 if (ret_val) 1306 goto release; 1307 phy_reg |= HV_PM_CTRL_K1_ENABLE; 1308 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg); 1309 1310 /* Clear ULP enabled configuration */ 1311 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg); 1312 if (ret_val) 1313 goto release; 1314 phy_reg &= ~(I218_ULP_CONFIG1_IND | 1315 I218_ULP_CONFIG1_STICKY_ULP | 1316 I218_ULP_CONFIG1_RESET_TO_SMBUS | 1317 I218_ULP_CONFIG1_WOL_HOST | 1318 I218_ULP_CONFIG1_INBAND_EXIT | 1319 I218_ULP_CONFIG1_EN_ULP_LANPHYPC | 1320 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST | 1321 I218_ULP_CONFIG1_DISABLE_SMB_PERST); 1322 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1323 1324 /* Commit ULP changes by starting auto ULP configuration */ 1325 phy_reg |= I218_ULP_CONFIG1_START; 1326 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg); 1327 1328 /* Clear Disable SMBus Release on PERST# in MAC */ 1329 mac_reg = er32(FEXTNVM7); 1330 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST; 1331 ew32(FEXTNVM7, mac_reg); 1332 1333 release: 1334 hw->phy.ops.release(hw); 1335 if (force) { 1336 e1000_phy_hw_reset(hw); 1337 msleep(50); 1338 } 1339 out: 1340 if (ret_val) 1341 e_dbg("Error in ULP disable flow: %d\n", ret_val); 1342 else 1343 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off; 1344 1345 return ret_val; 1346 } 1347 1348 /** 1349 * e1000_check_for_copper_link_ich8lan - Check for link (Copper) 1350 * @hw: pointer to the HW structure 1351 * 1352 * Checks to see of the link status of the hardware has changed. If a 1353 * change in link status has been detected, then we read the PHY registers 1354 * to get the current speed/duplex if link exists. 1355 **/ 1356 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) 1357 { 1358 struct e1000_mac_info *mac = &hw->mac; 1359 s32 ret_val, tipg_reg = 0; 1360 u16 emi_addr, emi_val = 0; 1361 bool link; 1362 u16 phy_reg; 1363 1364 /* We only want to go out to the PHY registers to see if Auto-Neg 1365 * has completed and/or if our link status has changed. The 1366 * get_link_status flag is set upon receiving a Link Status 1367 * Change or Rx Sequence Error interrupt. 1368 */ 1369 if (!mac->get_link_status) 1370 return 0; 1371 mac->get_link_status = false; 1372 1373 /* First we want to see if the MII Status Register reports 1374 * link. If so, then we want to get the current speed/duplex 1375 * of the PHY. 1376 */ 1377 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 1378 if (ret_val) 1379 goto out; 1380 1381 if (hw->mac.type == e1000_pchlan) { 1382 ret_val = e1000_k1_gig_workaround_hv(hw, link); 1383 if (ret_val) 1384 goto out; 1385 } 1386 1387 /* When connected at 10Mbps half-duplex, some parts are excessively 1388 * aggressive resulting in many collisions. To avoid this, increase 1389 * the IPG and reduce Rx latency in the PHY. 1390 */ 1391 if ((hw->mac.type >= e1000_pch2lan) && link) { 1392 u16 speed, duplex; 1393 1394 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex); 1395 tipg_reg = er32(TIPG); 1396 tipg_reg &= ~E1000_TIPG_IPGT_MASK; 1397 1398 if (duplex == HALF_DUPLEX && speed == SPEED_10) { 1399 tipg_reg |= 0xFF; 1400 /* Reduce Rx latency in analog PHY */ 1401 emi_val = 0; 1402 } else if (hw->mac.type >= e1000_pch_spt && 1403 duplex == FULL_DUPLEX && speed != SPEED_1000) { 1404 tipg_reg |= 0xC; 1405 emi_val = 1; 1406 } else { 1407 1408 /* Roll back the default values */ 1409 tipg_reg |= 0x08; 1410 emi_val = 1; 1411 } 1412 1413 ew32(TIPG, tipg_reg); 1414 1415 ret_val = hw->phy.ops.acquire(hw); 1416 if (ret_val) 1417 goto out; 1418 1419 if (hw->mac.type == e1000_pch2lan) 1420 emi_addr = I82579_RX_CONFIG; 1421 else 1422 emi_addr = I217_RX_CONFIG; 1423 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val); 1424 1425 if (hw->mac.type >= e1000_pch_lpt) { 1426 u16 phy_reg; 1427 1428 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg); 1429 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK; 1430 if (speed == SPEED_100 || speed == SPEED_10) 1431 phy_reg |= 0x3E8; 1432 else 1433 phy_reg |= 0xFA; 1434 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg); 1435 1436 if (speed == SPEED_1000) { 1437 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL, 1438 &phy_reg); 1439 1440 phy_reg |= HV_PM_CTRL_K1_CLK_REQ; 1441 1442 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL, 1443 phy_reg); 1444 } 1445 } 1446 hw->phy.ops.release(hw); 1447 1448 if (ret_val) 1449 goto out; 1450 1451 if (hw->mac.type >= e1000_pch_spt) { 1452 u16 data; 1453 u16 ptr_gap; 1454 1455 if (speed == SPEED_1000) { 1456 ret_val = hw->phy.ops.acquire(hw); 1457 if (ret_val) 1458 goto out; 1459 1460 ret_val = e1e_rphy_locked(hw, 1461 PHY_REG(776, 20), 1462 &data); 1463 if (ret_val) { 1464 hw->phy.ops.release(hw); 1465 goto out; 1466 } 1467 1468 ptr_gap = (data & (0x3FF << 2)) >> 2; 1469 if (ptr_gap < 0x18) { 1470 data &= ~(0x3FF << 2); 1471 data |= (0x18 << 2); 1472 ret_val = 1473 e1e_wphy_locked(hw, 1474 PHY_REG(776, 20), 1475 data); 1476 } 1477 hw->phy.ops.release(hw); 1478 if (ret_val) 1479 goto out; 1480 } else { 1481 ret_val = hw->phy.ops.acquire(hw); 1482 if (ret_val) 1483 goto out; 1484 1485 ret_val = e1e_wphy_locked(hw, 1486 PHY_REG(776, 20), 1487 0xC023); 1488 hw->phy.ops.release(hw); 1489 if (ret_val) 1490 goto out; 1491 1492 } 1493 } 1494 } 1495 1496 /* I217 Packet Loss issue: 1497 * ensure that FEXTNVM4 Beacon Duration is set correctly 1498 * on power up. 1499 * Set the Beacon Duration for I217 to 8 usec 1500 */ 1501 if (hw->mac.type >= e1000_pch_lpt) { 1502 u32 mac_reg; 1503 1504 mac_reg = er32(FEXTNVM4); 1505 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 1506 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; 1507 ew32(FEXTNVM4, mac_reg); 1508 } 1509 1510 /* Work-around I218 hang issue */ 1511 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 1512 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) || 1513 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) || 1514 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) { 1515 ret_val = e1000_k1_workaround_lpt_lp(hw, link); 1516 if (ret_val) 1517 goto out; 1518 } 1519 if (hw->mac.type >= e1000_pch_lpt) { 1520 /* Set platform power management values for 1521 * Latency Tolerance Reporting (LTR) 1522 */ 1523 ret_val = e1000_platform_pm_pch_lpt(hw, link); 1524 if (ret_val) 1525 goto out; 1526 } 1527 1528 /* Clear link partner's EEE ability */ 1529 hw->dev_spec.ich8lan.eee_lp_ability = 0; 1530 1531 if (hw->mac.type >= e1000_pch_lpt) { 1532 u32 fextnvm6 = er32(FEXTNVM6); 1533 1534 if (hw->mac.type == e1000_pch_spt) { 1535 /* FEXTNVM6 K1-off workaround - for SPT only */ 1536 u32 pcieanacfg = er32(PCIEANACFG); 1537 1538 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE) 1539 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE; 1540 else 1541 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE; 1542 } 1543 1544 ew32(FEXTNVM6, fextnvm6); 1545 } 1546 1547 if (!link) 1548 goto out; 1549 1550 switch (hw->mac.type) { 1551 case e1000_pch2lan: 1552 ret_val = e1000_k1_workaround_lv(hw); 1553 if (ret_val) 1554 return ret_val; 1555 /* fall-thru */ 1556 case e1000_pchlan: 1557 if (hw->phy.type == e1000_phy_82578) { 1558 ret_val = e1000_link_stall_workaround_hv(hw); 1559 if (ret_val) 1560 return ret_val; 1561 } 1562 1563 /* Workaround for PCHx parts in half-duplex: 1564 * Set the number of preambles removed from the packet 1565 * when it is passed from the PHY to the MAC to prevent 1566 * the MAC from misinterpreting the packet type. 1567 */ 1568 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); 1569 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; 1570 1571 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) 1572 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); 1573 1574 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); 1575 break; 1576 default: 1577 break; 1578 } 1579 1580 /* Check if there was DownShift, must be checked 1581 * immediately after link-up 1582 */ 1583 e1000e_check_downshift(hw); 1584 1585 /* Enable/Disable EEE after link up */ 1586 if (hw->phy.type > e1000_phy_82579) { 1587 ret_val = e1000_set_eee_pchlan(hw); 1588 if (ret_val) 1589 return ret_val; 1590 } 1591 1592 /* If we are forcing speed/duplex, then we simply return since 1593 * we have already determined whether we have link or not. 1594 */ 1595 if (!mac->autoneg) 1596 return -E1000_ERR_CONFIG; 1597 1598 /* Auto-Neg is enabled. Auto Speed Detection takes care 1599 * of MAC speed/duplex configuration. So we only need to 1600 * configure Collision Distance in the MAC. 1601 */ 1602 mac->ops.config_collision_dist(hw); 1603 1604 /* Configure Flow Control now that Auto-Neg has completed. 1605 * First, we need to restore the desired flow control 1606 * settings because we may have had to re-autoneg with a 1607 * different link partner. 1608 */ 1609 ret_val = e1000e_config_fc_after_link_up(hw); 1610 if (ret_val) 1611 e_dbg("Error configuring flow control\n"); 1612 1613 return ret_val; 1614 1615 out: 1616 mac->get_link_status = true; 1617 return ret_val; 1618 } 1619 1620 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) 1621 { 1622 struct e1000_hw *hw = &adapter->hw; 1623 s32 rc; 1624 1625 rc = e1000_init_mac_params_ich8lan(hw); 1626 if (rc) 1627 return rc; 1628 1629 rc = e1000_init_nvm_params_ich8lan(hw); 1630 if (rc) 1631 return rc; 1632 1633 switch (hw->mac.type) { 1634 case e1000_ich8lan: 1635 case e1000_ich9lan: 1636 case e1000_ich10lan: 1637 rc = e1000_init_phy_params_ich8lan(hw); 1638 break; 1639 case e1000_pchlan: 1640 case e1000_pch2lan: 1641 case e1000_pch_lpt: 1642 case e1000_pch_spt: 1643 case e1000_pch_cnp: 1644 case e1000_pch_tgp: 1645 rc = e1000_init_phy_params_pchlan(hw); 1646 break; 1647 default: 1648 break; 1649 } 1650 if (rc) 1651 return rc; 1652 1653 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or 1654 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). 1655 */ 1656 if ((adapter->hw.phy.type == e1000_phy_ife) || 1657 ((adapter->hw.mac.type >= e1000_pch2lan) && 1658 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { 1659 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; 1660 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 1661 1662 hw->mac.ops.blink_led = NULL; 1663 } 1664 1665 if ((adapter->hw.mac.type == e1000_ich8lan) && 1666 (adapter->hw.phy.type != e1000_phy_ife)) 1667 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; 1668 1669 /* Enable workaround for 82579 w/ ME enabled */ 1670 if ((adapter->hw.mac.type == e1000_pch2lan) && 1671 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 1672 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; 1673 1674 return 0; 1675 } 1676 1677 static DEFINE_MUTEX(nvm_mutex); 1678 1679 /** 1680 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex 1681 * @hw: pointer to the HW structure 1682 * 1683 * Acquires the mutex for performing NVM operations. 1684 **/ 1685 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1686 { 1687 mutex_lock(&nvm_mutex); 1688 1689 return 0; 1690 } 1691 1692 /** 1693 * e1000_release_nvm_ich8lan - Release NVM mutex 1694 * @hw: pointer to the HW structure 1695 * 1696 * Releases the mutex used while performing NVM operations. 1697 **/ 1698 static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw) 1699 { 1700 mutex_unlock(&nvm_mutex); 1701 } 1702 1703 /** 1704 * e1000_acquire_swflag_ich8lan - Acquire software control flag 1705 * @hw: pointer to the HW structure 1706 * 1707 * Acquires the software control flag for performing PHY and select 1708 * MAC CSR accesses. 1709 **/ 1710 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) 1711 { 1712 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 1713 s32 ret_val = 0; 1714 1715 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, 1716 &hw->adapter->state)) { 1717 e_dbg("contention for Phy access\n"); 1718 return -E1000_ERR_PHY; 1719 } 1720 1721 while (timeout) { 1722 extcnf_ctrl = er32(EXTCNF_CTRL); 1723 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 1724 break; 1725 1726 mdelay(1); 1727 timeout--; 1728 } 1729 1730 if (!timeout) { 1731 e_dbg("SW has already locked the resource.\n"); 1732 ret_val = -E1000_ERR_CONFIG; 1733 goto out; 1734 } 1735 1736 timeout = SW_FLAG_TIMEOUT; 1737 1738 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 1739 ew32(EXTCNF_CTRL, extcnf_ctrl); 1740 1741 while (timeout) { 1742 extcnf_ctrl = er32(EXTCNF_CTRL); 1743 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 1744 break; 1745 1746 mdelay(1); 1747 timeout--; 1748 } 1749 1750 if (!timeout) { 1751 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", 1752 er32(FWSM), extcnf_ctrl); 1753 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1754 ew32(EXTCNF_CTRL, extcnf_ctrl); 1755 ret_val = -E1000_ERR_CONFIG; 1756 goto out; 1757 } 1758 1759 out: 1760 if (ret_val) 1761 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1762 1763 return ret_val; 1764 } 1765 1766 /** 1767 * e1000_release_swflag_ich8lan - Release software control flag 1768 * @hw: pointer to the HW structure 1769 * 1770 * Releases the software control flag for performing PHY and select 1771 * MAC CSR accesses. 1772 **/ 1773 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) 1774 { 1775 u32 extcnf_ctrl; 1776 1777 extcnf_ctrl = er32(EXTCNF_CTRL); 1778 1779 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { 1780 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 1781 ew32(EXTCNF_CTRL, extcnf_ctrl); 1782 } else { 1783 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); 1784 } 1785 1786 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 1787 } 1788 1789 /** 1790 * e1000_check_mng_mode_ich8lan - Checks management mode 1791 * @hw: pointer to the HW structure 1792 * 1793 * This checks if the adapter has any manageability enabled. 1794 * This is a function pointer entry point only called by read/write 1795 * routines for the PHY and NVM parts. 1796 **/ 1797 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) 1798 { 1799 u32 fwsm; 1800 1801 fwsm = er32(FWSM); 1802 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1803 ((fwsm & E1000_FWSM_MODE_MASK) == 1804 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1805 } 1806 1807 /** 1808 * e1000_check_mng_mode_pchlan - Checks management mode 1809 * @hw: pointer to the HW structure 1810 * 1811 * This checks if the adapter has iAMT enabled. 1812 * This is a function pointer entry point only called by read/write 1813 * routines for the PHY and NVM parts. 1814 **/ 1815 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) 1816 { 1817 u32 fwsm; 1818 1819 fwsm = er32(FWSM); 1820 return (fwsm & E1000_ICH_FWSM_FW_VALID) && 1821 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); 1822 } 1823 1824 /** 1825 * e1000_rar_set_pch2lan - Set receive address register 1826 * @hw: pointer to the HW structure 1827 * @addr: pointer to the receive address 1828 * @index: receive address array register 1829 * 1830 * Sets the receive address array register at index to the address passed 1831 * in by addr. For 82579, RAR[0] is the base address register that is to 1832 * contain the MAC address but RAR[1-6] are reserved for manageability (ME). 1833 * Use SHRA[0-3] in place of those reserved for ME. 1834 **/ 1835 static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) 1836 { 1837 u32 rar_low, rar_high; 1838 1839 /* HW expects these in little endian so we reverse the byte order 1840 * from network order (big endian) to little endian 1841 */ 1842 rar_low = ((u32)addr[0] | 1843 ((u32)addr[1] << 8) | 1844 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1845 1846 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1847 1848 /* If MAC address zero, no need to set the AV bit */ 1849 if (rar_low || rar_high) 1850 rar_high |= E1000_RAH_AV; 1851 1852 if (index == 0) { 1853 ew32(RAL(index), rar_low); 1854 e1e_flush(); 1855 ew32(RAH(index), rar_high); 1856 e1e_flush(); 1857 return 0; 1858 } 1859 1860 /* RAR[1-6] are owned by manageability. Skip those and program the 1861 * next address into the SHRA register array. 1862 */ 1863 if (index < (u32)(hw->mac.rar_entry_count)) { 1864 s32 ret_val; 1865 1866 ret_val = e1000_acquire_swflag_ich8lan(hw); 1867 if (ret_val) 1868 goto out; 1869 1870 ew32(SHRAL(index - 1), rar_low); 1871 e1e_flush(); 1872 ew32(SHRAH(index - 1), rar_high); 1873 e1e_flush(); 1874 1875 e1000_release_swflag_ich8lan(hw); 1876 1877 /* verify the register updates */ 1878 if ((er32(SHRAL(index - 1)) == rar_low) && 1879 (er32(SHRAH(index - 1)) == rar_high)) 1880 return 0; 1881 1882 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", 1883 (index - 1), er32(FWSM)); 1884 } 1885 1886 out: 1887 e_dbg("Failed to write receive address at index %d\n", index); 1888 return -E1000_ERR_CONFIG; 1889 } 1890 1891 /** 1892 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA 1893 * @hw: pointer to the HW structure 1894 * 1895 * Get the number of available receive registers that the Host can 1896 * program. SHRA[0-10] are the shared receive address registers 1897 * that are shared between the Host and manageability engine (ME). 1898 * ME can reserve any number of addresses and the host needs to be 1899 * able to tell how many available registers it has access to. 1900 **/ 1901 static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw) 1902 { 1903 u32 wlock_mac; 1904 u32 num_entries; 1905 1906 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 1907 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 1908 1909 switch (wlock_mac) { 1910 case 0: 1911 /* All SHRA[0..10] and RAR[0] available */ 1912 num_entries = hw->mac.rar_entry_count; 1913 break; 1914 case 1: 1915 /* Only RAR[0] available */ 1916 num_entries = 1; 1917 break; 1918 default: 1919 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */ 1920 num_entries = wlock_mac + 1; 1921 break; 1922 } 1923 1924 return num_entries; 1925 } 1926 1927 /** 1928 * e1000_rar_set_pch_lpt - Set receive address registers 1929 * @hw: pointer to the HW structure 1930 * @addr: pointer to the receive address 1931 * @index: receive address array register 1932 * 1933 * Sets the receive address register array at index to the address passed 1934 * in by addr. For LPT, RAR[0] is the base address register that is to 1935 * contain the MAC address. SHRA[0-10] are the shared receive address 1936 * registers that are shared between the Host and manageability engine (ME). 1937 **/ 1938 static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) 1939 { 1940 u32 rar_low, rar_high; 1941 u32 wlock_mac; 1942 1943 /* HW expects these in little endian so we reverse the byte order 1944 * from network order (big endian) to little endian 1945 */ 1946 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 1947 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 1948 1949 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 1950 1951 /* If MAC address zero, no need to set the AV bit */ 1952 if (rar_low || rar_high) 1953 rar_high |= E1000_RAH_AV; 1954 1955 if (index == 0) { 1956 ew32(RAL(index), rar_low); 1957 e1e_flush(); 1958 ew32(RAH(index), rar_high); 1959 e1e_flush(); 1960 return 0; 1961 } 1962 1963 /* The manageability engine (ME) can lock certain SHRAR registers that 1964 * it is using - those registers are unavailable for use. 1965 */ 1966 if (index < hw->mac.rar_entry_count) { 1967 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; 1968 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; 1969 1970 /* Check if all SHRAR registers are locked */ 1971 if (wlock_mac == 1) 1972 goto out; 1973 1974 if ((wlock_mac == 0) || (index <= wlock_mac)) { 1975 s32 ret_val; 1976 1977 ret_val = e1000_acquire_swflag_ich8lan(hw); 1978 1979 if (ret_val) 1980 goto out; 1981 1982 ew32(SHRAL_PCH_LPT(index - 1), rar_low); 1983 e1e_flush(); 1984 ew32(SHRAH_PCH_LPT(index - 1), rar_high); 1985 e1e_flush(); 1986 1987 e1000_release_swflag_ich8lan(hw); 1988 1989 /* verify the register updates */ 1990 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && 1991 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) 1992 return 0; 1993 } 1994 } 1995 1996 out: 1997 e_dbg("Failed to write receive address at index %d\n", index); 1998 return -E1000_ERR_CONFIG; 1999 } 2000 2001 /** 2002 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked 2003 * @hw: pointer to the HW structure 2004 * 2005 * Checks if firmware is blocking the reset of the PHY. 2006 * This is a function pointer entry point only called by 2007 * reset routines. 2008 **/ 2009 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) 2010 { 2011 bool blocked = false; 2012 int i = 0; 2013 2014 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) && 2015 (i++ < 30)) 2016 usleep_range(10000, 11000); 2017 return blocked ? E1000_BLK_PHY_RESET : 0; 2018 } 2019 2020 /** 2021 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states 2022 * @hw: pointer to the HW structure 2023 * 2024 * Assumes semaphore already acquired. 2025 * 2026 **/ 2027 static s32 e1000_write_smbus_addr(struct e1000_hw *hw) 2028 { 2029 u16 phy_data; 2030 u32 strap = er32(STRAP); 2031 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> 2032 E1000_STRAP_SMT_FREQ_SHIFT; 2033 s32 ret_val; 2034 2035 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; 2036 2037 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); 2038 if (ret_val) 2039 return ret_val; 2040 2041 phy_data &= ~HV_SMB_ADDR_MASK; 2042 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); 2043 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 2044 2045 if (hw->phy.type == e1000_phy_i217) { 2046 /* Restore SMBus frequency */ 2047 if (freq--) { 2048 phy_data &= ~HV_SMB_ADDR_FREQ_MASK; 2049 phy_data |= (freq & BIT(0)) << 2050 HV_SMB_ADDR_FREQ_LOW_SHIFT; 2051 phy_data |= (freq & BIT(1)) << 2052 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); 2053 } else { 2054 e_dbg("Unsupported SMB frequency in PHY\n"); 2055 } 2056 } 2057 2058 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); 2059 } 2060 2061 /** 2062 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration 2063 * @hw: pointer to the HW structure 2064 * 2065 * SW should configure the LCD from the NVM extended configuration region 2066 * as a workaround for certain parts. 2067 **/ 2068 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) 2069 { 2070 struct e1000_phy_info *phy = &hw->phy; 2071 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 2072 s32 ret_val = 0; 2073 u16 word_addr, reg_data, reg_addr, phy_page = 0; 2074 2075 /* Initialize the PHY from the NVM on ICH platforms. This 2076 * is needed due to an issue where the NVM configuration is 2077 * not properly autoloaded after power transitions. 2078 * Therefore, after each PHY reset, we will load the 2079 * configuration data out of the NVM manually. 2080 */ 2081 switch (hw->mac.type) { 2082 case e1000_ich8lan: 2083 if (phy->type != e1000_phy_igp_3) 2084 return ret_val; 2085 2086 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || 2087 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { 2088 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 2089 break; 2090 } 2091 /* Fall-thru */ 2092 case e1000_pchlan: 2093 case e1000_pch2lan: 2094 case e1000_pch_lpt: 2095 case e1000_pch_spt: 2096 case e1000_pch_cnp: 2097 case e1000_pch_tgp: 2098 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 2099 break; 2100 default: 2101 return ret_val; 2102 } 2103 2104 ret_val = hw->phy.ops.acquire(hw); 2105 if (ret_val) 2106 return ret_val; 2107 2108 data = er32(FEXTNVM); 2109 if (!(data & sw_cfg_mask)) 2110 goto release; 2111 2112 /* Make sure HW does not configure LCD from PHY 2113 * extended configuration before SW configuration 2114 */ 2115 data = er32(EXTCNF_CTRL); 2116 if ((hw->mac.type < e1000_pch2lan) && 2117 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) 2118 goto release; 2119 2120 cnf_size = er32(EXTCNF_SIZE); 2121 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 2122 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 2123 if (!cnf_size) 2124 goto release; 2125 2126 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 2127 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 2128 2129 if (((hw->mac.type == e1000_pchlan) && 2130 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || 2131 (hw->mac.type > e1000_pchlan)) { 2132 /* HW configures the SMBus address and LEDs when the 2133 * OEM and LCD Write Enable bits are set in the NVM. 2134 * When both NVM bits are cleared, SW will configure 2135 * them instead. 2136 */ 2137 ret_val = e1000_write_smbus_addr(hw); 2138 if (ret_val) 2139 goto release; 2140 2141 data = er32(LEDCTL); 2142 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, 2143 (u16)data); 2144 if (ret_val) 2145 goto release; 2146 } 2147 2148 /* Configure LCD from extended configuration region. */ 2149 2150 /* cnf_base_addr is in DWORD */ 2151 word_addr = (u16)(cnf_base_addr << 1); 2152 2153 for (i = 0; i < cnf_size; i++) { 2154 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data); 2155 if (ret_val) 2156 goto release; 2157 2158 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), 2159 1, ®_addr); 2160 if (ret_val) 2161 goto release; 2162 2163 /* Save off the PHY page for future writes. */ 2164 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 2165 phy_page = reg_data; 2166 continue; 2167 } 2168 2169 reg_addr &= PHY_REG_MASK; 2170 reg_addr |= phy_page; 2171 2172 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); 2173 if (ret_val) 2174 goto release; 2175 } 2176 2177 release: 2178 hw->phy.ops.release(hw); 2179 return ret_val; 2180 } 2181 2182 /** 2183 * e1000_k1_gig_workaround_hv - K1 Si workaround 2184 * @hw: pointer to the HW structure 2185 * @link: link up bool flag 2186 * 2187 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning 2188 * from a lower speed. This workaround disables K1 whenever link is at 1Gig 2189 * If link is down, the function will restore the default K1 setting located 2190 * in the NVM. 2191 **/ 2192 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) 2193 { 2194 s32 ret_val = 0; 2195 u16 status_reg = 0; 2196 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 2197 2198 if (hw->mac.type != e1000_pchlan) 2199 return 0; 2200 2201 /* Wrap the whole flow with the sw flag */ 2202 ret_val = hw->phy.ops.acquire(hw); 2203 if (ret_val) 2204 return ret_val; 2205 2206 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 2207 if (link) { 2208 if (hw->phy.type == e1000_phy_82578) { 2209 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, 2210 &status_reg); 2211 if (ret_val) 2212 goto release; 2213 2214 status_reg &= (BM_CS_STATUS_LINK_UP | 2215 BM_CS_STATUS_RESOLVED | 2216 BM_CS_STATUS_SPEED_MASK); 2217 2218 if (status_reg == (BM_CS_STATUS_LINK_UP | 2219 BM_CS_STATUS_RESOLVED | 2220 BM_CS_STATUS_SPEED_1000)) 2221 k1_enable = false; 2222 } 2223 2224 if (hw->phy.type == e1000_phy_82577) { 2225 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); 2226 if (ret_val) 2227 goto release; 2228 2229 status_reg &= (HV_M_STATUS_LINK_UP | 2230 HV_M_STATUS_AUTONEG_COMPLETE | 2231 HV_M_STATUS_SPEED_MASK); 2232 2233 if (status_reg == (HV_M_STATUS_LINK_UP | 2234 HV_M_STATUS_AUTONEG_COMPLETE | 2235 HV_M_STATUS_SPEED_1000)) 2236 k1_enable = false; 2237 } 2238 2239 /* Link stall fix for link up */ 2240 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); 2241 if (ret_val) 2242 goto release; 2243 2244 } else { 2245 /* Link stall fix for link down */ 2246 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); 2247 if (ret_val) 2248 goto release; 2249 } 2250 2251 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); 2252 2253 release: 2254 hw->phy.ops.release(hw); 2255 2256 return ret_val; 2257 } 2258 2259 /** 2260 * e1000_configure_k1_ich8lan - Configure K1 power state 2261 * @hw: pointer to the HW structure 2262 * @enable: K1 state to configure 2263 * 2264 * Configure the K1 power state based on the provided parameter. 2265 * Assumes semaphore already acquired. 2266 * 2267 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2268 **/ 2269 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) 2270 { 2271 s32 ret_val; 2272 u32 ctrl_reg = 0; 2273 u32 ctrl_ext = 0; 2274 u32 reg = 0; 2275 u16 kmrn_reg = 0; 2276 2277 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2278 &kmrn_reg); 2279 if (ret_val) 2280 return ret_val; 2281 2282 if (k1_enable) 2283 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 2284 else 2285 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 2286 2287 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, 2288 kmrn_reg); 2289 if (ret_val) 2290 return ret_val; 2291 2292 usleep_range(20, 40); 2293 ctrl_ext = er32(CTRL_EXT); 2294 ctrl_reg = er32(CTRL); 2295 2296 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2297 reg |= E1000_CTRL_FRCSPD; 2298 ew32(CTRL, reg); 2299 2300 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 2301 e1e_flush(); 2302 usleep_range(20, 40); 2303 ew32(CTRL, ctrl_reg); 2304 ew32(CTRL_EXT, ctrl_ext); 2305 e1e_flush(); 2306 usleep_range(20, 40); 2307 2308 return 0; 2309 } 2310 2311 /** 2312 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration 2313 * @hw: pointer to the HW structure 2314 * @d0_state: boolean if entering d0 or d3 device state 2315 * 2316 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are 2317 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit 2318 * in NVM determines whether HW should configure LPLU and Gbe Disable. 2319 **/ 2320 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) 2321 { 2322 s32 ret_val = 0; 2323 u32 mac_reg; 2324 u16 oem_reg; 2325 2326 if (hw->mac.type < e1000_pchlan) 2327 return ret_val; 2328 2329 ret_val = hw->phy.ops.acquire(hw); 2330 if (ret_val) 2331 return ret_val; 2332 2333 if (hw->mac.type == e1000_pchlan) { 2334 mac_reg = er32(EXTCNF_CTRL); 2335 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 2336 goto release; 2337 } 2338 2339 mac_reg = er32(FEXTNVM); 2340 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 2341 goto release; 2342 2343 mac_reg = er32(PHY_CTRL); 2344 2345 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); 2346 if (ret_val) 2347 goto release; 2348 2349 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 2350 2351 if (d0_state) { 2352 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 2353 oem_reg |= HV_OEM_BITS_GBE_DIS; 2354 2355 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 2356 oem_reg |= HV_OEM_BITS_LPLU; 2357 } else { 2358 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | 2359 E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) 2360 oem_reg |= HV_OEM_BITS_GBE_DIS; 2361 2362 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | 2363 E1000_PHY_CTRL_NOND0A_LPLU)) 2364 oem_reg |= HV_OEM_BITS_LPLU; 2365 } 2366 2367 /* Set Restart auto-neg to activate the bits */ 2368 if ((d0_state || (hw->mac.type != e1000_pchlan)) && 2369 !hw->phy.ops.check_reset_block(hw)) 2370 oem_reg |= HV_OEM_BITS_RESTART_AN; 2371 2372 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); 2373 2374 release: 2375 hw->phy.ops.release(hw); 2376 2377 return ret_val; 2378 } 2379 2380 /** 2381 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode 2382 * @hw: pointer to the HW structure 2383 **/ 2384 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) 2385 { 2386 s32 ret_val; 2387 u16 data; 2388 2389 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); 2390 if (ret_val) 2391 return ret_val; 2392 2393 data |= HV_KMRN_MDIO_SLOW; 2394 2395 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); 2396 2397 return ret_val; 2398 } 2399 2400 /** 2401 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be 2402 * done after every PHY reset. 2403 **/ 2404 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2405 { 2406 s32 ret_val = 0; 2407 u16 phy_data; 2408 2409 if (hw->mac.type != e1000_pchlan) 2410 return 0; 2411 2412 /* Set MDIO slow mode before any other MDIO access */ 2413 if (hw->phy.type == e1000_phy_82577) { 2414 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2415 if (ret_val) 2416 return ret_val; 2417 } 2418 2419 if (((hw->phy.type == e1000_phy_82577) && 2420 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 2421 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 2422 /* Disable generation of early preamble */ 2423 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); 2424 if (ret_val) 2425 return ret_val; 2426 2427 /* Preamble tuning for SSC */ 2428 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); 2429 if (ret_val) 2430 return ret_val; 2431 } 2432 2433 if (hw->phy.type == e1000_phy_82578) { 2434 /* Return registers to default by doing a soft reset then 2435 * writing 0x3140 to the control register. 2436 */ 2437 if (hw->phy.revision < 2) { 2438 e1000e_phy_sw_reset(hw); 2439 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140); 2440 if (ret_val) 2441 return ret_val; 2442 } 2443 } 2444 2445 /* Select page 0 */ 2446 ret_val = hw->phy.ops.acquire(hw); 2447 if (ret_val) 2448 return ret_val; 2449 2450 hw->phy.addr = 1; 2451 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 2452 hw->phy.ops.release(hw); 2453 if (ret_val) 2454 return ret_val; 2455 2456 /* Configure the K1 Si workaround during phy reset assuming there is 2457 * link so that it disables K1 if link is in 1Gbps. 2458 */ 2459 ret_val = e1000_k1_gig_workaround_hv(hw, true); 2460 if (ret_val) 2461 return ret_val; 2462 2463 /* Workaround for link disconnects on a busy hub in half duplex */ 2464 ret_val = hw->phy.ops.acquire(hw); 2465 if (ret_val) 2466 return ret_val; 2467 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); 2468 if (ret_val) 2469 goto release; 2470 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); 2471 if (ret_val) 2472 goto release; 2473 2474 /* set MSE higher to enable link to stay up when noise is high */ 2475 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); 2476 release: 2477 hw->phy.ops.release(hw); 2478 2479 return ret_val; 2480 } 2481 2482 /** 2483 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY 2484 * @hw: pointer to the HW structure 2485 **/ 2486 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) 2487 { 2488 u32 mac_reg; 2489 u16 i, phy_reg = 0; 2490 s32 ret_val; 2491 2492 ret_val = hw->phy.ops.acquire(hw); 2493 if (ret_val) 2494 return; 2495 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2496 if (ret_val) 2497 goto release; 2498 2499 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */ 2500 for (i = 0; i < (hw->mac.rar_entry_count); i++) { 2501 mac_reg = er32(RAL(i)); 2502 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), 2503 (u16)(mac_reg & 0xFFFF)); 2504 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), 2505 (u16)((mac_reg >> 16) & 0xFFFF)); 2506 2507 mac_reg = er32(RAH(i)); 2508 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), 2509 (u16)(mac_reg & 0xFFFF)); 2510 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), 2511 (u16)((mac_reg & E1000_RAH_AV) 2512 >> 16)); 2513 } 2514 2515 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 2516 2517 release: 2518 hw->phy.ops.release(hw); 2519 } 2520 2521 /** 2522 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation 2523 * with 82579 PHY 2524 * @hw: pointer to the HW structure 2525 * @enable: flag to enable/disable workaround when enabling/disabling jumbos 2526 **/ 2527 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) 2528 { 2529 s32 ret_val = 0; 2530 u16 phy_reg, data; 2531 u32 mac_reg; 2532 u16 i; 2533 2534 if (hw->mac.type < e1000_pch2lan) 2535 return 0; 2536 2537 /* disable Rx path while enabling/disabling workaround */ 2538 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); 2539 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14)); 2540 if (ret_val) 2541 return ret_val; 2542 2543 if (enable) { 2544 /* Write Rx addresses (rar_entry_count for RAL/H, and 2545 * SHRAL/H) and initial CRC values to the MAC 2546 */ 2547 for (i = 0; i < hw->mac.rar_entry_count; i++) { 2548 u8 mac_addr[ETH_ALEN] = { 0 }; 2549 u32 addr_high, addr_low; 2550 2551 addr_high = er32(RAH(i)); 2552 if (!(addr_high & E1000_RAH_AV)) 2553 continue; 2554 addr_low = er32(RAL(i)); 2555 mac_addr[0] = (addr_low & 0xFF); 2556 mac_addr[1] = ((addr_low >> 8) & 0xFF); 2557 mac_addr[2] = ((addr_low >> 16) & 0xFF); 2558 mac_addr[3] = ((addr_low >> 24) & 0xFF); 2559 mac_addr[4] = (addr_high & 0xFF); 2560 mac_addr[5] = ((addr_high >> 8) & 0xFF); 2561 2562 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr)); 2563 } 2564 2565 /* Write Rx addresses to the PHY */ 2566 e1000_copy_rx_addrs_to_phy_ich8lan(hw); 2567 2568 /* Enable jumbo frame workaround in the MAC */ 2569 mac_reg = er32(FFLT_DBG); 2570 mac_reg &= ~BIT(14); 2571 mac_reg |= (7 << 15); 2572 ew32(FFLT_DBG, mac_reg); 2573 2574 mac_reg = er32(RCTL); 2575 mac_reg |= E1000_RCTL_SECRC; 2576 ew32(RCTL, mac_reg); 2577 2578 ret_val = e1000e_read_kmrn_reg(hw, 2579 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2580 &data); 2581 if (ret_val) 2582 return ret_val; 2583 ret_val = e1000e_write_kmrn_reg(hw, 2584 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2585 data | BIT(0)); 2586 if (ret_val) 2587 return ret_val; 2588 ret_val = e1000e_read_kmrn_reg(hw, 2589 E1000_KMRNCTRLSTA_HD_CTRL, 2590 &data); 2591 if (ret_val) 2592 return ret_val; 2593 data &= ~(0xF << 8); 2594 data |= (0xB << 8); 2595 ret_val = e1000e_write_kmrn_reg(hw, 2596 E1000_KMRNCTRLSTA_HD_CTRL, 2597 data); 2598 if (ret_val) 2599 return ret_val; 2600 2601 /* Enable jumbo frame workaround in the PHY */ 2602 e1e_rphy(hw, PHY_REG(769, 23), &data); 2603 data &= ~(0x7F << 5); 2604 data |= (0x37 << 5); 2605 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2606 if (ret_val) 2607 return ret_val; 2608 e1e_rphy(hw, PHY_REG(769, 16), &data); 2609 data &= ~BIT(13); 2610 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2611 if (ret_val) 2612 return ret_val; 2613 e1e_rphy(hw, PHY_REG(776, 20), &data); 2614 data &= ~(0x3FF << 2); 2615 data |= (E1000_TX_PTR_GAP << 2); 2616 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2617 if (ret_val) 2618 return ret_val; 2619 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); 2620 if (ret_val) 2621 return ret_val; 2622 e1e_rphy(hw, HV_PM_CTRL, &data); 2623 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10)); 2624 if (ret_val) 2625 return ret_val; 2626 } else { 2627 /* Write MAC register values back to h/w defaults */ 2628 mac_reg = er32(FFLT_DBG); 2629 mac_reg &= ~(0xF << 14); 2630 ew32(FFLT_DBG, mac_reg); 2631 2632 mac_reg = er32(RCTL); 2633 mac_reg &= ~E1000_RCTL_SECRC; 2634 ew32(RCTL, mac_reg); 2635 2636 ret_val = e1000e_read_kmrn_reg(hw, 2637 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2638 &data); 2639 if (ret_val) 2640 return ret_val; 2641 ret_val = e1000e_write_kmrn_reg(hw, 2642 E1000_KMRNCTRLSTA_CTRL_OFFSET, 2643 data & ~BIT(0)); 2644 if (ret_val) 2645 return ret_val; 2646 ret_val = e1000e_read_kmrn_reg(hw, 2647 E1000_KMRNCTRLSTA_HD_CTRL, 2648 &data); 2649 if (ret_val) 2650 return ret_val; 2651 data &= ~(0xF << 8); 2652 data |= (0xB << 8); 2653 ret_val = e1000e_write_kmrn_reg(hw, 2654 E1000_KMRNCTRLSTA_HD_CTRL, 2655 data); 2656 if (ret_val) 2657 return ret_val; 2658 2659 /* Write PHY register values back to h/w defaults */ 2660 e1e_rphy(hw, PHY_REG(769, 23), &data); 2661 data &= ~(0x7F << 5); 2662 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); 2663 if (ret_val) 2664 return ret_val; 2665 e1e_rphy(hw, PHY_REG(769, 16), &data); 2666 data |= BIT(13); 2667 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); 2668 if (ret_val) 2669 return ret_val; 2670 e1e_rphy(hw, PHY_REG(776, 20), &data); 2671 data &= ~(0x3FF << 2); 2672 data |= (0x8 << 2); 2673 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); 2674 if (ret_val) 2675 return ret_val; 2676 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); 2677 if (ret_val) 2678 return ret_val; 2679 e1e_rphy(hw, HV_PM_CTRL, &data); 2680 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10)); 2681 if (ret_val) 2682 return ret_val; 2683 } 2684 2685 /* re-enable Rx path after enabling/disabling workaround */ 2686 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14)); 2687 } 2688 2689 /** 2690 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be 2691 * done after every PHY reset. 2692 **/ 2693 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) 2694 { 2695 s32 ret_val = 0; 2696 2697 if (hw->mac.type != e1000_pch2lan) 2698 return 0; 2699 2700 /* Set MDIO slow mode before any other MDIO access */ 2701 ret_val = e1000_set_mdio_slow_mode_hv(hw); 2702 if (ret_val) 2703 return ret_val; 2704 2705 ret_val = hw->phy.ops.acquire(hw); 2706 if (ret_val) 2707 return ret_val; 2708 /* set MSE higher to enable link to stay up when noise is high */ 2709 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); 2710 if (ret_val) 2711 goto release; 2712 /* drop link after 5 times MSE threshold was reached */ 2713 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); 2714 release: 2715 hw->phy.ops.release(hw); 2716 2717 return ret_val; 2718 } 2719 2720 /** 2721 * e1000_k1_gig_workaround_lv - K1 Si workaround 2722 * @hw: pointer to the HW structure 2723 * 2724 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps 2725 * Disable K1 in 1000Mbps and 100Mbps 2726 **/ 2727 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) 2728 { 2729 s32 ret_val = 0; 2730 u16 status_reg = 0; 2731 2732 if (hw->mac.type != e1000_pch2lan) 2733 return 0; 2734 2735 /* Set K1 beacon duration based on 10Mbs speed */ 2736 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); 2737 if (ret_val) 2738 return ret_val; 2739 2740 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) 2741 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { 2742 if (status_reg & 2743 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) { 2744 u16 pm_phy_reg; 2745 2746 /* LV 1G/100 Packet drop issue wa */ 2747 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); 2748 if (ret_val) 2749 return ret_val; 2750 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE; 2751 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); 2752 if (ret_val) 2753 return ret_val; 2754 } else { 2755 u32 mac_reg; 2756 2757 mac_reg = er32(FEXTNVM4); 2758 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; 2759 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; 2760 ew32(FEXTNVM4, mac_reg); 2761 } 2762 } 2763 2764 return ret_val; 2765 } 2766 2767 /** 2768 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware 2769 * @hw: pointer to the HW structure 2770 * @gate: boolean set to true to gate, false to ungate 2771 * 2772 * Gate/ungate the automatic PHY configuration via hardware; perform 2773 * the configuration via software instead. 2774 **/ 2775 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) 2776 { 2777 u32 extcnf_ctrl; 2778 2779 if (hw->mac.type < e1000_pch2lan) 2780 return; 2781 2782 extcnf_ctrl = er32(EXTCNF_CTRL); 2783 2784 if (gate) 2785 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2786 else 2787 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; 2788 2789 ew32(EXTCNF_CTRL, extcnf_ctrl); 2790 } 2791 2792 /** 2793 * e1000_lan_init_done_ich8lan - Check for PHY config completion 2794 * @hw: pointer to the HW structure 2795 * 2796 * Check the appropriate indication the MAC has finished configuring the 2797 * PHY after a software reset. 2798 **/ 2799 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) 2800 { 2801 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 2802 2803 /* Wait for basic configuration completes before proceeding */ 2804 do { 2805 data = er32(STATUS); 2806 data &= E1000_STATUS_LAN_INIT_DONE; 2807 usleep_range(100, 200); 2808 } while ((!data) && --loop); 2809 2810 /* If basic configuration is incomplete before the above loop 2811 * count reaches 0, loading the configuration from NVM will 2812 * leave the PHY in a bad state possibly resulting in no link. 2813 */ 2814 if (loop == 0) 2815 e_dbg("LAN_INIT_DONE not set, increase timeout\n"); 2816 2817 /* Clear the Init Done bit for the next init event */ 2818 data = er32(STATUS); 2819 data &= ~E1000_STATUS_LAN_INIT_DONE; 2820 ew32(STATUS, data); 2821 } 2822 2823 /** 2824 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset 2825 * @hw: pointer to the HW structure 2826 **/ 2827 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) 2828 { 2829 s32 ret_val = 0; 2830 u16 reg; 2831 2832 if (hw->phy.ops.check_reset_block(hw)) 2833 return 0; 2834 2835 /* Allow time for h/w to get to quiescent state after reset */ 2836 usleep_range(10000, 11000); 2837 2838 /* Perform any necessary post-reset workarounds */ 2839 switch (hw->mac.type) { 2840 case e1000_pchlan: 2841 ret_val = e1000_hv_phy_workarounds_ich8lan(hw); 2842 if (ret_val) 2843 return ret_val; 2844 break; 2845 case e1000_pch2lan: 2846 ret_val = e1000_lv_phy_workarounds_ich8lan(hw); 2847 if (ret_val) 2848 return ret_val; 2849 break; 2850 default: 2851 break; 2852 } 2853 2854 /* Clear the host wakeup bit after lcd reset */ 2855 if (hw->mac.type >= e1000_pchlan) { 2856 e1e_rphy(hw, BM_PORT_GEN_CFG, ®); 2857 reg &= ~BM_WUC_HOST_WU_BIT; 2858 e1e_wphy(hw, BM_PORT_GEN_CFG, reg); 2859 } 2860 2861 /* Configure the LCD with the extended configuration region in NVM */ 2862 ret_val = e1000_sw_lcd_config_ich8lan(hw); 2863 if (ret_val) 2864 return ret_val; 2865 2866 /* Configure the LCD with the OEM bits in NVM */ 2867 ret_val = e1000_oem_bits_config_ich8lan(hw, true); 2868 2869 if (hw->mac.type == e1000_pch2lan) { 2870 /* Ungate automatic PHY configuration on non-managed 82579 */ 2871 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 2872 usleep_range(10000, 11000); 2873 e1000_gate_hw_phy_config_ich8lan(hw, false); 2874 } 2875 2876 /* Set EEE LPI Update Timer to 200usec */ 2877 ret_val = hw->phy.ops.acquire(hw); 2878 if (ret_val) 2879 return ret_val; 2880 ret_val = e1000_write_emi_reg_locked(hw, 2881 I82579_LPI_UPDATE_TIMER, 2882 0x1387); 2883 hw->phy.ops.release(hw); 2884 } 2885 2886 return ret_val; 2887 } 2888 2889 /** 2890 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset 2891 * @hw: pointer to the HW structure 2892 * 2893 * Resets the PHY 2894 * This is a function pointer entry point called by drivers 2895 * or other shared routines. 2896 **/ 2897 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) 2898 { 2899 s32 ret_val = 0; 2900 2901 /* Gate automatic PHY configuration by hardware on non-managed 82579 */ 2902 if ((hw->mac.type == e1000_pch2lan) && 2903 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 2904 e1000_gate_hw_phy_config_ich8lan(hw, true); 2905 2906 ret_val = e1000e_phy_hw_reset_generic(hw); 2907 if (ret_val) 2908 return ret_val; 2909 2910 return e1000_post_phy_reset_ich8lan(hw); 2911 } 2912 2913 /** 2914 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state 2915 * @hw: pointer to the HW structure 2916 * @active: true to enable LPLU, false to disable 2917 * 2918 * Sets the LPLU state according to the active flag. For PCH, if OEM write 2919 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set 2920 * the phy speed. This function will manually set the LPLU bit and restart 2921 * auto-neg as hw would do. D3 and D0 LPLU will call the same function 2922 * since it configures the same bit. 2923 **/ 2924 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) 2925 { 2926 s32 ret_val; 2927 u16 oem_reg; 2928 2929 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); 2930 if (ret_val) 2931 return ret_val; 2932 2933 if (active) 2934 oem_reg |= HV_OEM_BITS_LPLU; 2935 else 2936 oem_reg &= ~HV_OEM_BITS_LPLU; 2937 2938 if (!hw->phy.ops.check_reset_block(hw)) 2939 oem_reg |= HV_OEM_BITS_RESTART_AN; 2940 2941 return e1e_wphy(hw, HV_OEM_BITS, oem_reg); 2942 } 2943 2944 /** 2945 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state 2946 * @hw: pointer to the HW structure 2947 * @active: true to enable LPLU, false to disable 2948 * 2949 * Sets the LPLU D0 state according to the active flag. When 2950 * activating LPLU this function also disables smart speed 2951 * and vice versa. LPLU will not be activated unless the 2952 * device autonegotiation advertisement meets standards of 2953 * either 10 or 10/100 or 10/100/1000 at all duplexes. 2954 * This is a function pointer entry point only called by 2955 * PHY setup routines. 2956 **/ 2957 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 2958 { 2959 struct e1000_phy_info *phy = &hw->phy; 2960 u32 phy_ctrl; 2961 s32 ret_val = 0; 2962 u16 data; 2963 2964 if (phy->type == e1000_phy_ife) 2965 return 0; 2966 2967 phy_ctrl = er32(PHY_CTRL); 2968 2969 if (active) { 2970 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 2971 ew32(PHY_CTRL, phy_ctrl); 2972 2973 if (phy->type != e1000_phy_igp_3) 2974 return 0; 2975 2976 /* Call gig speed drop workaround on LPLU before accessing 2977 * any PHY registers 2978 */ 2979 if (hw->mac.type == e1000_ich8lan) 2980 e1000e_gig_downshift_workaround_ich8lan(hw); 2981 2982 /* When LPLU is enabled, we should disable SmartSpeed */ 2983 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 2984 if (ret_val) 2985 return ret_val; 2986 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2987 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 2988 if (ret_val) 2989 return ret_val; 2990 } else { 2991 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 2992 ew32(PHY_CTRL, phy_ctrl); 2993 2994 if (phy->type != e1000_phy_igp_3) 2995 return 0; 2996 2997 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 2998 * during Dx states where the power conservation is most 2999 * important. During driver activity we should enable 3000 * SmartSpeed, so performance is maintained. 3001 */ 3002 if (phy->smart_speed == e1000_smart_speed_on) { 3003 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3004 &data); 3005 if (ret_val) 3006 return ret_val; 3007 3008 data |= IGP01E1000_PSCFR_SMART_SPEED; 3009 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3010 data); 3011 if (ret_val) 3012 return ret_val; 3013 } else if (phy->smart_speed == e1000_smart_speed_off) { 3014 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3015 &data); 3016 if (ret_val) 3017 return ret_val; 3018 3019 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3020 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3021 data); 3022 if (ret_val) 3023 return ret_val; 3024 } 3025 } 3026 3027 return 0; 3028 } 3029 3030 /** 3031 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state 3032 * @hw: pointer to the HW structure 3033 * @active: true to enable LPLU, false to disable 3034 * 3035 * Sets the LPLU D3 state according to the active flag. When 3036 * activating LPLU this function also disables smart speed 3037 * and vice versa. LPLU will not be activated unless the 3038 * device autonegotiation advertisement meets standards of 3039 * either 10 or 10/100 or 10/100/1000 at all duplexes. 3040 * This is a function pointer entry point only called by 3041 * PHY setup routines. 3042 **/ 3043 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) 3044 { 3045 struct e1000_phy_info *phy = &hw->phy; 3046 u32 phy_ctrl; 3047 s32 ret_val = 0; 3048 u16 data; 3049 3050 phy_ctrl = er32(PHY_CTRL); 3051 3052 if (!active) { 3053 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 3054 ew32(PHY_CTRL, phy_ctrl); 3055 3056 if (phy->type != e1000_phy_igp_3) 3057 return 0; 3058 3059 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 3060 * during Dx states where the power conservation is most 3061 * important. During driver activity we should enable 3062 * SmartSpeed, so performance is maintained. 3063 */ 3064 if (phy->smart_speed == e1000_smart_speed_on) { 3065 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3066 &data); 3067 if (ret_val) 3068 return ret_val; 3069 3070 data |= IGP01E1000_PSCFR_SMART_SPEED; 3071 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3072 data); 3073 if (ret_val) 3074 return ret_val; 3075 } else if (phy->smart_speed == e1000_smart_speed_off) { 3076 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3077 &data); 3078 if (ret_val) 3079 return ret_val; 3080 3081 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3082 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 3083 data); 3084 if (ret_val) 3085 return ret_val; 3086 } 3087 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 3088 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 3089 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 3090 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 3091 ew32(PHY_CTRL, phy_ctrl); 3092 3093 if (phy->type != e1000_phy_igp_3) 3094 return 0; 3095 3096 /* Call gig speed drop workaround on LPLU before accessing 3097 * any PHY registers 3098 */ 3099 if (hw->mac.type == e1000_ich8lan) 3100 e1000e_gig_downshift_workaround_ich8lan(hw); 3101 3102 /* When LPLU is enabled, we should disable SmartSpeed */ 3103 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); 3104 if (ret_val) 3105 return ret_val; 3106 3107 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 3108 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); 3109 } 3110 3111 return ret_val; 3112 } 3113 3114 /** 3115 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 3116 * @hw: pointer to the HW structure 3117 * @bank: pointer to the variable that returns the active bank 3118 * 3119 * Reads signature byte from the NVM using the flash access registers. 3120 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. 3121 **/ 3122 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) 3123 { 3124 u32 eecd; 3125 struct e1000_nvm_info *nvm = &hw->nvm; 3126 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 3127 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 3128 u32 nvm_dword = 0; 3129 u8 sig_byte = 0; 3130 s32 ret_val; 3131 3132 switch (hw->mac.type) { 3133 case e1000_pch_spt: 3134 case e1000_pch_cnp: 3135 case e1000_pch_tgp: 3136 bank1_offset = nvm->flash_bank_size; 3137 act_offset = E1000_ICH_NVM_SIG_WORD; 3138 3139 /* set bank to 0 in case flash read fails */ 3140 *bank = 0; 3141 3142 /* Check bank 0 */ 3143 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, 3144 &nvm_dword); 3145 if (ret_val) 3146 return ret_val; 3147 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3148 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3149 E1000_ICH_NVM_SIG_VALUE) { 3150 *bank = 0; 3151 return 0; 3152 } 3153 3154 /* Check bank 1 */ 3155 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset + 3156 bank1_offset, 3157 &nvm_dword); 3158 if (ret_val) 3159 return ret_val; 3160 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8); 3161 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3162 E1000_ICH_NVM_SIG_VALUE) { 3163 *bank = 1; 3164 return 0; 3165 } 3166 3167 e_dbg("ERROR: No valid NVM bank present\n"); 3168 return -E1000_ERR_NVM; 3169 case e1000_ich8lan: 3170 case e1000_ich9lan: 3171 eecd = er32(EECD); 3172 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 3173 E1000_EECD_SEC1VAL_VALID_MASK) { 3174 if (eecd & E1000_EECD_SEC1VAL) 3175 *bank = 1; 3176 else 3177 *bank = 0; 3178 3179 return 0; 3180 } 3181 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); 3182 /* fall-thru */ 3183 default: 3184 /* set bank to 0 in case flash read fails */ 3185 *bank = 0; 3186 3187 /* Check bank 0 */ 3188 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, 3189 &sig_byte); 3190 if (ret_val) 3191 return ret_val; 3192 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3193 E1000_ICH_NVM_SIG_VALUE) { 3194 *bank = 0; 3195 return 0; 3196 } 3197 3198 /* Check bank 1 */ 3199 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + 3200 bank1_offset, 3201 &sig_byte); 3202 if (ret_val) 3203 return ret_val; 3204 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 3205 E1000_ICH_NVM_SIG_VALUE) { 3206 *bank = 1; 3207 return 0; 3208 } 3209 3210 e_dbg("ERROR: No valid NVM bank present\n"); 3211 return -E1000_ERR_NVM; 3212 } 3213 } 3214 3215 /** 3216 * e1000_read_nvm_spt - NVM access for SPT 3217 * @hw: pointer to the HW structure 3218 * @offset: The offset (in bytes) of the word(s) to read. 3219 * @words: Size of data to read in words. 3220 * @data: pointer to the word(s) to read at offset. 3221 * 3222 * Reads a word(s) from the NVM 3223 **/ 3224 static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words, 3225 u16 *data) 3226 { 3227 struct e1000_nvm_info *nvm = &hw->nvm; 3228 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3229 u32 act_offset; 3230 s32 ret_val = 0; 3231 u32 bank = 0; 3232 u32 dword = 0; 3233 u16 offset_to_read; 3234 u16 i; 3235 3236 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3237 (words == 0)) { 3238 e_dbg("nvm parameter(s) out of bounds\n"); 3239 ret_val = -E1000_ERR_NVM; 3240 goto out; 3241 } 3242 3243 nvm->ops.acquire(hw); 3244 3245 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3246 if (ret_val) { 3247 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3248 bank = 0; 3249 } 3250 3251 act_offset = (bank) ? nvm->flash_bank_size : 0; 3252 act_offset += offset; 3253 3254 ret_val = 0; 3255 3256 for (i = 0; i < words; i += 2) { 3257 if (words - i == 1) { 3258 if (dev_spec->shadow_ram[offset + i].modified) { 3259 data[i] = 3260 dev_spec->shadow_ram[offset + i].value; 3261 } else { 3262 offset_to_read = act_offset + i - 3263 ((act_offset + i) % 2); 3264 ret_val = 3265 e1000_read_flash_dword_ich8lan(hw, 3266 offset_to_read, 3267 &dword); 3268 if (ret_val) 3269 break; 3270 if ((act_offset + i) % 2 == 0) 3271 data[i] = (u16)(dword & 0xFFFF); 3272 else 3273 data[i] = (u16)((dword >> 16) & 0xFFFF); 3274 } 3275 } else { 3276 offset_to_read = act_offset + i; 3277 if (!(dev_spec->shadow_ram[offset + i].modified) || 3278 !(dev_spec->shadow_ram[offset + i + 1].modified)) { 3279 ret_val = 3280 e1000_read_flash_dword_ich8lan(hw, 3281 offset_to_read, 3282 &dword); 3283 if (ret_val) 3284 break; 3285 } 3286 if (dev_spec->shadow_ram[offset + i].modified) 3287 data[i] = 3288 dev_spec->shadow_ram[offset + i].value; 3289 else 3290 data[i] = (u16)(dword & 0xFFFF); 3291 if (dev_spec->shadow_ram[offset + i].modified) 3292 data[i + 1] = 3293 dev_spec->shadow_ram[offset + i + 1].value; 3294 else 3295 data[i + 1] = (u16)(dword >> 16 & 0xFFFF); 3296 } 3297 } 3298 3299 nvm->ops.release(hw); 3300 3301 out: 3302 if (ret_val) 3303 e_dbg("NVM read error: %d\n", ret_val); 3304 3305 return ret_val; 3306 } 3307 3308 /** 3309 * e1000_read_nvm_ich8lan - Read word(s) from the NVM 3310 * @hw: pointer to the HW structure 3311 * @offset: The offset (in bytes) of the word(s) to read. 3312 * @words: Size of data to read in words 3313 * @data: Pointer to the word(s) to read at offset. 3314 * 3315 * Reads a word(s) from the NVM using the flash access registers. 3316 **/ 3317 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3318 u16 *data) 3319 { 3320 struct e1000_nvm_info *nvm = &hw->nvm; 3321 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3322 u32 act_offset; 3323 s32 ret_val = 0; 3324 u32 bank = 0; 3325 u16 i, word; 3326 3327 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3328 (words == 0)) { 3329 e_dbg("nvm parameter(s) out of bounds\n"); 3330 ret_val = -E1000_ERR_NVM; 3331 goto out; 3332 } 3333 3334 nvm->ops.acquire(hw); 3335 3336 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3337 if (ret_val) { 3338 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3339 bank = 0; 3340 } 3341 3342 act_offset = (bank) ? nvm->flash_bank_size : 0; 3343 act_offset += offset; 3344 3345 ret_val = 0; 3346 for (i = 0; i < words; i++) { 3347 if (dev_spec->shadow_ram[offset + i].modified) { 3348 data[i] = dev_spec->shadow_ram[offset + i].value; 3349 } else { 3350 ret_val = e1000_read_flash_word_ich8lan(hw, 3351 act_offset + i, 3352 &word); 3353 if (ret_val) 3354 break; 3355 data[i] = word; 3356 } 3357 } 3358 3359 nvm->ops.release(hw); 3360 3361 out: 3362 if (ret_val) 3363 e_dbg("NVM read error: %d\n", ret_val); 3364 3365 return ret_val; 3366 } 3367 3368 /** 3369 * e1000_flash_cycle_init_ich8lan - Initialize flash 3370 * @hw: pointer to the HW structure 3371 * 3372 * This function does initial flash setup so that a new read/write/erase cycle 3373 * can be started. 3374 **/ 3375 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) 3376 { 3377 union ich8_hws_flash_status hsfsts; 3378 s32 ret_val = -E1000_ERR_NVM; 3379 3380 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3381 3382 /* Check if the flash descriptor is valid */ 3383 if (!hsfsts.hsf_status.fldesvalid) { 3384 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n"); 3385 return -E1000_ERR_NVM; 3386 } 3387 3388 /* Clear FCERR and DAEL in hw status by writing 1 */ 3389 hsfsts.hsf_status.flcerr = 1; 3390 hsfsts.hsf_status.dael = 1; 3391 if (hw->mac.type >= e1000_pch_spt) 3392 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3393 else 3394 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3395 3396 /* Either we should have a hardware SPI cycle in progress 3397 * bit to check against, in order to start a new cycle or 3398 * FDONE bit should be changed in the hardware so that it 3399 * is 1 after hardware reset, which can then be used as an 3400 * indication whether a cycle is in progress or has been 3401 * completed. 3402 */ 3403 3404 if (!hsfsts.hsf_status.flcinprog) { 3405 /* There is no cycle running at present, 3406 * so we can start a cycle. 3407 * Begin by setting Flash Cycle Done. 3408 */ 3409 hsfsts.hsf_status.flcdone = 1; 3410 if (hw->mac.type >= e1000_pch_spt) 3411 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF); 3412 else 3413 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3414 ret_val = 0; 3415 } else { 3416 s32 i; 3417 3418 /* Otherwise poll for sometime so the current 3419 * cycle has a chance to end before giving up. 3420 */ 3421 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 3422 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3423 if (!hsfsts.hsf_status.flcinprog) { 3424 ret_val = 0; 3425 break; 3426 } 3427 udelay(1); 3428 } 3429 if (!ret_val) { 3430 /* Successful in waiting for previous cycle to timeout, 3431 * now set the Flash Cycle Done. 3432 */ 3433 hsfsts.hsf_status.flcdone = 1; 3434 if (hw->mac.type >= e1000_pch_spt) 3435 ew32flash(ICH_FLASH_HSFSTS, 3436 hsfsts.regval & 0xFFFF); 3437 else 3438 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 3439 } else { 3440 e_dbg("Flash controller busy, cannot get access\n"); 3441 } 3442 } 3443 3444 return ret_val; 3445 } 3446 3447 /** 3448 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) 3449 * @hw: pointer to the HW structure 3450 * @timeout: maximum time to wait for completion 3451 * 3452 * This function starts a flash cycle and waits for its completion. 3453 **/ 3454 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) 3455 { 3456 union ich8_hws_flash_ctrl hsflctl; 3457 union ich8_hws_flash_status hsfsts; 3458 u32 i = 0; 3459 3460 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 3461 if (hw->mac.type >= e1000_pch_spt) 3462 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3463 else 3464 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3465 hsflctl.hsf_ctrl.flcgo = 1; 3466 3467 if (hw->mac.type >= e1000_pch_spt) 3468 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 3469 else 3470 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3471 3472 /* wait till FDONE bit is set to 1 */ 3473 do { 3474 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3475 if (hsfsts.hsf_status.flcdone) 3476 break; 3477 udelay(1); 3478 } while (i++ < timeout); 3479 3480 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) 3481 return 0; 3482 3483 return -E1000_ERR_NVM; 3484 } 3485 3486 /** 3487 * e1000_read_flash_dword_ich8lan - Read dword from flash 3488 * @hw: pointer to the HW structure 3489 * @offset: offset to data location 3490 * @data: pointer to the location for storing the data 3491 * 3492 * Reads the flash dword at offset into data. Offset is converted 3493 * to bytes before read. 3494 **/ 3495 static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset, 3496 u32 *data) 3497 { 3498 /* Must convert word offset into bytes. */ 3499 offset <<= 1; 3500 return e1000_read_flash_data32_ich8lan(hw, offset, data); 3501 } 3502 3503 /** 3504 * e1000_read_flash_word_ich8lan - Read word from flash 3505 * @hw: pointer to the HW structure 3506 * @offset: offset to data location 3507 * @data: pointer to the location for storing the data 3508 * 3509 * Reads the flash word at offset into data. Offset is converted 3510 * to bytes before read. 3511 **/ 3512 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, 3513 u16 *data) 3514 { 3515 /* Must convert offset into bytes. */ 3516 offset <<= 1; 3517 3518 return e1000_read_flash_data_ich8lan(hw, offset, 2, data); 3519 } 3520 3521 /** 3522 * e1000_read_flash_byte_ich8lan - Read byte from flash 3523 * @hw: pointer to the HW structure 3524 * @offset: The offset of the byte to read. 3525 * @data: Pointer to a byte to store the value read. 3526 * 3527 * Reads a single byte from the NVM using the flash access registers. 3528 **/ 3529 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 3530 u8 *data) 3531 { 3532 s32 ret_val; 3533 u16 word = 0; 3534 3535 /* In SPT, only 32 bits access is supported, 3536 * so this function should not be called. 3537 */ 3538 if (hw->mac.type >= e1000_pch_spt) 3539 return -E1000_ERR_NVM; 3540 else 3541 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); 3542 3543 if (ret_val) 3544 return ret_val; 3545 3546 *data = (u8)word; 3547 3548 return 0; 3549 } 3550 3551 /** 3552 * e1000_read_flash_data_ich8lan - Read byte or word from NVM 3553 * @hw: pointer to the HW structure 3554 * @offset: The offset (in bytes) of the byte or word to read. 3555 * @size: Size of data to read, 1=byte 2=word 3556 * @data: Pointer to the word to store the value read. 3557 * 3558 * Reads a byte or word from the NVM using the flash access registers. 3559 **/ 3560 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 3561 u8 size, u16 *data) 3562 { 3563 union ich8_hws_flash_status hsfsts; 3564 union ich8_hws_flash_ctrl hsflctl; 3565 u32 flash_linear_addr; 3566 u32 flash_data = 0; 3567 s32 ret_val = -E1000_ERR_NVM; 3568 u8 count = 0; 3569 3570 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 3571 return -E1000_ERR_NVM; 3572 3573 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3574 hw->nvm.flash_base_addr); 3575 3576 do { 3577 udelay(1); 3578 /* Steps */ 3579 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3580 if (ret_val) 3581 break; 3582 3583 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 3584 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3585 hsflctl.hsf_ctrl.fldbcount = size - 1; 3586 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3587 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 3588 3589 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3590 3591 ret_val = 3592 e1000_flash_cycle_ich8lan(hw, 3593 ICH_FLASH_READ_COMMAND_TIMEOUT); 3594 3595 /* Check if FCERR is set to 1, if set to 1, clear it 3596 * and try the whole sequence a few more times, else 3597 * read in (shift in) the Flash Data0, the order is 3598 * least significant byte first msb to lsb 3599 */ 3600 if (!ret_val) { 3601 flash_data = er32flash(ICH_FLASH_FDATA0); 3602 if (size == 1) 3603 *data = (u8)(flash_data & 0x000000FF); 3604 else if (size == 2) 3605 *data = (u16)(flash_data & 0x0000FFFF); 3606 break; 3607 } else { 3608 /* If we've gotten here, then things are probably 3609 * completely hosed, but if the error condition is 3610 * detected, it won't hurt to give it another try... 3611 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3612 */ 3613 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3614 if (hsfsts.hsf_status.flcerr) { 3615 /* Repeat for some time before giving up. */ 3616 continue; 3617 } else if (!hsfsts.hsf_status.flcdone) { 3618 e_dbg("Timeout error - flash cycle did not complete.\n"); 3619 break; 3620 } 3621 } 3622 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3623 3624 return ret_val; 3625 } 3626 3627 /** 3628 * e1000_read_flash_data32_ich8lan - Read dword from NVM 3629 * @hw: pointer to the HW structure 3630 * @offset: The offset (in bytes) of the dword to read. 3631 * @data: Pointer to the dword to store the value read. 3632 * 3633 * Reads a byte or word from the NVM using the flash access registers. 3634 **/ 3635 3636 static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 3637 u32 *data) 3638 { 3639 union ich8_hws_flash_status hsfsts; 3640 union ich8_hws_flash_ctrl hsflctl; 3641 u32 flash_linear_addr; 3642 s32 ret_val = -E1000_ERR_NVM; 3643 u8 count = 0; 3644 3645 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt) 3646 return -E1000_ERR_NVM; 3647 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 3648 hw->nvm.flash_base_addr); 3649 3650 do { 3651 udelay(1); 3652 /* Steps */ 3653 ret_val = e1000_flash_cycle_init_ich8lan(hw); 3654 if (ret_val) 3655 break; 3656 /* In SPT, This register is in Lan memory space, not flash. 3657 * Therefore, only 32 bit access is supported 3658 */ 3659 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 3660 3661 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 3662 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 3663 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 3664 /* In SPT, This register is in Lan memory space, not flash. 3665 * Therefore, only 32 bit access is supported 3666 */ 3667 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16); 3668 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 3669 3670 ret_val = 3671 e1000_flash_cycle_ich8lan(hw, 3672 ICH_FLASH_READ_COMMAND_TIMEOUT); 3673 3674 /* Check if FCERR is set to 1, if set to 1, clear it 3675 * and try the whole sequence a few more times, else 3676 * read in (shift in) the Flash Data0, the order is 3677 * least significant byte first msb to lsb 3678 */ 3679 if (!ret_val) { 3680 *data = er32flash(ICH_FLASH_FDATA0); 3681 break; 3682 } else { 3683 /* If we've gotten here, then things are probably 3684 * completely hosed, but if the error condition is 3685 * detected, it won't hurt to give it another try... 3686 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 3687 */ 3688 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 3689 if (hsfsts.hsf_status.flcerr) { 3690 /* Repeat for some time before giving up. */ 3691 continue; 3692 } else if (!hsfsts.hsf_status.flcdone) { 3693 e_dbg("Timeout error - flash cycle did not complete.\n"); 3694 break; 3695 } 3696 } 3697 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 3698 3699 return ret_val; 3700 } 3701 3702 /** 3703 * e1000_write_nvm_ich8lan - Write word(s) to the NVM 3704 * @hw: pointer to the HW structure 3705 * @offset: The offset (in bytes) of the word(s) to write. 3706 * @words: Size of data to write in words 3707 * @data: Pointer to the word(s) to write at offset. 3708 * 3709 * Writes a byte or word to the NVM using the flash access registers. 3710 **/ 3711 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, 3712 u16 *data) 3713 { 3714 struct e1000_nvm_info *nvm = &hw->nvm; 3715 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3716 u16 i; 3717 3718 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 3719 (words == 0)) { 3720 e_dbg("nvm parameter(s) out of bounds\n"); 3721 return -E1000_ERR_NVM; 3722 } 3723 3724 nvm->ops.acquire(hw); 3725 3726 for (i = 0; i < words; i++) { 3727 dev_spec->shadow_ram[offset + i].modified = true; 3728 dev_spec->shadow_ram[offset + i].value = data[i]; 3729 } 3730 3731 nvm->ops.release(hw); 3732 3733 return 0; 3734 } 3735 3736 /** 3737 * e1000_update_nvm_checksum_spt - Update the checksum for NVM 3738 * @hw: pointer to the HW structure 3739 * 3740 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3741 * which writes the checksum to the shadow ram. The changes in the shadow 3742 * ram are then committed to the EEPROM by processing each bank at a time 3743 * checking for the modified bit and writing only the pending changes. 3744 * After a successful commit, the shadow ram is cleared and is ready for 3745 * future writes. 3746 **/ 3747 static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw) 3748 { 3749 struct e1000_nvm_info *nvm = &hw->nvm; 3750 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3751 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3752 s32 ret_val; 3753 u32 dword = 0; 3754 3755 ret_val = e1000e_update_nvm_checksum_generic(hw); 3756 if (ret_val) 3757 goto out; 3758 3759 if (nvm->type != e1000_nvm_flash_sw) 3760 goto out; 3761 3762 nvm->ops.acquire(hw); 3763 3764 /* We're writing to the opposite bank so if we're on bank 1, 3765 * write to bank 0 etc. We also need to erase the segment that 3766 * is going to be written 3767 */ 3768 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3769 if (ret_val) { 3770 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3771 bank = 0; 3772 } 3773 3774 if (bank == 0) { 3775 new_bank_offset = nvm->flash_bank_size; 3776 old_bank_offset = 0; 3777 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3778 if (ret_val) 3779 goto release; 3780 } else { 3781 old_bank_offset = nvm->flash_bank_size; 3782 new_bank_offset = 0; 3783 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 3784 if (ret_val) 3785 goto release; 3786 } 3787 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) { 3788 /* Determine whether to write the value stored 3789 * in the other NVM bank or a modified value stored 3790 * in the shadow RAM 3791 */ 3792 ret_val = e1000_read_flash_dword_ich8lan(hw, 3793 i + old_bank_offset, 3794 &dword); 3795 3796 if (dev_spec->shadow_ram[i].modified) { 3797 dword &= 0xffff0000; 3798 dword |= (dev_spec->shadow_ram[i].value & 0xffff); 3799 } 3800 if (dev_spec->shadow_ram[i + 1].modified) { 3801 dword &= 0x0000ffff; 3802 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff) 3803 << 16); 3804 } 3805 if (ret_val) 3806 break; 3807 3808 /* If the word is 0x13, then make sure the signature bits 3809 * (15:14) are 11b until the commit has completed. 3810 * This will allow us to write 10b which indicates the 3811 * signature is valid. We want to do this after the write 3812 * has completed so that we don't mark the segment valid 3813 * while the write is still in progress 3814 */ 3815 if (i == E1000_ICH_NVM_SIG_WORD - 1) 3816 dword |= E1000_ICH_NVM_SIG_MASK << 16; 3817 3818 /* Convert offset to bytes. */ 3819 act_offset = (i + new_bank_offset) << 1; 3820 3821 usleep_range(100, 200); 3822 3823 /* Write the data to the new bank. Offset in words */ 3824 act_offset = i + new_bank_offset; 3825 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, 3826 dword); 3827 if (ret_val) 3828 break; 3829 } 3830 3831 /* Don't bother writing the segment valid bits if sector 3832 * programming failed. 3833 */ 3834 if (ret_val) { 3835 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 3836 e_dbg("Flash commit failed.\n"); 3837 goto release; 3838 } 3839 3840 /* Finally validate the new segment by setting bit 15:14 3841 * to 10b in word 0x13 , this can be done without an 3842 * erase as well since these bits are 11 to start with 3843 * and we need to change bit 14 to 0b 3844 */ 3845 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 3846 3847 /*offset in words but we read dword */ 3848 --act_offset; 3849 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 3850 3851 if (ret_val) 3852 goto release; 3853 3854 dword &= 0xBFFFFFFF; 3855 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 3856 3857 if (ret_val) 3858 goto release; 3859 3860 /* And invalidate the previously valid segment by setting 3861 * its signature word (0x13) high_byte to 0b. This can be 3862 * done without an erase because flash erase sets all bits 3863 * to 1's. We can write 1's to 0's without an erase 3864 */ 3865 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 3866 3867 /* offset in words but we read dword */ 3868 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1; 3869 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword); 3870 3871 if (ret_val) 3872 goto release; 3873 3874 dword &= 0x00FFFFFF; 3875 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword); 3876 3877 if (ret_val) 3878 goto release; 3879 3880 /* Great! Everything worked, we can now clear the cached entries. */ 3881 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 3882 dev_spec->shadow_ram[i].modified = false; 3883 dev_spec->shadow_ram[i].value = 0xFFFF; 3884 } 3885 3886 release: 3887 nvm->ops.release(hw); 3888 3889 /* Reload the EEPROM, or else modifications will not appear 3890 * until after the next adapter reset. 3891 */ 3892 if (!ret_val) { 3893 nvm->ops.reload(hw); 3894 usleep_range(10000, 11000); 3895 } 3896 3897 out: 3898 if (ret_val) 3899 e_dbg("NVM update error: %d\n", ret_val); 3900 3901 return ret_val; 3902 } 3903 3904 /** 3905 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM 3906 * @hw: pointer to the HW structure 3907 * 3908 * The NVM checksum is updated by calling the generic update_nvm_checksum, 3909 * which writes the checksum to the shadow ram. The changes in the shadow 3910 * ram are then committed to the EEPROM by processing each bank at a time 3911 * checking for the modified bit and writing only the pending changes. 3912 * After a successful commit, the shadow ram is cleared and is ready for 3913 * future writes. 3914 **/ 3915 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) 3916 { 3917 struct e1000_nvm_info *nvm = &hw->nvm; 3918 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 3919 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 3920 s32 ret_val; 3921 u16 data = 0; 3922 3923 ret_val = e1000e_update_nvm_checksum_generic(hw); 3924 if (ret_val) 3925 goto out; 3926 3927 if (nvm->type != e1000_nvm_flash_sw) 3928 goto out; 3929 3930 nvm->ops.acquire(hw); 3931 3932 /* We're writing to the opposite bank so if we're on bank 1, 3933 * write to bank 0 etc. We also need to erase the segment that 3934 * is going to be written 3935 */ 3936 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); 3937 if (ret_val) { 3938 e_dbg("Could not detect valid bank, assuming bank 0\n"); 3939 bank = 0; 3940 } 3941 3942 if (bank == 0) { 3943 new_bank_offset = nvm->flash_bank_size; 3944 old_bank_offset = 0; 3945 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); 3946 if (ret_val) 3947 goto release; 3948 } else { 3949 old_bank_offset = nvm->flash_bank_size; 3950 new_bank_offset = 0; 3951 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); 3952 if (ret_val) 3953 goto release; 3954 } 3955 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 3956 if (dev_spec->shadow_ram[i].modified) { 3957 data = dev_spec->shadow_ram[i].value; 3958 } else { 3959 ret_val = e1000_read_flash_word_ich8lan(hw, i + 3960 old_bank_offset, 3961 &data); 3962 if (ret_val) 3963 break; 3964 } 3965 3966 /* If the word is 0x13, then make sure the signature bits 3967 * (15:14) are 11b until the commit has completed. 3968 * This will allow us to write 10b which indicates the 3969 * signature is valid. We want to do this after the write 3970 * has completed so that we don't mark the segment valid 3971 * while the write is still in progress 3972 */ 3973 if (i == E1000_ICH_NVM_SIG_WORD) 3974 data |= E1000_ICH_NVM_SIG_MASK; 3975 3976 /* Convert offset to bytes. */ 3977 act_offset = (i + new_bank_offset) << 1; 3978 3979 usleep_range(100, 200); 3980 /* Write the bytes to the new bank. */ 3981 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 3982 act_offset, 3983 (u8)data); 3984 if (ret_val) 3985 break; 3986 3987 usleep_range(100, 200); 3988 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 3989 act_offset + 1, 3990 (u8)(data >> 8)); 3991 if (ret_val) 3992 break; 3993 } 3994 3995 /* Don't bother writing the segment valid bits if sector 3996 * programming failed. 3997 */ 3998 if (ret_val) { 3999 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ 4000 e_dbg("Flash commit failed.\n"); 4001 goto release; 4002 } 4003 4004 /* Finally validate the new segment by setting bit 15:14 4005 * to 10b in word 0x13 , this can be done without an 4006 * erase as well since these bits are 11 to start with 4007 * and we need to change bit 14 to 0b 4008 */ 4009 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 4010 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); 4011 if (ret_val) 4012 goto release; 4013 4014 data &= 0xBFFF; 4015 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, 4016 act_offset * 2 + 1, 4017 (u8)(data >> 8)); 4018 if (ret_val) 4019 goto release; 4020 4021 /* And invalidate the previously valid segment by setting 4022 * its signature word (0x13) high_byte to 0b. This can be 4023 * done without an erase because flash erase sets all bits 4024 * to 1's. We can write 1's to 0's without an erase 4025 */ 4026 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 4027 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 4028 if (ret_val) 4029 goto release; 4030 4031 /* Great! Everything worked, we can now clear the cached entries. */ 4032 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 4033 dev_spec->shadow_ram[i].modified = false; 4034 dev_spec->shadow_ram[i].value = 0xFFFF; 4035 } 4036 4037 release: 4038 nvm->ops.release(hw); 4039 4040 /* Reload the EEPROM, or else modifications will not appear 4041 * until after the next adapter reset. 4042 */ 4043 if (!ret_val) { 4044 nvm->ops.reload(hw); 4045 usleep_range(10000, 11000); 4046 } 4047 4048 out: 4049 if (ret_val) 4050 e_dbg("NVM update error: %d\n", ret_val); 4051 4052 return ret_val; 4053 } 4054 4055 /** 4056 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum 4057 * @hw: pointer to the HW structure 4058 * 4059 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. 4060 * If the bit is 0, that the EEPROM had been modified, but the checksum was not 4061 * calculated, in which case we need to calculate the checksum and set bit 6. 4062 **/ 4063 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) 4064 { 4065 s32 ret_val; 4066 u16 data; 4067 u16 word; 4068 u16 valid_csum_mask; 4069 4070 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, 4071 * the checksum needs to be fixed. This bit is an indication that 4072 * the NVM was prepared by OEM software and did not calculate 4073 * the checksum...a likely scenario. 4074 */ 4075 switch (hw->mac.type) { 4076 case e1000_pch_lpt: 4077 case e1000_pch_spt: 4078 case e1000_pch_cnp: 4079 case e1000_pch_tgp: 4080 word = NVM_COMPAT; 4081 valid_csum_mask = NVM_COMPAT_VALID_CSUM; 4082 break; 4083 default: 4084 word = NVM_FUTURE_INIT_WORD1; 4085 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; 4086 break; 4087 } 4088 4089 ret_val = e1000_read_nvm(hw, word, 1, &data); 4090 if (ret_val) 4091 return ret_val; 4092 4093 if (!(data & valid_csum_mask)) { 4094 data |= valid_csum_mask; 4095 ret_val = e1000_write_nvm(hw, word, 1, &data); 4096 if (ret_val) 4097 return ret_val; 4098 ret_val = e1000e_update_nvm_checksum(hw); 4099 if (ret_val) 4100 return ret_val; 4101 } 4102 4103 return e1000e_validate_nvm_checksum_generic(hw); 4104 } 4105 4106 /** 4107 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only 4108 * @hw: pointer to the HW structure 4109 * 4110 * To prevent malicious write/erase of the NVM, set it to be read-only 4111 * so that the hardware ignores all write/erase cycles of the NVM via 4112 * the flash control registers. The shadow-ram copy of the NVM will 4113 * still be updated, however any updates to this copy will not stick 4114 * across driver reloads. 4115 **/ 4116 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) 4117 { 4118 struct e1000_nvm_info *nvm = &hw->nvm; 4119 union ich8_flash_protected_range pr0; 4120 union ich8_hws_flash_status hsfsts; 4121 u32 gfpreg; 4122 4123 nvm->ops.acquire(hw); 4124 4125 gfpreg = er32flash(ICH_FLASH_GFPREG); 4126 4127 /* Write-protect GbE Sector of NVM */ 4128 pr0.regval = er32flash(ICH_FLASH_PR0); 4129 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; 4130 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); 4131 pr0.range.wpe = true; 4132 ew32flash(ICH_FLASH_PR0, pr0.regval); 4133 4134 /* Lock down a subset of GbE Flash Control Registers, e.g. 4135 * PR0 to prevent the write-protection from being lifted. 4136 * Once FLOCKDN is set, the registers protected by it cannot 4137 * be written until FLOCKDN is cleared by a hardware reset. 4138 */ 4139 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4140 hsfsts.hsf_status.flockdn = true; 4141 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); 4142 4143 nvm->ops.release(hw); 4144 } 4145 4146 /** 4147 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM 4148 * @hw: pointer to the HW structure 4149 * @offset: The offset (in bytes) of the byte/word to read. 4150 * @size: Size of data to read, 1=byte 2=word 4151 * @data: The byte(s) to write to the NVM. 4152 * 4153 * Writes one/two bytes to the NVM using the flash access registers. 4154 **/ 4155 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, 4156 u8 size, u16 data) 4157 { 4158 union ich8_hws_flash_status hsfsts; 4159 union ich8_hws_flash_ctrl hsflctl; 4160 u32 flash_linear_addr; 4161 u32 flash_data = 0; 4162 s32 ret_val; 4163 u8 count = 0; 4164 4165 if (hw->mac.type >= e1000_pch_spt) { 4166 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4167 return -E1000_ERR_NVM; 4168 } else { 4169 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 4170 return -E1000_ERR_NVM; 4171 } 4172 4173 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4174 hw->nvm.flash_base_addr); 4175 4176 do { 4177 udelay(1); 4178 /* Steps */ 4179 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4180 if (ret_val) 4181 break; 4182 /* In SPT, This register is in Lan memory space, not 4183 * flash. Therefore, only 32 bit access is supported 4184 */ 4185 if (hw->mac.type >= e1000_pch_spt) 4186 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16; 4187 else 4188 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4189 4190 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 4191 hsflctl.hsf_ctrl.fldbcount = size - 1; 4192 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4193 /* In SPT, This register is in Lan memory space, 4194 * not flash. Therefore, only 32 bit access is 4195 * supported 4196 */ 4197 if (hw->mac.type >= e1000_pch_spt) 4198 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4199 else 4200 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4201 4202 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4203 4204 if (size == 1) 4205 flash_data = (u32)data & 0x00FF; 4206 else 4207 flash_data = (u32)data; 4208 4209 ew32flash(ICH_FLASH_FDATA0, flash_data); 4210 4211 /* check if FCERR is set to 1 , if set to 1, clear it 4212 * and try the whole sequence a few more times else done 4213 */ 4214 ret_val = 4215 e1000_flash_cycle_ich8lan(hw, 4216 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4217 if (!ret_val) 4218 break; 4219 4220 /* If we're here, then things are most likely 4221 * completely hosed, but if the error condition 4222 * is detected, it won't hurt to give it another 4223 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4224 */ 4225 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4226 if (hsfsts.hsf_status.flcerr) 4227 /* Repeat for some time before giving up. */ 4228 continue; 4229 if (!hsfsts.hsf_status.flcdone) { 4230 e_dbg("Timeout error - flash cycle did not complete.\n"); 4231 break; 4232 } 4233 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4234 4235 return ret_val; 4236 } 4237 4238 /** 4239 * e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM 4240 * @hw: pointer to the HW structure 4241 * @offset: The offset (in bytes) of the dwords to read. 4242 * @data: The 4 bytes to write to the NVM. 4243 * 4244 * Writes one/two/four bytes to the NVM using the flash access registers. 4245 **/ 4246 static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset, 4247 u32 data) 4248 { 4249 union ich8_hws_flash_status hsfsts; 4250 union ich8_hws_flash_ctrl hsflctl; 4251 u32 flash_linear_addr; 4252 s32 ret_val; 4253 u8 count = 0; 4254 4255 if (hw->mac.type >= e1000_pch_spt) { 4256 if (offset > ICH_FLASH_LINEAR_ADDR_MASK) 4257 return -E1000_ERR_NVM; 4258 } 4259 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) + 4260 hw->nvm.flash_base_addr); 4261 do { 4262 udelay(1); 4263 /* Steps */ 4264 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4265 if (ret_val) 4266 break; 4267 4268 /* In SPT, This register is in Lan memory space, not 4269 * flash. Therefore, only 32 bit access is supported 4270 */ 4271 if (hw->mac.type >= e1000_pch_spt) 4272 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) 4273 >> 16; 4274 else 4275 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4276 4277 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1; 4278 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 4279 4280 /* In SPT, This register is in Lan memory space, 4281 * not flash. Therefore, only 32 bit access is 4282 * supported 4283 */ 4284 if (hw->mac.type >= e1000_pch_spt) 4285 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16); 4286 else 4287 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4288 4289 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4290 4291 ew32flash(ICH_FLASH_FDATA0, data); 4292 4293 /* check if FCERR is set to 1 , if set to 1, clear it 4294 * and try the whole sequence a few more times else done 4295 */ 4296 ret_val = 4297 e1000_flash_cycle_ich8lan(hw, 4298 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 4299 4300 if (!ret_val) 4301 break; 4302 4303 /* If we're here, then things are most likely 4304 * completely hosed, but if the error condition 4305 * is detected, it won't hurt to give it another 4306 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 4307 */ 4308 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4309 4310 if (hsfsts.hsf_status.flcerr) 4311 /* Repeat for some time before giving up. */ 4312 continue; 4313 if (!hsfsts.hsf_status.flcdone) { 4314 e_dbg("Timeout error - flash cycle did not complete.\n"); 4315 break; 4316 } 4317 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 4318 4319 return ret_val; 4320 } 4321 4322 /** 4323 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM 4324 * @hw: pointer to the HW structure 4325 * @offset: The index of the byte to read. 4326 * @data: The byte to write to the NVM. 4327 * 4328 * Writes a single byte to the NVM using the flash access registers. 4329 **/ 4330 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, 4331 u8 data) 4332 { 4333 u16 word = (u16)data; 4334 4335 return e1000_write_flash_data_ich8lan(hw, offset, 1, word); 4336 } 4337 4338 /** 4339 * e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM 4340 * @hw: pointer to the HW structure 4341 * @offset: The offset of the word to write. 4342 * @dword: The dword to write to the NVM. 4343 * 4344 * Writes a single dword to the NVM using the flash access registers. 4345 * Goes through a retry algorithm before giving up. 4346 **/ 4347 static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw, 4348 u32 offset, u32 dword) 4349 { 4350 s32 ret_val; 4351 u16 program_retries; 4352 4353 /* Must convert word offset into bytes. */ 4354 offset <<= 1; 4355 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4356 4357 if (!ret_val) 4358 return ret_val; 4359 for (program_retries = 0; program_retries < 100; program_retries++) { 4360 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset); 4361 usleep_range(100, 200); 4362 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword); 4363 if (!ret_val) 4364 break; 4365 } 4366 if (program_retries == 100) 4367 return -E1000_ERR_NVM; 4368 4369 return 0; 4370 } 4371 4372 /** 4373 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM 4374 * @hw: pointer to the HW structure 4375 * @offset: The offset of the byte to write. 4376 * @byte: The byte to write to the NVM. 4377 * 4378 * Writes a single byte to the NVM using the flash access registers. 4379 * Goes through a retry algorithm before giving up. 4380 **/ 4381 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, 4382 u32 offset, u8 byte) 4383 { 4384 s32 ret_val; 4385 u16 program_retries; 4386 4387 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4388 if (!ret_val) 4389 return ret_val; 4390 4391 for (program_retries = 0; program_retries < 100; program_retries++) { 4392 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); 4393 usleep_range(100, 200); 4394 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); 4395 if (!ret_val) 4396 break; 4397 } 4398 if (program_retries == 100) 4399 return -E1000_ERR_NVM; 4400 4401 return 0; 4402 } 4403 4404 /** 4405 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM 4406 * @hw: pointer to the HW structure 4407 * @bank: 0 for first bank, 1 for second bank, etc. 4408 * 4409 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. 4410 * bank N is 4096 * N + flash_reg_addr. 4411 **/ 4412 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) 4413 { 4414 struct e1000_nvm_info *nvm = &hw->nvm; 4415 union ich8_hws_flash_status hsfsts; 4416 union ich8_hws_flash_ctrl hsflctl; 4417 u32 flash_linear_addr; 4418 /* bank size is in 16bit words - adjust to bytes */ 4419 u32 flash_bank_size = nvm->flash_bank_size * 2; 4420 s32 ret_val; 4421 s32 count = 0; 4422 s32 j, iteration, sector_size; 4423 4424 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4425 4426 /* Determine HW Sector size: Read BERASE bits of hw flash status 4427 * register 4428 * 00: The Hw sector is 256 bytes, hence we need to erase 16 4429 * consecutive sectors. The start index for the nth Hw sector 4430 * can be calculated as = bank * 4096 + n * 256 4431 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 4432 * The start index for the nth Hw sector can be calculated 4433 * as = bank * 4096 4434 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 4435 * (ich9 only, otherwise error condition) 4436 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 4437 */ 4438 switch (hsfsts.hsf_status.berasesz) { 4439 case 0: 4440 /* Hw sector size 256 */ 4441 sector_size = ICH_FLASH_SEG_SIZE_256; 4442 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 4443 break; 4444 case 1: 4445 sector_size = ICH_FLASH_SEG_SIZE_4K; 4446 iteration = 1; 4447 break; 4448 case 2: 4449 sector_size = ICH_FLASH_SEG_SIZE_8K; 4450 iteration = 1; 4451 break; 4452 case 3: 4453 sector_size = ICH_FLASH_SEG_SIZE_64K; 4454 iteration = 1; 4455 break; 4456 default: 4457 return -E1000_ERR_NVM; 4458 } 4459 4460 /* Start with the base address, then add the sector offset. */ 4461 flash_linear_addr = hw->nvm.flash_base_addr; 4462 flash_linear_addr += (bank) ? flash_bank_size : 0; 4463 4464 for (j = 0; j < iteration; j++) { 4465 do { 4466 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT; 4467 4468 /* Steps */ 4469 ret_val = e1000_flash_cycle_init_ich8lan(hw); 4470 if (ret_val) 4471 return ret_val; 4472 4473 /* Write a value 11 (block Erase) in Flash 4474 * Cycle field in hw flash control 4475 */ 4476 if (hw->mac.type >= e1000_pch_spt) 4477 hsflctl.regval = 4478 er32flash(ICH_FLASH_HSFSTS) >> 16; 4479 else 4480 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 4481 4482 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 4483 if (hw->mac.type >= e1000_pch_spt) 4484 ew32flash(ICH_FLASH_HSFSTS, 4485 hsflctl.regval << 16); 4486 else 4487 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 4488 4489 /* Write the last 24 bits of an index within the 4490 * block into Flash Linear address field in Flash 4491 * Address. 4492 */ 4493 flash_linear_addr += (j * sector_size); 4494 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 4495 4496 ret_val = e1000_flash_cycle_ich8lan(hw, timeout); 4497 if (!ret_val) 4498 break; 4499 4500 /* Check if FCERR is set to 1. If 1, 4501 * clear it and try the whole sequence 4502 * a few more times else Done 4503 */ 4504 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 4505 if (hsfsts.hsf_status.flcerr) 4506 /* repeat for some time before giving up */ 4507 continue; 4508 else if (!hsfsts.hsf_status.flcdone) 4509 return ret_val; 4510 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 4511 } 4512 4513 return 0; 4514 } 4515 4516 /** 4517 * e1000_valid_led_default_ich8lan - Set the default LED settings 4518 * @hw: pointer to the HW structure 4519 * @data: Pointer to the LED settings 4520 * 4521 * Reads the LED default settings from the NVM to data. If the NVM LED 4522 * settings is all 0's or F's, set the LED default to a valid LED default 4523 * setting. 4524 **/ 4525 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) 4526 { 4527 s32 ret_val; 4528 4529 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 4530 if (ret_val) { 4531 e_dbg("NVM Read Error\n"); 4532 return ret_val; 4533 } 4534 4535 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 4536 *data = ID_LED_DEFAULT_ICH8LAN; 4537 4538 return 0; 4539 } 4540 4541 /** 4542 * e1000_id_led_init_pchlan - store LED configurations 4543 * @hw: pointer to the HW structure 4544 * 4545 * PCH does not control LEDs via the LEDCTL register, rather it uses 4546 * the PHY LED configuration register. 4547 * 4548 * PCH also does not have an "always on" or "always off" mode which 4549 * complicates the ID feature. Instead of using the "on" mode to indicate 4550 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()), 4551 * use "link_up" mode. The LEDs will still ID on request if there is no 4552 * link based on logic in e1000_led_[on|off]_pchlan(). 4553 **/ 4554 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) 4555 { 4556 struct e1000_mac_info *mac = &hw->mac; 4557 s32 ret_val; 4558 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 4559 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 4560 u16 data, i, temp, shift; 4561 4562 /* Get default ID LED modes */ 4563 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 4564 if (ret_val) 4565 return ret_val; 4566 4567 mac->ledctl_default = er32(LEDCTL); 4568 mac->ledctl_mode1 = mac->ledctl_default; 4569 mac->ledctl_mode2 = mac->ledctl_default; 4570 4571 for (i = 0; i < 4; i++) { 4572 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 4573 shift = (i * 5); 4574 switch (temp) { 4575 case ID_LED_ON1_DEF2: 4576 case ID_LED_ON1_ON2: 4577 case ID_LED_ON1_OFF2: 4578 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4579 mac->ledctl_mode1 |= (ledctl_on << shift); 4580 break; 4581 case ID_LED_OFF1_DEF2: 4582 case ID_LED_OFF1_ON2: 4583 case ID_LED_OFF1_OFF2: 4584 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 4585 mac->ledctl_mode1 |= (ledctl_off << shift); 4586 break; 4587 default: 4588 /* Do nothing */ 4589 break; 4590 } 4591 switch (temp) { 4592 case ID_LED_DEF1_ON2: 4593 case ID_LED_ON1_ON2: 4594 case ID_LED_OFF1_ON2: 4595 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4596 mac->ledctl_mode2 |= (ledctl_on << shift); 4597 break; 4598 case ID_LED_DEF1_OFF2: 4599 case ID_LED_ON1_OFF2: 4600 case ID_LED_OFF1_OFF2: 4601 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 4602 mac->ledctl_mode2 |= (ledctl_off << shift); 4603 break; 4604 default: 4605 /* Do nothing */ 4606 break; 4607 } 4608 } 4609 4610 return 0; 4611 } 4612 4613 /** 4614 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width 4615 * @hw: pointer to the HW structure 4616 * 4617 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability 4618 * register, so the the bus width is hard coded. 4619 **/ 4620 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) 4621 { 4622 struct e1000_bus_info *bus = &hw->bus; 4623 s32 ret_val; 4624 4625 ret_val = e1000e_get_bus_info_pcie(hw); 4626 4627 /* ICH devices are "PCI Express"-ish. They have 4628 * a configuration space, but do not contain 4629 * PCI Express Capability registers, so bus width 4630 * must be hardcoded. 4631 */ 4632 if (bus->width == e1000_bus_width_unknown) 4633 bus->width = e1000_bus_width_pcie_x1; 4634 4635 return ret_val; 4636 } 4637 4638 /** 4639 * e1000_reset_hw_ich8lan - Reset the hardware 4640 * @hw: pointer to the HW structure 4641 * 4642 * Does a full reset of the hardware which includes a reset of the PHY and 4643 * MAC. 4644 **/ 4645 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 4646 { 4647 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4648 u16 kum_cfg; 4649 u32 ctrl, reg; 4650 s32 ret_val; 4651 4652 /* Prevent the PCI-E bus from sticking if there is no TLP connection 4653 * on the last TLP read/write transaction when MAC is reset. 4654 */ 4655 ret_val = e1000e_disable_pcie_master(hw); 4656 if (ret_val) 4657 e_dbg("PCI-E Master disable polling has failed.\n"); 4658 4659 e_dbg("Masking off all interrupts\n"); 4660 ew32(IMC, 0xffffffff); 4661 4662 /* Disable the Transmit and Receive units. Then delay to allow 4663 * any pending transactions to complete before we hit the MAC 4664 * with the global reset. 4665 */ 4666 ew32(RCTL, 0); 4667 ew32(TCTL, E1000_TCTL_PSP); 4668 e1e_flush(); 4669 4670 usleep_range(10000, 11000); 4671 4672 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 4673 if (hw->mac.type == e1000_ich8lan) { 4674 /* Set Tx and Rx buffer allocation to 8k apiece. */ 4675 ew32(PBA, E1000_PBA_8K); 4676 /* Set Packet Buffer Size to 16k. */ 4677 ew32(PBS, E1000_PBS_16K); 4678 } 4679 4680 if (hw->mac.type == e1000_pchlan) { 4681 /* Save the NVM K1 bit setting */ 4682 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 4683 if (ret_val) 4684 return ret_val; 4685 4686 if (kum_cfg & E1000_NVM_K1_ENABLE) 4687 dev_spec->nvm_k1_enabled = true; 4688 else 4689 dev_spec->nvm_k1_enabled = false; 4690 } 4691 4692 ctrl = er32(CTRL); 4693 4694 if (!hw->phy.ops.check_reset_block(hw)) { 4695 /* Full-chip reset requires MAC and PHY reset at the same 4696 * time to make sure the interface between MAC and the 4697 * external PHY is reset. 4698 */ 4699 ctrl |= E1000_CTRL_PHY_RST; 4700 4701 /* Gate automatic PHY configuration by hardware on 4702 * non-managed 82579 4703 */ 4704 if ((hw->mac.type == e1000_pch2lan) && 4705 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 4706 e1000_gate_hw_phy_config_ich8lan(hw, true); 4707 } 4708 ret_val = e1000_acquire_swflag_ich8lan(hw); 4709 e_dbg("Issuing a global reset to ich8lan\n"); 4710 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 4711 /* cannot issue a flush here because it hangs the hardware */ 4712 msleep(20); 4713 4714 /* Set Phy Config Counter to 50msec */ 4715 if (hw->mac.type == e1000_pch2lan) { 4716 reg = er32(FEXTNVM3); 4717 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 4718 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 4719 ew32(FEXTNVM3, reg); 4720 } 4721 4722 if (!ret_val) 4723 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 4724 4725 if (ctrl & E1000_CTRL_PHY_RST) { 4726 ret_val = hw->phy.ops.get_cfg_done(hw); 4727 if (ret_val) 4728 return ret_val; 4729 4730 ret_val = e1000_post_phy_reset_ich8lan(hw); 4731 if (ret_val) 4732 return ret_val; 4733 } 4734 4735 /* For PCH, this write will make sure that any noise 4736 * will be detected as a CRC error and be dropped rather than show up 4737 * as a bad packet to the DMA engine. 4738 */ 4739 if (hw->mac.type == e1000_pchlan) 4740 ew32(CRC_OFFSET, 0x65656565); 4741 4742 ew32(IMC, 0xffffffff); 4743 er32(ICR); 4744 4745 reg = er32(KABGTXD); 4746 reg |= E1000_KABGTXD_BGSQLBIAS; 4747 ew32(KABGTXD, reg); 4748 4749 return 0; 4750 } 4751 4752 /** 4753 * e1000_init_hw_ich8lan - Initialize the hardware 4754 * @hw: pointer to the HW structure 4755 * 4756 * Prepares the hardware for transmit and receive by doing the following: 4757 * - initialize hardware bits 4758 * - initialize LED identification 4759 * - setup receive address registers 4760 * - setup flow control 4761 * - setup transmit descriptors 4762 * - clear statistics 4763 **/ 4764 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) 4765 { 4766 struct e1000_mac_info *mac = &hw->mac; 4767 u32 ctrl_ext, txdctl, snoop; 4768 s32 ret_val; 4769 u16 i; 4770 4771 e1000_initialize_hw_bits_ich8lan(hw); 4772 4773 /* Initialize identification LED */ 4774 ret_val = mac->ops.id_led_init(hw); 4775 /* An error is not fatal and we should not stop init due to this */ 4776 if (ret_val) 4777 e_dbg("Error initializing identification LED\n"); 4778 4779 /* Setup the receive address. */ 4780 e1000e_init_rx_addrs(hw, mac->rar_entry_count); 4781 4782 /* Zero out the Multicast HASH table */ 4783 e_dbg("Zeroing the MTA\n"); 4784 for (i = 0; i < mac->mta_reg_count; i++) 4785 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 4786 4787 /* The 82578 Rx buffer will stall if wakeup is enabled in host and 4788 * the ME. Disable wakeup by clearing the host wakeup bit. 4789 * Reset the phy after disabling host wakeup to reset the Rx buffer. 4790 */ 4791 if (hw->phy.type == e1000_phy_82578) { 4792 e1e_rphy(hw, BM_PORT_GEN_CFG, &i); 4793 i &= ~BM_WUC_HOST_WU_BIT; 4794 e1e_wphy(hw, BM_PORT_GEN_CFG, i); 4795 ret_val = e1000_phy_hw_reset_ich8lan(hw); 4796 if (ret_val) 4797 return ret_val; 4798 } 4799 4800 /* Setup link and flow control */ 4801 ret_val = mac->ops.setup_link(hw); 4802 4803 /* Set the transmit descriptor write-back policy for both queues */ 4804 txdctl = er32(TXDCTL(0)); 4805 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 4806 E1000_TXDCTL_FULL_TX_DESC_WB); 4807 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 4808 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 4809 ew32(TXDCTL(0), txdctl); 4810 txdctl = er32(TXDCTL(1)); 4811 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) | 4812 E1000_TXDCTL_FULL_TX_DESC_WB); 4813 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) | 4814 E1000_TXDCTL_MAX_TX_DESC_PREFETCH); 4815 ew32(TXDCTL(1), txdctl); 4816 4817 /* ICH8 has opposite polarity of no_snoop bits. 4818 * By default, we should use snoop behavior. 4819 */ 4820 if (mac->type == e1000_ich8lan) 4821 snoop = PCIE_ICH8_SNOOP_ALL; 4822 else 4823 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 4824 e1000e_set_pcie_no_snoop(hw, snoop); 4825 4826 ctrl_ext = er32(CTRL_EXT); 4827 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 4828 ew32(CTRL_EXT, ctrl_ext); 4829 4830 /* Clear all of the statistics registers (clear on read). It is 4831 * important that we do this after we have tried to establish link 4832 * because the symbol error count will increment wildly if there 4833 * is no link. 4834 */ 4835 e1000_clear_hw_cntrs_ich8lan(hw); 4836 4837 return ret_val; 4838 } 4839 4840 /** 4841 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits 4842 * @hw: pointer to the HW structure 4843 * 4844 * Sets/Clears required hardware bits necessary for correctly setting up the 4845 * hardware for transmit and receive. 4846 **/ 4847 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) 4848 { 4849 u32 reg; 4850 4851 /* Extended Device Control */ 4852 reg = er32(CTRL_EXT); 4853 reg |= BIT(22); 4854 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 4855 if (hw->mac.type >= e1000_pchlan) 4856 reg |= E1000_CTRL_EXT_PHYPDEN; 4857 ew32(CTRL_EXT, reg); 4858 4859 /* Transmit Descriptor Control 0 */ 4860 reg = er32(TXDCTL(0)); 4861 reg |= BIT(22); 4862 ew32(TXDCTL(0), reg); 4863 4864 /* Transmit Descriptor Control 1 */ 4865 reg = er32(TXDCTL(1)); 4866 reg |= BIT(22); 4867 ew32(TXDCTL(1), reg); 4868 4869 /* Transmit Arbitration Control 0 */ 4870 reg = er32(TARC(0)); 4871 if (hw->mac.type == e1000_ich8lan) 4872 reg |= BIT(28) | BIT(29); 4873 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27); 4874 ew32(TARC(0), reg); 4875 4876 /* Transmit Arbitration Control 1 */ 4877 reg = er32(TARC(1)); 4878 if (er32(TCTL) & E1000_TCTL_MULR) 4879 reg &= ~BIT(28); 4880 else 4881 reg |= BIT(28); 4882 reg |= BIT(24) | BIT(26) | BIT(30); 4883 ew32(TARC(1), reg); 4884 4885 /* Device Status */ 4886 if (hw->mac.type == e1000_ich8lan) { 4887 reg = er32(STATUS); 4888 reg &= ~BIT(31); 4889 ew32(STATUS, reg); 4890 } 4891 4892 /* work-around descriptor data corruption issue during nfs v2 udp 4893 * traffic, just disable the nfs filtering capability 4894 */ 4895 reg = er32(RFCTL); 4896 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); 4897 4898 /* Disable IPv6 extension header parsing because some malformed 4899 * IPv6 headers can hang the Rx. 4900 */ 4901 if (hw->mac.type == e1000_ich8lan) 4902 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 4903 ew32(RFCTL, reg); 4904 4905 /* Enable ECC on Lynxpoint */ 4906 if (hw->mac.type >= e1000_pch_lpt) { 4907 reg = er32(PBECCSTS); 4908 reg |= E1000_PBECCSTS_ECC_ENABLE; 4909 ew32(PBECCSTS, reg); 4910 4911 reg = er32(CTRL); 4912 reg |= E1000_CTRL_MEHE; 4913 ew32(CTRL, reg); 4914 } 4915 } 4916 4917 /** 4918 * e1000_setup_link_ich8lan - Setup flow control and link settings 4919 * @hw: pointer to the HW structure 4920 * 4921 * Determines which flow control settings to use, then configures flow 4922 * control. Calls the appropriate media-specific link configuration 4923 * function. Assuming the adapter has a valid link partner, a valid link 4924 * should be established. Assumes the hardware has previously been reset 4925 * and the transmitter and receiver are not enabled. 4926 **/ 4927 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) 4928 { 4929 s32 ret_val; 4930 4931 if (hw->phy.ops.check_reset_block(hw)) 4932 return 0; 4933 4934 /* ICH parts do not have a word in the NVM to determine 4935 * the default flow control setting, so we explicitly 4936 * set it to full. 4937 */ 4938 if (hw->fc.requested_mode == e1000_fc_default) { 4939 /* Workaround h/w hang when Tx flow control enabled */ 4940 if (hw->mac.type == e1000_pchlan) 4941 hw->fc.requested_mode = e1000_fc_rx_pause; 4942 else 4943 hw->fc.requested_mode = e1000_fc_full; 4944 } 4945 4946 /* Save off the requested flow control mode for use later. Depending 4947 * on the link partner's capabilities, we may or may not use this mode. 4948 */ 4949 hw->fc.current_mode = hw->fc.requested_mode; 4950 4951 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 4952 4953 /* Continue to configure the copper link. */ 4954 ret_val = hw->mac.ops.setup_physical_interface(hw); 4955 if (ret_val) 4956 return ret_val; 4957 4958 ew32(FCTTV, hw->fc.pause_time); 4959 if ((hw->phy.type == e1000_phy_82578) || 4960 (hw->phy.type == e1000_phy_82579) || 4961 (hw->phy.type == e1000_phy_i217) || 4962 (hw->phy.type == e1000_phy_82577)) { 4963 ew32(FCRTV_PCH, hw->fc.refresh_time); 4964 4965 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), 4966 hw->fc.pause_time); 4967 if (ret_val) 4968 return ret_val; 4969 } 4970 4971 return e1000e_set_fc_watermarks(hw); 4972 } 4973 4974 /** 4975 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface 4976 * @hw: pointer to the HW structure 4977 * 4978 * Configures the kumeran interface to the PHY to wait the appropriate time 4979 * when polling the PHY, then call the generic setup_copper_link to finish 4980 * configuring the copper link. 4981 **/ 4982 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) 4983 { 4984 u32 ctrl; 4985 s32 ret_val; 4986 u16 reg_data; 4987 4988 ctrl = er32(CTRL); 4989 ctrl |= E1000_CTRL_SLU; 4990 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 4991 ew32(CTRL, ctrl); 4992 4993 /* Set the mac to wait the maximum time between each iteration 4994 * and increase the max iterations when polling the phy; 4995 * this fixes erroneous timeouts at 10Mbps. 4996 */ 4997 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); 4998 if (ret_val) 4999 return ret_val; 5000 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5001 ®_data); 5002 if (ret_val) 5003 return ret_val; 5004 reg_data |= 0x3F; 5005 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 5006 reg_data); 5007 if (ret_val) 5008 return ret_val; 5009 5010 switch (hw->phy.type) { 5011 case e1000_phy_igp_3: 5012 ret_val = e1000e_copper_link_setup_igp(hw); 5013 if (ret_val) 5014 return ret_val; 5015 break; 5016 case e1000_phy_bm: 5017 case e1000_phy_82578: 5018 ret_val = e1000e_copper_link_setup_m88(hw); 5019 if (ret_val) 5020 return ret_val; 5021 break; 5022 case e1000_phy_82577: 5023 case e1000_phy_82579: 5024 ret_val = e1000_copper_link_setup_82577(hw); 5025 if (ret_val) 5026 return ret_val; 5027 break; 5028 case e1000_phy_ife: 5029 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); 5030 if (ret_val) 5031 return ret_val; 5032 5033 reg_data &= ~IFE_PMC_AUTO_MDIX; 5034 5035 switch (hw->phy.mdix) { 5036 case 1: 5037 reg_data &= ~IFE_PMC_FORCE_MDIX; 5038 break; 5039 case 2: 5040 reg_data |= IFE_PMC_FORCE_MDIX; 5041 break; 5042 case 0: 5043 default: 5044 reg_data |= IFE_PMC_AUTO_MDIX; 5045 break; 5046 } 5047 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); 5048 if (ret_val) 5049 return ret_val; 5050 break; 5051 default: 5052 break; 5053 } 5054 5055 return e1000e_setup_copper_link(hw); 5056 } 5057 5058 /** 5059 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface 5060 * @hw: pointer to the HW structure 5061 * 5062 * Calls the PHY specific link setup function and then calls the 5063 * generic setup_copper_link to finish configuring the link for 5064 * Lynxpoint PCH devices 5065 **/ 5066 static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw) 5067 { 5068 u32 ctrl; 5069 s32 ret_val; 5070 5071 ctrl = er32(CTRL); 5072 ctrl |= E1000_CTRL_SLU; 5073 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 5074 ew32(CTRL, ctrl); 5075 5076 ret_val = e1000_copper_link_setup_82577(hw); 5077 if (ret_val) 5078 return ret_val; 5079 5080 return e1000e_setup_copper_link(hw); 5081 } 5082 5083 /** 5084 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex 5085 * @hw: pointer to the HW structure 5086 * @speed: pointer to store current link speed 5087 * @duplex: pointer to store the current link duplex 5088 * 5089 * Calls the generic get_speed_and_duplex to retrieve the current link 5090 * information and then calls the Kumeran lock loss workaround for links at 5091 * gigabit speeds. 5092 **/ 5093 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, 5094 u16 *duplex) 5095 { 5096 s32 ret_val; 5097 5098 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); 5099 if (ret_val) 5100 return ret_val; 5101 5102 if ((hw->mac.type == e1000_ich8lan) && 5103 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { 5104 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); 5105 } 5106 5107 return ret_val; 5108 } 5109 5110 /** 5111 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround 5112 * @hw: pointer to the HW structure 5113 * 5114 * Work-around for 82566 Kumeran PCS lock loss: 5115 * On link status change (i.e. PCI reset, speed change) and link is up and 5116 * speed is gigabit- 5117 * 0) if workaround is optionally disabled do nothing 5118 * 1) wait 1ms for Kumeran link to come up 5119 * 2) check Kumeran Diagnostic register PCS lock loss bit 5120 * 3) if not set the link is locked (all is good), otherwise... 5121 * 4) reset the PHY 5122 * 5) repeat up to 10 times 5123 * Note: this is only called for IGP3 copper when speed is 1gb. 5124 **/ 5125 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) 5126 { 5127 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5128 u32 phy_ctrl; 5129 s32 ret_val; 5130 u16 i, data; 5131 bool link; 5132 5133 if (!dev_spec->kmrn_lock_loss_workaround_enabled) 5134 return 0; 5135 5136 /* Make sure link is up before proceeding. If not just return. 5137 * Attempting this while link is negotiating fouled up link 5138 * stability 5139 */ 5140 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 5141 if (!link) 5142 return 0; 5143 5144 for (i = 0; i < 10; i++) { 5145 /* read once to clear */ 5146 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5147 if (ret_val) 5148 return ret_val; 5149 /* and again to get new status */ 5150 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 5151 if (ret_val) 5152 return ret_val; 5153 5154 /* check for PCS lock */ 5155 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) 5156 return 0; 5157 5158 /* Issue PHY reset */ 5159 e1000_phy_hw_reset(hw); 5160 mdelay(5); 5161 } 5162 /* Disable GigE link negotiation */ 5163 phy_ctrl = er32(PHY_CTRL); 5164 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 5165 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5166 ew32(PHY_CTRL, phy_ctrl); 5167 5168 /* Call gig speed drop workaround on Gig disable before accessing 5169 * any PHY registers 5170 */ 5171 e1000e_gig_downshift_workaround_ich8lan(hw); 5172 5173 /* unable to acquire PCS lock */ 5174 return -E1000_ERR_PHY; 5175 } 5176 5177 /** 5178 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state 5179 * @hw: pointer to the HW structure 5180 * @state: boolean value used to set the current Kumeran workaround state 5181 * 5182 * If ICH8, set the current Kumeran workaround state (enabled - true 5183 * /disabled - false). 5184 **/ 5185 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 5186 bool state) 5187 { 5188 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5189 5190 if (hw->mac.type != e1000_ich8lan) { 5191 e_dbg("Workaround applies to ICH8 only.\n"); 5192 return; 5193 } 5194 5195 dev_spec->kmrn_lock_loss_workaround_enabled = state; 5196 } 5197 5198 /** 5199 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 5200 * @hw: pointer to the HW structure 5201 * 5202 * Workaround for 82566 power-down on D3 entry: 5203 * 1) disable gigabit link 5204 * 2) write VR power-down enable 5205 * 3) read it back 5206 * Continue if successful, else issue LCD reset and repeat 5207 **/ 5208 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) 5209 { 5210 u32 reg; 5211 u16 data; 5212 u8 retry = 0; 5213 5214 if (hw->phy.type != e1000_phy_igp_3) 5215 return; 5216 5217 /* Try the workaround twice (if needed) */ 5218 do { 5219 /* Disable link */ 5220 reg = er32(PHY_CTRL); 5221 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 5222 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 5223 ew32(PHY_CTRL, reg); 5224 5225 /* Call gig speed drop workaround on Gig disable before 5226 * accessing any PHY registers 5227 */ 5228 if (hw->mac.type == e1000_ich8lan) 5229 e1000e_gig_downshift_workaround_ich8lan(hw); 5230 5231 /* Write VR power-down enable */ 5232 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5233 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5234 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); 5235 5236 /* Read it back and test */ 5237 e1e_rphy(hw, IGP3_VR_CTRL, &data); 5238 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 5239 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 5240 break; 5241 5242 /* Issue PHY reset and repeat at most one more time */ 5243 reg = er32(CTRL); 5244 ew32(CTRL, reg | E1000_CTRL_PHY_RST); 5245 retry++; 5246 } while (retry); 5247 } 5248 5249 /** 5250 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working 5251 * @hw: pointer to the HW structure 5252 * 5253 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), 5254 * LPLU, Gig disable, MDIC PHY reset): 5255 * 1) Set Kumeran Near-end loopback 5256 * 2) Clear Kumeran Near-end loopback 5257 * Should only be called for ICH8[m] devices with any 1G Phy. 5258 **/ 5259 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) 5260 { 5261 s32 ret_val; 5262 u16 reg_data; 5263 5264 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) 5265 return; 5266 5267 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5268 ®_data); 5269 if (ret_val) 5270 return; 5271 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 5272 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 5273 reg_data); 5274 if (ret_val) 5275 return; 5276 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 5277 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data); 5278 } 5279 5280 /** 5281 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx 5282 * @hw: pointer to the HW structure 5283 * 5284 * During S0 to Sx transition, it is possible the link remains at gig 5285 * instead of negotiating to a lower speed. Before going to Sx, set 5286 * 'Gig Disable' to force link speed negotiation to a lower speed based on 5287 * the LPLU setting in the NVM or custom setting. For PCH and newer parts, 5288 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also 5289 * needs to be written. 5290 * Parts that support (and are linked to a partner which support) EEE in 5291 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power 5292 * than 10Mbps w/o EEE. 5293 **/ 5294 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) 5295 { 5296 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 5297 u32 phy_ctrl; 5298 s32 ret_val; 5299 5300 phy_ctrl = er32(PHY_CTRL); 5301 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; 5302 5303 if (hw->phy.type == e1000_phy_i217) { 5304 u16 phy_reg, device_id = hw->adapter->pdev->device; 5305 5306 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) || 5307 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) || 5308 (device_id == E1000_DEV_ID_PCH_I218_LM3) || 5309 (device_id == E1000_DEV_ID_PCH_I218_V3) || 5310 (hw->mac.type >= e1000_pch_spt)) { 5311 u32 fextnvm6 = er32(FEXTNVM6); 5312 5313 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK); 5314 } 5315 5316 ret_val = hw->phy.ops.acquire(hw); 5317 if (ret_val) 5318 goto out; 5319 5320 if (!dev_spec->eee_disable) { 5321 u16 eee_advert; 5322 5323 ret_val = 5324 e1000_read_emi_reg_locked(hw, 5325 I217_EEE_ADVERTISEMENT, 5326 &eee_advert); 5327 if (ret_val) 5328 goto release; 5329 5330 /* Disable LPLU if both link partners support 100BaseT 5331 * EEE and 100Full is advertised on both ends of the 5332 * link, and enable Auto Enable LPI since there will 5333 * be no driver to enable LPI while in Sx. 5334 */ 5335 if ((eee_advert & I82579_EEE_100_SUPPORTED) && 5336 (dev_spec->eee_lp_ability & 5337 I82579_EEE_100_SUPPORTED) && 5338 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) { 5339 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | 5340 E1000_PHY_CTRL_NOND0A_LPLU); 5341 5342 /* Set Auto Enable LPI after link up */ 5343 e1e_rphy_locked(hw, 5344 I217_LPI_GPIO_CTRL, &phy_reg); 5345 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5346 e1e_wphy_locked(hw, 5347 I217_LPI_GPIO_CTRL, phy_reg); 5348 } 5349 } 5350 5351 /* For i217 Intel Rapid Start Technology support, 5352 * when the system is going into Sx and no manageability engine 5353 * is present, the driver must configure proxy to reset only on 5354 * power good. LPI (Low Power Idle) state must also reset only 5355 * on power good, as well as the MTA (Multicast table array). 5356 * The SMBus release must also be disabled on LCD reset. 5357 */ 5358 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5359 /* Enable proxy to reset only on power good. */ 5360 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); 5361 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; 5362 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); 5363 5364 /* Set bit enable LPI (EEE) to reset only on 5365 * power good. 5366 */ 5367 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); 5368 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; 5369 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); 5370 5371 /* Disable the SMB release on LCD reset. */ 5372 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5373 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; 5374 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5375 } 5376 5377 /* Enable MTA to reset for Intel Rapid Start Technology 5378 * Support 5379 */ 5380 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5381 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; 5382 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5383 5384 release: 5385 hw->phy.ops.release(hw); 5386 } 5387 out: 5388 ew32(PHY_CTRL, phy_ctrl); 5389 5390 if (hw->mac.type == e1000_ich8lan) 5391 e1000e_gig_downshift_workaround_ich8lan(hw); 5392 5393 if (hw->mac.type >= e1000_pchlan) { 5394 e1000_oem_bits_config_ich8lan(hw, false); 5395 5396 /* Reset PHY to activate OEM bits on 82577/8 */ 5397 if (hw->mac.type == e1000_pchlan) 5398 e1000e_phy_hw_reset_generic(hw); 5399 5400 ret_val = hw->phy.ops.acquire(hw); 5401 if (ret_val) 5402 return; 5403 e1000_write_smbus_addr(hw); 5404 hw->phy.ops.release(hw); 5405 } 5406 } 5407 5408 /** 5409 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 5410 * @hw: pointer to the HW structure 5411 * 5412 * During Sx to S0 transitions on non-managed devices or managed devices 5413 * on which PHY resets are not blocked, if the PHY registers cannot be 5414 * accessed properly by the s/w toggle the LANPHYPC value to power cycle 5415 * the PHY. 5416 * On i217, setup Intel Rapid Start Technology. 5417 **/ 5418 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) 5419 { 5420 s32 ret_val; 5421 5422 if (hw->mac.type < e1000_pch2lan) 5423 return; 5424 5425 ret_val = e1000_init_phy_workarounds_pchlan(hw); 5426 if (ret_val) { 5427 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val); 5428 return; 5429 } 5430 5431 /* For i217 Intel Rapid Start Technology support when the system 5432 * is transitioning from Sx and no manageability engine is present 5433 * configure SMBus to restore on reset, disable proxy, and enable 5434 * the reset on MTA (Multicast table array). 5435 */ 5436 if (hw->phy.type == e1000_phy_i217) { 5437 u16 phy_reg; 5438 5439 ret_val = hw->phy.ops.acquire(hw); 5440 if (ret_val) { 5441 e_dbg("Failed to setup iRST\n"); 5442 return; 5443 } 5444 5445 /* Clear Auto Enable LPI after link up */ 5446 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg); 5447 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI; 5448 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg); 5449 5450 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { 5451 /* Restore clear on SMB if no manageability engine 5452 * is present 5453 */ 5454 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); 5455 if (ret_val) 5456 goto release; 5457 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; 5458 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); 5459 5460 /* Disable Proxy */ 5461 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); 5462 } 5463 /* Enable reset on MTA */ 5464 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); 5465 if (ret_val) 5466 goto release; 5467 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; 5468 e1e_wphy_locked(hw, I217_CGFREG, phy_reg); 5469 release: 5470 if (ret_val) 5471 e_dbg("Error %d in resume workarounds\n", ret_val); 5472 hw->phy.ops.release(hw); 5473 } 5474 } 5475 5476 /** 5477 * e1000_cleanup_led_ich8lan - Restore the default LED operation 5478 * @hw: pointer to the HW structure 5479 * 5480 * Return the LED back to the default configuration. 5481 **/ 5482 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) 5483 { 5484 if (hw->phy.type == e1000_phy_ife) 5485 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); 5486 5487 ew32(LEDCTL, hw->mac.ledctl_default); 5488 return 0; 5489 } 5490 5491 /** 5492 * e1000_led_on_ich8lan - Turn LEDs on 5493 * @hw: pointer to the HW structure 5494 * 5495 * Turn on the LEDs. 5496 **/ 5497 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) 5498 { 5499 if (hw->phy.type == e1000_phy_ife) 5500 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5501 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 5502 5503 ew32(LEDCTL, hw->mac.ledctl_mode2); 5504 return 0; 5505 } 5506 5507 /** 5508 * e1000_led_off_ich8lan - Turn LEDs off 5509 * @hw: pointer to the HW structure 5510 * 5511 * Turn off the LEDs. 5512 **/ 5513 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) 5514 { 5515 if (hw->phy.type == e1000_phy_ife) 5516 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 5517 (IFE_PSCL_PROBE_MODE | 5518 IFE_PSCL_PROBE_LEDS_OFF)); 5519 5520 ew32(LEDCTL, hw->mac.ledctl_mode1); 5521 return 0; 5522 } 5523 5524 /** 5525 * e1000_setup_led_pchlan - Configures SW controllable LED 5526 * @hw: pointer to the HW structure 5527 * 5528 * This prepares the SW controllable LED for use. 5529 **/ 5530 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) 5531 { 5532 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); 5533 } 5534 5535 /** 5536 * e1000_cleanup_led_pchlan - Restore the default LED operation 5537 * @hw: pointer to the HW structure 5538 * 5539 * Return the LED back to the default configuration. 5540 **/ 5541 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) 5542 { 5543 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); 5544 } 5545 5546 /** 5547 * e1000_led_on_pchlan - Turn LEDs on 5548 * @hw: pointer to the HW structure 5549 * 5550 * Turn on the LEDs. 5551 **/ 5552 static s32 e1000_led_on_pchlan(struct e1000_hw *hw) 5553 { 5554 u16 data = (u16)hw->mac.ledctl_mode2; 5555 u32 i, led; 5556 5557 /* If no link, then turn LED on by setting the invert bit 5558 * for each LED that's mode is "link_up" in ledctl_mode2. 5559 */ 5560 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5561 for (i = 0; i < 3; i++) { 5562 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5563 if ((led & E1000_PHY_LED0_MODE_MASK) != 5564 E1000_LEDCTL_MODE_LINK_UP) 5565 continue; 5566 if (led & E1000_PHY_LED0_IVRT) 5567 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5568 else 5569 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5570 } 5571 } 5572 5573 return e1e_wphy(hw, HV_LED_CONFIG, data); 5574 } 5575 5576 /** 5577 * e1000_led_off_pchlan - Turn LEDs off 5578 * @hw: pointer to the HW structure 5579 * 5580 * Turn off the LEDs. 5581 **/ 5582 static s32 e1000_led_off_pchlan(struct e1000_hw *hw) 5583 { 5584 u16 data = (u16)hw->mac.ledctl_mode1; 5585 u32 i, led; 5586 5587 /* If no link, then turn LED off by clearing the invert bit 5588 * for each LED that's mode is "link_up" in ledctl_mode1. 5589 */ 5590 if (!(er32(STATUS) & E1000_STATUS_LU)) { 5591 for (i = 0; i < 3; i++) { 5592 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 5593 if ((led & E1000_PHY_LED0_MODE_MASK) != 5594 E1000_LEDCTL_MODE_LINK_UP) 5595 continue; 5596 if (led & E1000_PHY_LED0_IVRT) 5597 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 5598 else 5599 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 5600 } 5601 } 5602 5603 return e1e_wphy(hw, HV_LED_CONFIG, data); 5604 } 5605 5606 /** 5607 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset 5608 * @hw: pointer to the HW structure 5609 * 5610 * Read appropriate register for the config done bit for completion status 5611 * and configure the PHY through s/w for EEPROM-less parts. 5612 * 5613 * NOTE: some silicon which is EEPROM-less will fail trying to read the 5614 * config done bit, so only an error is logged and continues. If we were 5615 * to return with error, EEPROM-less silicon would not be able to be reset 5616 * or change link. 5617 **/ 5618 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) 5619 { 5620 s32 ret_val = 0; 5621 u32 bank = 0; 5622 u32 status; 5623 5624 e1000e_get_cfg_done_generic(hw); 5625 5626 /* Wait for indication from h/w that it has completed basic config */ 5627 if (hw->mac.type >= e1000_ich10lan) { 5628 e1000_lan_init_done_ich8lan(hw); 5629 } else { 5630 ret_val = e1000e_get_auto_rd_done(hw); 5631 if (ret_val) { 5632 /* When auto config read does not complete, do not 5633 * return with an error. This can happen in situations 5634 * where there is no eeprom and prevents getting link. 5635 */ 5636 e_dbg("Auto Read Done did not complete\n"); 5637 ret_val = 0; 5638 } 5639 } 5640 5641 /* Clear PHY Reset Asserted bit */ 5642 status = er32(STATUS); 5643 if (status & E1000_STATUS_PHYRA) 5644 ew32(STATUS, status & ~E1000_STATUS_PHYRA); 5645 else 5646 e_dbg("PHY Reset Asserted not set - needs delay\n"); 5647 5648 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 5649 if (hw->mac.type <= e1000_ich9lan) { 5650 if (!(er32(EECD) & E1000_EECD_PRES) && 5651 (hw->phy.type == e1000_phy_igp_3)) { 5652 e1000e_phy_init_script_igp3(hw); 5653 } 5654 } else { 5655 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 5656 /* Maybe we should do a basic PHY config */ 5657 e_dbg("EEPROM not present\n"); 5658 ret_val = -E1000_ERR_CONFIG; 5659 } 5660 } 5661 5662 return ret_val; 5663 } 5664 5665 /** 5666 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down 5667 * @hw: pointer to the HW structure 5668 * 5669 * In the case of a PHY power down to save power, or to turn off link during a 5670 * driver unload, or wake on lan is not enabled, remove the link. 5671 **/ 5672 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) 5673 { 5674 /* If the management interface is not enabled, then power down */ 5675 if (!(hw->mac.ops.check_mng_mode(hw) || 5676 hw->phy.ops.check_reset_block(hw))) 5677 e1000_power_down_phy_copper(hw); 5678 } 5679 5680 /** 5681 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters 5682 * @hw: pointer to the HW structure 5683 * 5684 * Clears hardware counters specific to the silicon family and calls 5685 * clear_hw_cntrs_generic to clear all general purpose counters. 5686 **/ 5687 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) 5688 { 5689 u16 phy_data; 5690 s32 ret_val; 5691 5692 e1000e_clear_hw_cntrs_base(hw); 5693 5694 er32(ALGNERRC); 5695 er32(RXERRC); 5696 er32(TNCRS); 5697 er32(CEXTERR); 5698 er32(TSCTC); 5699 er32(TSCTFC); 5700 5701 er32(MGTPRC); 5702 er32(MGTPDC); 5703 er32(MGTPTC); 5704 5705 er32(IAC); 5706 er32(ICRXOC); 5707 5708 /* Clear PHY statistics registers */ 5709 if ((hw->phy.type == e1000_phy_82578) || 5710 (hw->phy.type == e1000_phy_82579) || 5711 (hw->phy.type == e1000_phy_i217) || 5712 (hw->phy.type == e1000_phy_82577)) { 5713 ret_val = hw->phy.ops.acquire(hw); 5714 if (ret_val) 5715 return; 5716 ret_val = hw->phy.ops.set_page(hw, 5717 HV_STATS_PAGE << IGP_PAGE_SHIFT); 5718 if (ret_val) 5719 goto release; 5720 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); 5721 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); 5722 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); 5723 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); 5724 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); 5725 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); 5726 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); 5727 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); 5728 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); 5729 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); 5730 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); 5731 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); 5732 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); 5733 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); 5734 release: 5735 hw->phy.ops.release(hw); 5736 } 5737 } 5738 5739 static const struct e1000_mac_operations ich8_mac_ops = { 5740 /* check_mng_mode dependent on mac type */ 5741 .check_for_link = e1000_check_for_copper_link_ich8lan, 5742 /* cleanup_led dependent on mac type */ 5743 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, 5744 .get_bus_info = e1000_get_bus_info_ich8lan, 5745 .set_lan_id = e1000_set_lan_id_single_port, 5746 .get_link_up_info = e1000_get_link_up_info_ich8lan, 5747 /* led_on dependent on mac type */ 5748 /* led_off dependent on mac type */ 5749 .update_mc_addr_list = e1000e_update_mc_addr_list_generic, 5750 .reset_hw = e1000_reset_hw_ich8lan, 5751 .init_hw = e1000_init_hw_ich8lan, 5752 .setup_link = e1000_setup_link_ich8lan, 5753 .setup_physical_interface = e1000_setup_copper_link_ich8lan, 5754 /* id_led_init dependent on mac type */ 5755 .config_collision_dist = e1000e_config_collision_dist_generic, 5756 .rar_set = e1000e_rar_set_generic, 5757 .rar_get_count = e1000e_rar_get_count_generic, 5758 }; 5759 5760 static const struct e1000_phy_operations ich8_phy_ops = { 5761 .acquire = e1000_acquire_swflag_ich8lan, 5762 .check_reset_block = e1000_check_reset_block_ich8lan, 5763 .commit = NULL, 5764 .get_cfg_done = e1000_get_cfg_done_ich8lan, 5765 .get_cable_length = e1000e_get_cable_length_igp_2, 5766 .read_reg = e1000e_read_phy_reg_igp, 5767 .release = e1000_release_swflag_ich8lan, 5768 .reset = e1000_phy_hw_reset_ich8lan, 5769 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, 5770 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, 5771 .write_reg = e1000e_write_phy_reg_igp, 5772 }; 5773 5774 static const struct e1000_nvm_operations ich8_nvm_ops = { 5775 .acquire = e1000_acquire_nvm_ich8lan, 5776 .read = e1000_read_nvm_ich8lan, 5777 .release = e1000_release_nvm_ich8lan, 5778 .reload = e1000e_reload_nvm_generic, 5779 .update = e1000_update_nvm_checksum_ich8lan, 5780 .valid_led_default = e1000_valid_led_default_ich8lan, 5781 .validate = e1000_validate_nvm_checksum_ich8lan, 5782 .write = e1000_write_nvm_ich8lan, 5783 }; 5784 5785 static const struct e1000_nvm_operations spt_nvm_ops = { 5786 .acquire = e1000_acquire_nvm_ich8lan, 5787 .release = e1000_release_nvm_ich8lan, 5788 .read = e1000_read_nvm_spt, 5789 .update = e1000_update_nvm_checksum_spt, 5790 .reload = e1000e_reload_nvm_generic, 5791 .valid_led_default = e1000_valid_led_default_ich8lan, 5792 .validate = e1000_validate_nvm_checksum_ich8lan, 5793 .write = e1000_write_nvm_ich8lan, 5794 }; 5795 5796 const struct e1000_info e1000_ich8_info = { 5797 .mac = e1000_ich8lan, 5798 .flags = FLAG_HAS_WOL 5799 | FLAG_IS_ICH 5800 | FLAG_HAS_CTRLEXT_ON_LOAD 5801 | FLAG_HAS_AMT 5802 | FLAG_HAS_FLASH 5803 | FLAG_APME_IN_WUC, 5804 .pba = 8, 5805 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN, 5806 .get_variants = e1000_get_variants_ich8lan, 5807 .mac_ops = &ich8_mac_ops, 5808 .phy_ops = &ich8_phy_ops, 5809 .nvm_ops = &ich8_nvm_ops, 5810 }; 5811 5812 const struct e1000_info e1000_ich9_info = { 5813 .mac = e1000_ich9lan, 5814 .flags = FLAG_HAS_JUMBO_FRAMES 5815 | FLAG_IS_ICH 5816 | FLAG_HAS_WOL 5817 | FLAG_HAS_CTRLEXT_ON_LOAD 5818 | FLAG_HAS_AMT 5819 | FLAG_HAS_FLASH 5820 | FLAG_APME_IN_WUC, 5821 .pba = 18, 5822 .max_hw_frame_size = DEFAULT_JUMBO, 5823 .get_variants = e1000_get_variants_ich8lan, 5824 .mac_ops = &ich8_mac_ops, 5825 .phy_ops = &ich8_phy_ops, 5826 .nvm_ops = &ich8_nvm_ops, 5827 }; 5828 5829 const struct e1000_info e1000_ich10_info = { 5830 .mac = e1000_ich10lan, 5831 .flags = FLAG_HAS_JUMBO_FRAMES 5832 | FLAG_IS_ICH 5833 | FLAG_HAS_WOL 5834 | FLAG_HAS_CTRLEXT_ON_LOAD 5835 | FLAG_HAS_AMT 5836 | FLAG_HAS_FLASH 5837 | FLAG_APME_IN_WUC, 5838 .pba = 18, 5839 .max_hw_frame_size = DEFAULT_JUMBO, 5840 .get_variants = e1000_get_variants_ich8lan, 5841 .mac_ops = &ich8_mac_ops, 5842 .phy_ops = &ich8_phy_ops, 5843 .nvm_ops = &ich8_nvm_ops, 5844 }; 5845 5846 const struct e1000_info e1000_pch_info = { 5847 .mac = e1000_pchlan, 5848 .flags = FLAG_IS_ICH 5849 | FLAG_HAS_WOL 5850 | FLAG_HAS_CTRLEXT_ON_LOAD 5851 | FLAG_HAS_AMT 5852 | FLAG_HAS_FLASH 5853 | FLAG_HAS_JUMBO_FRAMES 5854 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ 5855 | FLAG_APME_IN_WUC, 5856 .flags2 = FLAG2_HAS_PHY_STATS, 5857 .pba = 26, 5858 .max_hw_frame_size = 4096, 5859 .get_variants = e1000_get_variants_ich8lan, 5860 .mac_ops = &ich8_mac_ops, 5861 .phy_ops = &ich8_phy_ops, 5862 .nvm_ops = &ich8_nvm_ops, 5863 }; 5864 5865 const struct e1000_info e1000_pch2_info = { 5866 .mac = e1000_pch2lan, 5867 .flags = FLAG_IS_ICH 5868 | FLAG_HAS_WOL 5869 | FLAG_HAS_HW_TIMESTAMP 5870 | FLAG_HAS_CTRLEXT_ON_LOAD 5871 | FLAG_HAS_AMT 5872 | FLAG_HAS_FLASH 5873 | FLAG_HAS_JUMBO_FRAMES 5874 | FLAG_APME_IN_WUC, 5875 .flags2 = FLAG2_HAS_PHY_STATS 5876 | FLAG2_HAS_EEE 5877 | FLAG2_CHECK_SYSTIM_OVERFLOW, 5878 .pba = 26, 5879 .max_hw_frame_size = 9022, 5880 .get_variants = e1000_get_variants_ich8lan, 5881 .mac_ops = &ich8_mac_ops, 5882 .phy_ops = &ich8_phy_ops, 5883 .nvm_ops = &ich8_nvm_ops, 5884 }; 5885 5886 const struct e1000_info e1000_pch_lpt_info = { 5887 .mac = e1000_pch_lpt, 5888 .flags = FLAG_IS_ICH 5889 | FLAG_HAS_WOL 5890 | FLAG_HAS_HW_TIMESTAMP 5891 | FLAG_HAS_CTRLEXT_ON_LOAD 5892 | FLAG_HAS_AMT 5893 | FLAG_HAS_FLASH 5894 | FLAG_HAS_JUMBO_FRAMES 5895 | FLAG_APME_IN_WUC, 5896 .flags2 = FLAG2_HAS_PHY_STATS 5897 | FLAG2_HAS_EEE 5898 | FLAG2_CHECK_SYSTIM_OVERFLOW, 5899 .pba = 26, 5900 .max_hw_frame_size = 9022, 5901 .get_variants = e1000_get_variants_ich8lan, 5902 .mac_ops = &ich8_mac_ops, 5903 .phy_ops = &ich8_phy_ops, 5904 .nvm_ops = &ich8_nvm_ops, 5905 }; 5906 5907 const struct e1000_info e1000_pch_spt_info = { 5908 .mac = e1000_pch_spt, 5909 .flags = FLAG_IS_ICH 5910 | FLAG_HAS_WOL 5911 | FLAG_HAS_HW_TIMESTAMP 5912 | FLAG_HAS_CTRLEXT_ON_LOAD 5913 | FLAG_HAS_AMT 5914 | FLAG_HAS_FLASH 5915 | FLAG_HAS_JUMBO_FRAMES 5916 | FLAG_APME_IN_WUC, 5917 .flags2 = FLAG2_HAS_PHY_STATS 5918 | FLAG2_HAS_EEE, 5919 .pba = 26, 5920 .max_hw_frame_size = 9022, 5921 .get_variants = e1000_get_variants_ich8lan, 5922 .mac_ops = &ich8_mac_ops, 5923 .phy_ops = &ich8_phy_ops, 5924 .nvm_ops = &spt_nvm_ops, 5925 }; 5926 5927 const struct e1000_info e1000_pch_cnp_info = { 5928 .mac = e1000_pch_cnp, 5929 .flags = FLAG_IS_ICH 5930 | FLAG_HAS_WOL 5931 | FLAG_HAS_HW_TIMESTAMP 5932 | FLAG_HAS_CTRLEXT_ON_LOAD 5933 | FLAG_HAS_AMT 5934 | FLAG_HAS_FLASH 5935 | FLAG_HAS_JUMBO_FRAMES 5936 | FLAG_APME_IN_WUC, 5937 .flags2 = FLAG2_HAS_PHY_STATS 5938 | FLAG2_HAS_EEE, 5939 .pba = 26, 5940 .max_hw_frame_size = 9022, 5941 .get_variants = e1000_get_variants_ich8lan, 5942 .mac_ops = &ich8_mac_ops, 5943 .phy_ops = &ich8_phy_ops, 5944 .nvm_ops = &spt_nvm_ops, 5945 }; 5946