1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
8
9maintainers:
10  - Masahiro Yamada <yamada.masahiro@socionext.com>
11  - Piotr Sroka <piotrs@cadence.com>
12
13allOf:
14  - $ref: mmc-controller.yaml
15
16properties:
17  compatible:
18    items:
19      - enum:
20         - socionext,uniphier-sd4hc
21      - const: cdns,sd4hc
22
23  reg:
24    maxItems: 1
25
26  interrupts:
27    maxItems: 1
28
29  clocks:
30    maxItems: 1
31
32  # PHY DLL input delays:
33  # They are used to delay the data valid window, and align the window to
34  # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
35  # and it is increased by 2.5ns in each step.
36
37  cdns,phy-input-delay-sd-highspeed:
38    description: Value of the delay in the input path for SD high-speed timing
39    allOf:
40      - $ref: "/schemas/types.yaml#/definitions/uint32"
41      - minimum: 0
42      - maximum: 0x1f
43
44  cdns,phy-input-delay-legacy:
45    description: Value of the delay in the input path for legacy timing
46    allOf:
47      - $ref: "/schemas/types.yaml#/definitions/uint32"
48      - minimum: 0
49      - maximum: 0x1f
50
51  cdns,phy-input-delay-sd-uhs-sdr12:
52    description: Value of the delay in the input path for SD UHS SDR12 timing
53    allOf:
54      - $ref: "/schemas/types.yaml#/definitions/uint32"
55      - minimum: 0
56      - maximum: 0x1f
57
58  cdns,phy-input-delay-sd-uhs-sdr25:
59    description: Value of the delay in the input path for SD UHS SDR25 timing
60    allOf:
61      - $ref: "/schemas/types.yaml#/definitions/uint32"
62      - minimum: 0
63      - maximum: 0x1f
64
65  cdns,phy-input-delay-sd-uhs-sdr50:
66    description: Value of the delay in the input path for SD UHS SDR50 timing
67    allOf:
68      - $ref: "/schemas/types.yaml#/definitions/uint32"
69      - minimum: 0
70      - maximum: 0x1f
71
72  cdns,phy-input-delay-sd-uhs-ddr50:
73    description: Value of the delay in the input path for SD UHS DDR50 timing
74    allOf:
75      - $ref: "/schemas/types.yaml#/definitions/uint32"
76      - minimum: 0
77      - maximum: 0x1f
78
79  cdns,phy-input-delay-mmc-highspeed:
80    description: Value of the delay in the input path for MMC high-speed timing
81    allOf:
82      - $ref: "/schemas/types.yaml#/definitions/uint32"
83      - minimum: 0
84      - maximum: 0x1f
85
86  cdns,phy-input-delay-mmc-ddr:
87    description: Value of the delay in the input path for eMMC high-speed DDR timing
88    allOf:
89      - $ref: "/schemas/types.yaml#/definitions/uint32"
90      - minimum: 0
91      - maximum: 0x1f
92
93  # PHY DLL clock delays:
94  # Each delay property represents the fraction of the clock period.
95  # The approximate delay value will be
96  # (<delay property value>/128)*sdmclk_clock_period.
97
98  cdns,phy-dll-delay-sdclk:
99    description: |
100      Value of the delay introduced on the sdclk output for all modes except
101      HS200, HS400 and HS400_ES.
102    allOf:
103      - $ref: "/schemas/types.yaml#/definitions/uint32"
104      - minimum: 0
105      - maximum: 0x7f
106
107  cdns,phy-dll-delay-sdclk-hsmmc:
108    description: |
109      Value of the delay introduced on the sdclk output for HS200, HS400 and
110      HS400_ES speed modes.
111    allOf:
112      - $ref: "/schemas/types.yaml#/definitions/uint32"
113      - minimum: 0
114      - maximum: 0x7f
115
116  cdns,phy-dll-delay-strobe:
117    description: |
118      Value of the delay introduced on the dat_strobe input used in
119      HS400 / HS400_ES speed modes.
120    allOf:
121      - $ref: "/schemas/types.yaml#/definitions/uint32"
122      - minimum: 0
123      - maximum: 0x7f
124
125required:
126  - compatible
127  - reg
128  - interrupts
129  - clocks
130
131examples:
132  - |
133    emmc: mmc@5a000000 {
134        compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
135        reg = <0x5a000000 0x400>;
136        interrupts = <0 78 4>;
137        clocks = <&clk 4>;
138        bus-width = <8>;
139        mmc-ddr-1_8v;
140        mmc-hs200-1_8v;
141        mmc-hs400-1_8v;
142        cdns,phy-dll-delay-sdclk = <0>;
143    };
144