1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/etherdevice.h> 16 #include <linux/ethtool.h> 17 #include <linux/if_bridge.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/jiffies.h> 22 #include <linux/list.h> 23 #include <linux/mdio.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_mdio.h> 28 #include <linux/platform_data/mv88e6xxx.h> 29 #include <linux/netdevice.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/phylink.h> 32 #include <net/dsa.h> 33 34 #include "chip.h" 35 #include "global1.h" 36 #include "global2.h" 37 #include "hwtstamp.h" 38 #include "phy.h" 39 #include "port.h" 40 #include "ptp.h" 41 #include "serdes.h" 42 #include "smi.h" 43 44 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 45 { 46 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 47 dev_err(chip->dev, "Switch registers lock not held!\n"); 48 dump_stack(); 49 } 50 } 51 52 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 53 { 54 int err; 55 56 assert_reg_lock(chip); 57 58 err = mv88e6xxx_smi_read(chip, addr, reg, val); 59 if (err) 60 return err; 61 62 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 63 addr, reg, *val); 64 65 return 0; 66 } 67 68 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 69 { 70 int err; 71 72 assert_reg_lock(chip); 73 74 err = mv88e6xxx_smi_write(chip, addr, reg, val); 75 if (err) 76 return err; 77 78 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 79 addr, reg, val); 80 81 return 0; 82 } 83 84 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 85 u16 mask, u16 val) 86 { 87 u16 data; 88 int err; 89 int i; 90 91 /* There's no bus specific operation to wait for a mask */ 92 for (i = 0; i < 16; i++) { 93 err = mv88e6xxx_read(chip, addr, reg, &data); 94 if (err) 95 return err; 96 97 if ((data & mask) == val) 98 return 0; 99 100 usleep_range(1000, 2000); 101 } 102 103 dev_err(chip->dev, "Timeout while waiting for switch\n"); 104 return -ETIMEDOUT; 105 } 106 107 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 108 int bit, int val) 109 { 110 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 111 val ? BIT(bit) : 0x0000); 112 } 113 114 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 115 { 116 struct mv88e6xxx_mdio_bus *mdio_bus; 117 118 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 119 list); 120 if (!mdio_bus) 121 return NULL; 122 123 return mdio_bus->bus; 124 } 125 126 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 127 { 128 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 129 unsigned int n = d->hwirq; 130 131 chip->g1_irq.masked |= (1 << n); 132 } 133 134 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 135 { 136 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 137 unsigned int n = d->hwirq; 138 139 chip->g1_irq.masked &= ~(1 << n); 140 } 141 142 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 143 { 144 unsigned int nhandled = 0; 145 unsigned int sub_irq; 146 unsigned int n; 147 u16 reg; 148 u16 ctl1; 149 int err; 150 151 mv88e6xxx_reg_lock(chip); 152 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 153 mv88e6xxx_reg_unlock(chip); 154 155 if (err) 156 goto out; 157 158 do { 159 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 160 if (reg & (1 << n)) { 161 sub_irq = irq_find_mapping(chip->g1_irq.domain, 162 n); 163 handle_nested_irq(sub_irq); 164 ++nhandled; 165 } 166 } 167 168 mv88e6xxx_reg_lock(chip); 169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 170 if (err) 171 goto unlock; 172 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 173 unlock: 174 mv88e6xxx_reg_unlock(chip); 175 if (err) 176 goto out; 177 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 178 } while (reg & ctl1); 179 180 out: 181 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 182 } 183 184 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 185 { 186 struct mv88e6xxx_chip *chip = dev_id; 187 188 return mv88e6xxx_g1_irq_thread_work(chip); 189 } 190 191 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 192 { 193 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 194 195 mv88e6xxx_reg_lock(chip); 196 } 197 198 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 199 { 200 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 201 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 202 u16 reg; 203 int err; 204 205 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 206 if (err) 207 goto out; 208 209 reg &= ~mask; 210 reg |= (~chip->g1_irq.masked & mask); 211 212 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 213 if (err) 214 goto out; 215 216 out: 217 mv88e6xxx_reg_unlock(chip); 218 } 219 220 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 221 .name = "mv88e6xxx-g1", 222 .irq_mask = mv88e6xxx_g1_irq_mask, 223 .irq_unmask = mv88e6xxx_g1_irq_unmask, 224 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 225 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 226 }; 227 228 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 229 unsigned int irq, 230 irq_hw_number_t hwirq) 231 { 232 struct mv88e6xxx_chip *chip = d->host_data; 233 234 irq_set_chip_data(irq, d->host_data); 235 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 236 irq_set_noprobe(irq); 237 238 return 0; 239 } 240 241 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 242 .map = mv88e6xxx_g1_irq_domain_map, 243 .xlate = irq_domain_xlate_twocell, 244 }; 245 246 /* To be called with reg_lock held */ 247 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 248 { 249 int irq, virq; 250 u16 mask; 251 252 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 253 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 254 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 255 256 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 257 virq = irq_find_mapping(chip->g1_irq.domain, irq); 258 irq_dispose_mapping(virq); 259 } 260 261 irq_domain_remove(chip->g1_irq.domain); 262 } 263 264 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 265 { 266 /* 267 * free_irq must be called without reg_lock taken because the irq 268 * handler takes this lock, too. 269 */ 270 free_irq(chip->irq, chip); 271 272 mv88e6xxx_reg_lock(chip); 273 mv88e6xxx_g1_irq_free_common(chip); 274 mv88e6xxx_reg_unlock(chip); 275 } 276 277 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 278 { 279 int err, irq, virq; 280 u16 reg, mask; 281 282 chip->g1_irq.nirqs = chip->info->g1_irqs; 283 chip->g1_irq.domain = irq_domain_add_simple( 284 NULL, chip->g1_irq.nirqs, 0, 285 &mv88e6xxx_g1_irq_domain_ops, chip); 286 if (!chip->g1_irq.domain) 287 return -ENOMEM; 288 289 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 290 irq_create_mapping(chip->g1_irq.domain, irq); 291 292 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 293 chip->g1_irq.masked = ~0; 294 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 296 if (err) 297 goto out_mapping; 298 299 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 300 301 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 302 if (err) 303 goto out_disable; 304 305 /* Reading the interrupt status clears (most of) them */ 306 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 307 if (err) 308 goto out_disable; 309 310 return 0; 311 312 out_disable: 313 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 314 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 315 316 out_mapping: 317 for (irq = 0; irq < 16; irq++) { 318 virq = irq_find_mapping(chip->g1_irq.domain, irq); 319 irq_dispose_mapping(virq); 320 } 321 322 irq_domain_remove(chip->g1_irq.domain); 323 324 return err; 325 } 326 327 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 328 { 329 static struct lock_class_key lock_key; 330 static struct lock_class_key request_key; 331 int err; 332 333 err = mv88e6xxx_g1_irq_setup_common(chip); 334 if (err) 335 return err; 336 337 /* These lock classes tells lockdep that global 1 irqs are in 338 * a different category than their parent GPIO, so it won't 339 * report false recursion. 340 */ 341 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 342 343 snprintf(chip->irq_name, sizeof(chip->irq_name), 344 "mv88e6xxx-%s", dev_name(chip->dev)); 345 346 mv88e6xxx_reg_unlock(chip); 347 err = request_threaded_irq(chip->irq, NULL, 348 mv88e6xxx_g1_irq_thread_fn, 349 IRQF_ONESHOT | IRQF_SHARED, 350 chip->irq_name, chip); 351 mv88e6xxx_reg_lock(chip); 352 if (err) 353 mv88e6xxx_g1_irq_free_common(chip); 354 355 return err; 356 } 357 358 static void mv88e6xxx_irq_poll(struct kthread_work *work) 359 { 360 struct mv88e6xxx_chip *chip = container_of(work, 361 struct mv88e6xxx_chip, 362 irq_poll_work.work); 363 mv88e6xxx_g1_irq_thread_work(chip); 364 365 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 366 msecs_to_jiffies(100)); 367 } 368 369 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 370 { 371 int err; 372 373 err = mv88e6xxx_g1_irq_setup_common(chip); 374 if (err) 375 return err; 376 377 kthread_init_delayed_work(&chip->irq_poll_work, 378 mv88e6xxx_irq_poll); 379 380 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 381 if (IS_ERR(chip->kworker)) 382 return PTR_ERR(chip->kworker); 383 384 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 385 msecs_to_jiffies(100)); 386 387 return 0; 388 } 389 390 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 391 { 392 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 393 kthread_destroy_worker(chip->kworker); 394 395 mv88e6xxx_reg_lock(chip); 396 mv88e6xxx_g1_irq_free_common(chip); 397 mv88e6xxx_reg_unlock(chip); 398 } 399 400 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 401 int port, phy_interface_t interface) 402 { 403 int err; 404 405 if (chip->info->ops->port_set_rgmii_delay) { 406 err = chip->info->ops->port_set_rgmii_delay(chip, port, 407 interface); 408 if (err && err != -EOPNOTSUPP) 409 return err; 410 } 411 412 if (chip->info->ops->port_set_cmode) { 413 err = chip->info->ops->port_set_cmode(chip, port, 414 interface); 415 if (err && err != -EOPNOTSUPP) 416 return err; 417 } 418 419 return 0; 420 } 421 422 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 423 int link, int speed, int duplex, int pause, 424 phy_interface_t mode) 425 { 426 int err; 427 428 if (!chip->info->ops->port_set_link) 429 return 0; 430 431 /* Port's MAC control must not be changed unless the link is down */ 432 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 433 if (err) 434 return err; 435 436 if (chip->info->ops->port_set_speed_duplex) { 437 err = chip->info->ops->port_set_speed_duplex(chip, port, 438 speed, duplex); 439 if (err && err != -EOPNOTSUPP) 440 goto restore_link; 441 } 442 443 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 444 mode = chip->info->ops->port_max_speed_mode(port); 445 446 if (chip->info->ops->port_set_pause) { 447 err = chip->info->ops->port_set_pause(chip, port, pause); 448 if (err) 449 goto restore_link; 450 } 451 452 err = mv88e6xxx_port_config_interface(chip, port, mode); 453 restore_link: 454 if (chip->info->ops->port_set_link(chip, port, link)) 455 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 456 457 return err; 458 } 459 460 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 461 { 462 struct mv88e6xxx_chip *chip = ds->priv; 463 464 return port < chip->info->num_internal_phys; 465 } 466 467 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 468 { 469 u16 reg; 470 int err; 471 472 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 473 if (err) { 474 dev_err(chip->dev, 475 "p%d: %s: failed to read port status\n", 476 port, __func__); 477 return err; 478 } 479 480 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 481 } 482 483 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 484 struct phylink_link_state *state) 485 { 486 struct mv88e6xxx_chip *chip = ds->priv; 487 u8 lane; 488 int err; 489 490 mv88e6xxx_reg_lock(chip); 491 lane = mv88e6xxx_serdes_get_lane(chip, port); 492 if (lane && chip->info->ops->serdes_pcs_get_state) 493 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 494 state); 495 else 496 err = -EOPNOTSUPP; 497 mv88e6xxx_reg_unlock(chip); 498 499 return err; 500 } 501 502 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 503 unsigned int mode, 504 phy_interface_t interface, 505 const unsigned long *advertise) 506 { 507 const struct mv88e6xxx_ops *ops = chip->info->ops; 508 u8 lane; 509 510 if (ops->serdes_pcs_config) { 511 lane = mv88e6xxx_serdes_get_lane(chip, port); 512 if (lane) 513 return ops->serdes_pcs_config(chip, port, lane, mode, 514 interface, advertise); 515 } 516 517 return 0; 518 } 519 520 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 521 { 522 struct mv88e6xxx_chip *chip = ds->priv; 523 const struct mv88e6xxx_ops *ops; 524 int err = 0; 525 u8 lane; 526 527 ops = chip->info->ops; 528 529 if (ops->serdes_pcs_an_restart) { 530 mv88e6xxx_reg_lock(chip); 531 lane = mv88e6xxx_serdes_get_lane(chip, port); 532 if (lane) 533 err = ops->serdes_pcs_an_restart(chip, port, lane); 534 mv88e6xxx_reg_unlock(chip); 535 536 if (err) 537 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 538 } 539 } 540 541 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 542 unsigned int mode, 543 int speed, int duplex) 544 { 545 const struct mv88e6xxx_ops *ops = chip->info->ops; 546 u8 lane; 547 548 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 549 lane = mv88e6xxx_serdes_get_lane(chip, port); 550 if (lane) 551 return ops->serdes_pcs_link_up(chip, port, lane, 552 speed, duplex); 553 } 554 555 return 0; 556 } 557 558 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 559 unsigned long *mask, 560 struct phylink_link_state *state) 561 { 562 if (!phy_interface_mode_is_8023z(state->interface)) { 563 /* 10M and 100M are only supported in non-802.3z mode */ 564 phylink_set(mask, 10baseT_Half); 565 phylink_set(mask, 10baseT_Full); 566 phylink_set(mask, 100baseT_Half); 567 phylink_set(mask, 100baseT_Full); 568 } 569 } 570 571 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 572 unsigned long *mask, 573 struct phylink_link_state *state) 574 { 575 /* FIXME: if the port is in 1000Base-X mode, then it only supports 576 * 1000M FD speeds. In this case, CMODE will indicate 5. 577 */ 578 phylink_set(mask, 1000baseT_Full); 579 phylink_set(mask, 1000baseX_Full); 580 581 mv88e6065_phylink_validate(chip, port, mask, state); 582 } 583 584 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 585 unsigned long *mask, 586 struct phylink_link_state *state) 587 { 588 if (port >= 5) 589 phylink_set(mask, 2500baseX_Full); 590 591 /* No ethtool bits for 200Mbps */ 592 phylink_set(mask, 1000baseT_Full); 593 phylink_set(mask, 1000baseX_Full); 594 595 mv88e6065_phylink_validate(chip, port, mask, state); 596 } 597 598 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 599 unsigned long *mask, 600 struct phylink_link_state *state) 601 { 602 /* No ethtool bits for 200Mbps */ 603 phylink_set(mask, 1000baseT_Full); 604 phylink_set(mask, 1000baseX_Full); 605 606 mv88e6065_phylink_validate(chip, port, mask, state); 607 } 608 609 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 610 unsigned long *mask, 611 struct phylink_link_state *state) 612 { 613 if (port >= 9) { 614 phylink_set(mask, 2500baseX_Full); 615 phylink_set(mask, 2500baseT_Full); 616 } 617 618 /* No ethtool bits for 200Mbps */ 619 phylink_set(mask, 1000baseT_Full); 620 phylink_set(mask, 1000baseX_Full); 621 622 mv88e6065_phylink_validate(chip, port, mask, state); 623 } 624 625 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 626 unsigned long *mask, 627 struct phylink_link_state *state) 628 { 629 if (port >= 9) { 630 phylink_set(mask, 10000baseT_Full); 631 phylink_set(mask, 10000baseKR_Full); 632 } 633 634 mv88e6390_phylink_validate(chip, port, mask, state); 635 } 636 637 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 638 unsigned long *supported, 639 struct phylink_link_state *state) 640 { 641 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 642 struct mv88e6xxx_chip *chip = ds->priv; 643 644 /* Allow all the expected bits */ 645 phylink_set(mask, Autoneg); 646 phylink_set(mask, Pause); 647 phylink_set_port_modes(mask); 648 649 if (chip->info->ops->phylink_validate) 650 chip->info->ops->phylink_validate(chip, port, mask, state); 651 652 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 653 bitmap_and(state->advertising, state->advertising, mask, 654 __ETHTOOL_LINK_MODE_MASK_NBITS); 655 656 /* We can only operate at 2500BaseX or 1000BaseX. If requested 657 * to advertise both, only report advertising at 2500BaseX. 658 */ 659 phylink_helper_basex_speed(state); 660 } 661 662 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 663 unsigned int mode, 664 const struct phylink_link_state *state) 665 { 666 struct mv88e6xxx_chip *chip = ds->priv; 667 struct mv88e6xxx_port *p; 668 int err; 669 670 p = &chip->ports[port]; 671 672 /* FIXME: is this the correct test? If we're in fixed mode on an 673 * internal port, why should we process this any different from 674 * PHY mode? On the other hand, the port may be automedia between 675 * an internal PHY and the serdes... 676 */ 677 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 678 return; 679 680 mv88e6xxx_reg_lock(chip); 681 /* In inband mode, the link may come up at any time while the link 682 * is not forced down. Force the link down while we reconfigure the 683 * interface mode. 684 */ 685 if (mode == MLO_AN_INBAND && p->interface != state->interface && 686 chip->info->ops->port_set_link) 687 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 688 689 err = mv88e6xxx_port_config_interface(chip, port, state->interface); 690 if (err && err != -EOPNOTSUPP) 691 goto err_unlock; 692 693 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface, 694 state->advertising); 695 /* FIXME: we should restart negotiation if something changed - which 696 * is something we get if we convert to using phylinks PCS operations. 697 */ 698 if (err > 0) 699 err = 0; 700 701 /* Undo the forced down state above after completing configuration 702 * irrespective of its state on entry, which allows the link to come up. 703 */ 704 if (mode == MLO_AN_INBAND && p->interface != state->interface && 705 chip->info->ops->port_set_link) 706 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 707 708 p->interface = state->interface; 709 710 err_unlock: 711 mv88e6xxx_reg_unlock(chip); 712 713 if (err && err != -EOPNOTSUPP) 714 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 715 } 716 717 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 718 unsigned int mode, 719 phy_interface_t interface) 720 { 721 struct mv88e6xxx_chip *chip = ds->priv; 722 const struct mv88e6xxx_ops *ops; 723 int err = 0; 724 725 ops = chip->info->ops; 726 727 mv88e6xxx_reg_lock(chip); 728 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 729 mode == MLO_AN_FIXED) && ops->port_set_link) 730 err = ops->port_set_link(chip, port, LINK_FORCED_DOWN); 731 mv88e6xxx_reg_unlock(chip); 732 733 if (err) 734 dev_err(chip->dev, 735 "p%d: failed to force MAC link down\n", port); 736 } 737 738 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 739 unsigned int mode, phy_interface_t interface, 740 struct phy_device *phydev, 741 int speed, int duplex, 742 bool tx_pause, bool rx_pause) 743 { 744 struct mv88e6xxx_chip *chip = ds->priv; 745 const struct mv88e6xxx_ops *ops; 746 int err = 0; 747 748 ops = chip->info->ops; 749 750 mv88e6xxx_reg_lock(chip); 751 if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) { 752 /* FIXME: for an automedia port, should we force the link 753 * down here - what if the link comes up due to "other" media 754 * while we're bringing the port up, how is the exclusivity 755 * handled in the Marvell hardware? E.g. port 2 on 88E6390 756 * shared between internal PHY and Serdes. 757 */ 758 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 759 duplex); 760 if (err) 761 goto error; 762 763 if (ops->port_set_speed_duplex) { 764 err = ops->port_set_speed_duplex(chip, port, 765 speed, duplex); 766 if (err && err != -EOPNOTSUPP) 767 goto error; 768 } 769 770 if (ops->port_set_link) 771 err = ops->port_set_link(chip, port, LINK_FORCED_UP); 772 } 773 error: 774 mv88e6xxx_reg_unlock(chip); 775 776 if (err && err != -EOPNOTSUPP) 777 dev_err(ds->dev, 778 "p%d: failed to configure MAC link up\n", port); 779 } 780 781 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 782 { 783 if (!chip->info->ops->stats_snapshot) 784 return -EOPNOTSUPP; 785 786 return chip->info->ops->stats_snapshot(chip, port); 787 } 788 789 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 790 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 791 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 792 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 793 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 794 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 795 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 796 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 797 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 798 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 799 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 800 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 801 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 802 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 803 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 804 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 805 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 806 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 807 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 808 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 809 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 810 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 811 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 812 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 813 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 814 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 815 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 816 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 817 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 818 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 819 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 820 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 821 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 822 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 823 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 824 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 825 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 826 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 827 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 828 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 829 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 830 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 831 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 832 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 833 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 834 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 835 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 836 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 837 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 838 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 839 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 840 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 841 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 842 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 843 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 844 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 845 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 846 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 847 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 848 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 849 }; 850 851 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 852 struct mv88e6xxx_hw_stat *s, 853 int port, u16 bank1_select, 854 u16 histogram) 855 { 856 u32 low; 857 u32 high = 0; 858 u16 reg = 0; 859 int err; 860 u64 value; 861 862 switch (s->type) { 863 case STATS_TYPE_PORT: 864 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 865 if (err) 866 return U64_MAX; 867 868 low = reg; 869 if (s->size == 4) { 870 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 871 if (err) 872 return U64_MAX; 873 low |= ((u32)reg) << 16; 874 } 875 break; 876 case STATS_TYPE_BANK1: 877 reg = bank1_select; 878 /* fall through */ 879 case STATS_TYPE_BANK0: 880 reg |= s->reg | histogram; 881 mv88e6xxx_g1_stats_read(chip, reg, &low); 882 if (s->size == 8) 883 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 884 break; 885 default: 886 return U64_MAX; 887 } 888 value = (((u64)high) << 32) | low; 889 return value; 890 } 891 892 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 893 uint8_t *data, int types) 894 { 895 struct mv88e6xxx_hw_stat *stat; 896 int i, j; 897 898 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 899 stat = &mv88e6xxx_hw_stats[i]; 900 if (stat->type & types) { 901 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 902 ETH_GSTRING_LEN); 903 j++; 904 } 905 } 906 907 return j; 908 } 909 910 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 911 uint8_t *data) 912 { 913 return mv88e6xxx_stats_get_strings(chip, data, 914 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 915 } 916 917 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 918 uint8_t *data) 919 { 920 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 921 } 922 923 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 924 uint8_t *data) 925 { 926 return mv88e6xxx_stats_get_strings(chip, data, 927 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 928 } 929 930 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 931 "atu_member_violation", 932 "atu_miss_violation", 933 "atu_full_violation", 934 "vtu_member_violation", 935 "vtu_miss_violation", 936 }; 937 938 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 939 { 940 unsigned int i; 941 942 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 943 strlcpy(data + i * ETH_GSTRING_LEN, 944 mv88e6xxx_atu_vtu_stats_strings[i], 945 ETH_GSTRING_LEN); 946 } 947 948 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 949 u32 stringset, uint8_t *data) 950 { 951 struct mv88e6xxx_chip *chip = ds->priv; 952 int count = 0; 953 954 if (stringset != ETH_SS_STATS) 955 return; 956 957 mv88e6xxx_reg_lock(chip); 958 959 if (chip->info->ops->stats_get_strings) 960 count = chip->info->ops->stats_get_strings(chip, data); 961 962 if (chip->info->ops->serdes_get_strings) { 963 data += count * ETH_GSTRING_LEN; 964 count = chip->info->ops->serdes_get_strings(chip, port, data); 965 } 966 967 data += count * ETH_GSTRING_LEN; 968 mv88e6xxx_atu_vtu_get_strings(data); 969 970 mv88e6xxx_reg_unlock(chip); 971 } 972 973 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 974 int types) 975 { 976 struct mv88e6xxx_hw_stat *stat; 977 int i, j; 978 979 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 980 stat = &mv88e6xxx_hw_stats[i]; 981 if (stat->type & types) 982 j++; 983 } 984 return j; 985 } 986 987 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 988 { 989 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 990 STATS_TYPE_PORT); 991 } 992 993 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 994 { 995 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 996 } 997 998 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 999 { 1000 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1001 STATS_TYPE_BANK1); 1002 } 1003 1004 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1005 { 1006 struct mv88e6xxx_chip *chip = ds->priv; 1007 int serdes_count = 0; 1008 int count = 0; 1009 1010 if (sset != ETH_SS_STATS) 1011 return 0; 1012 1013 mv88e6xxx_reg_lock(chip); 1014 if (chip->info->ops->stats_get_sset_count) 1015 count = chip->info->ops->stats_get_sset_count(chip); 1016 if (count < 0) 1017 goto out; 1018 1019 if (chip->info->ops->serdes_get_sset_count) 1020 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1021 port); 1022 if (serdes_count < 0) { 1023 count = serdes_count; 1024 goto out; 1025 } 1026 count += serdes_count; 1027 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1028 1029 out: 1030 mv88e6xxx_reg_unlock(chip); 1031 1032 return count; 1033 } 1034 1035 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1036 uint64_t *data, int types, 1037 u16 bank1_select, u16 histogram) 1038 { 1039 struct mv88e6xxx_hw_stat *stat; 1040 int i, j; 1041 1042 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1043 stat = &mv88e6xxx_hw_stats[i]; 1044 if (stat->type & types) { 1045 mv88e6xxx_reg_lock(chip); 1046 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1047 bank1_select, 1048 histogram); 1049 mv88e6xxx_reg_unlock(chip); 1050 1051 j++; 1052 } 1053 } 1054 return j; 1055 } 1056 1057 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1058 uint64_t *data) 1059 { 1060 return mv88e6xxx_stats_get_stats(chip, port, data, 1061 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1062 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1063 } 1064 1065 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1066 uint64_t *data) 1067 { 1068 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1069 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1070 } 1071 1072 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1073 uint64_t *data) 1074 { 1075 return mv88e6xxx_stats_get_stats(chip, port, data, 1076 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1077 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1078 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1079 } 1080 1081 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1082 uint64_t *data) 1083 { 1084 return mv88e6xxx_stats_get_stats(chip, port, data, 1085 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1086 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1087 0); 1088 } 1089 1090 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1091 uint64_t *data) 1092 { 1093 *data++ = chip->ports[port].atu_member_violation; 1094 *data++ = chip->ports[port].atu_miss_violation; 1095 *data++ = chip->ports[port].atu_full_violation; 1096 *data++ = chip->ports[port].vtu_member_violation; 1097 *data++ = chip->ports[port].vtu_miss_violation; 1098 } 1099 1100 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1101 uint64_t *data) 1102 { 1103 int count = 0; 1104 1105 if (chip->info->ops->stats_get_stats) 1106 count = chip->info->ops->stats_get_stats(chip, port, data); 1107 1108 mv88e6xxx_reg_lock(chip); 1109 if (chip->info->ops->serdes_get_stats) { 1110 data += count; 1111 count = chip->info->ops->serdes_get_stats(chip, port, data); 1112 } 1113 data += count; 1114 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1115 mv88e6xxx_reg_unlock(chip); 1116 } 1117 1118 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1119 uint64_t *data) 1120 { 1121 struct mv88e6xxx_chip *chip = ds->priv; 1122 int ret; 1123 1124 mv88e6xxx_reg_lock(chip); 1125 1126 ret = mv88e6xxx_stats_snapshot(chip, port); 1127 mv88e6xxx_reg_unlock(chip); 1128 1129 if (ret < 0) 1130 return; 1131 1132 mv88e6xxx_get_stats(chip, port, data); 1133 1134 } 1135 1136 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1137 { 1138 struct mv88e6xxx_chip *chip = ds->priv; 1139 int len; 1140 1141 len = 32 * sizeof(u16); 1142 if (chip->info->ops->serdes_get_regs_len) 1143 len += chip->info->ops->serdes_get_regs_len(chip, port); 1144 1145 return len; 1146 } 1147 1148 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1149 struct ethtool_regs *regs, void *_p) 1150 { 1151 struct mv88e6xxx_chip *chip = ds->priv; 1152 int err; 1153 u16 reg; 1154 u16 *p = _p; 1155 int i; 1156 1157 regs->version = chip->info->prod_num; 1158 1159 memset(p, 0xff, 32 * sizeof(u16)); 1160 1161 mv88e6xxx_reg_lock(chip); 1162 1163 for (i = 0; i < 32; i++) { 1164 1165 err = mv88e6xxx_port_read(chip, port, i, ®); 1166 if (!err) 1167 p[i] = reg; 1168 } 1169 1170 if (chip->info->ops->serdes_get_regs) 1171 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1172 1173 mv88e6xxx_reg_unlock(chip); 1174 } 1175 1176 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1177 struct ethtool_eee *e) 1178 { 1179 /* Nothing to do on the port's MAC */ 1180 return 0; 1181 } 1182 1183 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1184 struct ethtool_eee *e) 1185 { 1186 /* Nothing to do on the port's MAC */ 1187 return 0; 1188 } 1189 1190 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1191 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1192 { 1193 struct dsa_switch *ds = chip->ds; 1194 struct dsa_switch_tree *dst = ds->dst; 1195 struct net_device *br; 1196 struct dsa_port *dp; 1197 bool found = false; 1198 u16 pvlan; 1199 1200 list_for_each_entry(dp, &dst->ports, list) { 1201 if (dp->ds->index == dev && dp->index == port) { 1202 found = true; 1203 break; 1204 } 1205 } 1206 1207 /* Prevent frames from unknown switch or port */ 1208 if (!found) 1209 return 0; 1210 1211 /* Frames from DSA links and CPU ports can egress any local port */ 1212 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1213 return mv88e6xxx_port_mask(chip); 1214 1215 br = dp->bridge_dev; 1216 pvlan = 0; 1217 1218 /* Frames from user ports can egress any local DSA links and CPU ports, 1219 * as well as any local member of their bridge group. 1220 */ 1221 list_for_each_entry(dp, &dst->ports, list) 1222 if (dp->ds == ds && 1223 (dp->type == DSA_PORT_TYPE_CPU || 1224 dp->type == DSA_PORT_TYPE_DSA || 1225 (br && dp->bridge_dev == br))) 1226 pvlan |= BIT(dp->index); 1227 1228 return pvlan; 1229 } 1230 1231 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1232 { 1233 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1234 1235 /* prevent frames from going back out of the port they came in on */ 1236 output_ports &= ~BIT(port); 1237 1238 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1239 } 1240 1241 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1242 u8 state) 1243 { 1244 struct mv88e6xxx_chip *chip = ds->priv; 1245 int err; 1246 1247 mv88e6xxx_reg_lock(chip); 1248 err = mv88e6xxx_port_set_state(chip, port, state); 1249 mv88e6xxx_reg_unlock(chip); 1250 1251 if (err) 1252 dev_err(ds->dev, "p%d: failed to update state\n", port); 1253 } 1254 1255 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1256 { 1257 int err; 1258 1259 if (chip->info->ops->ieee_pri_map) { 1260 err = chip->info->ops->ieee_pri_map(chip); 1261 if (err) 1262 return err; 1263 } 1264 1265 if (chip->info->ops->ip_pri_map) { 1266 err = chip->info->ops->ip_pri_map(chip); 1267 if (err) 1268 return err; 1269 } 1270 1271 return 0; 1272 } 1273 1274 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1275 { 1276 struct dsa_switch *ds = chip->ds; 1277 int target, port; 1278 int err; 1279 1280 if (!chip->info->global2_addr) 1281 return 0; 1282 1283 /* Initialize the routing port to the 32 possible target devices */ 1284 for (target = 0; target < 32; target++) { 1285 port = dsa_routing_port(ds, target); 1286 if (port == ds->num_ports) 1287 port = 0x1f; 1288 1289 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1290 if (err) 1291 return err; 1292 } 1293 1294 if (chip->info->ops->set_cascade_port) { 1295 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1296 err = chip->info->ops->set_cascade_port(chip, port); 1297 if (err) 1298 return err; 1299 } 1300 1301 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1302 if (err) 1303 return err; 1304 1305 return 0; 1306 } 1307 1308 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1309 { 1310 /* Clear all trunk masks and mapping */ 1311 if (chip->info->global2_addr) 1312 return mv88e6xxx_g2_trunk_clear(chip); 1313 1314 return 0; 1315 } 1316 1317 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1318 { 1319 if (chip->info->ops->rmu_disable) 1320 return chip->info->ops->rmu_disable(chip); 1321 1322 return 0; 1323 } 1324 1325 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1326 { 1327 if (chip->info->ops->pot_clear) 1328 return chip->info->ops->pot_clear(chip); 1329 1330 return 0; 1331 } 1332 1333 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1334 { 1335 if (chip->info->ops->mgmt_rsvd2cpu) 1336 return chip->info->ops->mgmt_rsvd2cpu(chip); 1337 1338 return 0; 1339 } 1340 1341 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1342 { 1343 int err; 1344 1345 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1346 if (err) 1347 return err; 1348 1349 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1350 if (err) 1351 return err; 1352 1353 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1354 } 1355 1356 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1357 { 1358 int port; 1359 int err; 1360 1361 if (!chip->info->ops->irl_init_all) 1362 return 0; 1363 1364 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1365 /* Disable ingress rate limiting by resetting all per port 1366 * ingress rate limit resources to their initial state. 1367 */ 1368 err = chip->info->ops->irl_init_all(chip, port); 1369 if (err) 1370 return err; 1371 } 1372 1373 return 0; 1374 } 1375 1376 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1377 { 1378 if (chip->info->ops->set_switch_mac) { 1379 u8 addr[ETH_ALEN]; 1380 1381 eth_random_addr(addr); 1382 1383 return chip->info->ops->set_switch_mac(chip, addr); 1384 } 1385 1386 return 0; 1387 } 1388 1389 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1390 { 1391 u16 pvlan = 0; 1392 1393 if (!mv88e6xxx_has_pvt(chip)) 1394 return 0; 1395 1396 /* Skip the local source device, which uses in-chip port VLAN */ 1397 if (dev != chip->ds->index) 1398 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1399 1400 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1401 } 1402 1403 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1404 { 1405 int dev, port; 1406 int err; 1407 1408 if (!mv88e6xxx_has_pvt(chip)) 1409 return 0; 1410 1411 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1412 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1413 */ 1414 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1415 if (err) 1416 return err; 1417 1418 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1419 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1420 err = mv88e6xxx_pvt_map(chip, dev, port); 1421 if (err) 1422 return err; 1423 } 1424 } 1425 1426 return 0; 1427 } 1428 1429 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1430 { 1431 struct mv88e6xxx_chip *chip = ds->priv; 1432 int err; 1433 1434 mv88e6xxx_reg_lock(chip); 1435 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1436 mv88e6xxx_reg_unlock(chip); 1437 1438 if (err) 1439 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1440 } 1441 1442 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1443 { 1444 if (!chip->info->max_vid) 1445 return 0; 1446 1447 return mv88e6xxx_g1_vtu_flush(chip); 1448 } 1449 1450 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1451 struct mv88e6xxx_vtu_entry *entry) 1452 { 1453 if (!chip->info->ops->vtu_getnext) 1454 return -EOPNOTSUPP; 1455 1456 return chip->info->ops->vtu_getnext(chip, entry); 1457 } 1458 1459 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1460 struct mv88e6xxx_vtu_entry *entry) 1461 { 1462 if (!chip->info->ops->vtu_loadpurge) 1463 return -EOPNOTSUPP; 1464 1465 return chip->info->ops->vtu_loadpurge(chip, entry); 1466 } 1467 1468 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1469 { 1470 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1471 struct mv88e6xxx_vtu_entry vlan; 1472 int i, err; 1473 1474 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1475 1476 /* Set every FID bit used by the (un)bridged ports */ 1477 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1478 err = mv88e6xxx_port_get_fid(chip, i, fid); 1479 if (err) 1480 return err; 1481 1482 set_bit(*fid, fid_bitmap); 1483 } 1484 1485 /* Set every FID bit used by the VLAN entries */ 1486 vlan.vid = chip->info->max_vid; 1487 vlan.valid = false; 1488 1489 do { 1490 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1491 if (err) 1492 return err; 1493 1494 if (!vlan.valid) 1495 break; 1496 1497 set_bit(vlan.fid, fid_bitmap); 1498 } while (vlan.vid < chip->info->max_vid); 1499 1500 /* The reset value 0x000 is used to indicate that multiple address 1501 * databases are not needed. Return the next positive available. 1502 */ 1503 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1504 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1505 return -ENOSPC; 1506 1507 /* Clear the database */ 1508 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1509 } 1510 1511 static int mv88e6xxx_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash) 1512 { 1513 if (chip->info->ops->atu_get_hash) 1514 return chip->info->ops->atu_get_hash(chip, hash); 1515 1516 return -EOPNOTSUPP; 1517 } 1518 1519 static int mv88e6xxx_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash) 1520 { 1521 if (chip->info->ops->atu_set_hash) 1522 return chip->info->ops->atu_set_hash(chip, hash); 1523 1524 return -EOPNOTSUPP; 1525 } 1526 1527 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1528 u16 vid_begin, u16 vid_end) 1529 { 1530 struct mv88e6xxx_chip *chip = ds->priv; 1531 struct mv88e6xxx_vtu_entry vlan; 1532 int i, err; 1533 1534 /* DSA and CPU ports have to be members of multiple vlans */ 1535 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1536 return 0; 1537 1538 if (!vid_begin) 1539 return -EOPNOTSUPP; 1540 1541 vlan.vid = vid_begin - 1; 1542 vlan.valid = false; 1543 1544 do { 1545 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1546 if (err) 1547 return err; 1548 1549 if (!vlan.valid) 1550 break; 1551 1552 if (vlan.vid > vid_end) 1553 break; 1554 1555 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1556 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1557 continue; 1558 1559 if (!dsa_to_port(ds, i)->slave) 1560 continue; 1561 1562 if (vlan.member[i] == 1563 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1564 continue; 1565 1566 if (dsa_to_port(ds, i)->bridge_dev == 1567 dsa_to_port(ds, port)->bridge_dev) 1568 break; /* same bridge, check next VLAN */ 1569 1570 if (!dsa_to_port(ds, i)->bridge_dev) 1571 continue; 1572 1573 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1574 port, vlan.vid, i, 1575 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1576 return -EOPNOTSUPP; 1577 } 1578 } while (vlan.vid < vid_end); 1579 1580 return 0; 1581 } 1582 1583 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1584 bool vlan_filtering) 1585 { 1586 struct mv88e6xxx_chip *chip = ds->priv; 1587 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1588 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1589 int err; 1590 1591 if (!chip->info->max_vid) 1592 return -EOPNOTSUPP; 1593 1594 mv88e6xxx_reg_lock(chip); 1595 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1596 mv88e6xxx_reg_unlock(chip); 1597 1598 return err; 1599 } 1600 1601 static int 1602 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1603 const struct switchdev_obj_port_vlan *vlan) 1604 { 1605 struct mv88e6xxx_chip *chip = ds->priv; 1606 int err; 1607 1608 if (!chip->info->max_vid) 1609 return -EOPNOTSUPP; 1610 1611 /* If the requested port doesn't belong to the same bridge as the VLAN 1612 * members, do not support it (yet) and fallback to software VLAN. 1613 */ 1614 mv88e6xxx_reg_lock(chip); 1615 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1616 vlan->vid_end); 1617 mv88e6xxx_reg_unlock(chip); 1618 1619 /* We don't need any dynamic resource from the kernel (yet), 1620 * so skip the prepare phase. 1621 */ 1622 return err; 1623 } 1624 1625 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1626 const unsigned char *addr, u16 vid, 1627 u8 state) 1628 { 1629 struct mv88e6xxx_atu_entry entry; 1630 struct mv88e6xxx_vtu_entry vlan; 1631 u16 fid; 1632 int err; 1633 1634 /* Null VLAN ID corresponds to the port private database */ 1635 if (vid == 0) { 1636 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1637 if (err) 1638 return err; 1639 } else { 1640 vlan.vid = vid - 1; 1641 vlan.valid = false; 1642 1643 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1644 if (err) 1645 return err; 1646 1647 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1648 if (vlan.vid != vid || !vlan.valid) 1649 return -EOPNOTSUPP; 1650 1651 fid = vlan.fid; 1652 } 1653 1654 entry.state = 0; 1655 ether_addr_copy(entry.mac, addr); 1656 eth_addr_dec(entry.mac); 1657 1658 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1659 if (err) 1660 return err; 1661 1662 /* Initialize a fresh ATU entry if it isn't found */ 1663 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1664 memset(&entry, 0, sizeof(entry)); 1665 ether_addr_copy(entry.mac, addr); 1666 } 1667 1668 /* Purge the ATU entry only if no port is using it anymore */ 1669 if (!state) { 1670 entry.portvec &= ~BIT(port); 1671 if (!entry.portvec) 1672 entry.state = 0; 1673 } else { 1674 entry.portvec |= BIT(port); 1675 entry.state = state; 1676 } 1677 1678 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1679 } 1680 1681 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1682 const struct mv88e6xxx_policy *policy) 1683 { 1684 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1685 enum mv88e6xxx_policy_action action = policy->action; 1686 const u8 *addr = policy->addr; 1687 u16 vid = policy->vid; 1688 u8 state; 1689 int err; 1690 int id; 1691 1692 if (!chip->info->ops->port_set_policy) 1693 return -EOPNOTSUPP; 1694 1695 switch (mapping) { 1696 case MV88E6XXX_POLICY_MAPPING_DA: 1697 case MV88E6XXX_POLICY_MAPPING_SA: 1698 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1699 state = 0; /* Dissociate the port and address */ 1700 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1701 is_multicast_ether_addr(addr)) 1702 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1703 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1704 is_unicast_ether_addr(addr)) 1705 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1706 else 1707 return -EOPNOTSUPP; 1708 1709 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1710 state); 1711 if (err) 1712 return err; 1713 break; 1714 default: 1715 return -EOPNOTSUPP; 1716 } 1717 1718 /* Skip the port's policy clearing if the mapping is still in use */ 1719 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1720 idr_for_each_entry(&chip->policies, policy, id) 1721 if (policy->port == port && 1722 policy->mapping == mapping && 1723 policy->action != action) 1724 return 0; 1725 1726 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1727 } 1728 1729 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1730 struct ethtool_rx_flow_spec *fs) 1731 { 1732 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1733 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1734 enum mv88e6xxx_policy_mapping mapping; 1735 enum mv88e6xxx_policy_action action; 1736 struct mv88e6xxx_policy *policy; 1737 u16 vid = 0; 1738 u8 *addr; 1739 int err; 1740 int id; 1741 1742 if (fs->location != RX_CLS_LOC_ANY) 1743 return -EINVAL; 1744 1745 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1746 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1747 else 1748 return -EOPNOTSUPP; 1749 1750 switch (fs->flow_type & ~FLOW_EXT) { 1751 case ETHER_FLOW: 1752 if (!is_zero_ether_addr(mac_mask->h_dest) && 1753 is_zero_ether_addr(mac_mask->h_source)) { 1754 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1755 addr = mac_entry->h_dest; 1756 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1757 !is_zero_ether_addr(mac_mask->h_source)) { 1758 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1759 addr = mac_entry->h_source; 1760 } else { 1761 /* Cannot support DA and SA mapping in the same rule */ 1762 return -EOPNOTSUPP; 1763 } 1764 break; 1765 default: 1766 return -EOPNOTSUPP; 1767 } 1768 1769 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1770 if (fs->m_ext.vlan_tci != htons(0xffff)) 1771 return -EOPNOTSUPP; 1772 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1773 } 1774 1775 idr_for_each_entry(&chip->policies, policy, id) { 1776 if (policy->port == port && policy->mapping == mapping && 1777 policy->action == action && policy->vid == vid && 1778 ether_addr_equal(policy->addr, addr)) 1779 return -EEXIST; 1780 } 1781 1782 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1783 if (!policy) 1784 return -ENOMEM; 1785 1786 fs->location = 0; 1787 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1788 GFP_KERNEL); 1789 if (err) { 1790 devm_kfree(chip->dev, policy); 1791 return err; 1792 } 1793 1794 memcpy(&policy->fs, fs, sizeof(*fs)); 1795 ether_addr_copy(policy->addr, addr); 1796 policy->mapping = mapping; 1797 policy->action = action; 1798 policy->port = port; 1799 policy->vid = vid; 1800 1801 err = mv88e6xxx_policy_apply(chip, port, policy); 1802 if (err) { 1803 idr_remove(&chip->policies, fs->location); 1804 devm_kfree(chip->dev, policy); 1805 return err; 1806 } 1807 1808 return 0; 1809 } 1810 1811 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1812 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1813 { 1814 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1815 struct mv88e6xxx_chip *chip = ds->priv; 1816 struct mv88e6xxx_policy *policy; 1817 int err; 1818 int id; 1819 1820 mv88e6xxx_reg_lock(chip); 1821 1822 switch (rxnfc->cmd) { 1823 case ETHTOOL_GRXCLSRLCNT: 1824 rxnfc->data = 0; 1825 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1826 rxnfc->rule_cnt = 0; 1827 idr_for_each_entry(&chip->policies, policy, id) 1828 if (policy->port == port) 1829 rxnfc->rule_cnt++; 1830 err = 0; 1831 break; 1832 case ETHTOOL_GRXCLSRULE: 1833 err = -ENOENT; 1834 policy = idr_find(&chip->policies, fs->location); 1835 if (policy) { 1836 memcpy(fs, &policy->fs, sizeof(*fs)); 1837 err = 0; 1838 } 1839 break; 1840 case ETHTOOL_GRXCLSRLALL: 1841 rxnfc->data = 0; 1842 rxnfc->rule_cnt = 0; 1843 idr_for_each_entry(&chip->policies, policy, id) 1844 if (policy->port == port) 1845 rule_locs[rxnfc->rule_cnt++] = id; 1846 err = 0; 1847 break; 1848 default: 1849 err = -EOPNOTSUPP; 1850 break; 1851 } 1852 1853 mv88e6xxx_reg_unlock(chip); 1854 1855 return err; 1856 } 1857 1858 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 1859 struct ethtool_rxnfc *rxnfc) 1860 { 1861 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1862 struct mv88e6xxx_chip *chip = ds->priv; 1863 struct mv88e6xxx_policy *policy; 1864 int err; 1865 1866 mv88e6xxx_reg_lock(chip); 1867 1868 switch (rxnfc->cmd) { 1869 case ETHTOOL_SRXCLSRLINS: 1870 err = mv88e6xxx_policy_insert(chip, port, fs); 1871 break; 1872 case ETHTOOL_SRXCLSRLDEL: 1873 err = -ENOENT; 1874 policy = idr_remove(&chip->policies, fs->location); 1875 if (policy) { 1876 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 1877 err = mv88e6xxx_policy_apply(chip, port, policy); 1878 devm_kfree(chip->dev, policy); 1879 } 1880 break; 1881 default: 1882 err = -EOPNOTSUPP; 1883 break; 1884 } 1885 1886 mv88e6xxx_reg_unlock(chip); 1887 1888 return err; 1889 } 1890 1891 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1892 u16 vid) 1893 { 1894 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1895 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1896 1897 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1898 } 1899 1900 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1901 { 1902 int port; 1903 int err; 1904 1905 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1906 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1907 if (err) 1908 return err; 1909 } 1910 1911 return 0; 1912 } 1913 1914 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 1915 u16 vid, u8 member, bool warn) 1916 { 1917 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1918 struct mv88e6xxx_vtu_entry vlan; 1919 int i, err; 1920 1921 if (!vid) 1922 return -EOPNOTSUPP; 1923 1924 vlan.vid = vid - 1; 1925 vlan.valid = false; 1926 1927 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1928 if (err) 1929 return err; 1930 1931 if (vlan.vid != vid || !vlan.valid) { 1932 memset(&vlan, 0, sizeof(vlan)); 1933 1934 err = mv88e6xxx_atu_new(chip, &vlan.fid); 1935 if (err) 1936 return err; 1937 1938 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1939 if (i == port) 1940 vlan.member[i] = member; 1941 else 1942 vlan.member[i] = non_member; 1943 1944 vlan.vid = vid; 1945 vlan.valid = true; 1946 1947 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1948 if (err) 1949 return err; 1950 1951 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 1952 if (err) 1953 return err; 1954 } else if (vlan.member[port] != member) { 1955 vlan.member[port] = member; 1956 1957 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1958 if (err) 1959 return err; 1960 } else if (warn) { 1961 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 1962 port, vid); 1963 } 1964 1965 return 0; 1966 } 1967 1968 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1969 const struct switchdev_obj_port_vlan *vlan) 1970 { 1971 struct mv88e6xxx_chip *chip = ds->priv; 1972 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1973 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1974 bool warn; 1975 u8 member; 1976 u16 vid; 1977 1978 if (!chip->info->max_vid) 1979 return; 1980 1981 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1982 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1983 else if (untagged) 1984 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1985 else 1986 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1987 1988 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 1989 * and then the CPU port. Do not warn for duplicates for the CPU port. 1990 */ 1991 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 1992 1993 mv88e6xxx_reg_lock(chip); 1994 1995 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1996 if (mv88e6xxx_port_vlan_join(chip, port, vid, member, warn)) 1997 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1998 vid, untagged ? 'u' : 't'); 1999 2000 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 2001 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 2002 vlan->vid_end); 2003 2004 mv88e6xxx_reg_unlock(chip); 2005 } 2006 2007 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2008 int port, u16 vid) 2009 { 2010 struct mv88e6xxx_vtu_entry vlan; 2011 int i, err; 2012 2013 if (!vid) 2014 return -EOPNOTSUPP; 2015 2016 vlan.vid = vid - 1; 2017 vlan.valid = false; 2018 2019 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2020 if (err) 2021 return err; 2022 2023 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2024 * tell switchdev that this VLAN is likely handled in software. 2025 */ 2026 if (vlan.vid != vid || !vlan.valid || 2027 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2028 return -EOPNOTSUPP; 2029 2030 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2031 2032 /* keep the VLAN unless all ports are excluded */ 2033 vlan.valid = false; 2034 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2035 if (vlan.member[i] != 2036 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2037 vlan.valid = true; 2038 break; 2039 } 2040 } 2041 2042 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2043 if (err) 2044 return err; 2045 2046 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2047 } 2048 2049 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2050 const struct switchdev_obj_port_vlan *vlan) 2051 { 2052 struct mv88e6xxx_chip *chip = ds->priv; 2053 u16 pvid, vid; 2054 int err = 0; 2055 2056 if (!chip->info->max_vid) 2057 return -EOPNOTSUPP; 2058 2059 mv88e6xxx_reg_lock(chip); 2060 2061 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2062 if (err) 2063 goto unlock; 2064 2065 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 2066 err = mv88e6xxx_port_vlan_leave(chip, port, vid); 2067 if (err) 2068 goto unlock; 2069 2070 if (vid == pvid) { 2071 err = mv88e6xxx_port_set_pvid(chip, port, 0); 2072 if (err) 2073 goto unlock; 2074 } 2075 } 2076 2077 unlock: 2078 mv88e6xxx_reg_unlock(chip); 2079 2080 return err; 2081 } 2082 2083 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2084 const unsigned char *addr, u16 vid) 2085 { 2086 struct mv88e6xxx_chip *chip = ds->priv; 2087 int err; 2088 2089 mv88e6xxx_reg_lock(chip); 2090 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2091 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2092 mv88e6xxx_reg_unlock(chip); 2093 2094 return err; 2095 } 2096 2097 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2098 const unsigned char *addr, u16 vid) 2099 { 2100 struct mv88e6xxx_chip *chip = ds->priv; 2101 int err; 2102 2103 mv88e6xxx_reg_lock(chip); 2104 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2105 mv88e6xxx_reg_unlock(chip); 2106 2107 return err; 2108 } 2109 2110 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2111 u16 fid, u16 vid, int port, 2112 dsa_fdb_dump_cb_t *cb, void *data) 2113 { 2114 struct mv88e6xxx_atu_entry addr; 2115 bool is_static; 2116 int err; 2117 2118 addr.state = 0; 2119 eth_broadcast_addr(addr.mac); 2120 2121 do { 2122 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2123 if (err) 2124 return err; 2125 2126 if (!addr.state) 2127 break; 2128 2129 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2130 continue; 2131 2132 if (!is_unicast_ether_addr(addr.mac)) 2133 continue; 2134 2135 is_static = (addr.state == 2136 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2137 err = cb(addr.mac, vid, is_static, data); 2138 if (err) 2139 return err; 2140 } while (!is_broadcast_ether_addr(addr.mac)); 2141 2142 return err; 2143 } 2144 2145 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2146 dsa_fdb_dump_cb_t *cb, void *data) 2147 { 2148 struct mv88e6xxx_vtu_entry vlan; 2149 u16 fid; 2150 int err; 2151 2152 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2153 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2154 if (err) 2155 return err; 2156 2157 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2158 if (err) 2159 return err; 2160 2161 /* Dump VLANs' Filtering Information Databases */ 2162 vlan.vid = chip->info->max_vid; 2163 vlan.valid = false; 2164 2165 do { 2166 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2167 if (err) 2168 return err; 2169 2170 if (!vlan.valid) 2171 break; 2172 2173 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 2174 cb, data); 2175 if (err) 2176 return err; 2177 } while (vlan.vid < chip->info->max_vid); 2178 2179 return err; 2180 } 2181 2182 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2183 dsa_fdb_dump_cb_t *cb, void *data) 2184 { 2185 struct mv88e6xxx_chip *chip = ds->priv; 2186 int err; 2187 2188 mv88e6xxx_reg_lock(chip); 2189 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2190 mv88e6xxx_reg_unlock(chip); 2191 2192 return err; 2193 } 2194 2195 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2196 struct net_device *br) 2197 { 2198 struct dsa_switch *ds = chip->ds; 2199 struct dsa_switch_tree *dst = ds->dst; 2200 struct dsa_port *dp; 2201 int err; 2202 2203 list_for_each_entry(dp, &dst->ports, list) { 2204 if (dp->bridge_dev == br) { 2205 if (dp->ds == ds) { 2206 /* This is a local bridge group member, 2207 * remap its Port VLAN Map. 2208 */ 2209 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2210 if (err) 2211 return err; 2212 } else { 2213 /* This is an external bridge group member, 2214 * remap its cross-chip Port VLAN Table entry. 2215 */ 2216 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2217 dp->index); 2218 if (err) 2219 return err; 2220 } 2221 } 2222 } 2223 2224 return 0; 2225 } 2226 2227 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2228 struct net_device *br) 2229 { 2230 struct mv88e6xxx_chip *chip = ds->priv; 2231 int err; 2232 2233 mv88e6xxx_reg_lock(chip); 2234 err = mv88e6xxx_bridge_map(chip, br); 2235 mv88e6xxx_reg_unlock(chip); 2236 2237 return err; 2238 } 2239 2240 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2241 struct net_device *br) 2242 { 2243 struct mv88e6xxx_chip *chip = ds->priv; 2244 2245 mv88e6xxx_reg_lock(chip); 2246 if (mv88e6xxx_bridge_map(chip, br) || 2247 mv88e6xxx_port_vlan_map(chip, port)) 2248 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2249 mv88e6xxx_reg_unlock(chip); 2250 } 2251 2252 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2253 int tree_index, int sw_index, 2254 int port, struct net_device *br) 2255 { 2256 struct mv88e6xxx_chip *chip = ds->priv; 2257 int err; 2258 2259 if (tree_index != ds->dst->index) 2260 return 0; 2261 2262 mv88e6xxx_reg_lock(chip); 2263 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2264 mv88e6xxx_reg_unlock(chip); 2265 2266 return err; 2267 } 2268 2269 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2270 int tree_index, int sw_index, 2271 int port, struct net_device *br) 2272 { 2273 struct mv88e6xxx_chip *chip = ds->priv; 2274 2275 if (tree_index != ds->dst->index) 2276 return; 2277 2278 mv88e6xxx_reg_lock(chip); 2279 if (mv88e6xxx_pvt_map(chip, sw_index, port)) 2280 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2281 mv88e6xxx_reg_unlock(chip); 2282 } 2283 2284 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2285 { 2286 if (chip->info->ops->reset) 2287 return chip->info->ops->reset(chip); 2288 2289 return 0; 2290 } 2291 2292 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2293 { 2294 struct gpio_desc *gpiod = chip->reset; 2295 2296 /* If there is a GPIO connected to the reset pin, toggle it */ 2297 if (gpiod) { 2298 gpiod_set_value_cansleep(gpiod, 1); 2299 usleep_range(10000, 20000); 2300 gpiod_set_value_cansleep(gpiod, 0); 2301 usleep_range(10000, 20000); 2302 } 2303 } 2304 2305 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2306 { 2307 int i, err; 2308 2309 /* Set all ports to the Disabled state */ 2310 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2311 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2312 if (err) 2313 return err; 2314 } 2315 2316 /* Wait for transmit queues to drain, 2317 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2318 */ 2319 usleep_range(2000, 4000); 2320 2321 return 0; 2322 } 2323 2324 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2325 { 2326 int err; 2327 2328 err = mv88e6xxx_disable_ports(chip); 2329 if (err) 2330 return err; 2331 2332 mv88e6xxx_hardware_reset(chip); 2333 2334 return mv88e6xxx_software_reset(chip); 2335 } 2336 2337 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2338 enum mv88e6xxx_frame_mode frame, 2339 enum mv88e6xxx_egress_mode egress, u16 etype) 2340 { 2341 int err; 2342 2343 if (!chip->info->ops->port_set_frame_mode) 2344 return -EOPNOTSUPP; 2345 2346 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2347 if (err) 2348 return err; 2349 2350 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2351 if (err) 2352 return err; 2353 2354 if (chip->info->ops->port_set_ether_type) 2355 return chip->info->ops->port_set_ether_type(chip, port, etype); 2356 2357 return 0; 2358 } 2359 2360 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2361 { 2362 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2363 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2364 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2365 } 2366 2367 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2368 { 2369 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2370 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2371 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2372 } 2373 2374 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2375 { 2376 return mv88e6xxx_set_port_mode(chip, port, 2377 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2378 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2379 ETH_P_EDSA); 2380 } 2381 2382 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2383 { 2384 if (dsa_is_dsa_port(chip->ds, port)) 2385 return mv88e6xxx_set_port_mode_dsa(chip, port); 2386 2387 if (dsa_is_user_port(chip->ds, port)) 2388 return mv88e6xxx_set_port_mode_normal(chip, port); 2389 2390 /* Setup CPU port mode depending on its supported tag format */ 2391 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2392 return mv88e6xxx_set_port_mode_dsa(chip, port); 2393 2394 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2395 return mv88e6xxx_set_port_mode_edsa(chip, port); 2396 2397 return -EINVAL; 2398 } 2399 2400 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2401 { 2402 bool message = dsa_is_dsa_port(chip->ds, port); 2403 2404 return mv88e6xxx_port_set_message_port(chip, port, message); 2405 } 2406 2407 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2408 { 2409 struct dsa_switch *ds = chip->ds; 2410 bool flood; 2411 2412 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2413 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2414 if (chip->info->ops->port_set_egress_floods) 2415 return chip->info->ops->port_set_egress_floods(chip, port, 2416 flood, flood); 2417 2418 return 0; 2419 } 2420 2421 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2422 { 2423 struct mv88e6xxx_port *mvp = dev_id; 2424 struct mv88e6xxx_chip *chip = mvp->chip; 2425 irqreturn_t ret = IRQ_NONE; 2426 int port = mvp->port; 2427 u8 lane; 2428 2429 mv88e6xxx_reg_lock(chip); 2430 lane = mv88e6xxx_serdes_get_lane(chip, port); 2431 if (lane) 2432 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2433 mv88e6xxx_reg_unlock(chip); 2434 2435 return ret; 2436 } 2437 2438 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2439 u8 lane) 2440 { 2441 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2442 unsigned int irq; 2443 int err; 2444 2445 /* Nothing to request if this SERDES port has no IRQ */ 2446 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2447 if (!irq) 2448 return 0; 2449 2450 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2451 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2452 2453 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2454 mv88e6xxx_reg_unlock(chip); 2455 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2456 IRQF_ONESHOT, dev_id->serdes_irq_name, 2457 dev_id); 2458 mv88e6xxx_reg_lock(chip); 2459 if (err) 2460 return err; 2461 2462 dev_id->serdes_irq = irq; 2463 2464 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2465 } 2466 2467 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2468 u8 lane) 2469 { 2470 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2471 unsigned int irq = dev_id->serdes_irq; 2472 int err; 2473 2474 /* Nothing to free if no IRQ has been requested */ 2475 if (!irq) 2476 return 0; 2477 2478 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2479 2480 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2481 mv88e6xxx_reg_unlock(chip); 2482 free_irq(irq, dev_id); 2483 mv88e6xxx_reg_lock(chip); 2484 2485 dev_id->serdes_irq = 0; 2486 2487 return err; 2488 } 2489 2490 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2491 bool on) 2492 { 2493 u8 lane; 2494 int err; 2495 2496 lane = mv88e6xxx_serdes_get_lane(chip, port); 2497 if (!lane) 2498 return 0; 2499 2500 if (on) { 2501 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2502 if (err) 2503 return err; 2504 2505 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2506 } else { 2507 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2508 if (err) 2509 return err; 2510 2511 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2512 } 2513 2514 return err; 2515 } 2516 2517 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2518 { 2519 struct dsa_switch *ds = chip->ds; 2520 int upstream_port; 2521 int err; 2522 2523 upstream_port = dsa_upstream_port(ds, port); 2524 if (chip->info->ops->port_set_upstream_port) { 2525 err = chip->info->ops->port_set_upstream_port(chip, port, 2526 upstream_port); 2527 if (err) 2528 return err; 2529 } 2530 2531 if (port == upstream_port) { 2532 if (chip->info->ops->set_cpu_port) { 2533 err = chip->info->ops->set_cpu_port(chip, 2534 upstream_port); 2535 if (err) 2536 return err; 2537 } 2538 2539 if (chip->info->ops->set_egress_port) { 2540 err = chip->info->ops->set_egress_port(chip, 2541 MV88E6XXX_EGRESS_DIR_INGRESS, 2542 upstream_port); 2543 if (err) 2544 return err; 2545 2546 err = chip->info->ops->set_egress_port(chip, 2547 MV88E6XXX_EGRESS_DIR_EGRESS, 2548 upstream_port); 2549 if (err) 2550 return err; 2551 } 2552 } 2553 2554 return 0; 2555 } 2556 2557 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2558 { 2559 struct dsa_switch *ds = chip->ds; 2560 int err; 2561 u16 reg; 2562 2563 chip->ports[port].chip = chip; 2564 chip->ports[port].port = port; 2565 2566 /* MAC Forcing register: don't force link, speed, duplex or flow control 2567 * state to any particular values on physical ports, but force the CPU 2568 * port and all DSA ports to their maximum bandwidth and full duplex. 2569 */ 2570 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2571 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2572 SPEED_MAX, DUPLEX_FULL, 2573 PAUSE_OFF, 2574 PHY_INTERFACE_MODE_NA); 2575 else 2576 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2577 SPEED_UNFORCED, DUPLEX_UNFORCED, 2578 PAUSE_ON, 2579 PHY_INTERFACE_MODE_NA); 2580 if (err) 2581 return err; 2582 2583 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2584 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2585 * tunneling, determine priority by looking at 802.1p and IP 2586 * priority fields (IP prio has precedence), and set STP state 2587 * to Forwarding. 2588 * 2589 * If this is the CPU link, use DSA or EDSA tagging depending 2590 * on which tagging mode was configured. 2591 * 2592 * If this is a link to another switch, use DSA tagging mode. 2593 * 2594 * If this is the upstream port for this switch, enable 2595 * forwarding of unknown unicasts and multicasts. 2596 */ 2597 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2598 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2599 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2600 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2601 if (err) 2602 return err; 2603 2604 err = mv88e6xxx_setup_port_mode(chip, port); 2605 if (err) 2606 return err; 2607 2608 err = mv88e6xxx_setup_egress_floods(chip, port); 2609 if (err) 2610 return err; 2611 2612 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2613 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2614 * untagged frames on this port, do a destination address lookup on all 2615 * received packets as usual, disable ARP mirroring and don't send a 2616 * copy of all transmitted/received frames on this port to the CPU. 2617 */ 2618 err = mv88e6xxx_port_set_map_da(chip, port); 2619 if (err) 2620 return err; 2621 2622 err = mv88e6xxx_setup_upstream_port(chip, port); 2623 if (err) 2624 return err; 2625 2626 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2627 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2628 if (err) 2629 return err; 2630 2631 if (chip->info->ops->port_set_jumbo_size) { 2632 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2633 if (err) 2634 return err; 2635 } 2636 2637 /* Port Association Vector: when learning source addresses 2638 * of packets, add the address to the address database using 2639 * a port bitmap that has only the bit for this port set and 2640 * the other bits clear. 2641 */ 2642 reg = 1 << port; 2643 /* Disable learning for CPU port */ 2644 if (dsa_is_cpu_port(ds, port)) 2645 reg = 0; 2646 2647 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2648 reg); 2649 if (err) 2650 return err; 2651 2652 /* Egress rate control 2: disable egress rate control. */ 2653 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2654 0x0000); 2655 if (err) 2656 return err; 2657 2658 if (chip->info->ops->port_pause_limit) { 2659 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2660 if (err) 2661 return err; 2662 } 2663 2664 if (chip->info->ops->port_disable_learn_limit) { 2665 err = chip->info->ops->port_disable_learn_limit(chip, port); 2666 if (err) 2667 return err; 2668 } 2669 2670 if (chip->info->ops->port_disable_pri_override) { 2671 err = chip->info->ops->port_disable_pri_override(chip, port); 2672 if (err) 2673 return err; 2674 } 2675 2676 if (chip->info->ops->port_tag_remap) { 2677 err = chip->info->ops->port_tag_remap(chip, port); 2678 if (err) 2679 return err; 2680 } 2681 2682 if (chip->info->ops->port_egress_rate_limiting) { 2683 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2684 if (err) 2685 return err; 2686 } 2687 2688 if (chip->info->ops->port_setup_message_port) { 2689 err = chip->info->ops->port_setup_message_port(chip, port); 2690 if (err) 2691 return err; 2692 } 2693 2694 /* Port based VLAN map: give each port the same default address 2695 * database, and allow bidirectional communication between the 2696 * CPU and DSA port(s), and the other ports. 2697 */ 2698 err = mv88e6xxx_port_set_fid(chip, port, 0); 2699 if (err) 2700 return err; 2701 2702 err = mv88e6xxx_port_vlan_map(chip, port); 2703 if (err) 2704 return err; 2705 2706 /* Default VLAN ID and priority: don't set a default VLAN 2707 * ID, and set the default packet priority to zero. 2708 */ 2709 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2710 } 2711 2712 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 2713 { 2714 struct mv88e6xxx_chip *chip = ds->priv; 2715 2716 if (chip->info->ops->port_set_jumbo_size) 2717 return 10240; 2718 else if (chip->info->ops->set_max_frame_size) 2719 return 1632; 2720 return 1522; 2721 } 2722 2723 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 2724 { 2725 struct mv88e6xxx_chip *chip = ds->priv; 2726 int ret = 0; 2727 2728 mv88e6xxx_reg_lock(chip); 2729 if (chip->info->ops->port_set_jumbo_size) 2730 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 2731 else if (chip->info->ops->set_max_frame_size) 2732 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 2733 else 2734 if (new_mtu > 1522) 2735 ret = -EINVAL; 2736 mv88e6xxx_reg_unlock(chip); 2737 2738 return ret; 2739 } 2740 2741 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2742 struct phy_device *phydev) 2743 { 2744 struct mv88e6xxx_chip *chip = ds->priv; 2745 int err; 2746 2747 mv88e6xxx_reg_lock(chip); 2748 err = mv88e6xxx_serdes_power(chip, port, true); 2749 mv88e6xxx_reg_unlock(chip); 2750 2751 return err; 2752 } 2753 2754 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2755 { 2756 struct mv88e6xxx_chip *chip = ds->priv; 2757 2758 mv88e6xxx_reg_lock(chip); 2759 if (mv88e6xxx_serdes_power(chip, port, false)) 2760 dev_err(chip->dev, "failed to power off SERDES\n"); 2761 mv88e6xxx_reg_unlock(chip); 2762 } 2763 2764 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2765 unsigned int ageing_time) 2766 { 2767 struct mv88e6xxx_chip *chip = ds->priv; 2768 int err; 2769 2770 mv88e6xxx_reg_lock(chip); 2771 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2772 mv88e6xxx_reg_unlock(chip); 2773 2774 return err; 2775 } 2776 2777 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2778 { 2779 int err; 2780 2781 /* Initialize the statistics unit */ 2782 if (chip->info->ops->stats_set_histogram) { 2783 err = chip->info->ops->stats_set_histogram(chip); 2784 if (err) 2785 return err; 2786 } 2787 2788 return mv88e6xxx_g1_stats_clear(chip); 2789 } 2790 2791 /* Check if the errata has already been applied. */ 2792 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2793 { 2794 int port; 2795 int err; 2796 u16 val; 2797 2798 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2799 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 2800 if (err) { 2801 dev_err(chip->dev, 2802 "Error reading hidden register: %d\n", err); 2803 return false; 2804 } 2805 if (val != 0x01c0) 2806 return false; 2807 } 2808 2809 return true; 2810 } 2811 2812 /* The 6390 copper ports have an errata which require poking magic 2813 * values into undocumented hidden registers and then performing a 2814 * software reset. 2815 */ 2816 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2817 { 2818 int port; 2819 int err; 2820 2821 if (mv88e6390_setup_errata_applied(chip)) 2822 return 0; 2823 2824 /* Set the ports into blocking mode */ 2825 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2826 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2827 if (err) 2828 return err; 2829 } 2830 2831 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2832 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 2833 if (err) 2834 return err; 2835 } 2836 2837 return mv88e6xxx_software_reset(chip); 2838 } 2839 2840 enum mv88e6xxx_devlink_param_id { 2841 MV88E6XXX_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, 2842 MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH, 2843 }; 2844 2845 static int mv88e6xxx_devlink_param_get(struct dsa_switch *ds, u32 id, 2846 struct devlink_param_gset_ctx *ctx) 2847 { 2848 struct mv88e6xxx_chip *chip = ds->priv; 2849 int err; 2850 2851 mv88e6xxx_reg_lock(chip); 2852 2853 switch (id) { 2854 case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH: 2855 err = mv88e6xxx_atu_get_hash(chip, &ctx->val.vu8); 2856 break; 2857 default: 2858 err = -EOPNOTSUPP; 2859 break; 2860 } 2861 2862 mv88e6xxx_reg_unlock(chip); 2863 2864 return err; 2865 } 2866 2867 static int mv88e6xxx_devlink_param_set(struct dsa_switch *ds, u32 id, 2868 struct devlink_param_gset_ctx *ctx) 2869 { 2870 struct mv88e6xxx_chip *chip = ds->priv; 2871 int err; 2872 2873 mv88e6xxx_reg_lock(chip); 2874 2875 switch (id) { 2876 case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH: 2877 err = mv88e6xxx_atu_set_hash(chip, ctx->val.vu8); 2878 break; 2879 default: 2880 err = -EOPNOTSUPP; 2881 break; 2882 } 2883 2884 mv88e6xxx_reg_unlock(chip); 2885 2886 return err; 2887 } 2888 2889 static const struct devlink_param mv88e6xxx_devlink_params[] = { 2890 DSA_DEVLINK_PARAM_DRIVER(MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH, 2891 "ATU_hash", DEVLINK_PARAM_TYPE_U8, 2892 BIT(DEVLINK_PARAM_CMODE_RUNTIME)), 2893 }; 2894 2895 static int mv88e6xxx_setup_devlink_params(struct dsa_switch *ds) 2896 { 2897 return dsa_devlink_params_register(ds, mv88e6xxx_devlink_params, 2898 ARRAY_SIZE(mv88e6xxx_devlink_params)); 2899 } 2900 2901 static void mv88e6xxx_teardown_devlink_params(struct dsa_switch *ds) 2902 { 2903 dsa_devlink_params_unregister(ds, mv88e6xxx_devlink_params, 2904 ARRAY_SIZE(mv88e6xxx_devlink_params)); 2905 } 2906 2907 enum mv88e6xxx_devlink_resource_id { 2908 MV88E6XXX_RESOURCE_ID_ATU, 2909 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 2910 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 2911 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 2912 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 2913 }; 2914 2915 static u64 mv88e6xxx_devlink_atu_bin_get(struct mv88e6xxx_chip *chip, 2916 u16 bin) 2917 { 2918 u16 occupancy = 0; 2919 int err; 2920 2921 mv88e6xxx_reg_lock(chip); 2922 2923 err = mv88e6xxx_g2_atu_stats_set(chip, MV88E6XXX_G2_ATU_STATS_MODE_ALL, 2924 bin); 2925 if (err) { 2926 dev_err(chip->dev, "failed to set ATU stats kind/bin\n"); 2927 goto unlock; 2928 } 2929 2930 err = mv88e6xxx_g1_atu_get_next(chip, 0); 2931 if (err) { 2932 dev_err(chip->dev, "failed to perform ATU get next\n"); 2933 goto unlock; 2934 } 2935 2936 err = mv88e6xxx_g2_atu_stats_get(chip, &occupancy); 2937 if (err) { 2938 dev_err(chip->dev, "failed to get ATU stats\n"); 2939 goto unlock; 2940 } 2941 2942 occupancy &= MV88E6XXX_G2_ATU_STATS_MASK; 2943 2944 unlock: 2945 mv88e6xxx_reg_unlock(chip); 2946 2947 return occupancy; 2948 } 2949 2950 static u64 mv88e6xxx_devlink_atu_bin_0_get(void *priv) 2951 { 2952 struct mv88e6xxx_chip *chip = priv; 2953 2954 return mv88e6xxx_devlink_atu_bin_get(chip, 2955 MV88E6XXX_G2_ATU_STATS_BIN_0); 2956 } 2957 2958 static u64 mv88e6xxx_devlink_atu_bin_1_get(void *priv) 2959 { 2960 struct mv88e6xxx_chip *chip = priv; 2961 2962 return mv88e6xxx_devlink_atu_bin_get(chip, 2963 MV88E6XXX_G2_ATU_STATS_BIN_1); 2964 } 2965 2966 static u64 mv88e6xxx_devlink_atu_bin_2_get(void *priv) 2967 { 2968 struct mv88e6xxx_chip *chip = priv; 2969 2970 return mv88e6xxx_devlink_atu_bin_get(chip, 2971 MV88E6XXX_G2_ATU_STATS_BIN_2); 2972 } 2973 2974 static u64 mv88e6xxx_devlink_atu_bin_3_get(void *priv) 2975 { 2976 struct mv88e6xxx_chip *chip = priv; 2977 2978 return mv88e6xxx_devlink_atu_bin_get(chip, 2979 MV88E6XXX_G2_ATU_STATS_BIN_3); 2980 } 2981 2982 static u64 mv88e6xxx_devlink_atu_get(void *priv) 2983 { 2984 return mv88e6xxx_devlink_atu_bin_0_get(priv) + 2985 mv88e6xxx_devlink_atu_bin_1_get(priv) + 2986 mv88e6xxx_devlink_atu_bin_2_get(priv) + 2987 mv88e6xxx_devlink_atu_bin_3_get(priv); 2988 } 2989 2990 static int mv88e6xxx_setup_devlink_resources(struct dsa_switch *ds) 2991 { 2992 struct devlink_resource_size_params size_params; 2993 struct mv88e6xxx_chip *chip = ds->priv; 2994 int err; 2995 2996 devlink_resource_size_params_init(&size_params, 2997 mv88e6xxx_num_macs(chip), 2998 mv88e6xxx_num_macs(chip), 2999 1, DEVLINK_RESOURCE_UNIT_ENTRY); 3000 3001 err = dsa_devlink_resource_register(ds, "ATU", 3002 mv88e6xxx_num_macs(chip), 3003 MV88E6XXX_RESOURCE_ID_ATU, 3004 DEVLINK_RESOURCE_ID_PARENT_TOP, 3005 &size_params); 3006 if (err) 3007 goto out; 3008 3009 devlink_resource_size_params_init(&size_params, 3010 mv88e6xxx_num_macs(chip) / 4, 3011 mv88e6xxx_num_macs(chip) / 4, 3012 1, DEVLINK_RESOURCE_UNIT_ENTRY); 3013 3014 err = dsa_devlink_resource_register(ds, "ATU_bin_0", 3015 mv88e6xxx_num_macs(chip) / 4, 3016 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 3017 MV88E6XXX_RESOURCE_ID_ATU, 3018 &size_params); 3019 if (err) 3020 goto out; 3021 3022 err = dsa_devlink_resource_register(ds, "ATU_bin_1", 3023 mv88e6xxx_num_macs(chip) / 4, 3024 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 3025 MV88E6XXX_RESOURCE_ID_ATU, 3026 &size_params); 3027 if (err) 3028 goto out; 3029 3030 err = dsa_devlink_resource_register(ds, "ATU_bin_2", 3031 mv88e6xxx_num_macs(chip) / 4, 3032 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 3033 MV88E6XXX_RESOURCE_ID_ATU, 3034 &size_params); 3035 if (err) 3036 goto out; 3037 3038 err = dsa_devlink_resource_register(ds, "ATU_bin_3", 3039 mv88e6xxx_num_macs(chip) / 4, 3040 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 3041 MV88E6XXX_RESOURCE_ID_ATU, 3042 &size_params); 3043 if (err) 3044 goto out; 3045 3046 dsa_devlink_resource_occ_get_register(ds, 3047 MV88E6XXX_RESOURCE_ID_ATU, 3048 mv88e6xxx_devlink_atu_get, 3049 chip); 3050 3051 dsa_devlink_resource_occ_get_register(ds, 3052 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 3053 mv88e6xxx_devlink_atu_bin_0_get, 3054 chip); 3055 3056 dsa_devlink_resource_occ_get_register(ds, 3057 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 3058 mv88e6xxx_devlink_atu_bin_1_get, 3059 chip); 3060 3061 dsa_devlink_resource_occ_get_register(ds, 3062 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 3063 mv88e6xxx_devlink_atu_bin_2_get, 3064 chip); 3065 3066 dsa_devlink_resource_occ_get_register(ds, 3067 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 3068 mv88e6xxx_devlink_atu_bin_3_get, 3069 chip); 3070 3071 return 0; 3072 3073 out: 3074 dsa_devlink_resources_unregister(ds); 3075 return err; 3076 } 3077 3078 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3079 { 3080 mv88e6xxx_teardown_devlink_params(ds); 3081 dsa_devlink_resources_unregister(ds); 3082 } 3083 3084 static int mv88e6xxx_setup(struct dsa_switch *ds) 3085 { 3086 struct mv88e6xxx_chip *chip = ds->priv; 3087 u8 cmode; 3088 int err; 3089 int i; 3090 3091 chip->ds = ds; 3092 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3093 3094 mv88e6xxx_reg_lock(chip); 3095 3096 if (chip->info->ops->setup_errata) { 3097 err = chip->info->ops->setup_errata(chip); 3098 if (err) 3099 goto unlock; 3100 } 3101 3102 /* Cache the cmode of each port. */ 3103 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3104 if (chip->info->ops->port_get_cmode) { 3105 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3106 if (err) 3107 goto unlock; 3108 3109 chip->ports[i].cmode = cmode; 3110 } 3111 } 3112 3113 /* Setup Switch Port Registers */ 3114 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3115 if (dsa_is_unused_port(ds, i)) 3116 continue; 3117 3118 /* Prevent the use of an invalid port. */ 3119 if (mv88e6xxx_is_invalid_port(chip, i)) { 3120 dev_err(chip->dev, "port %d is invalid\n", i); 3121 err = -EINVAL; 3122 goto unlock; 3123 } 3124 3125 err = mv88e6xxx_setup_port(chip, i); 3126 if (err) 3127 goto unlock; 3128 } 3129 3130 err = mv88e6xxx_irl_setup(chip); 3131 if (err) 3132 goto unlock; 3133 3134 err = mv88e6xxx_mac_setup(chip); 3135 if (err) 3136 goto unlock; 3137 3138 err = mv88e6xxx_phy_setup(chip); 3139 if (err) 3140 goto unlock; 3141 3142 err = mv88e6xxx_vtu_setup(chip); 3143 if (err) 3144 goto unlock; 3145 3146 err = mv88e6xxx_pvt_setup(chip); 3147 if (err) 3148 goto unlock; 3149 3150 err = mv88e6xxx_atu_setup(chip); 3151 if (err) 3152 goto unlock; 3153 3154 err = mv88e6xxx_broadcast_setup(chip, 0); 3155 if (err) 3156 goto unlock; 3157 3158 err = mv88e6xxx_pot_setup(chip); 3159 if (err) 3160 goto unlock; 3161 3162 err = mv88e6xxx_rmu_setup(chip); 3163 if (err) 3164 goto unlock; 3165 3166 err = mv88e6xxx_rsvd2cpu_setup(chip); 3167 if (err) 3168 goto unlock; 3169 3170 err = mv88e6xxx_trunk_setup(chip); 3171 if (err) 3172 goto unlock; 3173 3174 err = mv88e6xxx_devmap_setup(chip); 3175 if (err) 3176 goto unlock; 3177 3178 err = mv88e6xxx_pri_setup(chip); 3179 if (err) 3180 goto unlock; 3181 3182 /* Setup PTP Hardware Clock and timestamping */ 3183 if (chip->info->ptp_support) { 3184 err = mv88e6xxx_ptp_setup(chip); 3185 if (err) 3186 goto unlock; 3187 3188 err = mv88e6xxx_hwtstamp_setup(chip); 3189 if (err) 3190 goto unlock; 3191 } 3192 3193 err = mv88e6xxx_stats_setup(chip); 3194 if (err) 3195 goto unlock; 3196 3197 unlock: 3198 mv88e6xxx_reg_unlock(chip); 3199 3200 if (err) 3201 return err; 3202 3203 /* Have to be called without holding the register lock, since 3204 * they take the devlink lock, and we later take the locks in 3205 * the reverse order when getting/setting parameters or 3206 * resource occupancy. 3207 */ 3208 err = mv88e6xxx_setup_devlink_resources(ds); 3209 if (err) 3210 return err; 3211 3212 err = mv88e6xxx_setup_devlink_params(ds); 3213 if (err) 3214 dsa_devlink_resources_unregister(ds); 3215 3216 return err; 3217 } 3218 3219 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3220 { 3221 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3222 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3223 u16 val; 3224 int err; 3225 3226 if (!chip->info->ops->phy_read) 3227 return -EOPNOTSUPP; 3228 3229 mv88e6xxx_reg_lock(chip); 3230 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3231 mv88e6xxx_reg_unlock(chip); 3232 3233 if (reg == MII_PHYSID2) { 3234 /* Some internal PHYs don't have a model number. */ 3235 if (chip->info->family != MV88E6XXX_FAMILY_6165) 3236 /* Then there is the 6165 family. It gets is 3237 * PHYs correct. But it can also have two 3238 * SERDES interfaces in the PHY address 3239 * space. And these don't have a model 3240 * number. But they are not PHYs, so we don't 3241 * want to give them something a PHY driver 3242 * will recognise. 3243 * 3244 * Use the mv88e6390 family model number 3245 * instead, for anything which really could be 3246 * a PHY, 3247 */ 3248 if (!(val & 0x3f0)) 3249 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 3250 } 3251 3252 return err ? err : val; 3253 } 3254 3255 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3256 { 3257 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3258 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3259 int err; 3260 3261 if (!chip->info->ops->phy_write) 3262 return -EOPNOTSUPP; 3263 3264 mv88e6xxx_reg_lock(chip); 3265 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3266 mv88e6xxx_reg_unlock(chip); 3267 3268 return err; 3269 } 3270 3271 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3272 struct device_node *np, 3273 bool external) 3274 { 3275 static int index; 3276 struct mv88e6xxx_mdio_bus *mdio_bus; 3277 struct mii_bus *bus; 3278 int err; 3279 3280 if (external) { 3281 mv88e6xxx_reg_lock(chip); 3282 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3283 mv88e6xxx_reg_unlock(chip); 3284 3285 if (err) 3286 return err; 3287 } 3288 3289 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3290 if (!bus) 3291 return -ENOMEM; 3292 3293 mdio_bus = bus->priv; 3294 mdio_bus->bus = bus; 3295 mdio_bus->chip = chip; 3296 INIT_LIST_HEAD(&mdio_bus->list); 3297 mdio_bus->external = external; 3298 3299 if (np) { 3300 bus->name = np->full_name; 3301 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3302 } else { 3303 bus->name = "mv88e6xxx SMI"; 3304 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3305 } 3306 3307 bus->read = mv88e6xxx_mdio_read; 3308 bus->write = mv88e6xxx_mdio_write; 3309 bus->parent = chip->dev; 3310 3311 if (!external) { 3312 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3313 if (err) 3314 return err; 3315 } 3316 3317 err = of_mdiobus_register(bus, np); 3318 if (err) { 3319 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3320 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3321 return err; 3322 } 3323 3324 if (external) 3325 list_add_tail(&mdio_bus->list, &chip->mdios); 3326 else 3327 list_add(&mdio_bus->list, &chip->mdios); 3328 3329 return 0; 3330 } 3331 3332 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 3333 { .compatible = "marvell,mv88e6xxx-mdio-external", 3334 .data = (void *)true }, 3335 { }, 3336 }; 3337 3338 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3339 3340 { 3341 struct mv88e6xxx_mdio_bus *mdio_bus; 3342 struct mii_bus *bus; 3343 3344 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3345 bus = mdio_bus->bus; 3346 3347 if (!mdio_bus->external) 3348 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3349 3350 mdiobus_unregister(bus); 3351 } 3352 } 3353 3354 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3355 struct device_node *np) 3356 { 3357 const struct of_device_id *match; 3358 struct device_node *child; 3359 int err; 3360 3361 /* Always register one mdio bus for the internal/default mdio 3362 * bus. This maybe represented in the device tree, but is 3363 * optional. 3364 */ 3365 child = of_get_child_by_name(np, "mdio"); 3366 err = mv88e6xxx_mdio_register(chip, child, false); 3367 if (err) 3368 return err; 3369 3370 /* Walk the device tree, and see if there are any other nodes 3371 * which say they are compatible with the external mdio 3372 * bus. 3373 */ 3374 for_each_available_child_of_node(np, child) { 3375 match = of_match_node(mv88e6xxx_mdio_external_match, child); 3376 if (match) { 3377 err = mv88e6xxx_mdio_register(chip, child, true); 3378 if (err) { 3379 mv88e6xxx_mdios_unregister(chip); 3380 of_node_put(child); 3381 return err; 3382 } 3383 } 3384 } 3385 3386 return 0; 3387 } 3388 3389 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3390 { 3391 struct mv88e6xxx_chip *chip = ds->priv; 3392 3393 return chip->eeprom_len; 3394 } 3395 3396 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3397 struct ethtool_eeprom *eeprom, u8 *data) 3398 { 3399 struct mv88e6xxx_chip *chip = ds->priv; 3400 int err; 3401 3402 if (!chip->info->ops->get_eeprom) 3403 return -EOPNOTSUPP; 3404 3405 mv88e6xxx_reg_lock(chip); 3406 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3407 mv88e6xxx_reg_unlock(chip); 3408 3409 if (err) 3410 return err; 3411 3412 eeprom->magic = 0xc3ec4951; 3413 3414 return 0; 3415 } 3416 3417 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3418 struct ethtool_eeprom *eeprom, u8 *data) 3419 { 3420 struct mv88e6xxx_chip *chip = ds->priv; 3421 int err; 3422 3423 if (!chip->info->ops->set_eeprom) 3424 return -EOPNOTSUPP; 3425 3426 if (eeprom->magic != 0xc3ec4951) 3427 return -EINVAL; 3428 3429 mv88e6xxx_reg_lock(chip); 3430 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3431 mv88e6xxx_reg_unlock(chip); 3432 3433 return err; 3434 } 3435 3436 static const struct mv88e6xxx_ops mv88e6085_ops = { 3437 /* MV88E6XXX_FAMILY_6097 */ 3438 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3439 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3440 .irl_init_all = mv88e6352_g2_irl_init_all, 3441 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3442 .phy_read = mv88e6185_phy_ppu_read, 3443 .phy_write = mv88e6185_phy_ppu_write, 3444 .port_set_link = mv88e6xxx_port_set_link, 3445 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3446 .port_tag_remap = mv88e6095_port_tag_remap, 3447 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3448 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3449 .port_set_ether_type = mv88e6351_port_set_ether_type, 3450 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3451 .port_pause_limit = mv88e6097_port_pause_limit, 3452 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3453 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3454 .port_get_cmode = mv88e6185_port_get_cmode, 3455 .port_setup_message_port = mv88e6xxx_setup_message_port, 3456 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3457 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3458 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3459 .stats_get_strings = mv88e6095_stats_get_strings, 3460 .stats_get_stats = mv88e6095_stats_get_stats, 3461 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3462 .set_egress_port = mv88e6095_g1_set_egress_port, 3463 .watchdog_ops = &mv88e6097_watchdog_ops, 3464 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3465 .pot_clear = mv88e6xxx_g2_pot_clear, 3466 .ppu_enable = mv88e6185_g1_ppu_enable, 3467 .ppu_disable = mv88e6185_g1_ppu_disable, 3468 .reset = mv88e6185_g1_reset, 3469 .rmu_disable = mv88e6085_g1_rmu_disable, 3470 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3471 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3472 .phylink_validate = mv88e6185_phylink_validate, 3473 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3474 }; 3475 3476 static const struct mv88e6xxx_ops mv88e6095_ops = { 3477 /* MV88E6XXX_FAMILY_6095 */ 3478 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3479 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3480 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3481 .phy_read = mv88e6185_phy_ppu_read, 3482 .phy_write = mv88e6185_phy_ppu_write, 3483 .port_set_link = mv88e6xxx_port_set_link, 3484 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3485 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3486 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3487 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3488 .port_get_cmode = mv88e6185_port_get_cmode, 3489 .port_setup_message_port = mv88e6xxx_setup_message_port, 3490 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3491 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3492 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3493 .stats_get_strings = mv88e6095_stats_get_strings, 3494 .stats_get_stats = mv88e6095_stats_get_stats, 3495 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3496 .ppu_enable = mv88e6185_g1_ppu_enable, 3497 .ppu_disable = mv88e6185_g1_ppu_disable, 3498 .reset = mv88e6185_g1_reset, 3499 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3500 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3501 .phylink_validate = mv88e6185_phylink_validate, 3502 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3503 }; 3504 3505 static const struct mv88e6xxx_ops mv88e6097_ops = { 3506 /* MV88E6XXX_FAMILY_6097 */ 3507 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3508 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3509 .irl_init_all = mv88e6352_g2_irl_init_all, 3510 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3511 .phy_read = mv88e6xxx_g2_smi_phy_read, 3512 .phy_write = mv88e6xxx_g2_smi_phy_write, 3513 .port_set_link = mv88e6xxx_port_set_link, 3514 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3515 .port_tag_remap = mv88e6095_port_tag_remap, 3516 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3517 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3518 .port_set_ether_type = mv88e6351_port_set_ether_type, 3519 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3520 .port_pause_limit = mv88e6097_port_pause_limit, 3521 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3522 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3523 .port_get_cmode = mv88e6185_port_get_cmode, 3524 .port_setup_message_port = mv88e6xxx_setup_message_port, 3525 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3526 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3527 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3528 .stats_get_strings = mv88e6095_stats_get_strings, 3529 .stats_get_stats = mv88e6095_stats_get_stats, 3530 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3531 .set_egress_port = mv88e6095_g1_set_egress_port, 3532 .watchdog_ops = &mv88e6097_watchdog_ops, 3533 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3534 .pot_clear = mv88e6xxx_g2_pot_clear, 3535 .reset = mv88e6352_g1_reset, 3536 .rmu_disable = mv88e6085_g1_rmu_disable, 3537 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3538 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3539 .phylink_validate = mv88e6185_phylink_validate, 3540 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3541 }; 3542 3543 static const struct mv88e6xxx_ops mv88e6123_ops = { 3544 /* MV88E6XXX_FAMILY_6165 */ 3545 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3546 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3547 .irl_init_all = mv88e6352_g2_irl_init_all, 3548 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3549 .phy_read = mv88e6xxx_g2_smi_phy_read, 3550 .phy_write = mv88e6xxx_g2_smi_phy_write, 3551 .port_set_link = mv88e6xxx_port_set_link, 3552 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3553 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3554 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3555 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3556 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3557 .port_get_cmode = mv88e6185_port_get_cmode, 3558 .port_setup_message_port = mv88e6xxx_setup_message_port, 3559 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3560 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3561 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3562 .stats_get_strings = mv88e6095_stats_get_strings, 3563 .stats_get_stats = mv88e6095_stats_get_stats, 3564 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3565 .set_egress_port = mv88e6095_g1_set_egress_port, 3566 .watchdog_ops = &mv88e6097_watchdog_ops, 3567 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3568 .pot_clear = mv88e6xxx_g2_pot_clear, 3569 .reset = mv88e6352_g1_reset, 3570 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3571 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3572 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3573 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3574 .phylink_validate = mv88e6185_phylink_validate, 3575 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3576 }; 3577 3578 static const struct mv88e6xxx_ops mv88e6131_ops = { 3579 /* MV88E6XXX_FAMILY_6185 */ 3580 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3581 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3582 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3583 .phy_read = mv88e6185_phy_ppu_read, 3584 .phy_write = mv88e6185_phy_ppu_write, 3585 .port_set_link = mv88e6xxx_port_set_link, 3586 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3587 .port_tag_remap = mv88e6095_port_tag_remap, 3588 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3589 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3590 .port_set_ether_type = mv88e6351_port_set_ether_type, 3591 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3592 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3593 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3594 .port_pause_limit = mv88e6097_port_pause_limit, 3595 .port_set_pause = mv88e6185_port_set_pause, 3596 .port_get_cmode = mv88e6185_port_get_cmode, 3597 .port_setup_message_port = mv88e6xxx_setup_message_port, 3598 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3599 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3600 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3601 .stats_get_strings = mv88e6095_stats_get_strings, 3602 .stats_get_stats = mv88e6095_stats_get_stats, 3603 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3604 .set_egress_port = mv88e6095_g1_set_egress_port, 3605 .watchdog_ops = &mv88e6097_watchdog_ops, 3606 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3607 .ppu_enable = mv88e6185_g1_ppu_enable, 3608 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3609 .ppu_disable = mv88e6185_g1_ppu_disable, 3610 .reset = mv88e6185_g1_reset, 3611 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3612 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3613 .phylink_validate = mv88e6185_phylink_validate, 3614 }; 3615 3616 static const struct mv88e6xxx_ops mv88e6141_ops = { 3617 /* MV88E6XXX_FAMILY_6341 */ 3618 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3619 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3620 .irl_init_all = mv88e6352_g2_irl_init_all, 3621 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3622 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3623 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3624 .phy_read = mv88e6xxx_g2_smi_phy_read, 3625 .phy_write = mv88e6xxx_g2_smi_phy_write, 3626 .port_set_link = mv88e6xxx_port_set_link, 3627 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3628 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3629 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3630 .port_tag_remap = mv88e6095_port_tag_remap, 3631 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3632 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3633 .port_set_ether_type = mv88e6351_port_set_ether_type, 3634 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3635 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3636 .port_pause_limit = mv88e6097_port_pause_limit, 3637 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3638 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3639 .port_get_cmode = mv88e6352_port_get_cmode, 3640 .port_set_cmode = mv88e6341_port_set_cmode, 3641 .port_setup_message_port = mv88e6xxx_setup_message_port, 3642 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3643 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3644 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3645 .stats_get_strings = mv88e6320_stats_get_strings, 3646 .stats_get_stats = mv88e6390_stats_get_stats, 3647 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3648 .set_egress_port = mv88e6390_g1_set_egress_port, 3649 .watchdog_ops = &mv88e6390_watchdog_ops, 3650 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3651 .pot_clear = mv88e6xxx_g2_pot_clear, 3652 .reset = mv88e6352_g1_reset, 3653 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3654 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3655 .serdes_power = mv88e6390_serdes_power, 3656 .serdes_get_lane = mv88e6341_serdes_get_lane, 3657 /* Check status register pause & lpa register */ 3658 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3659 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3660 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3661 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3662 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3663 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3664 .serdes_irq_status = mv88e6390_serdes_irq_status, 3665 .gpio_ops = &mv88e6352_gpio_ops, 3666 .phylink_validate = mv88e6341_phylink_validate, 3667 }; 3668 3669 static const struct mv88e6xxx_ops mv88e6161_ops = { 3670 /* MV88E6XXX_FAMILY_6165 */ 3671 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3672 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3673 .irl_init_all = mv88e6352_g2_irl_init_all, 3674 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3675 .phy_read = mv88e6xxx_g2_smi_phy_read, 3676 .phy_write = mv88e6xxx_g2_smi_phy_write, 3677 .port_set_link = mv88e6xxx_port_set_link, 3678 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3679 .port_tag_remap = mv88e6095_port_tag_remap, 3680 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3681 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3682 .port_set_ether_type = mv88e6351_port_set_ether_type, 3683 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3684 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3685 .port_pause_limit = mv88e6097_port_pause_limit, 3686 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3687 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3688 .port_get_cmode = mv88e6185_port_get_cmode, 3689 .port_setup_message_port = mv88e6xxx_setup_message_port, 3690 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3691 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3692 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3693 .stats_get_strings = mv88e6095_stats_get_strings, 3694 .stats_get_stats = mv88e6095_stats_get_stats, 3695 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3696 .set_egress_port = mv88e6095_g1_set_egress_port, 3697 .watchdog_ops = &mv88e6097_watchdog_ops, 3698 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3699 .pot_clear = mv88e6xxx_g2_pot_clear, 3700 .reset = mv88e6352_g1_reset, 3701 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3702 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3703 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3704 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3705 .avb_ops = &mv88e6165_avb_ops, 3706 .ptp_ops = &mv88e6165_ptp_ops, 3707 .phylink_validate = mv88e6185_phylink_validate, 3708 }; 3709 3710 static const struct mv88e6xxx_ops mv88e6165_ops = { 3711 /* MV88E6XXX_FAMILY_6165 */ 3712 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3713 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3714 .irl_init_all = mv88e6352_g2_irl_init_all, 3715 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3716 .phy_read = mv88e6165_phy_read, 3717 .phy_write = mv88e6165_phy_write, 3718 .port_set_link = mv88e6xxx_port_set_link, 3719 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3720 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3721 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3722 .port_get_cmode = mv88e6185_port_get_cmode, 3723 .port_setup_message_port = mv88e6xxx_setup_message_port, 3724 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3725 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3726 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3727 .stats_get_strings = mv88e6095_stats_get_strings, 3728 .stats_get_stats = mv88e6095_stats_get_stats, 3729 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3730 .set_egress_port = mv88e6095_g1_set_egress_port, 3731 .watchdog_ops = &mv88e6097_watchdog_ops, 3732 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3733 .pot_clear = mv88e6xxx_g2_pot_clear, 3734 .reset = mv88e6352_g1_reset, 3735 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3736 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3737 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3738 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3739 .avb_ops = &mv88e6165_avb_ops, 3740 .ptp_ops = &mv88e6165_ptp_ops, 3741 .phylink_validate = mv88e6185_phylink_validate, 3742 }; 3743 3744 static const struct mv88e6xxx_ops mv88e6171_ops = { 3745 /* MV88E6XXX_FAMILY_6351 */ 3746 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3747 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3748 .irl_init_all = mv88e6352_g2_irl_init_all, 3749 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3750 .phy_read = mv88e6xxx_g2_smi_phy_read, 3751 .phy_write = mv88e6xxx_g2_smi_phy_write, 3752 .port_set_link = mv88e6xxx_port_set_link, 3753 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3754 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3755 .port_tag_remap = mv88e6095_port_tag_remap, 3756 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3757 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3758 .port_set_ether_type = mv88e6351_port_set_ether_type, 3759 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3760 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3761 .port_pause_limit = mv88e6097_port_pause_limit, 3762 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3763 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3764 .port_get_cmode = mv88e6352_port_get_cmode, 3765 .port_setup_message_port = mv88e6xxx_setup_message_port, 3766 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3767 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3768 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3769 .stats_get_strings = mv88e6095_stats_get_strings, 3770 .stats_get_stats = mv88e6095_stats_get_stats, 3771 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3772 .set_egress_port = mv88e6095_g1_set_egress_port, 3773 .watchdog_ops = &mv88e6097_watchdog_ops, 3774 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3775 .pot_clear = mv88e6xxx_g2_pot_clear, 3776 .reset = mv88e6352_g1_reset, 3777 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3778 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3779 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3780 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3781 .phylink_validate = mv88e6185_phylink_validate, 3782 }; 3783 3784 static const struct mv88e6xxx_ops mv88e6172_ops = { 3785 /* MV88E6XXX_FAMILY_6352 */ 3786 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3787 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3788 .irl_init_all = mv88e6352_g2_irl_init_all, 3789 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3790 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3791 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3792 .phy_read = mv88e6xxx_g2_smi_phy_read, 3793 .phy_write = mv88e6xxx_g2_smi_phy_write, 3794 .port_set_link = mv88e6xxx_port_set_link, 3795 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3796 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3797 .port_tag_remap = mv88e6095_port_tag_remap, 3798 .port_set_policy = mv88e6352_port_set_policy, 3799 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3800 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3801 .port_set_ether_type = mv88e6351_port_set_ether_type, 3802 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3803 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3804 .port_pause_limit = mv88e6097_port_pause_limit, 3805 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3806 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3807 .port_get_cmode = mv88e6352_port_get_cmode, 3808 .port_setup_message_port = mv88e6xxx_setup_message_port, 3809 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3810 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3811 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3812 .stats_get_strings = mv88e6095_stats_get_strings, 3813 .stats_get_stats = mv88e6095_stats_get_stats, 3814 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3815 .set_egress_port = mv88e6095_g1_set_egress_port, 3816 .watchdog_ops = &mv88e6097_watchdog_ops, 3817 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3818 .pot_clear = mv88e6xxx_g2_pot_clear, 3819 .reset = mv88e6352_g1_reset, 3820 .rmu_disable = mv88e6352_g1_rmu_disable, 3821 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3822 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3823 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3824 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3825 .serdes_get_lane = mv88e6352_serdes_get_lane, 3826 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3827 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3828 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3829 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3830 .serdes_power = mv88e6352_serdes_power, 3831 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3832 .serdes_get_regs = mv88e6352_serdes_get_regs, 3833 .gpio_ops = &mv88e6352_gpio_ops, 3834 .phylink_validate = mv88e6352_phylink_validate, 3835 }; 3836 3837 static const struct mv88e6xxx_ops mv88e6175_ops = { 3838 /* MV88E6XXX_FAMILY_6351 */ 3839 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3840 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3841 .irl_init_all = mv88e6352_g2_irl_init_all, 3842 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3843 .phy_read = mv88e6xxx_g2_smi_phy_read, 3844 .phy_write = mv88e6xxx_g2_smi_phy_write, 3845 .port_set_link = mv88e6xxx_port_set_link, 3846 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3847 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3848 .port_tag_remap = mv88e6095_port_tag_remap, 3849 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3850 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3851 .port_set_ether_type = mv88e6351_port_set_ether_type, 3852 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3853 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3854 .port_pause_limit = mv88e6097_port_pause_limit, 3855 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3856 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3857 .port_get_cmode = mv88e6352_port_get_cmode, 3858 .port_setup_message_port = mv88e6xxx_setup_message_port, 3859 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3860 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3861 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3862 .stats_get_strings = mv88e6095_stats_get_strings, 3863 .stats_get_stats = mv88e6095_stats_get_stats, 3864 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3865 .set_egress_port = mv88e6095_g1_set_egress_port, 3866 .watchdog_ops = &mv88e6097_watchdog_ops, 3867 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3868 .pot_clear = mv88e6xxx_g2_pot_clear, 3869 .reset = mv88e6352_g1_reset, 3870 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3871 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3872 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3873 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3874 .phylink_validate = mv88e6185_phylink_validate, 3875 }; 3876 3877 static const struct mv88e6xxx_ops mv88e6176_ops = { 3878 /* MV88E6XXX_FAMILY_6352 */ 3879 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3880 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3881 .irl_init_all = mv88e6352_g2_irl_init_all, 3882 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3883 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3884 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3885 .phy_read = mv88e6xxx_g2_smi_phy_read, 3886 .phy_write = mv88e6xxx_g2_smi_phy_write, 3887 .port_set_link = mv88e6xxx_port_set_link, 3888 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3889 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3890 .port_tag_remap = mv88e6095_port_tag_remap, 3891 .port_set_policy = mv88e6352_port_set_policy, 3892 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3893 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3894 .port_set_ether_type = mv88e6351_port_set_ether_type, 3895 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3896 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3897 .port_pause_limit = mv88e6097_port_pause_limit, 3898 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3899 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3900 .port_get_cmode = mv88e6352_port_get_cmode, 3901 .port_setup_message_port = mv88e6xxx_setup_message_port, 3902 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3903 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3904 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3905 .stats_get_strings = mv88e6095_stats_get_strings, 3906 .stats_get_stats = mv88e6095_stats_get_stats, 3907 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3908 .set_egress_port = mv88e6095_g1_set_egress_port, 3909 .watchdog_ops = &mv88e6097_watchdog_ops, 3910 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3911 .pot_clear = mv88e6xxx_g2_pot_clear, 3912 .reset = mv88e6352_g1_reset, 3913 .rmu_disable = mv88e6352_g1_rmu_disable, 3914 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3915 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3916 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3917 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3918 .serdes_get_lane = mv88e6352_serdes_get_lane, 3919 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3920 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3921 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3922 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3923 .serdes_power = mv88e6352_serdes_power, 3924 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3925 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3926 .serdes_irq_status = mv88e6352_serdes_irq_status, 3927 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3928 .serdes_get_regs = mv88e6352_serdes_get_regs, 3929 .gpio_ops = &mv88e6352_gpio_ops, 3930 .phylink_validate = mv88e6352_phylink_validate, 3931 }; 3932 3933 static const struct mv88e6xxx_ops mv88e6185_ops = { 3934 /* MV88E6XXX_FAMILY_6185 */ 3935 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3936 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3937 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3938 .phy_read = mv88e6185_phy_ppu_read, 3939 .phy_write = mv88e6185_phy_ppu_write, 3940 .port_set_link = mv88e6xxx_port_set_link, 3941 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3942 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3943 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3944 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3945 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3946 .port_set_pause = mv88e6185_port_set_pause, 3947 .port_get_cmode = mv88e6185_port_get_cmode, 3948 .port_setup_message_port = mv88e6xxx_setup_message_port, 3949 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3950 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3951 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3952 .stats_get_strings = mv88e6095_stats_get_strings, 3953 .stats_get_stats = mv88e6095_stats_get_stats, 3954 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3955 .set_egress_port = mv88e6095_g1_set_egress_port, 3956 .watchdog_ops = &mv88e6097_watchdog_ops, 3957 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3958 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3959 .ppu_enable = mv88e6185_g1_ppu_enable, 3960 .ppu_disable = mv88e6185_g1_ppu_disable, 3961 .reset = mv88e6185_g1_reset, 3962 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3963 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3964 .phylink_validate = mv88e6185_phylink_validate, 3965 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3966 }; 3967 3968 static const struct mv88e6xxx_ops mv88e6190_ops = { 3969 /* MV88E6XXX_FAMILY_6390 */ 3970 .setup_errata = mv88e6390_setup_errata, 3971 .irl_init_all = mv88e6390_g2_irl_init_all, 3972 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3973 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3974 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3975 .phy_read = mv88e6xxx_g2_smi_phy_read, 3976 .phy_write = mv88e6xxx_g2_smi_phy_write, 3977 .port_set_link = mv88e6xxx_port_set_link, 3978 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3979 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 3980 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3981 .port_tag_remap = mv88e6390_port_tag_remap, 3982 .port_set_policy = mv88e6352_port_set_policy, 3983 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3984 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3985 .port_set_ether_type = mv88e6351_port_set_ether_type, 3986 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3987 .port_pause_limit = mv88e6390_port_pause_limit, 3988 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3989 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3990 .port_get_cmode = mv88e6352_port_get_cmode, 3991 .port_set_cmode = mv88e6390_port_set_cmode, 3992 .port_setup_message_port = mv88e6xxx_setup_message_port, 3993 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3994 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3995 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3996 .stats_get_strings = mv88e6320_stats_get_strings, 3997 .stats_get_stats = mv88e6390_stats_get_stats, 3998 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3999 .set_egress_port = mv88e6390_g1_set_egress_port, 4000 .watchdog_ops = &mv88e6390_watchdog_ops, 4001 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4002 .pot_clear = mv88e6xxx_g2_pot_clear, 4003 .reset = mv88e6352_g1_reset, 4004 .rmu_disable = mv88e6390_g1_rmu_disable, 4005 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4006 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4007 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4008 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4009 .serdes_power = mv88e6390_serdes_power, 4010 .serdes_get_lane = mv88e6390_serdes_get_lane, 4011 /* Check status register pause & lpa register */ 4012 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4013 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4014 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4015 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4016 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4017 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4018 .serdes_irq_status = mv88e6390_serdes_irq_status, 4019 .serdes_get_strings = mv88e6390_serdes_get_strings, 4020 .serdes_get_stats = mv88e6390_serdes_get_stats, 4021 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4022 .serdes_get_regs = mv88e6390_serdes_get_regs, 4023 .gpio_ops = &mv88e6352_gpio_ops, 4024 .phylink_validate = mv88e6390_phylink_validate, 4025 }; 4026 4027 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4028 /* MV88E6XXX_FAMILY_6390 */ 4029 .setup_errata = mv88e6390_setup_errata, 4030 .irl_init_all = mv88e6390_g2_irl_init_all, 4031 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4032 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4033 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4034 .phy_read = mv88e6xxx_g2_smi_phy_read, 4035 .phy_write = mv88e6xxx_g2_smi_phy_write, 4036 .port_set_link = mv88e6xxx_port_set_link, 4037 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4038 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4039 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4040 .port_tag_remap = mv88e6390_port_tag_remap, 4041 .port_set_policy = mv88e6352_port_set_policy, 4042 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4043 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4044 .port_set_ether_type = mv88e6351_port_set_ether_type, 4045 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4046 .port_pause_limit = mv88e6390_port_pause_limit, 4047 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4048 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4049 .port_get_cmode = mv88e6352_port_get_cmode, 4050 .port_set_cmode = mv88e6390x_port_set_cmode, 4051 .port_setup_message_port = mv88e6xxx_setup_message_port, 4052 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4053 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4054 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4055 .stats_get_strings = mv88e6320_stats_get_strings, 4056 .stats_get_stats = mv88e6390_stats_get_stats, 4057 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4058 .set_egress_port = mv88e6390_g1_set_egress_port, 4059 .watchdog_ops = &mv88e6390_watchdog_ops, 4060 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4061 .pot_clear = mv88e6xxx_g2_pot_clear, 4062 .reset = mv88e6352_g1_reset, 4063 .rmu_disable = mv88e6390_g1_rmu_disable, 4064 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4065 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4066 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4067 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4068 .serdes_power = mv88e6390_serdes_power, 4069 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4070 /* Check status register pause & lpa register */ 4071 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4072 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4073 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4074 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4075 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4076 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4077 .serdes_irq_status = mv88e6390_serdes_irq_status, 4078 .serdes_get_strings = mv88e6390_serdes_get_strings, 4079 .serdes_get_stats = mv88e6390_serdes_get_stats, 4080 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4081 .serdes_get_regs = mv88e6390_serdes_get_regs, 4082 .gpio_ops = &mv88e6352_gpio_ops, 4083 .phylink_validate = mv88e6390x_phylink_validate, 4084 }; 4085 4086 static const struct mv88e6xxx_ops mv88e6191_ops = { 4087 /* MV88E6XXX_FAMILY_6390 */ 4088 .setup_errata = mv88e6390_setup_errata, 4089 .irl_init_all = mv88e6390_g2_irl_init_all, 4090 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4091 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4092 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4093 .phy_read = mv88e6xxx_g2_smi_phy_read, 4094 .phy_write = mv88e6xxx_g2_smi_phy_write, 4095 .port_set_link = mv88e6xxx_port_set_link, 4096 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4097 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4098 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4099 .port_tag_remap = mv88e6390_port_tag_remap, 4100 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4101 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4102 .port_set_ether_type = mv88e6351_port_set_ether_type, 4103 .port_pause_limit = mv88e6390_port_pause_limit, 4104 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4105 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4106 .port_get_cmode = mv88e6352_port_get_cmode, 4107 .port_set_cmode = mv88e6390_port_set_cmode, 4108 .port_setup_message_port = mv88e6xxx_setup_message_port, 4109 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4110 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4111 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4112 .stats_get_strings = mv88e6320_stats_get_strings, 4113 .stats_get_stats = mv88e6390_stats_get_stats, 4114 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4115 .set_egress_port = mv88e6390_g1_set_egress_port, 4116 .watchdog_ops = &mv88e6390_watchdog_ops, 4117 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4118 .pot_clear = mv88e6xxx_g2_pot_clear, 4119 .reset = mv88e6352_g1_reset, 4120 .rmu_disable = mv88e6390_g1_rmu_disable, 4121 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4122 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4123 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4124 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4125 .serdes_power = mv88e6390_serdes_power, 4126 .serdes_get_lane = mv88e6390_serdes_get_lane, 4127 /* Check status register pause & lpa register */ 4128 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4129 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4130 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4131 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4132 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4133 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4134 .serdes_irq_status = mv88e6390_serdes_irq_status, 4135 .serdes_get_strings = mv88e6390_serdes_get_strings, 4136 .serdes_get_stats = mv88e6390_serdes_get_stats, 4137 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4138 .serdes_get_regs = mv88e6390_serdes_get_regs, 4139 .avb_ops = &mv88e6390_avb_ops, 4140 .ptp_ops = &mv88e6352_ptp_ops, 4141 .phylink_validate = mv88e6390_phylink_validate, 4142 }; 4143 4144 static const struct mv88e6xxx_ops mv88e6240_ops = { 4145 /* MV88E6XXX_FAMILY_6352 */ 4146 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4147 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4148 .irl_init_all = mv88e6352_g2_irl_init_all, 4149 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4150 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4151 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4152 .phy_read = mv88e6xxx_g2_smi_phy_read, 4153 .phy_write = mv88e6xxx_g2_smi_phy_write, 4154 .port_set_link = mv88e6xxx_port_set_link, 4155 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4156 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4157 .port_tag_remap = mv88e6095_port_tag_remap, 4158 .port_set_policy = mv88e6352_port_set_policy, 4159 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4160 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4161 .port_set_ether_type = mv88e6351_port_set_ether_type, 4162 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4163 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4164 .port_pause_limit = mv88e6097_port_pause_limit, 4165 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4166 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4167 .port_get_cmode = mv88e6352_port_get_cmode, 4168 .port_setup_message_port = mv88e6xxx_setup_message_port, 4169 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4170 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4171 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4172 .stats_get_strings = mv88e6095_stats_get_strings, 4173 .stats_get_stats = mv88e6095_stats_get_stats, 4174 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4175 .set_egress_port = mv88e6095_g1_set_egress_port, 4176 .watchdog_ops = &mv88e6097_watchdog_ops, 4177 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4178 .pot_clear = mv88e6xxx_g2_pot_clear, 4179 .reset = mv88e6352_g1_reset, 4180 .rmu_disable = mv88e6352_g1_rmu_disable, 4181 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4182 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4183 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4184 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4185 .serdes_get_lane = mv88e6352_serdes_get_lane, 4186 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4187 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4188 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4189 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4190 .serdes_power = mv88e6352_serdes_power, 4191 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4192 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4193 .serdes_irq_status = mv88e6352_serdes_irq_status, 4194 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4195 .serdes_get_regs = mv88e6352_serdes_get_regs, 4196 .gpio_ops = &mv88e6352_gpio_ops, 4197 .avb_ops = &mv88e6352_avb_ops, 4198 .ptp_ops = &mv88e6352_ptp_ops, 4199 .phylink_validate = mv88e6352_phylink_validate, 4200 }; 4201 4202 static const struct mv88e6xxx_ops mv88e6250_ops = { 4203 /* MV88E6XXX_FAMILY_6250 */ 4204 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4205 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4206 .irl_init_all = mv88e6352_g2_irl_init_all, 4207 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4208 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4209 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4210 .phy_read = mv88e6xxx_g2_smi_phy_read, 4211 .phy_write = mv88e6xxx_g2_smi_phy_write, 4212 .port_set_link = mv88e6xxx_port_set_link, 4213 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4214 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4215 .port_tag_remap = mv88e6095_port_tag_remap, 4216 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4217 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4218 .port_set_ether_type = mv88e6351_port_set_ether_type, 4219 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4220 .port_pause_limit = mv88e6097_port_pause_limit, 4221 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4222 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4223 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4224 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4225 .stats_get_strings = mv88e6250_stats_get_strings, 4226 .stats_get_stats = mv88e6250_stats_get_stats, 4227 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4228 .set_egress_port = mv88e6095_g1_set_egress_port, 4229 .watchdog_ops = &mv88e6250_watchdog_ops, 4230 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4231 .pot_clear = mv88e6xxx_g2_pot_clear, 4232 .reset = mv88e6250_g1_reset, 4233 .vtu_getnext = mv88e6250_g1_vtu_getnext, 4234 .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge, 4235 .avb_ops = &mv88e6352_avb_ops, 4236 .ptp_ops = &mv88e6250_ptp_ops, 4237 .phylink_validate = mv88e6065_phylink_validate, 4238 }; 4239 4240 static const struct mv88e6xxx_ops mv88e6290_ops = { 4241 /* MV88E6XXX_FAMILY_6390 */ 4242 .setup_errata = mv88e6390_setup_errata, 4243 .irl_init_all = mv88e6390_g2_irl_init_all, 4244 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4245 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4246 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4247 .phy_read = mv88e6xxx_g2_smi_phy_read, 4248 .phy_write = mv88e6xxx_g2_smi_phy_write, 4249 .port_set_link = mv88e6xxx_port_set_link, 4250 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4251 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4252 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4253 .port_tag_remap = mv88e6390_port_tag_remap, 4254 .port_set_policy = mv88e6352_port_set_policy, 4255 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4256 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4257 .port_set_ether_type = mv88e6351_port_set_ether_type, 4258 .port_pause_limit = mv88e6390_port_pause_limit, 4259 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4260 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4261 .port_get_cmode = mv88e6352_port_get_cmode, 4262 .port_set_cmode = mv88e6390_port_set_cmode, 4263 .port_setup_message_port = mv88e6xxx_setup_message_port, 4264 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4265 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4266 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4267 .stats_get_strings = mv88e6320_stats_get_strings, 4268 .stats_get_stats = mv88e6390_stats_get_stats, 4269 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4270 .set_egress_port = mv88e6390_g1_set_egress_port, 4271 .watchdog_ops = &mv88e6390_watchdog_ops, 4272 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4273 .pot_clear = mv88e6xxx_g2_pot_clear, 4274 .reset = mv88e6352_g1_reset, 4275 .rmu_disable = mv88e6390_g1_rmu_disable, 4276 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4277 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4278 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4279 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4280 .serdes_power = mv88e6390_serdes_power, 4281 .serdes_get_lane = mv88e6390_serdes_get_lane, 4282 /* Check status register pause & lpa register */ 4283 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4284 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4285 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4286 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4287 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4288 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4289 .serdes_irq_status = mv88e6390_serdes_irq_status, 4290 .serdes_get_strings = mv88e6390_serdes_get_strings, 4291 .serdes_get_stats = mv88e6390_serdes_get_stats, 4292 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4293 .serdes_get_regs = mv88e6390_serdes_get_regs, 4294 .gpio_ops = &mv88e6352_gpio_ops, 4295 .avb_ops = &mv88e6390_avb_ops, 4296 .ptp_ops = &mv88e6352_ptp_ops, 4297 .phylink_validate = mv88e6390_phylink_validate, 4298 }; 4299 4300 static const struct mv88e6xxx_ops mv88e6320_ops = { 4301 /* MV88E6XXX_FAMILY_6320 */ 4302 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4303 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4304 .irl_init_all = mv88e6352_g2_irl_init_all, 4305 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4306 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4307 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4308 .phy_read = mv88e6xxx_g2_smi_phy_read, 4309 .phy_write = mv88e6xxx_g2_smi_phy_write, 4310 .port_set_link = mv88e6xxx_port_set_link, 4311 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4312 .port_tag_remap = mv88e6095_port_tag_remap, 4313 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4314 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4315 .port_set_ether_type = mv88e6351_port_set_ether_type, 4316 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4317 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4318 .port_pause_limit = mv88e6097_port_pause_limit, 4319 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4320 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4321 .port_get_cmode = mv88e6352_port_get_cmode, 4322 .port_setup_message_port = mv88e6xxx_setup_message_port, 4323 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4324 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4325 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4326 .stats_get_strings = mv88e6320_stats_get_strings, 4327 .stats_get_stats = mv88e6320_stats_get_stats, 4328 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4329 .set_egress_port = mv88e6095_g1_set_egress_port, 4330 .watchdog_ops = &mv88e6390_watchdog_ops, 4331 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4332 .pot_clear = mv88e6xxx_g2_pot_clear, 4333 .reset = mv88e6352_g1_reset, 4334 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4335 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4336 .gpio_ops = &mv88e6352_gpio_ops, 4337 .avb_ops = &mv88e6352_avb_ops, 4338 .ptp_ops = &mv88e6352_ptp_ops, 4339 .phylink_validate = mv88e6185_phylink_validate, 4340 }; 4341 4342 static const struct mv88e6xxx_ops mv88e6321_ops = { 4343 /* MV88E6XXX_FAMILY_6320 */ 4344 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4345 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4346 .irl_init_all = mv88e6352_g2_irl_init_all, 4347 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4348 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4349 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4350 .phy_read = mv88e6xxx_g2_smi_phy_read, 4351 .phy_write = mv88e6xxx_g2_smi_phy_write, 4352 .port_set_link = mv88e6xxx_port_set_link, 4353 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4354 .port_tag_remap = mv88e6095_port_tag_remap, 4355 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4356 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4357 .port_set_ether_type = mv88e6351_port_set_ether_type, 4358 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4359 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4360 .port_pause_limit = mv88e6097_port_pause_limit, 4361 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4362 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4363 .port_get_cmode = mv88e6352_port_get_cmode, 4364 .port_setup_message_port = mv88e6xxx_setup_message_port, 4365 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4366 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4367 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4368 .stats_get_strings = mv88e6320_stats_get_strings, 4369 .stats_get_stats = mv88e6320_stats_get_stats, 4370 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4371 .set_egress_port = mv88e6095_g1_set_egress_port, 4372 .watchdog_ops = &mv88e6390_watchdog_ops, 4373 .reset = mv88e6352_g1_reset, 4374 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4375 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4376 .gpio_ops = &mv88e6352_gpio_ops, 4377 .avb_ops = &mv88e6352_avb_ops, 4378 .ptp_ops = &mv88e6352_ptp_ops, 4379 .phylink_validate = mv88e6185_phylink_validate, 4380 }; 4381 4382 static const struct mv88e6xxx_ops mv88e6341_ops = { 4383 /* MV88E6XXX_FAMILY_6341 */ 4384 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4385 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4386 .irl_init_all = mv88e6352_g2_irl_init_all, 4387 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4388 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4389 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4390 .phy_read = mv88e6xxx_g2_smi_phy_read, 4391 .phy_write = mv88e6xxx_g2_smi_phy_write, 4392 .port_set_link = mv88e6xxx_port_set_link, 4393 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4394 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4395 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4396 .port_tag_remap = mv88e6095_port_tag_remap, 4397 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4398 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4399 .port_set_ether_type = mv88e6351_port_set_ether_type, 4400 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4401 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4402 .port_pause_limit = mv88e6097_port_pause_limit, 4403 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4404 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4405 .port_get_cmode = mv88e6352_port_get_cmode, 4406 .port_set_cmode = mv88e6341_port_set_cmode, 4407 .port_setup_message_port = mv88e6xxx_setup_message_port, 4408 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4409 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4410 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4411 .stats_get_strings = mv88e6320_stats_get_strings, 4412 .stats_get_stats = mv88e6390_stats_get_stats, 4413 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4414 .set_egress_port = mv88e6390_g1_set_egress_port, 4415 .watchdog_ops = &mv88e6390_watchdog_ops, 4416 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4417 .pot_clear = mv88e6xxx_g2_pot_clear, 4418 .reset = mv88e6352_g1_reset, 4419 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4420 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4421 .serdes_power = mv88e6390_serdes_power, 4422 .serdes_get_lane = mv88e6341_serdes_get_lane, 4423 /* Check status register pause & lpa register */ 4424 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4425 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4426 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4427 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4428 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4429 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4430 .serdes_irq_status = mv88e6390_serdes_irq_status, 4431 .gpio_ops = &mv88e6352_gpio_ops, 4432 .avb_ops = &mv88e6390_avb_ops, 4433 .ptp_ops = &mv88e6352_ptp_ops, 4434 .phylink_validate = mv88e6341_phylink_validate, 4435 }; 4436 4437 static const struct mv88e6xxx_ops mv88e6350_ops = { 4438 /* MV88E6XXX_FAMILY_6351 */ 4439 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4440 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4441 .irl_init_all = mv88e6352_g2_irl_init_all, 4442 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4443 .phy_read = mv88e6xxx_g2_smi_phy_read, 4444 .phy_write = mv88e6xxx_g2_smi_phy_write, 4445 .port_set_link = mv88e6xxx_port_set_link, 4446 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4447 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4448 .port_tag_remap = mv88e6095_port_tag_remap, 4449 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4450 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4451 .port_set_ether_type = mv88e6351_port_set_ether_type, 4452 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4453 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4454 .port_pause_limit = mv88e6097_port_pause_limit, 4455 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4456 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4457 .port_get_cmode = mv88e6352_port_get_cmode, 4458 .port_setup_message_port = mv88e6xxx_setup_message_port, 4459 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4460 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4461 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4462 .stats_get_strings = mv88e6095_stats_get_strings, 4463 .stats_get_stats = mv88e6095_stats_get_stats, 4464 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4465 .set_egress_port = mv88e6095_g1_set_egress_port, 4466 .watchdog_ops = &mv88e6097_watchdog_ops, 4467 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4468 .pot_clear = mv88e6xxx_g2_pot_clear, 4469 .reset = mv88e6352_g1_reset, 4470 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4471 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4472 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4473 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4474 .phylink_validate = mv88e6185_phylink_validate, 4475 }; 4476 4477 static const struct mv88e6xxx_ops mv88e6351_ops = { 4478 /* MV88E6XXX_FAMILY_6351 */ 4479 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4480 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4481 .irl_init_all = mv88e6352_g2_irl_init_all, 4482 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4483 .phy_read = mv88e6xxx_g2_smi_phy_read, 4484 .phy_write = mv88e6xxx_g2_smi_phy_write, 4485 .port_set_link = mv88e6xxx_port_set_link, 4486 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4487 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4488 .port_tag_remap = mv88e6095_port_tag_remap, 4489 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4490 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4491 .port_set_ether_type = mv88e6351_port_set_ether_type, 4492 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4493 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4494 .port_pause_limit = mv88e6097_port_pause_limit, 4495 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4496 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4497 .port_get_cmode = mv88e6352_port_get_cmode, 4498 .port_setup_message_port = mv88e6xxx_setup_message_port, 4499 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4500 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4501 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4502 .stats_get_strings = mv88e6095_stats_get_strings, 4503 .stats_get_stats = mv88e6095_stats_get_stats, 4504 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4505 .set_egress_port = mv88e6095_g1_set_egress_port, 4506 .watchdog_ops = &mv88e6097_watchdog_ops, 4507 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4508 .pot_clear = mv88e6xxx_g2_pot_clear, 4509 .reset = mv88e6352_g1_reset, 4510 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4511 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4512 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4513 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4514 .avb_ops = &mv88e6352_avb_ops, 4515 .ptp_ops = &mv88e6352_ptp_ops, 4516 .phylink_validate = mv88e6185_phylink_validate, 4517 }; 4518 4519 static const struct mv88e6xxx_ops mv88e6352_ops = { 4520 /* MV88E6XXX_FAMILY_6352 */ 4521 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4522 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4523 .irl_init_all = mv88e6352_g2_irl_init_all, 4524 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4525 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4526 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4527 .phy_read = mv88e6xxx_g2_smi_phy_read, 4528 .phy_write = mv88e6xxx_g2_smi_phy_write, 4529 .port_set_link = mv88e6xxx_port_set_link, 4530 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4531 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4532 .port_tag_remap = mv88e6095_port_tag_remap, 4533 .port_set_policy = mv88e6352_port_set_policy, 4534 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4535 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4536 .port_set_ether_type = mv88e6351_port_set_ether_type, 4537 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4538 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4539 .port_pause_limit = mv88e6097_port_pause_limit, 4540 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4541 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4542 .port_get_cmode = mv88e6352_port_get_cmode, 4543 .port_setup_message_port = mv88e6xxx_setup_message_port, 4544 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4545 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4546 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4547 .stats_get_strings = mv88e6095_stats_get_strings, 4548 .stats_get_stats = mv88e6095_stats_get_stats, 4549 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4550 .set_egress_port = mv88e6095_g1_set_egress_port, 4551 .watchdog_ops = &mv88e6097_watchdog_ops, 4552 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4553 .pot_clear = mv88e6xxx_g2_pot_clear, 4554 .reset = mv88e6352_g1_reset, 4555 .rmu_disable = mv88e6352_g1_rmu_disable, 4556 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4557 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4558 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4559 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4560 .serdes_get_lane = mv88e6352_serdes_get_lane, 4561 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4562 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4563 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4564 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4565 .serdes_power = mv88e6352_serdes_power, 4566 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4567 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4568 .serdes_irq_status = mv88e6352_serdes_irq_status, 4569 .gpio_ops = &mv88e6352_gpio_ops, 4570 .avb_ops = &mv88e6352_avb_ops, 4571 .ptp_ops = &mv88e6352_ptp_ops, 4572 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4573 .serdes_get_strings = mv88e6352_serdes_get_strings, 4574 .serdes_get_stats = mv88e6352_serdes_get_stats, 4575 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4576 .serdes_get_regs = mv88e6352_serdes_get_regs, 4577 .phylink_validate = mv88e6352_phylink_validate, 4578 }; 4579 4580 static const struct mv88e6xxx_ops mv88e6390_ops = { 4581 /* MV88E6XXX_FAMILY_6390 */ 4582 .setup_errata = mv88e6390_setup_errata, 4583 .irl_init_all = mv88e6390_g2_irl_init_all, 4584 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4585 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4586 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4587 .phy_read = mv88e6xxx_g2_smi_phy_read, 4588 .phy_write = mv88e6xxx_g2_smi_phy_write, 4589 .port_set_link = mv88e6xxx_port_set_link, 4590 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4591 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4592 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4593 .port_tag_remap = mv88e6390_port_tag_remap, 4594 .port_set_policy = mv88e6352_port_set_policy, 4595 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4596 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4597 .port_set_ether_type = mv88e6351_port_set_ether_type, 4598 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4599 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4600 .port_pause_limit = mv88e6390_port_pause_limit, 4601 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4602 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4603 .port_get_cmode = mv88e6352_port_get_cmode, 4604 .port_set_cmode = mv88e6390_port_set_cmode, 4605 .port_setup_message_port = mv88e6xxx_setup_message_port, 4606 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4607 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4608 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4609 .stats_get_strings = mv88e6320_stats_get_strings, 4610 .stats_get_stats = mv88e6390_stats_get_stats, 4611 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4612 .set_egress_port = mv88e6390_g1_set_egress_port, 4613 .watchdog_ops = &mv88e6390_watchdog_ops, 4614 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4615 .pot_clear = mv88e6xxx_g2_pot_clear, 4616 .reset = mv88e6352_g1_reset, 4617 .rmu_disable = mv88e6390_g1_rmu_disable, 4618 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4619 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4620 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4621 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4622 .serdes_power = mv88e6390_serdes_power, 4623 .serdes_get_lane = mv88e6390_serdes_get_lane, 4624 /* Check status register pause & lpa register */ 4625 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4626 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4627 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4628 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4629 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4630 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4631 .serdes_irq_status = mv88e6390_serdes_irq_status, 4632 .gpio_ops = &mv88e6352_gpio_ops, 4633 .avb_ops = &mv88e6390_avb_ops, 4634 .ptp_ops = &mv88e6352_ptp_ops, 4635 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4636 .serdes_get_strings = mv88e6390_serdes_get_strings, 4637 .serdes_get_stats = mv88e6390_serdes_get_stats, 4638 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4639 .serdes_get_regs = mv88e6390_serdes_get_regs, 4640 .phylink_validate = mv88e6390_phylink_validate, 4641 }; 4642 4643 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4644 /* MV88E6XXX_FAMILY_6390 */ 4645 .setup_errata = mv88e6390_setup_errata, 4646 .irl_init_all = mv88e6390_g2_irl_init_all, 4647 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4648 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4649 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4650 .phy_read = mv88e6xxx_g2_smi_phy_read, 4651 .phy_write = mv88e6xxx_g2_smi_phy_write, 4652 .port_set_link = mv88e6xxx_port_set_link, 4653 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4654 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4655 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4656 .port_tag_remap = mv88e6390_port_tag_remap, 4657 .port_set_policy = mv88e6352_port_set_policy, 4658 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4659 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4660 .port_set_ether_type = mv88e6351_port_set_ether_type, 4661 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4662 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4663 .port_pause_limit = mv88e6390_port_pause_limit, 4664 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4665 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4666 .port_get_cmode = mv88e6352_port_get_cmode, 4667 .port_set_cmode = mv88e6390x_port_set_cmode, 4668 .port_setup_message_port = mv88e6xxx_setup_message_port, 4669 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4670 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4671 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4672 .stats_get_strings = mv88e6320_stats_get_strings, 4673 .stats_get_stats = mv88e6390_stats_get_stats, 4674 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4675 .set_egress_port = mv88e6390_g1_set_egress_port, 4676 .watchdog_ops = &mv88e6390_watchdog_ops, 4677 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4678 .pot_clear = mv88e6xxx_g2_pot_clear, 4679 .reset = mv88e6352_g1_reset, 4680 .rmu_disable = mv88e6390_g1_rmu_disable, 4681 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4682 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4683 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4684 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4685 .serdes_power = mv88e6390_serdes_power, 4686 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4687 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4688 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4689 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4690 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4691 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4692 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4693 .serdes_irq_status = mv88e6390_serdes_irq_status, 4694 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4695 .serdes_get_strings = mv88e6390_serdes_get_strings, 4696 .serdes_get_stats = mv88e6390_serdes_get_stats, 4697 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4698 .serdes_get_regs = mv88e6390_serdes_get_regs, 4699 .gpio_ops = &mv88e6352_gpio_ops, 4700 .avb_ops = &mv88e6390_avb_ops, 4701 .ptp_ops = &mv88e6352_ptp_ops, 4702 .phylink_validate = mv88e6390x_phylink_validate, 4703 }; 4704 4705 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4706 [MV88E6085] = { 4707 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4708 .family = MV88E6XXX_FAMILY_6097, 4709 .name = "Marvell 88E6085", 4710 .num_databases = 4096, 4711 .num_macs = 8192, 4712 .num_ports = 10, 4713 .num_internal_phys = 5, 4714 .max_vid = 4095, 4715 .port_base_addr = 0x10, 4716 .phy_base_addr = 0x0, 4717 .global1_addr = 0x1b, 4718 .global2_addr = 0x1c, 4719 .age_time_coeff = 15000, 4720 .g1_irqs = 8, 4721 .g2_irqs = 10, 4722 .atu_move_port_mask = 0xf, 4723 .pvt = true, 4724 .multi_chip = true, 4725 .tag_protocol = DSA_TAG_PROTO_DSA, 4726 .ops = &mv88e6085_ops, 4727 }, 4728 4729 [MV88E6095] = { 4730 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4731 .family = MV88E6XXX_FAMILY_6095, 4732 .name = "Marvell 88E6095/88E6095F", 4733 .num_databases = 256, 4734 .num_macs = 8192, 4735 .num_ports = 11, 4736 .num_internal_phys = 0, 4737 .max_vid = 4095, 4738 .port_base_addr = 0x10, 4739 .phy_base_addr = 0x0, 4740 .global1_addr = 0x1b, 4741 .global2_addr = 0x1c, 4742 .age_time_coeff = 15000, 4743 .g1_irqs = 8, 4744 .atu_move_port_mask = 0xf, 4745 .multi_chip = true, 4746 .tag_protocol = DSA_TAG_PROTO_DSA, 4747 .ops = &mv88e6095_ops, 4748 }, 4749 4750 [MV88E6097] = { 4751 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4752 .family = MV88E6XXX_FAMILY_6097, 4753 .name = "Marvell 88E6097/88E6097F", 4754 .num_databases = 4096, 4755 .num_macs = 8192, 4756 .num_ports = 11, 4757 .num_internal_phys = 8, 4758 .max_vid = 4095, 4759 .port_base_addr = 0x10, 4760 .phy_base_addr = 0x0, 4761 .global1_addr = 0x1b, 4762 .global2_addr = 0x1c, 4763 .age_time_coeff = 15000, 4764 .g1_irqs = 8, 4765 .g2_irqs = 10, 4766 .atu_move_port_mask = 0xf, 4767 .pvt = true, 4768 .multi_chip = true, 4769 .tag_protocol = DSA_TAG_PROTO_EDSA, 4770 .ops = &mv88e6097_ops, 4771 }, 4772 4773 [MV88E6123] = { 4774 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 4775 .family = MV88E6XXX_FAMILY_6165, 4776 .name = "Marvell 88E6123", 4777 .num_databases = 4096, 4778 .num_macs = 1024, 4779 .num_ports = 3, 4780 .num_internal_phys = 5, 4781 .max_vid = 4095, 4782 .port_base_addr = 0x10, 4783 .phy_base_addr = 0x0, 4784 .global1_addr = 0x1b, 4785 .global2_addr = 0x1c, 4786 .age_time_coeff = 15000, 4787 .g1_irqs = 9, 4788 .g2_irqs = 10, 4789 .atu_move_port_mask = 0xf, 4790 .pvt = true, 4791 .multi_chip = true, 4792 .tag_protocol = DSA_TAG_PROTO_EDSA, 4793 .ops = &mv88e6123_ops, 4794 }, 4795 4796 [MV88E6131] = { 4797 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4798 .family = MV88E6XXX_FAMILY_6185, 4799 .name = "Marvell 88E6131", 4800 .num_databases = 256, 4801 .num_macs = 8192, 4802 .num_ports = 8, 4803 .num_internal_phys = 0, 4804 .max_vid = 4095, 4805 .port_base_addr = 0x10, 4806 .phy_base_addr = 0x0, 4807 .global1_addr = 0x1b, 4808 .global2_addr = 0x1c, 4809 .age_time_coeff = 15000, 4810 .g1_irqs = 9, 4811 .atu_move_port_mask = 0xf, 4812 .multi_chip = true, 4813 .tag_protocol = DSA_TAG_PROTO_DSA, 4814 .ops = &mv88e6131_ops, 4815 }, 4816 4817 [MV88E6141] = { 4818 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4819 .family = MV88E6XXX_FAMILY_6341, 4820 .name = "Marvell 88E6141", 4821 .num_databases = 4096, 4822 .num_macs = 2048, 4823 .num_ports = 6, 4824 .num_internal_phys = 5, 4825 .num_gpio = 11, 4826 .max_vid = 4095, 4827 .port_base_addr = 0x10, 4828 .phy_base_addr = 0x10, 4829 .global1_addr = 0x1b, 4830 .global2_addr = 0x1c, 4831 .age_time_coeff = 3750, 4832 .atu_move_port_mask = 0x1f, 4833 .g1_irqs = 9, 4834 .g2_irqs = 10, 4835 .pvt = true, 4836 .multi_chip = true, 4837 .tag_protocol = DSA_TAG_PROTO_EDSA, 4838 .ops = &mv88e6141_ops, 4839 }, 4840 4841 [MV88E6161] = { 4842 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 4843 .family = MV88E6XXX_FAMILY_6165, 4844 .name = "Marvell 88E6161", 4845 .num_databases = 4096, 4846 .num_macs = 1024, 4847 .num_ports = 6, 4848 .num_internal_phys = 5, 4849 .max_vid = 4095, 4850 .port_base_addr = 0x10, 4851 .phy_base_addr = 0x0, 4852 .global1_addr = 0x1b, 4853 .global2_addr = 0x1c, 4854 .age_time_coeff = 15000, 4855 .g1_irqs = 9, 4856 .g2_irqs = 10, 4857 .atu_move_port_mask = 0xf, 4858 .pvt = true, 4859 .multi_chip = true, 4860 .tag_protocol = DSA_TAG_PROTO_EDSA, 4861 .ptp_support = true, 4862 .ops = &mv88e6161_ops, 4863 }, 4864 4865 [MV88E6165] = { 4866 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4867 .family = MV88E6XXX_FAMILY_6165, 4868 .name = "Marvell 88E6165", 4869 .num_databases = 4096, 4870 .num_macs = 8192, 4871 .num_ports = 6, 4872 .num_internal_phys = 0, 4873 .max_vid = 4095, 4874 .port_base_addr = 0x10, 4875 .phy_base_addr = 0x0, 4876 .global1_addr = 0x1b, 4877 .global2_addr = 0x1c, 4878 .age_time_coeff = 15000, 4879 .g1_irqs = 9, 4880 .g2_irqs = 10, 4881 .atu_move_port_mask = 0xf, 4882 .pvt = true, 4883 .multi_chip = true, 4884 .tag_protocol = DSA_TAG_PROTO_DSA, 4885 .ptp_support = true, 4886 .ops = &mv88e6165_ops, 4887 }, 4888 4889 [MV88E6171] = { 4890 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4891 .family = MV88E6XXX_FAMILY_6351, 4892 .name = "Marvell 88E6171", 4893 .num_databases = 4096, 4894 .num_macs = 8192, 4895 .num_ports = 7, 4896 .num_internal_phys = 5, 4897 .max_vid = 4095, 4898 .port_base_addr = 0x10, 4899 .phy_base_addr = 0x0, 4900 .global1_addr = 0x1b, 4901 .global2_addr = 0x1c, 4902 .age_time_coeff = 15000, 4903 .g1_irqs = 9, 4904 .g2_irqs = 10, 4905 .atu_move_port_mask = 0xf, 4906 .pvt = true, 4907 .multi_chip = true, 4908 .tag_protocol = DSA_TAG_PROTO_EDSA, 4909 .ops = &mv88e6171_ops, 4910 }, 4911 4912 [MV88E6172] = { 4913 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4914 .family = MV88E6XXX_FAMILY_6352, 4915 .name = "Marvell 88E6172", 4916 .num_databases = 4096, 4917 .num_macs = 8192, 4918 .num_ports = 7, 4919 .num_internal_phys = 5, 4920 .num_gpio = 15, 4921 .max_vid = 4095, 4922 .port_base_addr = 0x10, 4923 .phy_base_addr = 0x0, 4924 .global1_addr = 0x1b, 4925 .global2_addr = 0x1c, 4926 .age_time_coeff = 15000, 4927 .g1_irqs = 9, 4928 .g2_irqs = 10, 4929 .atu_move_port_mask = 0xf, 4930 .pvt = true, 4931 .multi_chip = true, 4932 .tag_protocol = DSA_TAG_PROTO_EDSA, 4933 .ops = &mv88e6172_ops, 4934 }, 4935 4936 [MV88E6175] = { 4937 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4938 .family = MV88E6XXX_FAMILY_6351, 4939 .name = "Marvell 88E6175", 4940 .num_databases = 4096, 4941 .num_macs = 8192, 4942 .num_ports = 7, 4943 .num_internal_phys = 5, 4944 .max_vid = 4095, 4945 .port_base_addr = 0x10, 4946 .phy_base_addr = 0x0, 4947 .global1_addr = 0x1b, 4948 .global2_addr = 0x1c, 4949 .age_time_coeff = 15000, 4950 .g1_irqs = 9, 4951 .g2_irqs = 10, 4952 .atu_move_port_mask = 0xf, 4953 .pvt = true, 4954 .multi_chip = true, 4955 .tag_protocol = DSA_TAG_PROTO_EDSA, 4956 .ops = &mv88e6175_ops, 4957 }, 4958 4959 [MV88E6176] = { 4960 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4961 .family = MV88E6XXX_FAMILY_6352, 4962 .name = "Marvell 88E6176", 4963 .num_databases = 4096, 4964 .num_macs = 8192, 4965 .num_ports = 7, 4966 .num_internal_phys = 5, 4967 .num_gpio = 15, 4968 .max_vid = 4095, 4969 .port_base_addr = 0x10, 4970 .phy_base_addr = 0x0, 4971 .global1_addr = 0x1b, 4972 .global2_addr = 0x1c, 4973 .age_time_coeff = 15000, 4974 .g1_irqs = 9, 4975 .g2_irqs = 10, 4976 .atu_move_port_mask = 0xf, 4977 .pvt = true, 4978 .multi_chip = true, 4979 .tag_protocol = DSA_TAG_PROTO_EDSA, 4980 .ops = &mv88e6176_ops, 4981 }, 4982 4983 [MV88E6185] = { 4984 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4985 .family = MV88E6XXX_FAMILY_6185, 4986 .name = "Marvell 88E6185", 4987 .num_databases = 256, 4988 .num_macs = 8192, 4989 .num_ports = 10, 4990 .num_internal_phys = 0, 4991 .max_vid = 4095, 4992 .port_base_addr = 0x10, 4993 .phy_base_addr = 0x0, 4994 .global1_addr = 0x1b, 4995 .global2_addr = 0x1c, 4996 .age_time_coeff = 15000, 4997 .g1_irqs = 8, 4998 .atu_move_port_mask = 0xf, 4999 .multi_chip = true, 5000 .tag_protocol = DSA_TAG_PROTO_EDSA, 5001 .ops = &mv88e6185_ops, 5002 }, 5003 5004 [MV88E6190] = { 5005 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5006 .family = MV88E6XXX_FAMILY_6390, 5007 .name = "Marvell 88E6190", 5008 .num_databases = 4096, 5009 .num_macs = 16384, 5010 .num_ports = 11, /* 10 + Z80 */ 5011 .num_internal_phys = 9, 5012 .num_gpio = 16, 5013 .max_vid = 8191, 5014 .port_base_addr = 0x0, 5015 .phy_base_addr = 0x0, 5016 .global1_addr = 0x1b, 5017 .global2_addr = 0x1c, 5018 .tag_protocol = DSA_TAG_PROTO_DSA, 5019 .age_time_coeff = 3750, 5020 .g1_irqs = 9, 5021 .g2_irqs = 14, 5022 .pvt = true, 5023 .multi_chip = true, 5024 .atu_move_port_mask = 0x1f, 5025 .ops = &mv88e6190_ops, 5026 }, 5027 5028 [MV88E6190X] = { 5029 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5030 .family = MV88E6XXX_FAMILY_6390, 5031 .name = "Marvell 88E6190X", 5032 .num_databases = 4096, 5033 .num_macs = 16384, 5034 .num_ports = 11, /* 10 + Z80 */ 5035 .num_internal_phys = 9, 5036 .num_gpio = 16, 5037 .max_vid = 8191, 5038 .port_base_addr = 0x0, 5039 .phy_base_addr = 0x0, 5040 .global1_addr = 0x1b, 5041 .global2_addr = 0x1c, 5042 .age_time_coeff = 3750, 5043 .g1_irqs = 9, 5044 .g2_irqs = 14, 5045 .atu_move_port_mask = 0x1f, 5046 .pvt = true, 5047 .multi_chip = true, 5048 .tag_protocol = DSA_TAG_PROTO_DSA, 5049 .ops = &mv88e6190x_ops, 5050 }, 5051 5052 [MV88E6191] = { 5053 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5054 .family = MV88E6XXX_FAMILY_6390, 5055 .name = "Marvell 88E6191", 5056 .num_databases = 4096, 5057 .num_macs = 16384, 5058 .num_ports = 11, /* 10 + Z80 */ 5059 .num_internal_phys = 9, 5060 .max_vid = 8191, 5061 .port_base_addr = 0x0, 5062 .phy_base_addr = 0x0, 5063 .global1_addr = 0x1b, 5064 .global2_addr = 0x1c, 5065 .age_time_coeff = 3750, 5066 .g1_irqs = 9, 5067 .g2_irqs = 14, 5068 .atu_move_port_mask = 0x1f, 5069 .pvt = true, 5070 .multi_chip = true, 5071 .tag_protocol = DSA_TAG_PROTO_DSA, 5072 .ptp_support = true, 5073 .ops = &mv88e6191_ops, 5074 }, 5075 5076 [MV88E6220] = { 5077 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5078 .family = MV88E6XXX_FAMILY_6250, 5079 .name = "Marvell 88E6220", 5080 .num_databases = 64, 5081 5082 /* Ports 2-4 are not routed to pins 5083 * => usable ports 0, 1, 5, 6 5084 */ 5085 .num_ports = 7, 5086 .num_internal_phys = 2, 5087 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5088 .max_vid = 4095, 5089 .port_base_addr = 0x08, 5090 .phy_base_addr = 0x00, 5091 .global1_addr = 0x0f, 5092 .global2_addr = 0x07, 5093 .age_time_coeff = 15000, 5094 .g1_irqs = 9, 5095 .g2_irqs = 10, 5096 .atu_move_port_mask = 0xf, 5097 .dual_chip = true, 5098 .tag_protocol = DSA_TAG_PROTO_DSA, 5099 .ptp_support = true, 5100 .ops = &mv88e6250_ops, 5101 }, 5102 5103 [MV88E6240] = { 5104 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5105 .family = MV88E6XXX_FAMILY_6352, 5106 .name = "Marvell 88E6240", 5107 .num_databases = 4096, 5108 .num_macs = 8192, 5109 .num_ports = 7, 5110 .num_internal_phys = 5, 5111 .num_gpio = 15, 5112 .max_vid = 4095, 5113 .port_base_addr = 0x10, 5114 .phy_base_addr = 0x0, 5115 .global1_addr = 0x1b, 5116 .global2_addr = 0x1c, 5117 .age_time_coeff = 15000, 5118 .g1_irqs = 9, 5119 .g2_irqs = 10, 5120 .atu_move_port_mask = 0xf, 5121 .pvt = true, 5122 .multi_chip = true, 5123 .tag_protocol = DSA_TAG_PROTO_EDSA, 5124 .ptp_support = true, 5125 .ops = &mv88e6240_ops, 5126 }, 5127 5128 [MV88E6250] = { 5129 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5130 .family = MV88E6XXX_FAMILY_6250, 5131 .name = "Marvell 88E6250", 5132 .num_databases = 64, 5133 .num_ports = 7, 5134 .num_internal_phys = 5, 5135 .max_vid = 4095, 5136 .port_base_addr = 0x08, 5137 .phy_base_addr = 0x00, 5138 .global1_addr = 0x0f, 5139 .global2_addr = 0x07, 5140 .age_time_coeff = 15000, 5141 .g1_irqs = 9, 5142 .g2_irqs = 10, 5143 .atu_move_port_mask = 0xf, 5144 .dual_chip = true, 5145 .tag_protocol = DSA_TAG_PROTO_DSA, 5146 .ptp_support = true, 5147 .ops = &mv88e6250_ops, 5148 }, 5149 5150 [MV88E6290] = { 5151 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5152 .family = MV88E6XXX_FAMILY_6390, 5153 .name = "Marvell 88E6290", 5154 .num_databases = 4096, 5155 .num_ports = 11, /* 10 + Z80 */ 5156 .num_internal_phys = 9, 5157 .num_gpio = 16, 5158 .max_vid = 8191, 5159 .port_base_addr = 0x0, 5160 .phy_base_addr = 0x0, 5161 .global1_addr = 0x1b, 5162 .global2_addr = 0x1c, 5163 .age_time_coeff = 3750, 5164 .g1_irqs = 9, 5165 .g2_irqs = 14, 5166 .atu_move_port_mask = 0x1f, 5167 .pvt = true, 5168 .multi_chip = true, 5169 .tag_protocol = DSA_TAG_PROTO_DSA, 5170 .ptp_support = true, 5171 .ops = &mv88e6290_ops, 5172 }, 5173 5174 [MV88E6320] = { 5175 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5176 .family = MV88E6XXX_FAMILY_6320, 5177 .name = "Marvell 88E6320", 5178 .num_databases = 4096, 5179 .num_macs = 8192, 5180 .num_ports = 7, 5181 .num_internal_phys = 5, 5182 .num_gpio = 15, 5183 .max_vid = 4095, 5184 .port_base_addr = 0x10, 5185 .phy_base_addr = 0x0, 5186 .global1_addr = 0x1b, 5187 .global2_addr = 0x1c, 5188 .age_time_coeff = 15000, 5189 .g1_irqs = 8, 5190 .g2_irqs = 10, 5191 .atu_move_port_mask = 0xf, 5192 .pvt = true, 5193 .multi_chip = true, 5194 .tag_protocol = DSA_TAG_PROTO_EDSA, 5195 .ptp_support = true, 5196 .ops = &mv88e6320_ops, 5197 }, 5198 5199 [MV88E6321] = { 5200 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5201 .family = MV88E6XXX_FAMILY_6320, 5202 .name = "Marvell 88E6321", 5203 .num_databases = 4096, 5204 .num_macs = 8192, 5205 .num_ports = 7, 5206 .num_internal_phys = 5, 5207 .num_gpio = 15, 5208 .max_vid = 4095, 5209 .port_base_addr = 0x10, 5210 .phy_base_addr = 0x0, 5211 .global1_addr = 0x1b, 5212 .global2_addr = 0x1c, 5213 .age_time_coeff = 15000, 5214 .g1_irqs = 8, 5215 .g2_irqs = 10, 5216 .atu_move_port_mask = 0xf, 5217 .multi_chip = true, 5218 .tag_protocol = DSA_TAG_PROTO_EDSA, 5219 .ptp_support = true, 5220 .ops = &mv88e6321_ops, 5221 }, 5222 5223 [MV88E6341] = { 5224 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5225 .family = MV88E6XXX_FAMILY_6341, 5226 .name = "Marvell 88E6341", 5227 .num_databases = 4096, 5228 .num_macs = 2048, 5229 .num_internal_phys = 5, 5230 .num_ports = 6, 5231 .num_gpio = 11, 5232 .max_vid = 4095, 5233 .port_base_addr = 0x10, 5234 .phy_base_addr = 0x10, 5235 .global1_addr = 0x1b, 5236 .global2_addr = 0x1c, 5237 .age_time_coeff = 3750, 5238 .atu_move_port_mask = 0x1f, 5239 .g1_irqs = 9, 5240 .g2_irqs = 10, 5241 .pvt = true, 5242 .multi_chip = true, 5243 .tag_protocol = DSA_TAG_PROTO_EDSA, 5244 .ptp_support = true, 5245 .ops = &mv88e6341_ops, 5246 }, 5247 5248 [MV88E6350] = { 5249 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5250 .family = MV88E6XXX_FAMILY_6351, 5251 .name = "Marvell 88E6350", 5252 .num_databases = 4096, 5253 .num_macs = 8192, 5254 .num_ports = 7, 5255 .num_internal_phys = 5, 5256 .max_vid = 4095, 5257 .port_base_addr = 0x10, 5258 .phy_base_addr = 0x0, 5259 .global1_addr = 0x1b, 5260 .global2_addr = 0x1c, 5261 .age_time_coeff = 15000, 5262 .g1_irqs = 9, 5263 .g2_irqs = 10, 5264 .atu_move_port_mask = 0xf, 5265 .pvt = true, 5266 .multi_chip = true, 5267 .tag_protocol = DSA_TAG_PROTO_EDSA, 5268 .ops = &mv88e6350_ops, 5269 }, 5270 5271 [MV88E6351] = { 5272 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5273 .family = MV88E6XXX_FAMILY_6351, 5274 .name = "Marvell 88E6351", 5275 .num_databases = 4096, 5276 .num_macs = 8192, 5277 .num_ports = 7, 5278 .num_internal_phys = 5, 5279 .max_vid = 4095, 5280 .port_base_addr = 0x10, 5281 .phy_base_addr = 0x0, 5282 .global1_addr = 0x1b, 5283 .global2_addr = 0x1c, 5284 .age_time_coeff = 15000, 5285 .g1_irqs = 9, 5286 .g2_irqs = 10, 5287 .atu_move_port_mask = 0xf, 5288 .pvt = true, 5289 .multi_chip = true, 5290 .tag_protocol = DSA_TAG_PROTO_EDSA, 5291 .ops = &mv88e6351_ops, 5292 }, 5293 5294 [MV88E6352] = { 5295 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5296 .family = MV88E6XXX_FAMILY_6352, 5297 .name = "Marvell 88E6352", 5298 .num_databases = 4096, 5299 .num_macs = 8192, 5300 .num_ports = 7, 5301 .num_internal_phys = 5, 5302 .num_gpio = 15, 5303 .max_vid = 4095, 5304 .port_base_addr = 0x10, 5305 .phy_base_addr = 0x0, 5306 .global1_addr = 0x1b, 5307 .global2_addr = 0x1c, 5308 .age_time_coeff = 15000, 5309 .g1_irqs = 9, 5310 .g2_irqs = 10, 5311 .atu_move_port_mask = 0xf, 5312 .pvt = true, 5313 .multi_chip = true, 5314 .tag_protocol = DSA_TAG_PROTO_EDSA, 5315 .ptp_support = true, 5316 .ops = &mv88e6352_ops, 5317 }, 5318 [MV88E6390] = { 5319 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5320 .family = MV88E6XXX_FAMILY_6390, 5321 .name = "Marvell 88E6390", 5322 .num_databases = 4096, 5323 .num_macs = 16384, 5324 .num_ports = 11, /* 10 + Z80 */ 5325 .num_internal_phys = 9, 5326 .num_gpio = 16, 5327 .max_vid = 8191, 5328 .port_base_addr = 0x0, 5329 .phy_base_addr = 0x0, 5330 .global1_addr = 0x1b, 5331 .global2_addr = 0x1c, 5332 .age_time_coeff = 3750, 5333 .g1_irqs = 9, 5334 .g2_irqs = 14, 5335 .atu_move_port_mask = 0x1f, 5336 .pvt = true, 5337 .multi_chip = true, 5338 .tag_protocol = DSA_TAG_PROTO_DSA, 5339 .ptp_support = true, 5340 .ops = &mv88e6390_ops, 5341 }, 5342 [MV88E6390X] = { 5343 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5344 .family = MV88E6XXX_FAMILY_6390, 5345 .name = "Marvell 88E6390X", 5346 .num_databases = 4096, 5347 .num_macs = 16384, 5348 .num_ports = 11, /* 10 + Z80 */ 5349 .num_internal_phys = 9, 5350 .num_gpio = 16, 5351 .max_vid = 8191, 5352 .port_base_addr = 0x0, 5353 .phy_base_addr = 0x0, 5354 .global1_addr = 0x1b, 5355 .global2_addr = 0x1c, 5356 .age_time_coeff = 3750, 5357 .g1_irqs = 9, 5358 .g2_irqs = 14, 5359 .atu_move_port_mask = 0x1f, 5360 .pvt = true, 5361 .multi_chip = true, 5362 .tag_protocol = DSA_TAG_PROTO_DSA, 5363 .ptp_support = true, 5364 .ops = &mv88e6390x_ops, 5365 }, 5366 }; 5367 5368 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5369 { 5370 int i; 5371 5372 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5373 if (mv88e6xxx_table[i].prod_num == prod_num) 5374 return &mv88e6xxx_table[i]; 5375 5376 return NULL; 5377 } 5378 5379 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5380 { 5381 const struct mv88e6xxx_info *info; 5382 unsigned int prod_num, rev; 5383 u16 id; 5384 int err; 5385 5386 mv88e6xxx_reg_lock(chip); 5387 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5388 mv88e6xxx_reg_unlock(chip); 5389 if (err) 5390 return err; 5391 5392 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5393 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5394 5395 info = mv88e6xxx_lookup_info(prod_num); 5396 if (!info) 5397 return -ENODEV; 5398 5399 /* Update the compatible info with the probed one */ 5400 chip->info = info; 5401 5402 err = mv88e6xxx_g2_require(chip); 5403 if (err) 5404 return err; 5405 5406 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5407 chip->info->prod_num, chip->info->name, rev); 5408 5409 return 0; 5410 } 5411 5412 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5413 { 5414 struct mv88e6xxx_chip *chip; 5415 5416 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5417 if (!chip) 5418 return NULL; 5419 5420 chip->dev = dev; 5421 5422 mutex_init(&chip->reg_lock); 5423 INIT_LIST_HEAD(&chip->mdios); 5424 idr_init(&chip->policies); 5425 5426 return chip; 5427 } 5428 5429 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5430 int port, 5431 enum dsa_tag_protocol m) 5432 { 5433 struct mv88e6xxx_chip *chip = ds->priv; 5434 5435 return chip->info->tag_protocol; 5436 } 5437 5438 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 5439 const struct switchdev_obj_port_mdb *mdb) 5440 { 5441 /* We don't need any dynamic resource from the kernel (yet), 5442 * so skip the prepare phase. 5443 */ 5444 5445 return 0; 5446 } 5447 5448 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5449 const struct switchdev_obj_port_mdb *mdb) 5450 { 5451 struct mv88e6xxx_chip *chip = ds->priv; 5452 5453 mv88e6xxx_reg_lock(chip); 5454 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5455 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 5456 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 5457 port); 5458 mv88e6xxx_reg_unlock(chip); 5459 } 5460 5461 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5462 const struct switchdev_obj_port_mdb *mdb) 5463 { 5464 struct mv88e6xxx_chip *chip = ds->priv; 5465 int err; 5466 5467 mv88e6xxx_reg_lock(chip); 5468 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5469 mv88e6xxx_reg_unlock(chip); 5470 5471 return err; 5472 } 5473 5474 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5475 struct dsa_mall_mirror_tc_entry *mirror, 5476 bool ingress) 5477 { 5478 enum mv88e6xxx_egress_direction direction = ingress ? 5479 MV88E6XXX_EGRESS_DIR_INGRESS : 5480 MV88E6XXX_EGRESS_DIR_EGRESS; 5481 struct mv88e6xxx_chip *chip = ds->priv; 5482 bool other_mirrors = false; 5483 int i; 5484 int err; 5485 5486 if (!chip->info->ops->set_egress_port) 5487 return -EOPNOTSUPP; 5488 5489 mutex_lock(&chip->reg_lock); 5490 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5491 mirror->to_local_port) { 5492 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5493 other_mirrors |= ingress ? 5494 chip->ports[i].mirror_ingress : 5495 chip->ports[i].mirror_egress; 5496 5497 /* Can't change egress port when other mirror is active */ 5498 if (other_mirrors) { 5499 err = -EBUSY; 5500 goto out; 5501 } 5502 5503 err = chip->info->ops->set_egress_port(chip, 5504 direction, 5505 mirror->to_local_port); 5506 if (err) 5507 goto out; 5508 } 5509 5510 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5511 out: 5512 mutex_unlock(&chip->reg_lock); 5513 5514 return err; 5515 } 5516 5517 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5518 struct dsa_mall_mirror_tc_entry *mirror) 5519 { 5520 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5521 MV88E6XXX_EGRESS_DIR_INGRESS : 5522 MV88E6XXX_EGRESS_DIR_EGRESS; 5523 struct mv88e6xxx_chip *chip = ds->priv; 5524 bool other_mirrors = false; 5525 int i; 5526 5527 mutex_lock(&chip->reg_lock); 5528 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5529 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5530 5531 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5532 other_mirrors |= mirror->ingress ? 5533 chip->ports[i].mirror_ingress : 5534 chip->ports[i].mirror_egress; 5535 5536 /* Reset egress port when no other mirror is active */ 5537 if (!other_mirrors) { 5538 if (chip->info->ops->set_egress_port(chip, 5539 direction, 5540 dsa_upstream_port(ds, 5541 port))) 5542 dev_err(ds->dev, "failed to set egress port\n"); 5543 } 5544 5545 mutex_unlock(&chip->reg_lock); 5546 } 5547 5548 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port, 5549 bool unicast, bool multicast) 5550 { 5551 struct mv88e6xxx_chip *chip = ds->priv; 5552 int err = -EOPNOTSUPP; 5553 5554 mv88e6xxx_reg_lock(chip); 5555 if (chip->info->ops->port_set_egress_floods) 5556 err = chip->info->ops->port_set_egress_floods(chip, port, 5557 unicast, 5558 multicast); 5559 mv88e6xxx_reg_unlock(chip); 5560 5561 return err; 5562 } 5563 5564 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 5565 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 5566 .setup = mv88e6xxx_setup, 5567 .teardown = mv88e6xxx_teardown, 5568 .phylink_validate = mv88e6xxx_validate, 5569 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 5570 .phylink_mac_config = mv88e6xxx_mac_config, 5571 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 5572 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 5573 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 5574 .get_strings = mv88e6xxx_get_strings, 5575 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 5576 .get_sset_count = mv88e6xxx_get_sset_count, 5577 .port_enable = mv88e6xxx_port_enable, 5578 .port_disable = mv88e6xxx_port_disable, 5579 .port_max_mtu = mv88e6xxx_get_max_mtu, 5580 .port_change_mtu = mv88e6xxx_change_mtu, 5581 .get_mac_eee = mv88e6xxx_get_mac_eee, 5582 .set_mac_eee = mv88e6xxx_set_mac_eee, 5583 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 5584 .get_eeprom = mv88e6xxx_get_eeprom, 5585 .set_eeprom = mv88e6xxx_set_eeprom, 5586 .get_regs_len = mv88e6xxx_get_regs_len, 5587 .get_regs = mv88e6xxx_get_regs, 5588 .get_rxnfc = mv88e6xxx_get_rxnfc, 5589 .set_rxnfc = mv88e6xxx_set_rxnfc, 5590 .set_ageing_time = mv88e6xxx_set_ageing_time, 5591 .port_bridge_join = mv88e6xxx_port_bridge_join, 5592 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 5593 .port_egress_floods = mv88e6xxx_port_egress_floods, 5594 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 5595 .port_fast_age = mv88e6xxx_port_fast_age, 5596 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 5597 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 5598 .port_vlan_add = mv88e6xxx_port_vlan_add, 5599 .port_vlan_del = mv88e6xxx_port_vlan_del, 5600 .port_fdb_add = mv88e6xxx_port_fdb_add, 5601 .port_fdb_del = mv88e6xxx_port_fdb_del, 5602 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 5603 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 5604 .port_mdb_add = mv88e6xxx_port_mdb_add, 5605 .port_mdb_del = mv88e6xxx_port_mdb_del, 5606 .port_mirror_add = mv88e6xxx_port_mirror_add, 5607 .port_mirror_del = mv88e6xxx_port_mirror_del, 5608 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 5609 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 5610 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 5611 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 5612 .port_txtstamp = mv88e6xxx_port_txtstamp, 5613 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 5614 .get_ts_info = mv88e6xxx_get_ts_info, 5615 .devlink_param_get = mv88e6xxx_devlink_param_get, 5616 .devlink_param_set = mv88e6xxx_devlink_param_set, 5617 }; 5618 5619 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 5620 { 5621 struct device *dev = chip->dev; 5622 struct dsa_switch *ds; 5623 5624 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 5625 if (!ds) 5626 return -ENOMEM; 5627 5628 ds->dev = dev; 5629 ds->num_ports = mv88e6xxx_num_ports(chip); 5630 ds->priv = chip; 5631 ds->dev = dev; 5632 ds->ops = &mv88e6xxx_switch_ops; 5633 ds->ageing_time_min = chip->info->age_time_coeff; 5634 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 5635 5636 dev_set_drvdata(dev, ds); 5637 5638 return dsa_register_switch(ds); 5639 } 5640 5641 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 5642 { 5643 dsa_unregister_switch(chip->ds); 5644 } 5645 5646 static const void *pdata_device_get_match_data(struct device *dev) 5647 { 5648 const struct of_device_id *matches = dev->driver->of_match_table; 5649 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 5650 5651 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 5652 matches++) { 5653 if (!strcmp(pdata->compatible, matches->compatible)) 5654 return matches->data; 5655 } 5656 return NULL; 5657 } 5658 5659 /* There is no suspend to RAM support at DSA level yet, the switch configuration 5660 * would be lost after a power cycle so prevent it to be suspended. 5661 */ 5662 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 5663 { 5664 return -EOPNOTSUPP; 5665 } 5666 5667 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 5668 { 5669 return 0; 5670 } 5671 5672 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 5673 5674 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 5675 { 5676 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 5677 const struct mv88e6xxx_info *compat_info = NULL; 5678 struct device *dev = &mdiodev->dev; 5679 struct device_node *np = dev->of_node; 5680 struct mv88e6xxx_chip *chip; 5681 int port; 5682 int err; 5683 5684 if (!np && !pdata) 5685 return -EINVAL; 5686 5687 if (np) 5688 compat_info = of_device_get_match_data(dev); 5689 5690 if (pdata) { 5691 compat_info = pdata_device_get_match_data(dev); 5692 5693 if (!pdata->netdev) 5694 return -EINVAL; 5695 5696 for (port = 0; port < DSA_MAX_PORTS; port++) { 5697 if (!(pdata->enabled_ports & (1 << port))) 5698 continue; 5699 if (strcmp(pdata->cd.port_names[port], "cpu")) 5700 continue; 5701 pdata->cd.netdev[port] = &pdata->netdev->dev; 5702 break; 5703 } 5704 } 5705 5706 if (!compat_info) 5707 return -EINVAL; 5708 5709 chip = mv88e6xxx_alloc_chip(dev); 5710 if (!chip) { 5711 err = -ENOMEM; 5712 goto out; 5713 } 5714 5715 chip->info = compat_info; 5716 5717 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 5718 if (err) 5719 goto out; 5720 5721 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 5722 if (IS_ERR(chip->reset)) { 5723 err = PTR_ERR(chip->reset); 5724 goto out; 5725 } 5726 if (chip->reset) 5727 usleep_range(1000, 2000); 5728 5729 err = mv88e6xxx_detect(chip); 5730 if (err) 5731 goto out; 5732 5733 mv88e6xxx_phy_init(chip); 5734 5735 if (chip->info->ops->get_eeprom) { 5736 if (np) 5737 of_property_read_u32(np, "eeprom-length", 5738 &chip->eeprom_len); 5739 else 5740 chip->eeprom_len = pdata->eeprom_len; 5741 } 5742 5743 mv88e6xxx_reg_lock(chip); 5744 err = mv88e6xxx_switch_reset(chip); 5745 mv88e6xxx_reg_unlock(chip); 5746 if (err) 5747 goto out; 5748 5749 if (np) { 5750 chip->irq = of_irq_get(np, 0); 5751 if (chip->irq == -EPROBE_DEFER) { 5752 err = chip->irq; 5753 goto out; 5754 } 5755 } 5756 5757 if (pdata) 5758 chip->irq = pdata->irq; 5759 5760 /* Has to be performed before the MDIO bus is created, because 5761 * the PHYs will link their interrupts to these interrupt 5762 * controllers 5763 */ 5764 mv88e6xxx_reg_lock(chip); 5765 if (chip->irq > 0) 5766 err = mv88e6xxx_g1_irq_setup(chip); 5767 else 5768 err = mv88e6xxx_irq_poll_setup(chip); 5769 mv88e6xxx_reg_unlock(chip); 5770 5771 if (err) 5772 goto out; 5773 5774 if (chip->info->g2_irqs > 0) { 5775 err = mv88e6xxx_g2_irq_setup(chip); 5776 if (err) 5777 goto out_g1_irq; 5778 } 5779 5780 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 5781 if (err) 5782 goto out_g2_irq; 5783 5784 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 5785 if (err) 5786 goto out_g1_atu_prob_irq; 5787 5788 err = mv88e6xxx_mdios_register(chip, np); 5789 if (err) 5790 goto out_g1_vtu_prob_irq; 5791 5792 err = mv88e6xxx_register_switch(chip); 5793 if (err) 5794 goto out_mdio; 5795 5796 return 0; 5797 5798 out_mdio: 5799 mv88e6xxx_mdios_unregister(chip); 5800 out_g1_vtu_prob_irq: 5801 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5802 out_g1_atu_prob_irq: 5803 mv88e6xxx_g1_atu_prob_irq_free(chip); 5804 out_g2_irq: 5805 if (chip->info->g2_irqs > 0) 5806 mv88e6xxx_g2_irq_free(chip); 5807 out_g1_irq: 5808 if (chip->irq > 0) 5809 mv88e6xxx_g1_irq_free(chip); 5810 else 5811 mv88e6xxx_irq_poll_free(chip); 5812 out: 5813 if (pdata) 5814 dev_put(pdata->netdev); 5815 5816 return err; 5817 } 5818 5819 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 5820 { 5821 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 5822 struct mv88e6xxx_chip *chip = ds->priv; 5823 5824 if (chip->info->ptp_support) { 5825 mv88e6xxx_hwtstamp_free(chip); 5826 mv88e6xxx_ptp_free(chip); 5827 } 5828 5829 mv88e6xxx_phy_destroy(chip); 5830 mv88e6xxx_unregister_switch(chip); 5831 mv88e6xxx_mdios_unregister(chip); 5832 5833 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5834 mv88e6xxx_g1_atu_prob_irq_free(chip); 5835 5836 if (chip->info->g2_irqs > 0) 5837 mv88e6xxx_g2_irq_free(chip); 5838 5839 if (chip->irq > 0) 5840 mv88e6xxx_g1_irq_free(chip); 5841 else 5842 mv88e6xxx_irq_poll_free(chip); 5843 } 5844 5845 static const struct of_device_id mv88e6xxx_of_match[] = { 5846 { 5847 .compatible = "marvell,mv88e6085", 5848 .data = &mv88e6xxx_table[MV88E6085], 5849 }, 5850 { 5851 .compatible = "marvell,mv88e6190", 5852 .data = &mv88e6xxx_table[MV88E6190], 5853 }, 5854 { 5855 .compatible = "marvell,mv88e6250", 5856 .data = &mv88e6xxx_table[MV88E6250], 5857 }, 5858 { /* sentinel */ }, 5859 }; 5860 5861 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 5862 5863 static struct mdio_driver mv88e6xxx_driver = { 5864 .probe = mv88e6xxx_probe, 5865 .remove = mv88e6xxx_remove, 5866 .mdiodrv.driver = { 5867 .name = "mv88e6085", 5868 .of_match_table = mv88e6xxx_of_match, 5869 .pm = &mv88e6xxx_pm_ops, 5870 }, 5871 }; 5872 5873 mdio_module_driver(mv88e6xxx_driver); 5874 5875 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 5876 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 5877 MODULE_LICENSE("GPL"); 5878