1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (C) 2007, 2011 Wolfgang Grandegger <wg@grandegger.com> 3 * Copyright (C) 2012 Stephane Grosjean <s.grosjean@peak-system.com> 4 * 5 * Derived from the PCAN project file driver/src/pcan_pci.c: 6 * 7 * Copyright (C) 2001-2006 PEAK System-Technik GmbH 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/interrupt.h> 13 #include <linux/netdevice.h> 14 #include <linux/delay.h> 15 #include <linux/pci.h> 16 #include <linux/io.h> 17 #include <linux/can.h> 18 #include <linux/can/dev.h> 19 20 #include "peak_canfd_user.h" 21 22 MODULE_AUTHOR("Stephane Grosjean <s.grosjean@peak-system.com>"); 23 MODULE_DESCRIPTION("Socket-CAN driver for PEAK PCAN PCIe/M.2 FD family cards"); 24 MODULE_SUPPORTED_DEVICE("PEAK PCAN PCIe/M.2 FD CAN cards"); 25 MODULE_LICENSE("GPL v2"); 26 27 #define PCIEFD_DRV_NAME "peak_pciefd" 28 29 #define PEAK_PCI_VENDOR_ID 0x001c /* The PCI device and vendor IDs */ 30 #define PEAK_PCIEFD_ID 0x0013 /* for PCIe slot cards */ 31 #define PCAN_CPCIEFD_ID 0x0014 /* for Compact-PCI Serial slot cards */ 32 #define PCAN_PCIE104FD_ID 0x0017 /* for PCIe-104 Express slot cards */ 33 #define PCAN_MINIPCIEFD_ID 0x0018 /* for mini-PCIe slot cards */ 34 #define PCAN_PCIEFD_OEM_ID 0x0019 /* for PCIe slot OEM cards */ 35 #define PCAN_M2_ID 0x001a /* for M2 slot cards */ 36 37 /* PEAK PCIe board access description */ 38 #define PCIEFD_BAR0_SIZE (64 * 1024) 39 #define PCIEFD_RX_DMA_SIZE (4 * 1024) 40 #define PCIEFD_TX_DMA_SIZE (4 * 1024) 41 42 #define PCIEFD_TX_PAGE_SIZE (2 * 1024) 43 44 /* System Control Registers */ 45 #define PCIEFD_REG_SYS_CTL_SET 0x0000 /* set bits */ 46 #define PCIEFD_REG_SYS_CTL_CLR 0x0004 /* clear bits */ 47 48 /* Version info registers */ 49 #define PCIEFD_REG_SYS_VER1 0x0040 /* version reg #1 */ 50 #define PCIEFD_REG_SYS_VER2 0x0044 /* version reg #2 */ 51 52 #define PCIEFD_FW_VERSION(x, y, z) (((u32)(x) << 24) | \ 53 ((u32)(y) << 16) | \ 54 ((u32)(z) << 8)) 55 56 /* System Control Registers Bits */ 57 #define PCIEFD_SYS_CTL_TS_RST 0x00000001 /* timestamp clock */ 58 #define PCIEFD_SYS_CTL_CLK_EN 0x00000002 /* system clock */ 59 60 /* CAN-FD channel addresses */ 61 #define PCIEFD_CANX_OFF(c) (((c) + 1) * 0x1000) 62 63 #define PCIEFD_ECHO_SKB_MAX PCANFD_ECHO_SKB_DEF 64 65 /* CAN-FD channel registers */ 66 #define PCIEFD_REG_CAN_MISC 0x0000 /* Misc. control */ 67 #define PCIEFD_REG_CAN_CLK_SEL 0x0008 /* Clock selector */ 68 #define PCIEFD_REG_CAN_CMD_PORT_L 0x0010 /* 64-bits command port */ 69 #define PCIEFD_REG_CAN_CMD_PORT_H 0x0014 70 #define PCIEFD_REG_CAN_TX_REQ_ACC 0x0020 /* Tx request accumulator */ 71 #define PCIEFD_REG_CAN_TX_CTL_SET 0x0030 /* Tx control set register */ 72 #define PCIEFD_REG_CAN_TX_CTL_CLR 0x0038 /* Tx control clear register */ 73 #define PCIEFD_REG_CAN_TX_DMA_ADDR_L 0x0040 /* 64-bits addr for Tx DMA */ 74 #define PCIEFD_REG_CAN_TX_DMA_ADDR_H 0x0044 75 #define PCIEFD_REG_CAN_RX_CTL_SET 0x0050 /* Rx control set register */ 76 #define PCIEFD_REG_CAN_RX_CTL_CLR 0x0058 /* Rx control clear register */ 77 #define PCIEFD_REG_CAN_RX_CTL_WRT 0x0060 /* Rx control write register */ 78 #define PCIEFD_REG_CAN_RX_CTL_ACK 0x0068 /* Rx control ACK register */ 79 #define PCIEFD_REG_CAN_RX_DMA_ADDR_L 0x0070 /* 64-bits addr for Rx DMA */ 80 #define PCIEFD_REG_CAN_RX_DMA_ADDR_H 0x0074 81 82 /* CAN-FD channel misc register bits */ 83 #define CANFD_MISC_TS_RST 0x00000001 /* timestamp cnt rst */ 84 85 /* CAN-FD channel Clock SELector Source & DIVider */ 86 #define CANFD_CLK_SEL_DIV_MASK 0x00000007 87 #define CANFD_CLK_SEL_DIV_60MHZ 0x00000000 /* SRC=240MHz only */ 88 #define CANFD_CLK_SEL_DIV_40MHZ 0x00000001 /* SRC=240MHz only */ 89 #define CANFD_CLK_SEL_DIV_30MHZ 0x00000002 /* SRC=240MHz only */ 90 #define CANFD_CLK_SEL_DIV_24MHZ 0x00000003 /* SRC=240MHz only */ 91 #define CANFD_CLK_SEL_DIV_20MHZ 0x00000004 /* SRC=240MHz only */ 92 93 #define CANFD_CLK_SEL_SRC_MASK 0x00000008 /* 0=80MHz, 1=240MHz */ 94 #define CANFD_CLK_SEL_SRC_240MHZ 0x00000008 95 #define CANFD_CLK_SEL_SRC_80MHZ (~CANFD_CLK_SEL_SRC_240MHZ & \ 96 CANFD_CLK_SEL_SRC_MASK) 97 98 #define CANFD_CLK_SEL_20MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ 99 CANFD_CLK_SEL_DIV_20MHZ) 100 #define CANFD_CLK_SEL_24MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ 101 CANFD_CLK_SEL_DIV_24MHZ) 102 #define CANFD_CLK_SEL_30MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ 103 CANFD_CLK_SEL_DIV_30MHZ) 104 #define CANFD_CLK_SEL_40MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ 105 CANFD_CLK_SEL_DIV_40MHZ) 106 #define CANFD_CLK_SEL_60MHZ (CANFD_CLK_SEL_SRC_240MHZ |\ 107 CANFD_CLK_SEL_DIV_60MHZ) 108 #define CANFD_CLK_SEL_80MHZ (CANFD_CLK_SEL_SRC_80MHZ) 109 110 /* CAN-FD channel Rx/Tx control register bits */ 111 #define CANFD_CTL_UNC_BIT 0x00010000 /* Uncached DMA mem */ 112 #define CANFD_CTL_RST_BIT 0x00020000 /* reset DMA action */ 113 #define CANFD_CTL_IEN_BIT 0x00040000 /* IRQ enable */ 114 115 /* Rx IRQ Count and Time Limits */ 116 #define CANFD_CTL_IRQ_CL_DEF 16 /* Rx msg max nb per IRQ in Rx DMA */ 117 #define CANFD_CTL_IRQ_TL_DEF 10 /* Time before IRQ if < CL (x100 µs) */ 118 119 #define CANFD_OPTIONS_SET (CANFD_OPTION_ERROR | CANFD_OPTION_BUSLOAD) 120 121 /* Tx anticipation window (link logical address should be aligned on 2K 122 * boundary) 123 */ 124 #define PCIEFD_TX_PAGE_COUNT (PCIEFD_TX_DMA_SIZE / PCIEFD_TX_PAGE_SIZE) 125 126 #define CANFD_MSG_LNK_TX 0x1001 /* Tx msgs link */ 127 128 /* 32-bits IRQ status fields, heading Rx DMA area */ 129 static inline int pciefd_irq_tag(u32 irq_status) 130 { 131 return irq_status & 0x0000000f; 132 } 133 134 static inline int pciefd_irq_rx_cnt(u32 irq_status) 135 { 136 return (irq_status & 0x000007f0) >> 4; 137 } 138 139 static inline int pciefd_irq_is_lnk(u32 irq_status) 140 { 141 return irq_status & 0x00010000; 142 } 143 144 /* Rx record */ 145 struct pciefd_rx_dma { 146 __le32 irq_status; 147 __le32 sys_time_low; 148 __le32 sys_time_high; 149 struct pucan_rx_msg msg[0]; 150 } __packed __aligned(4); 151 152 /* Tx Link record */ 153 struct pciefd_tx_link { 154 __le16 size; 155 __le16 type; 156 __le32 laddr_lo; 157 __le32 laddr_hi; 158 } __packed __aligned(4); 159 160 /* Tx page descriptor */ 161 struct pciefd_page { 162 void *vbase; /* page virtual address */ 163 dma_addr_t lbase; /* page logical address */ 164 u32 offset; 165 u32 size; 166 }; 167 168 /* CAN-FD channel object */ 169 struct pciefd_board; 170 struct pciefd_can { 171 struct peak_canfd_priv ucan; /* must be the first member */ 172 void __iomem *reg_base; /* channel config base addr */ 173 struct pciefd_board *board; /* reverse link */ 174 175 struct pucan_command pucan_cmd; /* command buffer */ 176 177 dma_addr_t rx_dma_laddr; /* DMA virtual and logical addr */ 178 void *rx_dma_vaddr; /* for Rx and Tx areas */ 179 dma_addr_t tx_dma_laddr; 180 void *tx_dma_vaddr; 181 182 struct pciefd_page tx_pages[PCIEFD_TX_PAGE_COUNT]; 183 u16 tx_pages_free; /* free Tx pages counter */ 184 u16 tx_page_index; /* current page used for Tx */ 185 spinlock_t tx_lock; 186 187 u32 irq_status; 188 u32 irq_tag; /* next irq tag */ 189 }; 190 191 /* PEAK-PCIe FD board object */ 192 struct pciefd_board { 193 void __iomem *reg_base; 194 struct pci_dev *pci_dev; 195 int can_count; 196 spinlock_t cmd_lock; /* 64-bits cmds must be atomic */ 197 struct pciefd_can *can[0]; /* array of network devices */ 198 }; 199 200 /* supported device ids. */ 201 static const struct pci_device_id peak_pciefd_tbl[] = { 202 {PEAK_PCI_VENDOR_ID, PEAK_PCIEFD_ID, PCI_ANY_ID, PCI_ANY_ID,}, 203 {PEAK_PCI_VENDOR_ID, PCAN_CPCIEFD_ID, PCI_ANY_ID, PCI_ANY_ID,}, 204 {PEAK_PCI_VENDOR_ID, PCAN_PCIE104FD_ID, PCI_ANY_ID, PCI_ANY_ID,}, 205 {PEAK_PCI_VENDOR_ID, PCAN_MINIPCIEFD_ID, PCI_ANY_ID, PCI_ANY_ID,}, 206 {PEAK_PCI_VENDOR_ID, PCAN_PCIEFD_OEM_ID, PCI_ANY_ID, PCI_ANY_ID,}, 207 {PEAK_PCI_VENDOR_ID, PCAN_M2_ID, PCI_ANY_ID, PCI_ANY_ID,}, 208 {0,} 209 }; 210 211 MODULE_DEVICE_TABLE(pci, peak_pciefd_tbl); 212 213 /* read a 32 bits value from a SYS block register */ 214 static inline u32 pciefd_sys_readreg(const struct pciefd_board *priv, u16 reg) 215 { 216 return readl(priv->reg_base + reg); 217 } 218 219 /* write a 32 bits value into a SYS block register */ 220 static inline void pciefd_sys_writereg(const struct pciefd_board *priv, 221 u32 val, u16 reg) 222 { 223 writel(val, priv->reg_base + reg); 224 } 225 226 /* read a 32 bits value from CAN-FD block register */ 227 static inline u32 pciefd_can_readreg(const struct pciefd_can *priv, u16 reg) 228 { 229 return readl(priv->reg_base + reg); 230 } 231 232 /* write a 32 bits value into a CAN-FD block register */ 233 static inline void pciefd_can_writereg(const struct pciefd_can *priv, 234 u32 val, u16 reg) 235 { 236 writel(val, priv->reg_base + reg); 237 } 238 239 /* give a channel logical Rx DMA address to the board */ 240 static void pciefd_can_setup_rx_dma(struct pciefd_can *priv) 241 { 242 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 243 const u32 dma_addr_h = (u32)(priv->rx_dma_laddr >> 32); 244 #else 245 const u32 dma_addr_h = 0; 246 #endif 247 248 /* (DMA must be reset for Rx) */ 249 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_RX_CTL_SET); 250 251 /* write the logical address of the Rx DMA area for this channel */ 252 pciefd_can_writereg(priv, (u32)priv->rx_dma_laddr, 253 PCIEFD_REG_CAN_RX_DMA_ADDR_L); 254 pciefd_can_writereg(priv, dma_addr_h, PCIEFD_REG_CAN_RX_DMA_ADDR_H); 255 256 /* also indicates that Rx DMA is cacheable */ 257 pciefd_can_writereg(priv, CANFD_CTL_UNC_BIT, PCIEFD_REG_CAN_RX_CTL_CLR); 258 } 259 260 /* clear channel logical Rx DMA address from the board */ 261 static void pciefd_can_clear_rx_dma(struct pciefd_can *priv) 262 { 263 /* DMA must be reset for Rx */ 264 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_RX_CTL_SET); 265 266 /* clear the logical address of the Rx DMA area for this channel */ 267 pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_RX_DMA_ADDR_L); 268 pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_RX_DMA_ADDR_H); 269 } 270 271 /* give a channel logical Tx DMA address to the board */ 272 static void pciefd_can_setup_tx_dma(struct pciefd_can *priv) 273 { 274 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 275 const u32 dma_addr_h = (u32)(priv->tx_dma_laddr >> 32); 276 #else 277 const u32 dma_addr_h = 0; 278 #endif 279 280 /* (DMA must be reset for Tx) */ 281 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_SET); 282 283 /* write the logical address of the Tx DMA area for this channel */ 284 pciefd_can_writereg(priv, (u32)priv->tx_dma_laddr, 285 PCIEFD_REG_CAN_TX_DMA_ADDR_L); 286 pciefd_can_writereg(priv, dma_addr_h, PCIEFD_REG_CAN_TX_DMA_ADDR_H); 287 288 /* also indicates that Tx DMA is cacheable */ 289 pciefd_can_writereg(priv, CANFD_CTL_UNC_BIT, PCIEFD_REG_CAN_TX_CTL_CLR); 290 } 291 292 /* clear channel logical Tx DMA address from the board */ 293 static void pciefd_can_clear_tx_dma(struct pciefd_can *priv) 294 { 295 /* DMA must be reset for Tx */ 296 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_SET); 297 298 /* clear the logical address of the Tx DMA area for this channel */ 299 pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_TX_DMA_ADDR_L); 300 pciefd_can_writereg(priv, 0, PCIEFD_REG_CAN_TX_DMA_ADDR_H); 301 } 302 303 static void pciefd_can_ack_rx_dma(struct pciefd_can *priv) 304 { 305 /* read value of current IRQ tag and inc it for next one */ 306 priv->irq_tag = le32_to_cpu(*(__le32 *)priv->rx_dma_vaddr); 307 priv->irq_tag++; 308 priv->irq_tag &= 0xf; 309 310 /* write the next IRQ tag for this CAN */ 311 pciefd_can_writereg(priv, priv->irq_tag, PCIEFD_REG_CAN_RX_CTL_ACK); 312 } 313 314 /* IRQ handler */ 315 static irqreturn_t pciefd_irq_handler(int irq, void *arg) 316 { 317 struct pciefd_can *priv = arg; 318 struct pciefd_rx_dma *rx_dma = priv->rx_dma_vaddr; 319 320 /* INTA mode only to sync with PCIe transaction */ 321 if (!pci_dev_msi_enabled(priv->board->pci_dev)) 322 (void)pciefd_sys_readreg(priv->board, PCIEFD_REG_SYS_VER1); 323 324 /* read IRQ status from the first 32-bits of the Rx DMA area */ 325 priv->irq_status = le32_to_cpu(rx_dma->irq_status); 326 327 /* check if this (shared) IRQ is for this CAN */ 328 if (pciefd_irq_tag(priv->irq_status) != priv->irq_tag) 329 return IRQ_NONE; 330 331 /* handle rx messages (if any) */ 332 peak_canfd_handle_msgs_list(&priv->ucan, 333 rx_dma->msg, 334 pciefd_irq_rx_cnt(priv->irq_status)); 335 336 /* handle tx link interrupt (if any) */ 337 if (pciefd_irq_is_lnk(priv->irq_status)) { 338 unsigned long flags; 339 340 spin_lock_irqsave(&priv->tx_lock, flags); 341 priv->tx_pages_free++; 342 spin_unlock_irqrestore(&priv->tx_lock, flags); 343 344 /* wake producer up (only if enough room in echo_skb array) */ 345 spin_lock_irqsave(&priv->ucan.echo_lock, flags); 346 if (!priv->ucan.can.echo_skb[priv->ucan.echo_idx]) 347 netif_wake_queue(priv->ucan.ndev); 348 349 spin_unlock_irqrestore(&priv->ucan.echo_lock, flags); 350 } 351 352 /* re-enable Rx DMA transfer for this CAN */ 353 pciefd_can_ack_rx_dma(priv); 354 355 return IRQ_HANDLED; 356 } 357 358 static int pciefd_enable_tx_path(struct peak_canfd_priv *ucan) 359 { 360 struct pciefd_can *priv = (struct pciefd_can *)ucan; 361 int i; 362 363 /* initialize the Tx pages descriptors */ 364 priv->tx_pages_free = PCIEFD_TX_PAGE_COUNT - 1; 365 priv->tx_page_index = 0; 366 367 priv->tx_pages[0].vbase = priv->tx_dma_vaddr; 368 priv->tx_pages[0].lbase = priv->tx_dma_laddr; 369 370 for (i = 0; i < PCIEFD_TX_PAGE_COUNT; i++) { 371 priv->tx_pages[i].offset = 0; 372 priv->tx_pages[i].size = PCIEFD_TX_PAGE_SIZE - 373 sizeof(struct pciefd_tx_link); 374 if (i) { 375 priv->tx_pages[i].vbase = 376 priv->tx_pages[i - 1].vbase + 377 PCIEFD_TX_PAGE_SIZE; 378 priv->tx_pages[i].lbase = 379 priv->tx_pages[i - 1].lbase + 380 PCIEFD_TX_PAGE_SIZE; 381 } 382 } 383 384 /* setup Tx DMA addresses into IP core */ 385 pciefd_can_setup_tx_dma(priv); 386 387 /* start (TX_RST=0) Tx Path */ 388 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, PCIEFD_REG_CAN_TX_CTL_CLR); 389 390 return 0; 391 } 392 393 /* board specific CANFD command pre-processing */ 394 static int pciefd_pre_cmd(struct peak_canfd_priv *ucan) 395 { 396 struct pciefd_can *priv = (struct pciefd_can *)ucan; 397 u16 cmd = pucan_cmd_get_opcode(&priv->pucan_cmd); 398 int err; 399 400 /* pre-process command */ 401 switch (cmd) { 402 case PUCAN_CMD_NORMAL_MODE: 403 case PUCAN_CMD_LISTEN_ONLY_MODE: 404 405 if (ucan->can.state == CAN_STATE_BUS_OFF) 406 break; 407 408 /* going into operational mode: setup IRQ handler */ 409 err = request_irq(priv->ucan.ndev->irq, 410 pciefd_irq_handler, 411 IRQF_SHARED, 412 PCIEFD_DRV_NAME, 413 priv); 414 if (err) 415 return err; 416 417 /* setup Rx DMA address */ 418 pciefd_can_setup_rx_dma(priv); 419 420 /* setup max count of msgs per IRQ */ 421 pciefd_can_writereg(priv, (CANFD_CTL_IRQ_TL_DEF) << 8 | 422 CANFD_CTL_IRQ_CL_DEF, 423 PCIEFD_REG_CAN_RX_CTL_WRT); 424 425 /* clear DMA RST for Rx (Rx start) */ 426 pciefd_can_writereg(priv, CANFD_CTL_RST_BIT, 427 PCIEFD_REG_CAN_RX_CTL_CLR); 428 429 /* reset timestamps */ 430 pciefd_can_writereg(priv, !CANFD_MISC_TS_RST, 431 PCIEFD_REG_CAN_MISC); 432 433 /* do an initial ACK */ 434 pciefd_can_ack_rx_dma(priv); 435 436 /* enable IRQ for this CAN after having set next irq_tag */ 437 pciefd_can_writereg(priv, CANFD_CTL_IEN_BIT, 438 PCIEFD_REG_CAN_RX_CTL_SET); 439 440 /* Tx path will be setup as soon as RX_BARRIER is received */ 441 break; 442 default: 443 break; 444 } 445 446 return 0; 447 } 448 449 /* write a command */ 450 static int pciefd_write_cmd(struct peak_canfd_priv *ucan) 451 { 452 struct pciefd_can *priv = (struct pciefd_can *)ucan; 453 unsigned long flags; 454 455 /* 64-bits command is atomic */ 456 spin_lock_irqsave(&priv->board->cmd_lock, flags); 457 458 pciefd_can_writereg(priv, *(u32 *)ucan->cmd_buffer, 459 PCIEFD_REG_CAN_CMD_PORT_L); 460 pciefd_can_writereg(priv, *(u32 *)(ucan->cmd_buffer + 4), 461 PCIEFD_REG_CAN_CMD_PORT_H); 462 463 spin_unlock_irqrestore(&priv->board->cmd_lock, flags); 464 465 return 0; 466 } 467 468 /* board specific CANFD command post-processing */ 469 static int pciefd_post_cmd(struct peak_canfd_priv *ucan) 470 { 471 struct pciefd_can *priv = (struct pciefd_can *)ucan; 472 u16 cmd = pucan_cmd_get_opcode(&priv->pucan_cmd); 473 474 switch (cmd) { 475 case PUCAN_CMD_RESET_MODE: 476 477 if (ucan->can.state == CAN_STATE_STOPPED) 478 break; 479 480 /* controller now in reset mode: */ 481 482 /* disable IRQ for this CAN */ 483 pciefd_can_writereg(priv, CANFD_CTL_IEN_BIT, 484 PCIEFD_REG_CAN_RX_CTL_CLR); 485 486 /* stop and reset DMA addresses in Tx/Rx engines */ 487 pciefd_can_clear_tx_dma(priv); 488 pciefd_can_clear_rx_dma(priv); 489 490 /* wait for above commands to complete (read cycle) */ 491 (void)pciefd_sys_readreg(priv->board, PCIEFD_REG_SYS_VER1); 492 493 free_irq(priv->ucan.ndev->irq, priv); 494 495 ucan->can.state = CAN_STATE_STOPPED; 496 497 break; 498 } 499 500 return 0; 501 } 502 503 static void *pciefd_alloc_tx_msg(struct peak_canfd_priv *ucan, u16 msg_size, 504 int *room_left) 505 { 506 struct pciefd_can *priv = (struct pciefd_can *)ucan; 507 struct pciefd_page *page = priv->tx_pages + priv->tx_page_index; 508 unsigned long flags; 509 void *msg; 510 511 spin_lock_irqsave(&priv->tx_lock, flags); 512 513 if (page->offset + msg_size > page->size) { 514 struct pciefd_tx_link *lk; 515 516 /* not enough space in this page: try another one */ 517 if (!priv->tx_pages_free) { 518 spin_unlock_irqrestore(&priv->tx_lock, flags); 519 520 /* Tx overflow */ 521 return NULL; 522 } 523 524 priv->tx_pages_free--; 525 526 /* keep address of the very last free slot of current page */ 527 lk = page->vbase + page->offset; 528 529 /* next, move on a new free page */ 530 priv->tx_page_index = (priv->tx_page_index + 1) % 531 PCIEFD_TX_PAGE_COUNT; 532 page = priv->tx_pages + priv->tx_page_index; 533 534 /* put link record to this new page at the end of prev one */ 535 lk->size = cpu_to_le16(sizeof(*lk)); 536 lk->type = cpu_to_le16(CANFD_MSG_LNK_TX); 537 lk->laddr_lo = cpu_to_le32(page->lbase); 538 539 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 540 lk->laddr_hi = cpu_to_le32(page->lbase >> 32); 541 #else 542 lk->laddr_hi = 0; 543 #endif 544 /* next msgs will be put from the begininng of this new page */ 545 page->offset = 0; 546 } 547 548 *room_left = priv->tx_pages_free * page->size; 549 550 spin_unlock_irqrestore(&priv->tx_lock, flags); 551 552 msg = page->vbase + page->offset; 553 554 /* give back room left in the tx ring */ 555 *room_left += page->size - (page->offset + msg_size); 556 557 return msg; 558 } 559 560 static int pciefd_write_tx_msg(struct peak_canfd_priv *ucan, 561 struct pucan_tx_msg *msg) 562 { 563 struct pciefd_can *priv = (struct pciefd_can *)ucan; 564 struct pciefd_page *page = priv->tx_pages + priv->tx_page_index; 565 566 /* this slot is now reserved for writing the frame */ 567 page->offset += le16_to_cpu(msg->size); 568 569 /* tell the board a frame has been written in Tx DMA area */ 570 pciefd_can_writereg(priv, 1, PCIEFD_REG_CAN_TX_REQ_ACC); 571 572 return 0; 573 } 574 575 /* probe for CAN-FD channel #pciefd_board->can_count */ 576 static int pciefd_can_probe(struct pciefd_board *pciefd) 577 { 578 struct net_device *ndev; 579 struct pciefd_can *priv; 580 u32 clk; 581 int err; 582 583 /* allocate the candev object with default isize of echo skbs ring */ 584 ndev = alloc_peak_canfd_dev(sizeof(*priv), pciefd->can_count, 585 PCIEFD_ECHO_SKB_MAX); 586 if (!ndev) { 587 dev_err(&pciefd->pci_dev->dev, 588 "failed to alloc candev object\n"); 589 goto failure; 590 } 591 592 priv = netdev_priv(ndev); 593 594 /* fill-in candev private object: */ 595 596 /* setup PCIe-FD own callbacks */ 597 priv->ucan.pre_cmd = pciefd_pre_cmd; 598 priv->ucan.write_cmd = pciefd_write_cmd; 599 priv->ucan.post_cmd = pciefd_post_cmd; 600 priv->ucan.enable_tx_path = pciefd_enable_tx_path; 601 priv->ucan.alloc_tx_msg = pciefd_alloc_tx_msg; 602 priv->ucan.write_tx_msg = pciefd_write_tx_msg; 603 604 /* setup PCIe-FD own command buffer */ 605 priv->ucan.cmd_buffer = &priv->pucan_cmd; 606 priv->ucan.cmd_maxlen = sizeof(priv->pucan_cmd); 607 608 priv->board = pciefd; 609 610 /* CAN config regs block address */ 611 priv->reg_base = pciefd->reg_base + PCIEFD_CANX_OFF(priv->ucan.index); 612 613 /* allocate non-cacheable DMA'able 4KB memory area for Rx */ 614 priv->rx_dma_vaddr = dmam_alloc_coherent(&pciefd->pci_dev->dev, 615 PCIEFD_RX_DMA_SIZE, 616 &priv->rx_dma_laddr, 617 GFP_KERNEL); 618 if (!priv->rx_dma_vaddr) { 619 dev_err(&pciefd->pci_dev->dev, 620 "Rx dmam_alloc_coherent(%u) failure\n", 621 PCIEFD_RX_DMA_SIZE); 622 goto err_free_candev; 623 } 624 625 /* allocate non-cacheable DMA'able 4KB memory area for Tx */ 626 priv->tx_dma_vaddr = dmam_alloc_coherent(&pciefd->pci_dev->dev, 627 PCIEFD_TX_DMA_SIZE, 628 &priv->tx_dma_laddr, 629 GFP_KERNEL); 630 if (!priv->tx_dma_vaddr) { 631 dev_err(&pciefd->pci_dev->dev, 632 "Tx dmam_alloc_coherent(%u) failure\n", 633 PCIEFD_TX_DMA_SIZE); 634 goto err_free_candev; 635 } 636 637 /* CAN clock in RST mode */ 638 pciefd_can_writereg(priv, CANFD_MISC_TS_RST, PCIEFD_REG_CAN_MISC); 639 640 /* read current clock value */ 641 clk = pciefd_can_readreg(priv, PCIEFD_REG_CAN_CLK_SEL); 642 switch (clk) { 643 case CANFD_CLK_SEL_20MHZ: 644 priv->ucan.can.clock.freq = 20 * 1000 * 1000; 645 break; 646 case CANFD_CLK_SEL_24MHZ: 647 priv->ucan.can.clock.freq = 24 * 1000 * 1000; 648 break; 649 case CANFD_CLK_SEL_30MHZ: 650 priv->ucan.can.clock.freq = 30 * 1000 * 1000; 651 break; 652 case CANFD_CLK_SEL_40MHZ: 653 priv->ucan.can.clock.freq = 40 * 1000 * 1000; 654 break; 655 case CANFD_CLK_SEL_60MHZ: 656 priv->ucan.can.clock.freq = 60 * 1000 * 1000; 657 break; 658 default: 659 pciefd_can_writereg(priv, CANFD_CLK_SEL_80MHZ, 660 PCIEFD_REG_CAN_CLK_SEL); 661 662 /* fall through */ 663 case CANFD_CLK_SEL_80MHZ: 664 priv->ucan.can.clock.freq = 80 * 1000 * 1000; 665 break; 666 } 667 668 ndev->irq = pciefd->pci_dev->irq; 669 670 SET_NETDEV_DEV(ndev, &pciefd->pci_dev->dev); 671 672 err = register_candev(ndev); 673 if (err) { 674 dev_err(&pciefd->pci_dev->dev, 675 "couldn't register CAN device: %d\n", err); 676 goto err_free_candev; 677 } 678 679 spin_lock_init(&priv->tx_lock); 680 681 /* save the object address in the board structure */ 682 pciefd->can[pciefd->can_count] = priv; 683 684 dev_info(&pciefd->pci_dev->dev, "%s at reg_base=0x%p irq=%d\n", 685 ndev->name, priv->reg_base, ndev->irq); 686 687 return 0; 688 689 err_free_candev: 690 free_candev(ndev); 691 692 failure: 693 return -ENOMEM; 694 } 695 696 /* remove a CAN-FD channel by releasing all of its resources */ 697 static void pciefd_can_remove(struct pciefd_can *priv) 698 { 699 /* unregister (close) the can device to go back to RST mode first */ 700 unregister_candev(priv->ucan.ndev); 701 702 /* finally, free the candev object */ 703 free_candev(priv->ucan.ndev); 704 } 705 706 /* remove all CAN-FD channels by releasing their own resources */ 707 static void pciefd_can_remove_all(struct pciefd_board *pciefd) 708 { 709 while (pciefd->can_count > 0) 710 pciefd_can_remove(pciefd->can[--pciefd->can_count]); 711 } 712 713 /* probe for the entire device */ 714 static int peak_pciefd_probe(struct pci_dev *pdev, 715 const struct pci_device_id *ent) 716 { 717 struct pciefd_board *pciefd; 718 int err, can_count; 719 u16 sub_sys_id; 720 u8 hw_ver_major; 721 u8 hw_ver_minor; 722 u8 hw_ver_sub; 723 u32 v2; 724 725 err = pci_enable_device(pdev); 726 if (err) 727 return err; 728 err = pci_request_regions(pdev, PCIEFD_DRV_NAME); 729 if (err) 730 goto err_disable_pci; 731 732 /* the number of channels depends on sub-system id */ 733 err = pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sub_sys_id); 734 if (err) 735 goto err_release_regions; 736 737 dev_dbg(&pdev->dev, "probing device %04x:%04x:%04x\n", 738 pdev->vendor, pdev->device, sub_sys_id); 739 740 if (sub_sys_id >= 0x0012) 741 can_count = 4; 742 else if (sub_sys_id >= 0x0010) 743 can_count = 3; 744 else if (sub_sys_id >= 0x0004) 745 can_count = 2; 746 else 747 can_count = 1; 748 749 /* allocate board structure object */ 750 pciefd = devm_kzalloc(&pdev->dev, struct_size(pciefd, can, can_count), 751 GFP_KERNEL); 752 if (!pciefd) { 753 err = -ENOMEM; 754 goto err_release_regions; 755 } 756 757 /* initialize the board structure */ 758 pciefd->pci_dev = pdev; 759 spin_lock_init(&pciefd->cmd_lock); 760 761 /* save the PCI BAR0 virtual address for further system regs access */ 762 pciefd->reg_base = pci_iomap(pdev, 0, PCIEFD_BAR0_SIZE); 763 if (!pciefd->reg_base) { 764 dev_err(&pdev->dev, "failed to map PCI resource #0\n"); 765 err = -ENOMEM; 766 goto err_release_regions; 767 } 768 769 /* read the firmware version number */ 770 v2 = pciefd_sys_readreg(pciefd, PCIEFD_REG_SYS_VER2); 771 772 hw_ver_major = (v2 & 0x0000f000) >> 12; 773 hw_ver_minor = (v2 & 0x00000f00) >> 8; 774 hw_ver_sub = (v2 & 0x000000f0) >> 4; 775 776 dev_info(&pdev->dev, 777 "%ux CAN-FD PCAN-PCIe FPGA v%u.%u.%u:\n", can_count, 778 hw_ver_major, hw_ver_minor, hw_ver_sub); 779 780 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 781 /* FW < v3.3.0 DMA logic doesn't handle correctly the mix of 32-bit and 782 * 64-bit logical addresses: this workaround forces usage of 32-bit 783 * DMA addresses only when such a fw is detected. 784 */ 785 if (PCIEFD_FW_VERSION(hw_ver_major, hw_ver_minor, hw_ver_sub) < 786 PCIEFD_FW_VERSION(3, 3, 0)) { 787 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 788 if (err) 789 dev_warn(&pdev->dev, 790 "warning: can't set DMA mask %llxh (err %d)\n", 791 DMA_BIT_MASK(32), err); 792 } 793 #endif 794 795 /* stop system clock */ 796 pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_CLK_EN, 797 PCIEFD_REG_SYS_CTL_CLR); 798 799 pci_set_master(pdev); 800 801 /* create now the corresponding channels objects */ 802 while (pciefd->can_count < can_count) { 803 err = pciefd_can_probe(pciefd); 804 if (err) 805 goto err_free_canfd; 806 807 pciefd->can_count++; 808 } 809 810 /* set system timestamps counter in RST mode */ 811 pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_TS_RST, 812 PCIEFD_REG_SYS_CTL_SET); 813 814 /* wait a bit (read cycle) */ 815 (void)pciefd_sys_readreg(pciefd, PCIEFD_REG_SYS_VER1); 816 817 /* free all clocks */ 818 pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_TS_RST, 819 PCIEFD_REG_SYS_CTL_CLR); 820 821 /* start system clock */ 822 pciefd_sys_writereg(pciefd, PCIEFD_SYS_CTL_CLK_EN, 823 PCIEFD_REG_SYS_CTL_SET); 824 825 /* remember the board structure address in the device user data */ 826 pci_set_drvdata(pdev, pciefd); 827 828 return 0; 829 830 err_free_canfd: 831 pciefd_can_remove_all(pciefd); 832 833 pci_iounmap(pdev, pciefd->reg_base); 834 835 err_release_regions: 836 pci_release_regions(pdev); 837 838 err_disable_pci: 839 pci_disable_device(pdev); 840 841 /* pci_xxx_config_word() return positive PCIBIOS_xxx error codes while 842 * the probe() function must return a negative errno in case of failure 843 * (err is unchanged if negative) 844 */ 845 return pcibios_err_to_errno(err); 846 } 847 848 /* free the board structure object, as well as its resources: */ 849 static void peak_pciefd_remove(struct pci_dev *pdev) 850 { 851 struct pciefd_board *pciefd = pci_get_drvdata(pdev); 852 853 /* release CAN-FD channels resources */ 854 pciefd_can_remove_all(pciefd); 855 856 pci_iounmap(pdev, pciefd->reg_base); 857 858 pci_release_regions(pdev); 859 pci_disable_device(pdev); 860 } 861 862 static struct pci_driver peak_pciefd_driver = { 863 .name = PCIEFD_DRV_NAME, 864 .id_table = peak_pciefd_tbl, 865 .probe = peak_pciefd_probe, 866 .remove = peak_pciefd_remove, 867 }; 868 869 module_pci_driver(peak_pciefd_driver); 870