1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 ethernet0 = &gmac2io; 31 ethernet1 = &gmac2phy; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 cpu0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0x0 0x0>; 42 clocks = <&cru ARMCLK>; 43 #cooling-cells = <2>; 44 cpu-idle-states = <&CPU_SLEEP>; 45 dynamic-power-coefficient = <120>; 46 enable-method = "psci"; 47 next-level-cache = <&l2>; 48 operating-points-v2 = <&cpu0_opp_table>; 49 }; 50 51 cpu1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0x0 0x1>; 55 clocks = <&cru ARMCLK>; 56 #cooling-cells = <2>; 57 cpu-idle-states = <&CPU_SLEEP>; 58 dynamic-power-coefficient = <120>; 59 enable-method = "psci"; 60 next-level-cache = <&l2>; 61 operating-points-v2 = <&cpu0_opp_table>; 62 }; 63 64 cpu2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x0 0x2>; 68 clocks = <&cru ARMCLK>; 69 #cooling-cells = <2>; 70 cpu-idle-states = <&CPU_SLEEP>; 71 dynamic-power-coefficient = <120>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 operating-points-v2 = <&cpu0_opp_table>; 75 }; 76 77 cpu3: cpu@3 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a53"; 80 reg = <0x0 0x3>; 81 clocks = <&cru ARMCLK>; 82 #cooling-cells = <2>; 83 cpu-idle-states = <&CPU_SLEEP>; 84 dynamic-power-coefficient = <120>; 85 enable-method = "psci"; 86 next-level-cache = <&l2>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 90 idle-states { 91 entry-method = "psci"; 92 93 CPU_SLEEP: cpu-sleep { 94 compatible = "arm,idle-state"; 95 local-timer-stop; 96 arm,psci-suspend-param = <0x0010000>; 97 entry-latency-us = <120>; 98 exit-latency-us = <250>; 99 min-residency-us = <900>; 100 }; 101 }; 102 103 l2: l2-cache0 { 104 compatible = "cache"; 105 }; 106 }; 107 108 cpu0_opp_table: opp_table0 { 109 compatible = "operating-points-v2"; 110 opp-shared; 111 112 opp-408000000 { 113 opp-hz = /bits/ 64 <408000000>; 114 opp-microvolt = <950000>; 115 clock-latency-ns = <40000>; 116 opp-suspend; 117 }; 118 opp-600000000 { 119 opp-hz = /bits/ 64 <600000000>; 120 opp-microvolt = <950000>; 121 clock-latency-ns = <40000>; 122 }; 123 opp-816000000 { 124 opp-hz = /bits/ 64 <816000000>; 125 opp-microvolt = <1000000>; 126 clock-latency-ns = <40000>; 127 }; 128 opp-1008000000 { 129 opp-hz = /bits/ 64 <1008000000>; 130 opp-microvolt = <1100000>; 131 clock-latency-ns = <40000>; 132 }; 133 opp-1200000000 { 134 opp-hz = /bits/ 64 <1200000000>; 135 opp-microvolt = <1225000>; 136 clock-latency-ns = <40000>; 137 }; 138 opp-1296000000 { 139 opp-hz = /bits/ 64 <1296000000>; 140 opp-microvolt = <1300000>; 141 clock-latency-ns = <40000>; 142 }; 143 }; 144 145 amba: bus { 146 compatible = "simple-bus"; 147 #address-cells = <2>; 148 #size-cells = <2>; 149 ranges; 150 151 dmac: dmac@ff1f0000 { 152 compatible = "arm,pl330", "arm,primecell"; 153 reg = <0x0 0xff1f0000 0x0 0x4000>; 154 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&cru ACLK_DMAC>; 157 clock-names = "apb_pclk"; 158 #dma-cells = <1>; 159 }; 160 }; 161 162 analog_sound: analog-sound { 163 compatible = "simple-audio-card"; 164 simple-audio-card,format = "i2s"; 165 simple-audio-card,mclk-fs = <256>; 166 simple-audio-card,name = "Analog"; 167 status = "disabled"; 168 169 simple-audio-card,cpu { 170 sound-dai = <&i2s1>; 171 }; 172 173 simple-audio-card,codec { 174 sound-dai = <&codec>; 175 }; 176 }; 177 178 arm-pmu { 179 compatible = "arm,cortex-a53-pmu"; 180 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 184 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 185 }; 186 187 display_subsystem: display-subsystem { 188 compatible = "rockchip,display-subsystem"; 189 ports = <&vop_out>; 190 }; 191 192 hdmi_sound: hdmi-sound { 193 compatible = "simple-audio-card"; 194 simple-audio-card,format = "i2s"; 195 simple-audio-card,mclk-fs = <128>; 196 simple-audio-card,name = "HDMI"; 197 status = "disabled"; 198 199 simple-audio-card,cpu { 200 sound-dai = <&i2s0>; 201 }; 202 203 simple-audio-card,codec { 204 sound-dai = <&hdmi>; 205 }; 206 }; 207 208 psci { 209 compatible = "arm,psci-1.0", "arm,psci-0.2"; 210 method = "smc"; 211 }; 212 213 timer { 214 compatible = "arm,armv8-timer"; 215 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 216 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 217 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 218 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 219 }; 220 221 xin24m: xin24m { 222 compatible = "fixed-clock"; 223 #clock-cells = <0>; 224 clock-frequency = <24000000>; 225 clock-output-names = "xin24m"; 226 }; 227 228 i2s0: i2s@ff000000 { 229 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 230 reg = <0x0 0xff000000 0x0 0x1000>; 231 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 233 clock-names = "i2s_clk", "i2s_hclk"; 234 dmas = <&dmac 11>, <&dmac 12>; 235 dma-names = "tx", "rx"; 236 #sound-dai-cells = <0>; 237 status = "disabled"; 238 }; 239 240 i2s1: i2s@ff010000 { 241 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 242 reg = <0x0 0xff010000 0x0 0x1000>; 243 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 245 clock-names = "i2s_clk", "i2s_hclk"; 246 dmas = <&dmac 14>, <&dmac 15>; 247 dma-names = "tx", "rx"; 248 #sound-dai-cells = <0>; 249 status = "disabled"; 250 }; 251 252 i2s2: i2s@ff020000 { 253 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 254 reg = <0x0 0xff020000 0x0 0x1000>; 255 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 257 clock-names = "i2s_clk", "i2s_hclk"; 258 dmas = <&dmac 0>, <&dmac 1>; 259 dma-names = "tx", "rx"; 260 #sound-dai-cells = <0>; 261 status = "disabled"; 262 }; 263 264 spdif: spdif@ff030000 { 265 compatible = "rockchip,rk3328-spdif"; 266 reg = <0x0 0xff030000 0x0 0x1000>; 267 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 269 clock-names = "mclk", "hclk"; 270 dmas = <&dmac 10>; 271 dma-names = "tx"; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&spdifm2_tx>; 274 #sound-dai-cells = <0>; 275 status = "disabled"; 276 }; 277 278 pdm: pdm@ff040000 { 279 compatible = "rockchip,pdm"; 280 reg = <0x0 0xff040000 0x0 0x1000>; 281 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 282 clock-names = "pdm_clk", "pdm_hclk"; 283 dmas = <&dmac 16>; 284 dma-names = "rx"; 285 pinctrl-names = "default", "sleep"; 286 pinctrl-0 = <&pdmm0_clk 287 &pdmm0_sdi0 288 &pdmm0_sdi1 289 &pdmm0_sdi2 290 &pdmm0_sdi3>; 291 pinctrl-1 = <&pdmm0_clk_sleep 292 &pdmm0_sdi0_sleep 293 &pdmm0_sdi1_sleep 294 &pdmm0_sdi2_sleep 295 &pdmm0_sdi3_sleep>; 296 status = "disabled"; 297 }; 298 299 grf: syscon@ff100000 { 300 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 301 reg = <0x0 0xff100000 0x0 0x1000>; 302 #address-cells = <1>; 303 #size-cells = <1>; 304 305 io_domains: io-domains { 306 compatible = "rockchip,rk3328-io-voltage-domain"; 307 status = "disabled"; 308 }; 309 310 grf_gpio: grf-gpio { 311 compatible = "rockchip,rk3328-grf-gpio"; 312 gpio-controller; 313 #gpio-cells = <2>; 314 }; 315 316 power: power-controller { 317 compatible = "rockchip,rk3328-power-controller"; 318 #power-domain-cells = <1>; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 322 pd_hevc@RK3328_PD_HEVC { 323 reg = <RK3328_PD_HEVC>; 324 }; 325 pd_video@RK3328_PD_VIDEO { 326 reg = <RK3328_PD_VIDEO>; 327 }; 328 pd_vpu@RK3328_PD_VPU { 329 reg = <RK3328_PD_VPU>; 330 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 331 }; 332 }; 333 334 reboot-mode { 335 compatible = "syscon-reboot-mode"; 336 offset = <0x5c8>; 337 mode-normal = <BOOT_NORMAL>; 338 mode-recovery = <BOOT_RECOVERY>; 339 mode-bootloader = <BOOT_FASTBOOT>; 340 mode-loader = <BOOT_BL_DOWNLOAD>; 341 }; 342 }; 343 344 uart0: serial@ff110000 { 345 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 346 reg = <0x0 0xff110000 0x0 0x100>; 347 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 349 clock-names = "baudclk", "apb_pclk"; 350 dmas = <&dmac 2>, <&dmac 3>; 351 dma-names = "tx", "rx"; 352 pinctrl-names = "default"; 353 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 354 reg-io-width = <4>; 355 reg-shift = <2>; 356 status = "disabled"; 357 }; 358 359 uart1: serial@ff120000 { 360 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 361 reg = <0x0 0xff120000 0x0 0x100>; 362 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 364 clock-names = "baudclk", "apb_pclk"; 365 dmas = <&dmac 4>, <&dmac 5>; 366 dma-names = "tx", "rx"; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 369 reg-io-width = <4>; 370 reg-shift = <2>; 371 status = "disabled"; 372 }; 373 374 uart2: serial@ff130000 { 375 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 376 reg = <0x0 0xff130000 0x0 0x100>; 377 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 379 clock-names = "baudclk", "apb_pclk"; 380 dmas = <&dmac 6>, <&dmac 7>; 381 dma-names = "tx", "rx"; 382 pinctrl-names = "default"; 383 pinctrl-0 = <&uart2m1_xfer>; 384 reg-io-width = <4>; 385 reg-shift = <2>; 386 status = "disabled"; 387 }; 388 389 i2c0: i2c@ff150000 { 390 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 391 reg = <0x0 0xff150000 0x0 0x1000>; 392 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 393 #address-cells = <1>; 394 #size-cells = <0>; 395 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 396 clock-names = "i2c", "pclk"; 397 pinctrl-names = "default"; 398 pinctrl-0 = <&i2c0_xfer>; 399 status = "disabled"; 400 }; 401 402 i2c1: i2c@ff160000 { 403 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 404 reg = <0x0 0xff160000 0x0 0x1000>; 405 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 409 clock-names = "i2c", "pclk"; 410 pinctrl-names = "default"; 411 pinctrl-0 = <&i2c1_xfer>; 412 status = "disabled"; 413 }; 414 415 i2c2: i2c@ff170000 { 416 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 417 reg = <0x0 0xff170000 0x0 0x1000>; 418 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 422 clock-names = "i2c", "pclk"; 423 pinctrl-names = "default"; 424 pinctrl-0 = <&i2c2_xfer>; 425 status = "disabled"; 426 }; 427 428 i2c3: i2c@ff180000 { 429 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 430 reg = <0x0 0xff180000 0x0 0x1000>; 431 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 435 clock-names = "i2c", "pclk"; 436 pinctrl-names = "default"; 437 pinctrl-0 = <&i2c3_xfer>; 438 status = "disabled"; 439 }; 440 441 spi0: spi@ff190000 { 442 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 443 reg = <0x0 0xff190000 0x0 0x1000>; 444 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 448 clock-names = "spiclk", "apb_pclk"; 449 dmas = <&dmac 8>, <&dmac 9>; 450 dma-names = "tx", "rx"; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 453 status = "disabled"; 454 }; 455 456 wdt: watchdog@ff1a0000 { 457 compatible = "snps,dw-wdt"; 458 reg = <0x0 0xff1a0000 0x0 0x100>; 459 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&cru PCLK_WDT>; 461 }; 462 463 pwm0: pwm@ff1b0000 { 464 compatible = "rockchip,rk3328-pwm"; 465 reg = <0x0 0xff1b0000 0x0 0x10>; 466 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 467 clock-names = "pwm", "pclk"; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&pwm0_pin>; 470 #pwm-cells = <3>; 471 status = "disabled"; 472 }; 473 474 pwm1: pwm@ff1b0010 { 475 compatible = "rockchip,rk3328-pwm"; 476 reg = <0x0 0xff1b0010 0x0 0x10>; 477 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 478 clock-names = "pwm", "pclk"; 479 pinctrl-names = "default"; 480 pinctrl-0 = <&pwm1_pin>; 481 #pwm-cells = <3>; 482 status = "disabled"; 483 }; 484 485 pwm2: pwm@ff1b0020 { 486 compatible = "rockchip,rk3328-pwm"; 487 reg = <0x0 0xff1b0020 0x0 0x10>; 488 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 489 clock-names = "pwm", "pclk"; 490 pinctrl-names = "default"; 491 pinctrl-0 = <&pwm2_pin>; 492 #pwm-cells = <3>; 493 status = "disabled"; 494 }; 495 496 pwm3: pwm@ff1b0030 { 497 compatible = "rockchip,rk3328-pwm"; 498 reg = <0x0 0xff1b0030 0x0 0x10>; 499 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 501 clock-names = "pwm", "pclk"; 502 pinctrl-names = "default"; 503 pinctrl-0 = <&pwmir_pin>; 504 #pwm-cells = <3>; 505 status = "disabled"; 506 }; 507 508 thermal-zones { 509 soc_thermal: soc-thermal { 510 polling-delay-passive = <20>; 511 polling-delay = <1000>; 512 sustainable-power = <1000>; 513 514 thermal-sensors = <&tsadc 0>; 515 516 trips { 517 threshold: trip-point0 { 518 temperature = <70000>; 519 hysteresis = <2000>; 520 type = "passive"; 521 }; 522 target: trip-point1 { 523 temperature = <85000>; 524 hysteresis = <2000>; 525 type = "passive"; 526 }; 527 soc_crit: soc-crit { 528 temperature = <95000>; 529 hysteresis = <2000>; 530 type = "critical"; 531 }; 532 }; 533 534 cooling-maps { 535 map0 { 536 trip = <&target>; 537 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 538 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 539 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 540 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 541 contribution = <4096>; 542 }; 543 }; 544 }; 545 546 }; 547 548 tsadc: tsadc@ff250000 { 549 compatible = "rockchip,rk3328-tsadc"; 550 reg = <0x0 0xff250000 0x0 0x100>; 551 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 552 assigned-clocks = <&cru SCLK_TSADC>; 553 assigned-clock-rates = <50000>; 554 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 555 clock-names = "tsadc", "apb_pclk"; 556 pinctrl-names = "init", "default", "sleep"; 557 pinctrl-0 = <&otp_gpio>; 558 pinctrl-1 = <&otp_out>; 559 pinctrl-2 = <&otp_gpio>; 560 resets = <&cru SRST_TSADC>; 561 reset-names = "tsadc-apb"; 562 rockchip,grf = <&grf>; 563 rockchip,hw-tshut-temp = <100000>; 564 #thermal-sensor-cells = <1>; 565 status = "disabled"; 566 }; 567 568 efuse: efuse@ff260000 { 569 compatible = "rockchip,rk3328-efuse"; 570 reg = <0x0 0xff260000 0x0 0x50>; 571 #address-cells = <1>; 572 #size-cells = <1>; 573 clocks = <&cru SCLK_EFUSE>; 574 clock-names = "pclk_efuse"; 575 rockchip,efuse-size = <0x20>; 576 577 /* Data cells */ 578 efuse_id: id@7 { 579 reg = <0x07 0x10>; 580 }; 581 cpu_leakage: cpu-leakage@17 { 582 reg = <0x17 0x1>; 583 }; 584 logic_leakage: logic-leakage@19 { 585 reg = <0x19 0x1>; 586 }; 587 efuse_cpu_version: cpu-version@1a { 588 reg = <0x1a 0x1>; 589 bits = <3 3>; 590 }; 591 }; 592 593 saradc: adc@ff280000 { 594 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 595 reg = <0x0 0xff280000 0x0 0x100>; 596 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 597 #io-channel-cells = <1>; 598 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 599 clock-names = "saradc", "apb_pclk"; 600 resets = <&cru SRST_SARADC_P>; 601 reset-names = "saradc-apb"; 602 status = "disabled"; 603 }; 604 605 gpu: gpu@ff300000 { 606 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 607 reg = <0x0 0xff300000 0x0 0x40000>; 608 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 615 interrupt-names = "gp", 616 "gpmmu", 617 "pp", 618 "pp0", 619 "ppmmu0", 620 "pp1", 621 "ppmmu1"; 622 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 623 clock-names = "bus", "core"; 624 resets = <&cru SRST_GPU_A>; 625 }; 626 627 h265e_mmu: iommu@ff330200 { 628 compatible = "rockchip,iommu"; 629 reg = <0x0 0xff330200 0 0x100>; 630 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 631 interrupt-names = "h265e_mmu"; 632 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 633 clock-names = "aclk", "iface"; 634 #iommu-cells = <0>; 635 status = "disabled"; 636 }; 637 638 vepu_mmu: iommu@ff340800 { 639 compatible = "rockchip,iommu"; 640 reg = <0x0 0xff340800 0x0 0x40>; 641 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 642 interrupt-names = "vepu_mmu"; 643 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 644 clock-names = "aclk", "iface"; 645 #iommu-cells = <0>; 646 status = "disabled"; 647 }; 648 649 vpu: video-codec@ff350000 { 650 compatible = "rockchip,rk3328-vpu"; 651 reg = <0x0 0xff350000 0x0 0x800>; 652 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 653 interrupt-names = "vdpu"; 654 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 655 clock-names = "aclk", "hclk"; 656 iommus = <&vpu_mmu>; 657 power-domains = <&power RK3328_PD_VPU>; 658 }; 659 660 vpu_mmu: iommu@ff350800 { 661 compatible = "rockchip,iommu"; 662 reg = <0x0 0xff350800 0x0 0x40>; 663 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 664 interrupt-names = "vpu_mmu"; 665 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 666 clock-names = "aclk", "iface"; 667 #iommu-cells = <0>; 668 power-domains = <&power RK3328_PD_VPU>; 669 }; 670 671 rkvdec_mmu: iommu@ff360480 { 672 compatible = "rockchip,iommu"; 673 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 674 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 675 interrupt-names = "rkvdec_mmu"; 676 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 677 clock-names = "aclk", "iface"; 678 #iommu-cells = <0>; 679 status = "disabled"; 680 }; 681 682 vop: vop@ff370000 { 683 compatible = "rockchip,rk3328-vop"; 684 reg = <0x0 0xff370000 0x0 0x3efc>; 685 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 687 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 688 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 689 reset-names = "axi", "ahb", "dclk"; 690 iommus = <&vop_mmu>; 691 status = "disabled"; 692 693 vop_out: port { 694 #address-cells = <1>; 695 #size-cells = <0>; 696 697 vop_out_hdmi: endpoint@0 { 698 reg = <0>; 699 remote-endpoint = <&hdmi_in_vop>; 700 }; 701 }; 702 }; 703 704 vop_mmu: iommu@ff373f00 { 705 compatible = "rockchip,iommu"; 706 reg = <0x0 0xff373f00 0x0 0x100>; 707 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 708 interrupt-names = "vop_mmu"; 709 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 710 clock-names = "aclk", "iface"; 711 #iommu-cells = <0>; 712 status = "disabled"; 713 }; 714 715 hdmi: hdmi@ff3c0000 { 716 compatible = "rockchip,rk3328-dw-hdmi"; 717 reg = <0x0 0xff3c0000 0x0 0x20000>; 718 reg-io-width = <4>; 719 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&cru PCLK_HDMI>, 722 <&cru SCLK_HDMI_SFC>, 723 <&cru SCLK_RTC32K>; 724 clock-names = "iahb", 725 "isfr", 726 "cec"; 727 phys = <&hdmiphy>; 728 phy-names = "hdmi"; 729 pinctrl-names = "default"; 730 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 731 rockchip,grf = <&grf>; 732 #sound-dai-cells = <0>; 733 status = "disabled"; 734 735 ports { 736 hdmi_in: port { 737 hdmi_in_vop: endpoint { 738 remote-endpoint = <&vop_out_hdmi>; 739 }; 740 }; 741 }; 742 }; 743 744 codec: codec@ff410000 { 745 compatible = "rockchip,rk3328-codec"; 746 reg = <0x0 0xff410000 0x0 0x1000>; 747 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 748 clock-names = "pclk", "mclk"; 749 rockchip,grf = <&grf>; 750 #sound-dai-cells = <0>; 751 status = "disabled"; 752 }; 753 754 hdmiphy: phy@ff430000 { 755 compatible = "rockchip,rk3328-hdmi-phy"; 756 reg = <0x0 0xff430000 0x0 0x10000>; 757 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 759 clock-names = "sysclk", "refoclk", "refpclk"; 760 clock-output-names = "hdmi_phy"; 761 #clock-cells = <0>; 762 nvmem-cells = <&efuse_cpu_version>; 763 nvmem-cell-names = "cpu-version"; 764 #phy-cells = <0>; 765 status = "disabled"; 766 }; 767 768 cru: clock-controller@ff440000 { 769 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 770 reg = <0x0 0xff440000 0x0 0x1000>; 771 rockchip,grf = <&grf>; 772 #clock-cells = <1>; 773 #reset-cells = <1>; 774 assigned-clocks = 775 /* 776 * CPLL should run at 1200, but that is to high for 777 * the initial dividers of most of its children. 778 * We need set cpll child clk div first, 779 * and then set the cpll frequency. 780 */ 781 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 782 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 783 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 784 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 785 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 786 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 787 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 788 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 789 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 790 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 791 <&cru SCLK_WIFI>, <&cru ARMCLK>, 792 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 793 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 794 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 795 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 796 <&cru SCLK_RTC32K>; 797 assigned-clock-parents = 798 <&cru HDMIPHY>, <&cru PLL_APLL>, 799 <&cru PLL_GPLL>, <&xin24m>, 800 <&xin24m>, <&xin24m>; 801 assigned-clock-rates = 802 <0>, <61440000>, 803 <0>, <24000000>, 804 <24000000>, <24000000>, 805 <15000000>, <15000000>, 806 <100000000>, <100000000>, 807 <100000000>, <100000000>, 808 <50000000>, <100000000>, 809 <100000000>, <100000000>, 810 <50000000>, <50000000>, 811 <50000000>, <50000000>, 812 <24000000>, <600000000>, 813 <491520000>, <1200000000>, 814 <150000000>, <75000000>, 815 <75000000>, <150000000>, 816 <75000000>, <75000000>, 817 <32768>; 818 }; 819 820 usb2phy_grf: syscon@ff450000 { 821 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 822 "simple-mfd"; 823 reg = <0x0 0xff450000 0x0 0x10000>; 824 #address-cells = <1>; 825 #size-cells = <1>; 826 827 u2phy: usb2-phy@100 { 828 compatible = "rockchip,rk3328-usb2phy"; 829 reg = <0x100 0x10>; 830 clocks = <&xin24m>; 831 clock-names = "phyclk"; 832 clock-output-names = "usb480m_phy"; 833 #clock-cells = <0>; 834 assigned-clocks = <&cru USB480M>; 835 assigned-clock-parents = <&u2phy>; 836 status = "disabled"; 837 838 u2phy_otg: otg-port { 839 #phy-cells = <0>; 840 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 843 interrupt-names = "otg-bvalid", "otg-id", 844 "linestate"; 845 status = "disabled"; 846 }; 847 848 u2phy_host: host-port { 849 #phy-cells = <0>; 850 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 851 interrupt-names = "linestate"; 852 status = "disabled"; 853 }; 854 }; 855 }; 856 857 sdmmc: mmc@ff500000 { 858 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 859 reg = <0x0 0xff500000 0x0 0x4000>; 860 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 862 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 863 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 864 fifo-depth = <0x100>; 865 max-frequency = <150000000>; 866 status = "disabled"; 867 }; 868 869 sdio: mmc@ff510000 { 870 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 871 reg = <0x0 0xff510000 0x0 0x4000>; 872 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 873 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 874 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 875 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 876 fifo-depth = <0x100>; 877 max-frequency = <150000000>; 878 status = "disabled"; 879 }; 880 881 emmc: mmc@ff520000 { 882 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 883 reg = <0x0 0xff520000 0x0 0x4000>; 884 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 886 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 887 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 888 fifo-depth = <0x100>; 889 max-frequency = <150000000>; 890 status = "disabled"; 891 }; 892 893 gmac2io: ethernet@ff540000 { 894 compatible = "rockchip,rk3328-gmac"; 895 reg = <0x0 0xff540000 0x0 0x10000>; 896 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 897 interrupt-names = "macirq"; 898 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 899 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 900 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 901 <&cru PCLK_MAC2IO>; 902 clock-names = "stmmaceth", "mac_clk_rx", 903 "mac_clk_tx", "clk_mac_ref", 904 "clk_mac_refout", "aclk_mac", 905 "pclk_mac"; 906 resets = <&cru SRST_GMAC2IO_A>; 907 reset-names = "stmmaceth"; 908 rockchip,grf = <&grf>; 909 snps,txpbl = <0x4>; 910 status = "disabled"; 911 }; 912 913 gmac2phy: ethernet@ff550000 { 914 compatible = "rockchip,rk3328-gmac"; 915 reg = <0x0 0xff550000 0x0 0x10000>; 916 rockchip,grf = <&grf>; 917 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 918 interrupt-names = "macirq"; 919 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 920 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 921 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 922 <&cru SCLK_MAC2PHY_OUT>; 923 clock-names = "stmmaceth", "mac_clk_rx", 924 "mac_clk_tx", "clk_mac_ref", 925 "aclk_mac", "pclk_mac", 926 "clk_macphy"; 927 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; 928 reset-names = "stmmaceth", "mac-phy"; 929 phy-mode = "rmii"; 930 phy-handle = <&phy>; 931 snps,txpbl = <0x4>; 932 status = "disabled"; 933 934 mdio { 935 compatible = "snps,dwmac-mdio"; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 939 phy: phy@0 { 940 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 941 reg = <0>; 942 clocks = <&cru SCLK_MAC2PHY_OUT>; 943 resets = <&cru SRST_MACPHY>; 944 pinctrl-names = "default"; 945 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 946 phy-is-integrated; 947 }; 948 }; 949 }; 950 951 usb20_otg: usb@ff580000 { 952 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 953 "snps,dwc2"; 954 reg = <0x0 0xff580000 0x0 0x40000>; 955 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 956 clocks = <&cru HCLK_OTG>; 957 clock-names = "otg"; 958 dr_mode = "otg"; 959 g-np-tx-fifo-size = <16>; 960 g-rx-fifo-size = <280>; 961 g-tx-fifo-size = <256 128 128 64 32 16>; 962 phys = <&u2phy_otg>; 963 phy-names = "usb2-phy"; 964 status = "disabled"; 965 }; 966 967 usb_host0_ehci: usb@ff5c0000 { 968 compatible = "generic-ehci"; 969 reg = <0x0 0xff5c0000 0x0 0x10000>; 970 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&cru HCLK_HOST0>, <&u2phy>; 972 phys = <&u2phy_host>; 973 phy-names = "usb"; 974 status = "disabled"; 975 }; 976 977 usb_host0_ohci: usb@ff5d0000 { 978 compatible = "generic-ohci"; 979 reg = <0x0 0xff5d0000 0x0 0x10000>; 980 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 981 clocks = <&cru HCLK_HOST0>, <&u2phy>; 982 phys = <&u2phy_host>; 983 phy-names = "usb"; 984 status = "disabled"; 985 }; 986 987 gic: interrupt-controller@ff811000 { 988 compatible = "arm,gic-400"; 989 #interrupt-cells = <3>; 990 #address-cells = <0>; 991 interrupt-controller; 992 reg = <0x0 0xff811000 0 0x1000>, 993 <0x0 0xff812000 0 0x2000>, 994 <0x0 0xff814000 0 0x2000>, 995 <0x0 0xff816000 0 0x2000>; 996 interrupts = <GIC_PPI 9 997 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 998 }; 999 1000 pinctrl: pinctrl { 1001 compatible = "rockchip,rk3328-pinctrl"; 1002 rockchip,grf = <&grf>; 1003 #address-cells = <2>; 1004 #size-cells = <2>; 1005 ranges; 1006 1007 gpio0: gpio0@ff210000 { 1008 compatible = "rockchip,gpio-bank"; 1009 reg = <0x0 0xff210000 0x0 0x100>; 1010 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&cru PCLK_GPIO0>; 1012 1013 gpio-controller; 1014 #gpio-cells = <2>; 1015 1016 interrupt-controller; 1017 #interrupt-cells = <2>; 1018 }; 1019 1020 gpio1: gpio1@ff220000 { 1021 compatible = "rockchip,gpio-bank"; 1022 reg = <0x0 0xff220000 0x0 0x100>; 1023 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1024 clocks = <&cru PCLK_GPIO1>; 1025 1026 gpio-controller; 1027 #gpio-cells = <2>; 1028 1029 interrupt-controller; 1030 #interrupt-cells = <2>; 1031 }; 1032 1033 gpio2: gpio2@ff230000 { 1034 compatible = "rockchip,gpio-bank"; 1035 reg = <0x0 0xff230000 0x0 0x100>; 1036 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&cru PCLK_GPIO2>; 1038 1039 gpio-controller; 1040 #gpio-cells = <2>; 1041 1042 interrupt-controller; 1043 #interrupt-cells = <2>; 1044 }; 1045 1046 gpio3: gpio3@ff240000 { 1047 compatible = "rockchip,gpio-bank"; 1048 reg = <0x0 0xff240000 0x0 0x100>; 1049 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1050 clocks = <&cru PCLK_GPIO3>; 1051 1052 gpio-controller; 1053 #gpio-cells = <2>; 1054 1055 interrupt-controller; 1056 #interrupt-cells = <2>; 1057 }; 1058 1059 pcfg_pull_up: pcfg-pull-up { 1060 bias-pull-up; 1061 }; 1062 1063 pcfg_pull_down: pcfg-pull-down { 1064 bias-pull-down; 1065 }; 1066 1067 pcfg_pull_none: pcfg-pull-none { 1068 bias-disable; 1069 }; 1070 1071 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1072 bias-disable; 1073 drive-strength = <2>; 1074 }; 1075 1076 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1077 bias-pull-up; 1078 drive-strength = <2>; 1079 }; 1080 1081 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1082 bias-pull-up; 1083 drive-strength = <4>; 1084 }; 1085 1086 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1087 bias-disable; 1088 drive-strength = <4>; 1089 }; 1090 1091 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1092 bias-pull-down; 1093 drive-strength = <4>; 1094 }; 1095 1096 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1097 bias-disable; 1098 drive-strength = <8>; 1099 }; 1100 1101 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1102 bias-pull-up; 1103 drive-strength = <8>; 1104 }; 1105 1106 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1107 bias-disable; 1108 drive-strength = <12>; 1109 }; 1110 1111 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1112 bias-pull-up; 1113 drive-strength = <12>; 1114 }; 1115 1116 pcfg_output_high: pcfg-output-high { 1117 output-high; 1118 }; 1119 1120 pcfg_output_low: pcfg-output-low { 1121 output-low; 1122 }; 1123 1124 pcfg_input_high: pcfg-input-high { 1125 bias-pull-up; 1126 input-enable; 1127 }; 1128 1129 pcfg_input: pcfg-input { 1130 input-enable; 1131 }; 1132 1133 i2c0 { 1134 i2c0_xfer: i2c0-xfer { 1135 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1136 <2 RK_PD1 1 &pcfg_pull_none>; 1137 }; 1138 }; 1139 1140 i2c1 { 1141 i2c1_xfer: i2c1-xfer { 1142 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1143 <2 RK_PA5 2 &pcfg_pull_none>; 1144 }; 1145 }; 1146 1147 i2c2 { 1148 i2c2_xfer: i2c2-xfer { 1149 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1150 <2 RK_PB6 1 &pcfg_pull_none>; 1151 }; 1152 }; 1153 1154 i2c3 { 1155 i2c3_xfer: i2c3-xfer { 1156 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1157 <0 RK_PA6 2 &pcfg_pull_none>; 1158 }; 1159 i2c3_gpio: i2c3-gpio { 1160 rockchip,pins = 1161 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1162 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1163 }; 1164 }; 1165 1166 hdmi_i2c { 1167 hdmii2c_xfer: hdmii2c-xfer { 1168 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1169 <0 RK_PA6 1 &pcfg_pull_none>; 1170 }; 1171 }; 1172 1173 pdm-0 { 1174 pdmm0_clk: pdmm0-clk { 1175 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1176 }; 1177 1178 pdmm0_fsync: pdmm0-fsync { 1179 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1180 }; 1181 1182 pdmm0_sdi0: pdmm0-sdi0 { 1183 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1184 }; 1185 1186 pdmm0_sdi1: pdmm0-sdi1 { 1187 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1188 }; 1189 1190 pdmm0_sdi2: pdmm0-sdi2 { 1191 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1192 }; 1193 1194 pdmm0_sdi3: pdmm0-sdi3 { 1195 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1196 }; 1197 1198 pdmm0_clk_sleep: pdmm0-clk-sleep { 1199 rockchip,pins = 1200 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1201 }; 1202 1203 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1204 rockchip,pins = 1205 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1206 }; 1207 1208 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1209 rockchip,pins = 1210 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1211 }; 1212 1213 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1214 rockchip,pins = 1215 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1216 }; 1217 1218 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1219 rockchip,pins = 1220 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1221 }; 1222 1223 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1224 rockchip,pins = 1225 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1226 }; 1227 }; 1228 1229 tsadc { 1230 otp_gpio: otp-gpio { 1231 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1232 }; 1233 1234 otp_out: otp-out { 1235 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1236 }; 1237 }; 1238 1239 uart0 { 1240 uart0_xfer: uart0-xfer { 1241 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>, 1242 <1 RK_PB0 1 &pcfg_pull_none>; 1243 }; 1244 1245 uart0_cts: uart0-cts { 1246 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1247 }; 1248 1249 uart0_rts: uart0-rts { 1250 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1251 }; 1252 1253 uart0_rts_gpio: uart0-rts-gpio { 1254 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1255 }; 1256 }; 1257 1258 uart1 { 1259 uart1_xfer: uart1-xfer { 1260 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>, 1261 <3 RK_PA6 4 &pcfg_pull_none>; 1262 }; 1263 1264 uart1_cts: uart1-cts { 1265 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1266 }; 1267 1268 uart1_rts: uart1-rts { 1269 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1270 }; 1271 1272 uart1_rts_gpio: uart1-rts-gpio { 1273 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1274 }; 1275 }; 1276 1277 uart2-0 { 1278 uart2m0_xfer: uart2m0-xfer { 1279 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>, 1280 <1 RK_PA1 2 &pcfg_pull_none>; 1281 }; 1282 }; 1283 1284 uart2-1 { 1285 uart2m1_xfer: uart2m1-xfer { 1286 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>, 1287 <2 RK_PA1 1 &pcfg_pull_none>; 1288 }; 1289 }; 1290 1291 spi0-0 { 1292 spi0m0_clk: spi0m0-clk { 1293 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1294 }; 1295 1296 spi0m0_cs0: spi0m0-cs0 { 1297 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1298 }; 1299 1300 spi0m0_tx: spi0m0-tx { 1301 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1302 }; 1303 1304 spi0m0_rx: spi0m0-rx { 1305 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1306 }; 1307 1308 spi0m0_cs1: spi0m0-cs1 { 1309 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1310 }; 1311 }; 1312 1313 spi0-1 { 1314 spi0m1_clk: spi0m1-clk { 1315 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1316 }; 1317 1318 spi0m1_cs0: spi0m1-cs0 { 1319 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1320 }; 1321 1322 spi0m1_tx: spi0m1-tx { 1323 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1324 }; 1325 1326 spi0m1_rx: spi0m1-rx { 1327 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1328 }; 1329 1330 spi0m1_cs1: spi0m1-cs1 { 1331 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1332 }; 1333 }; 1334 1335 spi0-2 { 1336 spi0m2_clk: spi0m2-clk { 1337 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1338 }; 1339 1340 spi0m2_cs0: spi0m2-cs0 { 1341 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1342 }; 1343 1344 spi0m2_tx: spi0m2-tx { 1345 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1346 }; 1347 1348 spi0m2_rx: spi0m2-rx { 1349 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1350 }; 1351 }; 1352 1353 i2s1 { 1354 i2s1_mclk: i2s1-mclk { 1355 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1356 }; 1357 1358 i2s1_sclk: i2s1-sclk { 1359 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1360 }; 1361 1362 i2s1_lrckrx: i2s1-lrckrx { 1363 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1364 }; 1365 1366 i2s1_lrcktx: i2s1-lrcktx { 1367 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1368 }; 1369 1370 i2s1_sdi: i2s1-sdi { 1371 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1372 }; 1373 1374 i2s1_sdo: i2s1-sdo { 1375 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1376 }; 1377 1378 i2s1_sdio1: i2s1-sdio1 { 1379 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1380 }; 1381 1382 i2s1_sdio2: i2s1-sdio2 { 1383 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1384 }; 1385 1386 i2s1_sdio3: i2s1-sdio3 { 1387 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1388 }; 1389 1390 i2s1_sleep: i2s1-sleep { 1391 rockchip,pins = 1392 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1393 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1394 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1395 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1396 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1397 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1398 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1399 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1400 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1401 }; 1402 }; 1403 1404 i2s2-0 { 1405 i2s2m0_mclk: i2s2m0-mclk { 1406 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1407 }; 1408 1409 i2s2m0_sclk: i2s2m0-sclk { 1410 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1411 }; 1412 1413 i2s2m0_lrckrx: i2s2m0-lrckrx { 1414 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1415 }; 1416 1417 i2s2m0_lrcktx: i2s2m0-lrcktx { 1418 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1419 }; 1420 1421 i2s2m0_sdi: i2s2m0-sdi { 1422 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1423 }; 1424 1425 i2s2m0_sdo: i2s2m0-sdo { 1426 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1427 }; 1428 1429 i2s2m0_sleep: i2s2m0-sleep { 1430 rockchip,pins = 1431 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1432 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1433 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1434 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1435 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1436 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1437 }; 1438 }; 1439 1440 i2s2-1 { 1441 i2s2m1_mclk: i2s2m1-mclk { 1442 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1443 }; 1444 1445 i2s2m1_sclk: i2s2m1-sclk { 1446 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1447 }; 1448 1449 i2s2m1_lrckrx: i2sm1-lrckrx { 1450 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1451 }; 1452 1453 i2s2m1_lrcktx: i2s2m1-lrcktx { 1454 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1455 }; 1456 1457 i2s2m1_sdi: i2s2m1-sdi { 1458 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1459 }; 1460 1461 i2s2m1_sdo: i2s2m1-sdo { 1462 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1463 }; 1464 1465 i2s2m1_sleep: i2s2m1-sleep { 1466 rockchip,pins = 1467 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1468 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1469 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1470 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1471 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1472 }; 1473 }; 1474 1475 spdif-0 { 1476 spdifm0_tx: spdifm0-tx { 1477 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1478 }; 1479 }; 1480 1481 spdif-1 { 1482 spdifm1_tx: spdifm1-tx { 1483 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1484 }; 1485 }; 1486 1487 spdif-2 { 1488 spdifm2_tx: spdifm2-tx { 1489 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1490 }; 1491 }; 1492 1493 sdmmc0-0 { 1494 sdmmc0m0_pwren: sdmmc0m0-pwren { 1495 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1496 }; 1497 1498 sdmmc0m0_gpio: sdmmc0m0-gpio { 1499 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1500 }; 1501 }; 1502 1503 sdmmc0-1 { 1504 sdmmc0m1_pwren: sdmmc0m1-pwren { 1505 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1506 }; 1507 1508 sdmmc0m1_gpio: sdmmc0m1-gpio { 1509 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1510 }; 1511 }; 1512 1513 sdmmc0 { 1514 sdmmc0_clk: sdmmc0-clk { 1515 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1516 }; 1517 1518 sdmmc0_cmd: sdmmc0-cmd { 1519 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1520 }; 1521 1522 sdmmc0_dectn: sdmmc0-dectn { 1523 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1524 }; 1525 1526 sdmmc0_wrprt: sdmmc0-wrprt { 1527 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1528 }; 1529 1530 sdmmc0_bus1: sdmmc0-bus1 { 1531 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1532 }; 1533 1534 sdmmc0_bus4: sdmmc0-bus4 { 1535 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1536 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1537 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1538 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1539 }; 1540 1541 sdmmc0_gpio: sdmmc0-gpio { 1542 rockchip,pins = 1543 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1544 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1545 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1546 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1547 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1548 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1549 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1550 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1551 }; 1552 }; 1553 1554 sdmmc0ext { 1555 sdmmc0ext_clk: sdmmc0ext-clk { 1556 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1557 }; 1558 1559 sdmmc0ext_cmd: sdmmc0ext-cmd { 1560 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1561 }; 1562 1563 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1564 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1565 }; 1566 1567 sdmmc0ext_dectn: sdmmc0ext-dectn { 1568 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1569 }; 1570 1571 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1572 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1573 }; 1574 1575 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1576 rockchip,pins = 1577 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1578 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1579 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1580 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1581 }; 1582 1583 sdmmc0ext_gpio: sdmmc0ext-gpio { 1584 rockchip,pins = 1585 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1586 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1587 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1588 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1589 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1590 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1591 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1592 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1593 }; 1594 }; 1595 1596 sdmmc1 { 1597 sdmmc1_clk: sdmmc1-clk { 1598 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1599 }; 1600 1601 sdmmc1_cmd: sdmmc1-cmd { 1602 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1603 }; 1604 1605 sdmmc1_pwren: sdmmc1-pwren { 1606 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1607 }; 1608 1609 sdmmc1_wrprt: sdmmc1-wrprt { 1610 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1611 }; 1612 1613 sdmmc1_dectn: sdmmc1-dectn { 1614 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1615 }; 1616 1617 sdmmc1_bus1: sdmmc1-bus1 { 1618 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1619 }; 1620 1621 sdmmc1_bus4: sdmmc1-bus4 { 1622 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1623 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1624 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1625 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1626 }; 1627 1628 sdmmc1_gpio: sdmmc1-gpio { 1629 rockchip,pins = 1630 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1631 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1632 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1633 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1634 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1635 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1636 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1637 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1638 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1639 }; 1640 }; 1641 1642 emmc { 1643 emmc_clk: emmc-clk { 1644 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1645 }; 1646 1647 emmc_cmd: emmc-cmd { 1648 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1649 }; 1650 1651 emmc_pwren: emmc-pwren { 1652 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1653 }; 1654 1655 emmc_rstnout: emmc-rstnout { 1656 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1657 }; 1658 1659 emmc_bus1: emmc-bus1 { 1660 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1661 }; 1662 1663 emmc_bus4: emmc-bus4 { 1664 rockchip,pins = 1665 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1666 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1667 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1668 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1669 }; 1670 1671 emmc_bus8: emmc-bus8 { 1672 rockchip,pins = 1673 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1674 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1675 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1676 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1677 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1678 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1679 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1680 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1681 }; 1682 }; 1683 1684 pwm0 { 1685 pwm0_pin: pwm0-pin { 1686 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1687 }; 1688 }; 1689 1690 pwm1 { 1691 pwm1_pin: pwm1-pin { 1692 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1693 }; 1694 }; 1695 1696 pwm2 { 1697 pwm2_pin: pwm2-pin { 1698 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1699 }; 1700 }; 1701 1702 pwmir { 1703 pwmir_pin: pwmir-pin { 1704 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1705 }; 1706 }; 1707 1708 gmac-1 { 1709 rgmiim1_pins: rgmiim1-pins { 1710 rockchip,pins = 1711 /* mac_txclk */ 1712 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1713 /* mac_rxclk */ 1714 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1715 /* mac_mdio */ 1716 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1717 /* mac_txen */ 1718 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1719 /* mac_clk */ 1720 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1721 /* mac_rxdv */ 1722 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1723 /* mac_mdc */ 1724 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1725 /* mac_rxd1 */ 1726 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1727 /* mac_rxd0 */ 1728 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1729 /* mac_txd1 */ 1730 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1731 /* mac_txd0 */ 1732 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1733 /* mac_rxd3 */ 1734 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1735 /* mac_rxd2 */ 1736 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1737 /* mac_txd3 */ 1738 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1739 /* mac_txd2 */ 1740 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1741 1742 /* mac_txclk */ 1743 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1744 /* mac_txen */ 1745 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1746 /* mac_clk */ 1747 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1748 /* mac_txd1 */ 1749 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1750 /* mac_txd0 */ 1751 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1752 /* mac_txd3 */ 1753 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1754 /* mac_txd2 */ 1755 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1756 }; 1757 1758 rmiim1_pins: rmiim1-pins { 1759 rockchip,pins = 1760 /* mac_mdio */ 1761 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1762 /* mac_txen */ 1763 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1764 /* mac_clk */ 1765 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1766 /* mac_rxer */ 1767 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1768 /* mac_rxdv */ 1769 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1770 /* mac_mdc */ 1771 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1772 /* mac_rxd1 */ 1773 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1774 /* mac_rxd0 */ 1775 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1776 /* mac_txd1 */ 1777 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1778 /* mac_txd0 */ 1779 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1780 1781 /* mac_mdio */ 1782 <0 RK_PB3 1 &pcfg_pull_none>, 1783 /* mac_txen */ 1784 <0 RK_PB4 1 &pcfg_pull_none>, 1785 /* mac_clk */ 1786 <0 RK_PD0 1 &pcfg_pull_none>, 1787 /* mac_mdc */ 1788 <0 RK_PC3 1 &pcfg_pull_none>, 1789 /* mac_txd1 */ 1790 <0 RK_PC0 1 &pcfg_pull_none>, 1791 /* mac_txd0 */ 1792 <0 RK_PC1 1 &pcfg_pull_none>; 1793 }; 1794 }; 1795 1796 gmac2phy { 1797 fephyled_speed100: fephyled-speed100 { 1798 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; 1799 }; 1800 1801 fephyled_speed10: fephyled-speed10 { 1802 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1803 }; 1804 1805 fephyled_duplex: fephyled-duplex { 1806 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1807 }; 1808 1809 fephyled_rxm0: fephyled-rxm0 { 1810 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>; 1811 }; 1812 1813 fephyled_txm0: fephyled-txm0 { 1814 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>; 1815 }; 1816 1817 fephyled_linkm0: fephyled-linkm0 { 1818 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; 1819 }; 1820 1821 fephyled_rxm1: fephyled-rxm1 { 1822 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1823 }; 1824 1825 fephyled_txm1: fephyled-txm1 { 1826 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1827 }; 1828 1829 fephyled_linkm1: fephyled-linkm1 { 1830 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1831 }; 1832 }; 1833 1834 tsadc_pin { 1835 tsadc_int: tsadc-int { 1836 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1837 }; 1838 tsadc_gpio: tsadc-gpio { 1839 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1840 }; 1841 }; 1842 1843 hdmi_pin { 1844 hdmi_cec: hdmi-cec { 1845 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1846 }; 1847 1848 hdmi_hpd: hdmi-hpd { 1849 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1850 }; 1851 }; 1852 1853 cif-0 { 1854 dvp_d2d9_m0:dvp-d2d9-m0 { 1855 rockchip,pins = 1856 /* cif_d0 */ 1857 <3 RK_PA4 2 &pcfg_pull_none>, 1858 /* cif_d1 */ 1859 <3 RK_PA5 2 &pcfg_pull_none>, 1860 /* cif_d2 */ 1861 <3 RK_PA6 2 &pcfg_pull_none>, 1862 /* cif_d3 */ 1863 <3 RK_PA7 2 &pcfg_pull_none>, 1864 /* cif_d4 */ 1865 <3 RK_PB0 2 &pcfg_pull_none>, 1866 /* cif_d5m0 */ 1867 <3 RK_PB1 2 &pcfg_pull_none>, 1868 /* cif_d6m0 */ 1869 <3 RK_PB2 2 &pcfg_pull_none>, 1870 /* cif_d7m0 */ 1871 <3 RK_PB3 2 &pcfg_pull_none>, 1872 /* cif_href */ 1873 <3 RK_PA1 2 &pcfg_pull_none>, 1874 /* cif_vsync */ 1875 <3 RK_PA0 2 &pcfg_pull_none>, 1876 /* cif_clkoutm0 */ 1877 <3 RK_PA3 2 &pcfg_pull_none>, 1878 /* cif_clkin */ 1879 <3 RK_PA2 2 &pcfg_pull_none>; 1880 }; 1881 }; 1882 1883 cif-1 { 1884 dvp_d2d9_m1:dvp-d2d9-m1 { 1885 rockchip,pins = 1886 /* cif_d0 */ 1887 <3 RK_PA4 2 &pcfg_pull_none>, 1888 /* cif_d1 */ 1889 <3 RK_PA5 2 &pcfg_pull_none>, 1890 /* cif_d2 */ 1891 <3 RK_PA6 2 &pcfg_pull_none>, 1892 /* cif_d3 */ 1893 <3 RK_PA7 2 &pcfg_pull_none>, 1894 /* cif_d4 */ 1895 <3 RK_PB0 2 &pcfg_pull_none>, 1896 /* cif_d5m1 */ 1897 <2 RK_PC0 4 &pcfg_pull_none>, 1898 /* cif_d6m1 */ 1899 <2 RK_PC1 4 &pcfg_pull_none>, 1900 /* cif_d7m1 */ 1901 <2 RK_PC2 4 &pcfg_pull_none>, 1902 /* cif_href */ 1903 <3 RK_PA1 2 &pcfg_pull_none>, 1904 /* cif_vsync */ 1905 <3 RK_PA0 2 &pcfg_pull_none>, 1906 /* cif_clkoutm1 */ 1907 <2 RK_PB7 4 &pcfg_pull_none>, 1908 /* cif_clkin */ 1909 <3 RK_PA2 2 &pcfg_pull_none>; 1910 }; 1911 }; 1912 }; 1913}; 1914