1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM memory mapped architected timer
8
9maintainers:
10  - Marc Zyngier <marc.zyngier@arm.com>
11  - Mark Rutland <mark.rutland@arm.com>
12
13description: |+
14  ARM cores may have a memory mapped architected timer, which provides up to 8
15  frames with a physical and optional virtual timer per frame.
16
17  The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
18
19properties:
20  compatible:
21    items:
22      - enum:
23        - arm,armv7-timer-mem
24
25  reg:
26    maxItems: 1
27    description: The control frame base address
28
29  '#address-cells':
30    enum: [1, 2]
31
32  '#size-cells':
33    const: 1
34
35  clock-frequency:
36    description: The frequency of the main counter, in Hz. Should be present
37      only where necessary to work around broken firmware which does not configure
38      CNTFRQ on all CPUs to a uniform correct value. Use of this property is
39      strongly discouraged; fix your firmware unless absolutely impossible.
40
41  always-on:
42    type: boolean
43    description: If present, the timer is powered through an always-on power
44      domain, therefore it never loses context.
45
46  arm,cpu-registers-not-fw-configured:
47    type: boolean
48    description: Firmware does not initialize any of the generic timer CPU
49      registers, which contain their architecturally-defined reset values. Only
50      supported for 32-bit systems which follow the ARMv7 architected reset
51      values.
52
53  arm,no-tick-in-suspend:
54    type: boolean
55    description: The main counter does not tick when the system is in
56      low-power system suspend on some SoCs. This behavior does not match the
57      Architecture Reference Manual's specification that the system counter "must
58      be implemented in an always-on power domain."
59
60patternProperties:
61  '^frame@[0-9a-z]*$':
62    type: object
63    description: A timer node has up to 8 frame sub-nodes, each with the following properties.
64    properties:
65      frame-number:
66        allOf:
67          - $ref: "/schemas/types.yaml#/definitions/uint32"
68          - minimum: 0
69            maximum: 7
70
71      interrupts:
72        minItems: 1
73        maxItems: 2
74        items:
75          - description: physical timer irq
76          - description: virtual timer irq
77
78      reg :
79        minItems: 1
80        maxItems: 2
81        items:
82          - description: 1st view base address
83          - description: 2nd optional view base address
84
85    required:
86      - frame-number
87      - interrupts
88      - reg
89
90required:
91  - compatible
92  - reg
93  - '#address-cells'
94  - '#size-cells'
95
96examples:
97  - |
98    timer@f0000000 {
99      compatible = "arm,armv7-timer-mem";
100      #address-cells = <1>;
101      #size-cells = <1>;
102      ranges = <0 0xf0001000 0x1000>;
103      reg = <0xf0000000 0x1000>;
104      clock-frequency = <50000000>;
105
106      frame@0 {
107        frame-number = <0>;
108        interrupts = <0 13 0x8>,
109               <0 14 0x8>;
110        reg = <0x0000 0x1000>,
111              <0x1000 0x1000>;
112      };
113
114      frame@2000 {
115        frame-number = <1>;
116        interrupts = <0 15 0x8>;
117        reg = <0x2000 0x1000>;
118      };
119    };
120
121...
122