1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef _DPU_HW_CTL_H 6 #define _DPU_HW_CTL_H 7 8 #include "dpu_hw_mdss.h" 9 #include "dpu_hw_util.h" 10 #include "dpu_hw_catalog.h" 11 #include "dpu_hw_sspp.h" 12 #include "dpu_hw_blk.h" 13 14 /** 15 * dpu_ctl_mode_sel: Interface mode selection 16 * DPU_CTL_MODE_SEL_VID: Video mode interface 17 * DPU_CTL_MODE_SEL_CMD: Command mode interface 18 */ 19 enum dpu_ctl_mode_sel { 20 DPU_CTL_MODE_SEL_VID = 0, 21 DPU_CTL_MODE_SEL_CMD 22 }; 23 24 struct dpu_hw_ctl; 25 /** 26 * struct dpu_hw_stage_cfg - blending stage cfg 27 * @stage : SSPP_ID at each stage 28 * @multirect_index: index of the rectangle of SSPP. 29 */ 30 struct dpu_hw_stage_cfg { 31 enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE]; 32 enum dpu_sspp_multirect_index multirect_index 33 [DPU_STAGE_MAX][PIPES_PER_STAGE]; 34 }; 35 36 /** 37 * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface 38 * @intf : Interface id 39 * @mode_3d: 3d mux configuration 40 * @intf_mode_sel: Interface mode, cmd / vid 41 * @stream_sel: Stream selection for multi-stream interfaces 42 */ 43 struct dpu_hw_intf_cfg { 44 enum dpu_intf intf; 45 enum dpu_3d_blend_mode mode_3d; 46 enum dpu_ctl_mode_sel intf_mode_sel; 47 int stream_sel; 48 }; 49 50 /** 51 * struct dpu_hw_ctl_ops - Interface to the wb Hw driver functions 52 * Assumption is these functions will be called after clocks are enabled 53 */ 54 struct dpu_hw_ctl_ops { 55 /** 56 * kickoff hw operation for Sw controlled interfaces 57 * DSI cmd mode and WB interface are SW controlled 58 * @ctx : ctl path ctx pointer 59 */ 60 void (*trigger_start)(struct dpu_hw_ctl *ctx); 61 62 /** 63 * kickoff prepare is in progress hw operation for sw 64 * controlled interfaces: DSI cmd mode and WB interface 65 * are SW controlled 66 * @ctx : ctl path ctx pointer 67 */ 68 void (*trigger_pending)(struct dpu_hw_ctl *ctx); 69 70 /** 71 * Clear the value of the cached pending_flush_mask 72 * No effect on hardware 73 * @ctx : ctl path ctx pointer 74 */ 75 void (*clear_pending_flush)(struct dpu_hw_ctl *ctx); 76 77 /** 78 * Query the value of the cached pending_flush_mask 79 * No effect on hardware 80 * @ctx : ctl path ctx pointer 81 */ 82 u32 (*get_pending_flush)(struct dpu_hw_ctl *ctx); 83 84 /** 85 * OR in the given flushbits to the cached pending_flush_mask 86 * No effect on hardware 87 * @ctx : ctl path ctx pointer 88 * @flushbits : module flushmask 89 */ 90 void (*update_pending_flush)(struct dpu_hw_ctl *ctx, 91 u32 flushbits); 92 93 /** 94 * OR in the given flushbits to the cached pending_intf_flush_mask 95 * No effect on hardware 96 * @ctx : ctl path ctx pointer 97 * @flushbits : module flushmask 98 */ 99 void (*update_pending_intf_flush)(struct dpu_hw_ctl *ctx, 100 u32 flushbits); 101 102 /** 103 * Write the value of the pending_flush_mask to hardware 104 * @ctx : ctl path ctx pointer 105 */ 106 void (*trigger_flush)(struct dpu_hw_ctl *ctx); 107 108 /** 109 * Read the value of the flush register 110 * @ctx : ctl path ctx pointer 111 * @Return: value of the ctl flush register. 112 */ 113 u32 (*get_flush_register)(struct dpu_hw_ctl *ctx); 114 115 /** 116 * Setup ctl_path interface config 117 * @ctx 118 * @cfg : interface config structure pointer 119 */ 120 void (*setup_intf_cfg)(struct dpu_hw_ctl *ctx, 121 struct dpu_hw_intf_cfg *cfg); 122 123 int (*reset)(struct dpu_hw_ctl *c); 124 125 /* 126 * wait_reset_status - checks ctl reset status 127 * @ctx : ctl path ctx pointer 128 * 129 * This function checks the ctl reset status bit. 130 * If the reset bit is set, it keeps polling the status till the hw 131 * reset is complete. 132 * Returns: 0 on success or -error if reset incomplete within interval 133 */ 134 int (*wait_reset_status)(struct dpu_hw_ctl *ctx); 135 136 uint32_t (*get_bitmask_sspp)(struct dpu_hw_ctl *ctx, 137 enum dpu_sspp blk); 138 139 uint32_t (*get_bitmask_mixer)(struct dpu_hw_ctl *ctx, 140 enum dpu_lm blk); 141 142 /** 143 * Query the value of the intf flush mask 144 * No effect on hardware 145 * @ctx : ctl path ctx pointer 146 */ 147 int (*get_bitmask_intf)(struct dpu_hw_ctl *ctx, 148 u32 *flushbits, 149 enum dpu_intf blk); 150 151 /** 152 * Query the value of the intf active flush mask 153 * No effect on hardware 154 * @ctx : ctl path ctx pointer 155 */ 156 int (*get_bitmask_active_intf)(struct dpu_hw_ctl *ctx, 157 u32 *flushbits, enum dpu_intf blk); 158 159 /** 160 * Set all blend stages to disabled 161 * @ctx : ctl path ctx pointer 162 */ 163 void (*clear_all_blendstages)(struct dpu_hw_ctl *ctx); 164 165 /** 166 * Configure layer mixer to pipe configuration 167 * @ctx : ctl path ctx pointer 168 * @lm : layer mixer enumeration 169 * @cfg : blend stage configuration 170 */ 171 void (*setup_blendstage)(struct dpu_hw_ctl *ctx, 172 enum dpu_lm lm, struct dpu_hw_stage_cfg *cfg); 173 }; 174 175 /** 176 * struct dpu_hw_ctl : CTL PATH driver object 177 * @base: hardware block base structure 178 * @hw: block register map object 179 * @idx: control path index 180 * @caps: control path capabilities 181 * @mixer_count: number of mixers 182 * @mixer_hw_caps: mixer hardware capabilities 183 * @pending_flush_mask: storage for pending ctl_flush managed via ops 184 * @pending_intf_flush_mask: pending INTF flush 185 * @ops: operation list 186 */ 187 struct dpu_hw_ctl { 188 struct dpu_hw_blk base; 189 struct dpu_hw_blk_reg_map hw; 190 191 /* ctl path */ 192 int idx; 193 const struct dpu_ctl_cfg *caps; 194 int mixer_count; 195 const struct dpu_lm_cfg *mixer_hw_caps; 196 u32 pending_flush_mask; 197 u32 pending_intf_flush_mask; 198 199 /* ops */ 200 struct dpu_hw_ctl_ops ops; 201 }; 202 203 /** 204 * dpu_hw_ctl - convert base object dpu_hw_base to container 205 * @hw: Pointer to base hardware block 206 * return: Pointer to hardware block container 207 */ 208 static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw) 209 { 210 return container_of(hw, struct dpu_hw_ctl, base); 211 } 212 213 /** 214 * dpu_hw_ctl_init(): Initializes the ctl_path hw driver object. 215 * should be called before accessing every ctl path registers. 216 * @idx: ctl_path index for which driver object is required 217 * @addr: mapped register io address of MDP 218 * @m : pointer to mdss catalog data 219 */ 220 struct dpu_hw_ctl *dpu_hw_ctl_init(enum dpu_ctl idx, 221 void __iomem *addr, 222 const struct dpu_mdss_cfg *m); 223 224 /** 225 * dpu_hw_ctl_destroy(): Destroys ctl driver context 226 * should be called to free the context 227 */ 228 void dpu_hw_ctl_destroy(struct dpu_hw_ctl *ctx); 229 230 #endif /*_DPU_HW_CTL_H */ 231