1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/clk-provider.h> 3 #include <linux/mfd/syscon.h> 4 #include <linux/slab.h> 5 6 #include <dt-bindings/clock/at91.h> 7 8 #include "pmc.h" 9 10 static DEFINE_SPINLOCK(pmc_pll_lock); 11 12 static const struct clk_master_characteristics mck_characteristics = { 13 .output = { .min = 140000000, .max = 200000000 }, 14 .divisors = { 1, 2, 4, 3 }, 15 .have_div3_pres = 1, 16 }; 17 18 static const struct clk_master_layout sam9x60_master_layout = { 19 .mask = 0x373, 20 .pres_shift = 4, 21 .offset = 0x28, 22 }; 23 24 static const struct clk_range plla_outputs[] = { 25 { .min = 2343750, .max = 1200000000 }, 26 }; 27 28 static const struct clk_pll_characteristics plla_characteristics = { 29 .input = { .min = 12000000, .max = 48000000 }, 30 .num_output = ARRAY_SIZE(plla_outputs), 31 .output = plla_outputs, 32 }; 33 34 static const struct clk_range upll_outputs[] = { 35 { .min = 300000000, .max = 500000000 }, 36 }; 37 38 static const struct clk_pll_characteristics upll_characteristics = { 39 .input = { .min = 12000000, .max = 48000000 }, 40 .num_output = ARRAY_SIZE(upll_outputs), 41 .output = upll_outputs, 42 .upll = true, 43 }; 44 45 static const struct clk_pll_layout pll_frac_layout = { 46 .mul_mask = GENMASK(31, 24), 47 .frac_mask = GENMASK(21, 0), 48 .mul_shift = 24, 49 .frac_shift = 0, 50 }; 51 52 static const struct clk_pll_layout pll_div_layout = { 53 .div_mask = GENMASK(7, 0), 54 .endiv_mask = BIT(29), 55 .div_shift = 0, 56 .endiv_shift = 29, 57 }; 58 59 static const struct clk_programmable_layout sam9x60_programmable_layout = { 60 .pres_mask = 0xff, 61 .pres_shift = 8, 62 .css_mask = 0x1f, 63 .have_slck_mck = 0, 64 .is_pres_direct = 1, 65 }; 66 67 static const struct clk_pcr_layout sam9x60_pcr_layout = { 68 .offset = 0x88, 69 .cmd = BIT(31), 70 .gckcss_mask = GENMASK(12, 8), 71 .pid_mask = GENMASK(6, 0), 72 }; 73 74 static const struct { 75 char *n; 76 char *p; 77 u8 id; 78 } sam9x60_systemck[] = { 79 { .n = "ddrck", .p = "masterck", .id = 2 }, 80 { .n = "uhpck", .p = "usbck", .id = 6 }, 81 { .n = "pck0", .p = "prog0", .id = 8 }, 82 { .n = "pck1", .p = "prog1", .id = 9 }, 83 { .n = "qspick", .p = "masterck", .id = 19 }, 84 }; 85 86 static const struct { 87 char *n; 88 u8 id; 89 } sam9x60_periphck[] = { 90 { .n = "pioA_clk", .id = 2, }, 91 { .n = "pioB_clk", .id = 3, }, 92 { .n = "pioC_clk", .id = 4, }, 93 { .n = "flex0_clk", .id = 5, }, 94 { .n = "flex1_clk", .id = 6, }, 95 { .n = "flex2_clk", .id = 7, }, 96 { .n = "flex3_clk", .id = 8, }, 97 { .n = "flex6_clk", .id = 9, }, 98 { .n = "flex7_clk", .id = 10, }, 99 { .n = "flex8_clk", .id = 11, }, 100 { .n = "sdmmc0_clk", .id = 12, }, 101 { .n = "flex4_clk", .id = 13, }, 102 { .n = "flex5_clk", .id = 14, }, 103 { .n = "flex9_clk", .id = 15, }, 104 { .n = "flex10_clk", .id = 16, }, 105 { .n = "tcb0_clk", .id = 17, }, 106 { .n = "pwm_clk", .id = 18, }, 107 { .n = "adc_clk", .id = 19, }, 108 { .n = "dma0_clk", .id = 20, }, 109 { .n = "matrix_clk", .id = 21, }, 110 { .n = "uhphs_clk", .id = 22, }, 111 { .n = "udphs_clk", .id = 23, }, 112 { .n = "macb0_clk", .id = 24, }, 113 { .n = "lcd_clk", .id = 25, }, 114 { .n = "sdmmc1_clk", .id = 26, }, 115 { .n = "macb1_clk", .id = 27, }, 116 { .n = "ssc_clk", .id = 28, }, 117 { .n = "can0_clk", .id = 29, }, 118 { .n = "can1_clk", .id = 30, }, 119 { .n = "flex11_clk", .id = 32, }, 120 { .n = "flex12_clk", .id = 33, }, 121 { .n = "i2s_clk", .id = 34, }, 122 { .n = "qspi_clk", .id = 35, }, 123 { .n = "gfx2d_clk", .id = 36, }, 124 { .n = "pit64b_clk", .id = 37, }, 125 { .n = "trng_clk", .id = 38, }, 126 { .n = "aes_clk", .id = 39, }, 127 { .n = "tdes_clk", .id = 40, }, 128 { .n = "sha_clk", .id = 41, }, 129 { .n = "classd_clk", .id = 42, }, 130 { .n = "isi_clk", .id = 43, }, 131 { .n = "pioD_clk", .id = 44, }, 132 { .n = "tcb1_clk", .id = 45, }, 133 { .n = "dbgu_clk", .id = 47, }, 134 { .n = "mpddr_clk", .id = 49, }, 135 }; 136 137 static const struct { 138 char *n; 139 u8 id; 140 struct clk_range r; 141 } sam9x60_gck[] = { 142 { .n = "flex0_gclk", .id = 5, }, 143 { .n = "flex1_gclk", .id = 6, }, 144 { .n = "flex2_gclk", .id = 7, }, 145 { .n = "flex3_gclk", .id = 8, }, 146 { .n = "flex6_gclk", .id = 9, }, 147 { .n = "flex7_gclk", .id = 10, }, 148 { .n = "flex8_gclk", .id = 11, }, 149 { .n = "sdmmc0_gclk", .id = 12, .r = { .min = 0, .max = 105000000 }, }, 150 { .n = "flex4_gclk", .id = 13, }, 151 { .n = "flex5_gclk", .id = 14, }, 152 { .n = "flex9_gclk", .id = 15, }, 153 { .n = "flex10_gclk", .id = 16, }, 154 { .n = "tcb0_gclk", .id = 17, }, 155 { .n = "adc_gclk", .id = 19, }, 156 { .n = "lcd_gclk", .id = 25, .r = { .min = 0, .max = 140000000 }, }, 157 { .n = "sdmmc1_gclk", .id = 26, .r = { .min = 0, .max = 105000000 }, }, 158 { .n = "flex11_gclk", .id = 32, }, 159 { .n = "flex12_gclk", .id = 33, }, 160 { .n = "i2s_gclk", .id = 34, .r = { .min = 0, .max = 105000000 }, }, 161 { .n = "pit64b_gclk", .id = 37, }, 162 { .n = "classd_gclk", .id = 42, .r = { .min = 0, .max = 100000000 }, }, 163 { .n = "tcb1_gclk", .id = 45, }, 164 { .n = "dbgu_gclk", .id = 47, }, 165 }; 166 167 static void __init sam9x60_pmc_setup(struct device_node *np) 168 { 169 struct clk_range range = CLK_RANGE(0, 0); 170 const char *td_slck_name, *md_slck_name, *mainxtal_name; 171 struct pmc_data *sam9x60_pmc; 172 const char *parent_names[6]; 173 struct clk_hw *main_osc_hw; 174 struct regmap *regmap; 175 struct clk_hw *hw; 176 int i; 177 bool bypass; 178 179 i = of_property_match_string(np, "clock-names", "td_slck"); 180 if (i < 0) 181 return; 182 183 td_slck_name = of_clk_get_parent_name(np, i); 184 185 i = of_property_match_string(np, "clock-names", "md_slck"); 186 if (i < 0) 187 return; 188 189 md_slck_name = of_clk_get_parent_name(np, i); 190 191 i = of_property_match_string(np, "clock-names", "main_xtal"); 192 if (i < 0) 193 return; 194 mainxtal_name = of_clk_get_parent_name(np, i); 195 196 regmap = device_node_to_regmap(np); 197 if (IS_ERR(regmap)) 198 return; 199 200 sam9x60_pmc = pmc_data_allocate(PMC_PLLACK + 1, 201 nck(sam9x60_systemck), 202 nck(sam9x60_periphck), 203 nck(sam9x60_gck), 8); 204 if (!sam9x60_pmc) 205 return; 206 207 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, 208 50000000); 209 if (IS_ERR(hw)) 210 goto err_free; 211 212 bypass = of_property_read_bool(np, "atmel,osc-bypass"); 213 214 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, 215 bypass); 216 if (IS_ERR(hw)) 217 goto err_free; 218 main_osc_hw = hw; 219 220 parent_names[0] = "main_rc_osc"; 221 parent_names[1] = "main_osc"; 222 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2); 223 if (IS_ERR(hw)) 224 goto err_free; 225 226 sam9x60_pmc->chws[PMC_MAIN] = hw; 227 228 hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck", 229 "mainck", sam9x60_pmc->chws[PMC_MAIN], 230 0, &plla_characteristics, 231 &pll_frac_layout, true); 232 if (IS_ERR(hw)) 233 goto err_free; 234 235 hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck", 236 "pllack_fracck", 0, &plla_characteristics, 237 &pll_div_layout, true); 238 if (IS_ERR(hw)) 239 goto err_free; 240 241 sam9x60_pmc->chws[PMC_PLLACK] = hw; 242 243 hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck", 244 "main_osc", main_osc_hw, 1, 245 &upll_characteristics, 246 &pll_frac_layout, false); 247 if (IS_ERR(hw)) 248 goto err_free; 249 250 hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck", 251 "upllck_fracck", 1, &upll_characteristics, 252 &pll_div_layout, false); 253 if (IS_ERR(hw)) 254 goto err_free; 255 256 sam9x60_pmc->chws[PMC_UTMI] = hw; 257 258 parent_names[0] = md_slck_name; 259 parent_names[1] = "mainck"; 260 parent_names[2] = "pllack_divck"; 261 hw = at91_clk_register_master(regmap, "masterck", 3, parent_names, 262 &sam9x60_master_layout, 263 &mck_characteristics); 264 if (IS_ERR(hw)) 265 goto err_free; 266 267 sam9x60_pmc->chws[PMC_MCK] = hw; 268 269 parent_names[0] = "pllack_divck"; 270 parent_names[1] = "upllck_divck"; 271 parent_names[2] = "main_osc"; 272 hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); 273 if (IS_ERR(hw)) 274 goto err_free; 275 276 parent_names[0] = md_slck_name; 277 parent_names[1] = td_slck_name; 278 parent_names[2] = "mainck"; 279 parent_names[3] = "masterck"; 280 parent_names[4] = "pllack_divck"; 281 parent_names[5] = "upllck_divck"; 282 for (i = 0; i < 8; i++) { 283 char name[6]; 284 285 snprintf(name, sizeof(name), "prog%d", i); 286 287 hw = at91_clk_register_programmable(regmap, name, 288 parent_names, 6, i, 289 &sam9x60_programmable_layout, 290 NULL); 291 if (IS_ERR(hw)) 292 goto err_free; 293 294 sam9x60_pmc->pchws[i] = hw; 295 } 296 297 for (i = 0; i < ARRAY_SIZE(sam9x60_systemck); i++) { 298 hw = at91_clk_register_system(regmap, sam9x60_systemck[i].n, 299 sam9x60_systemck[i].p, 300 sam9x60_systemck[i].id); 301 if (IS_ERR(hw)) 302 goto err_free; 303 304 sam9x60_pmc->shws[sam9x60_systemck[i].id] = hw; 305 } 306 307 for (i = 0; i < ARRAY_SIZE(sam9x60_periphck); i++) { 308 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, 309 &sam9x60_pcr_layout, 310 sam9x60_periphck[i].n, 311 "masterck", 312 sam9x60_periphck[i].id, 313 &range, INT_MIN); 314 if (IS_ERR(hw)) 315 goto err_free; 316 317 sam9x60_pmc->phws[sam9x60_periphck[i].id] = hw; 318 } 319 320 for (i = 0; i < ARRAY_SIZE(sam9x60_gck); i++) { 321 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, 322 &sam9x60_pcr_layout, 323 sam9x60_gck[i].n, 324 parent_names, NULL, 6, 325 sam9x60_gck[i].id, 326 &sam9x60_gck[i].r, INT_MIN); 327 if (IS_ERR(hw)) 328 goto err_free; 329 330 sam9x60_pmc->ghws[sam9x60_gck[i].id] = hw; 331 } 332 333 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x60_pmc); 334 335 return; 336 337 err_free: 338 kfree(sam9x60_pmc); 339 } 340 /* Some clks are used for a clocksource */ 341 CLK_OF_DECLARE(sam9x60_pmc, "microchip,sam9x60-pmc", sam9x60_pmc_setup); 342