1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_ucode.h" 31 #include "amdgpu_trace.h" 32 33 #include "gc/gc_10_1_0_offset.h" 34 #include "gc/gc_10_1_0_sh_mask.h" 35 #include "hdp/hdp_5_0_0_offset.h" 36 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h" 37 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h" 38 39 #include "soc15_common.h" 40 #include "soc15.h" 41 #include "navi10_sdma_pkt_open.h" 42 #include "nbio_v2_3.h" 43 #include "sdma_v5_0.h" 44 45 MODULE_FIRMWARE("amdgpu/navi10_sdma.bin"); 46 MODULE_FIRMWARE("amdgpu/navi10_sdma1.bin"); 47 48 MODULE_FIRMWARE("amdgpu/navi14_sdma.bin"); 49 MODULE_FIRMWARE("amdgpu/navi14_sdma1.bin"); 50 51 MODULE_FIRMWARE("amdgpu/navi12_sdma.bin"); 52 MODULE_FIRMWARE("amdgpu/navi12_sdma1.bin"); 53 54 #define SDMA1_REG_OFFSET 0x600 55 #define SDMA0_HYP_DEC_REG_START 0x5880 56 #define SDMA0_HYP_DEC_REG_END 0x5893 57 #define SDMA1_HYP_DEC_REG_OFFSET 0x20 58 59 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev); 60 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev); 61 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev); 62 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev); 63 64 static const struct soc15_reg_golden golden_settings_sdma_5[] = { 65 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 66 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 67 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 68 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 69 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 70 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 71 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 72 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 73 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 75 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 76 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_UTCL1_PAGE, 0x00ffffff, 0x000c5c00), 77 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_CHICKEN_BITS, 0xffbf1f0f, 0x03ab0107), 78 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 79 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 80 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 81 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ffffff, 0x000c5c00) 89 }; 90 91 static const struct soc15_reg_golden golden_settings_sdma_nv10[] = { 92 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 93 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000), 94 }; 95 96 static const struct soc15_reg_golden golden_settings_sdma_nv14[] = { 97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 99 }; 100 101 static const struct soc15_reg_golden golden_settings_sdma_nv12[] = { 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), 104 }; 105 106 static u32 sdma_v5_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset) 107 { 108 u32 base; 109 110 if (internal_offset >= SDMA0_HYP_DEC_REG_START && 111 internal_offset <= SDMA0_HYP_DEC_REG_END) { 112 base = adev->reg_offset[GC_HWIP][0][1]; 113 if (instance == 1) 114 internal_offset += SDMA1_HYP_DEC_REG_OFFSET; 115 } else { 116 base = adev->reg_offset[GC_HWIP][0][0]; 117 if (instance == 1) 118 internal_offset += SDMA1_REG_OFFSET; 119 } 120 121 return base + internal_offset; 122 } 123 124 static void sdma_v5_0_init_golden_registers(struct amdgpu_device *adev) 125 { 126 switch (adev->asic_type) { 127 case CHIP_NAVI10: 128 soc15_program_register_sequence(adev, 129 golden_settings_sdma_5, 130 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 131 soc15_program_register_sequence(adev, 132 golden_settings_sdma_nv10, 133 (const u32)ARRAY_SIZE(golden_settings_sdma_nv10)); 134 break; 135 case CHIP_NAVI14: 136 soc15_program_register_sequence(adev, 137 golden_settings_sdma_5, 138 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 139 soc15_program_register_sequence(adev, 140 golden_settings_sdma_nv14, 141 (const u32)ARRAY_SIZE(golden_settings_sdma_nv14)); 142 break; 143 case CHIP_NAVI12: 144 soc15_program_register_sequence(adev, 145 golden_settings_sdma_5, 146 (const u32)ARRAY_SIZE(golden_settings_sdma_5)); 147 soc15_program_register_sequence(adev, 148 golden_settings_sdma_nv12, 149 (const u32)ARRAY_SIZE(golden_settings_sdma_nv12)); 150 break; 151 default: 152 break; 153 } 154 } 155 156 /** 157 * sdma_v5_0_init_microcode - load ucode images from disk 158 * 159 * @adev: amdgpu_device pointer 160 * 161 * Use the firmware interface to load the ucode images into 162 * the driver (not loaded into hw). 163 * Returns 0 on success, error on failure. 164 */ 165 166 // emulation only, won't work on real chip 167 // navi10 real chip need to use PSP to load firmware 168 static int sdma_v5_0_init_microcode(struct amdgpu_device *adev) 169 { 170 const char *chip_name; 171 char fw_name[30]; 172 int err = 0, i; 173 struct amdgpu_firmware_info *info = NULL; 174 const struct common_firmware_header *header = NULL; 175 const struct sdma_firmware_header_v1_0 *hdr; 176 177 DRM_DEBUG("\n"); 178 179 switch (adev->asic_type) { 180 case CHIP_NAVI10: 181 chip_name = "navi10"; 182 break; 183 case CHIP_NAVI14: 184 chip_name = "navi14"; 185 break; 186 case CHIP_NAVI12: 187 chip_name = "navi12"; 188 break; 189 default: 190 BUG(); 191 } 192 193 for (i = 0; i < adev->sdma.num_instances; i++) { 194 if (i == 0) 195 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); 196 else 197 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); 198 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 199 if (err) 200 goto out; 201 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 202 if (err) 203 goto out; 204 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 205 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 206 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 207 if (adev->sdma.instance[i].feature_version >= 20) 208 adev->sdma.instance[i].burst_nop = true; 209 DRM_DEBUG("psp_load == '%s'\n", 210 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false"); 211 212 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 213 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; 214 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; 215 info->fw = adev->sdma.instance[i].fw; 216 header = (const struct common_firmware_header *)info->fw->data; 217 adev->firmware.fw_size += 218 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 219 } 220 } 221 out: 222 if (err) { 223 DRM_ERROR("sdma_v5_0: Failed to load firmware \"%s\"\n", fw_name); 224 for (i = 0; i < adev->sdma.num_instances; i++) { 225 release_firmware(adev->sdma.instance[i].fw); 226 adev->sdma.instance[i].fw = NULL; 227 } 228 } 229 return err; 230 } 231 232 static unsigned sdma_v5_0_ring_init_cond_exec(struct amdgpu_ring *ring) 233 { 234 unsigned ret; 235 236 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE)); 237 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 238 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 239 amdgpu_ring_write(ring, 1); 240 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ 241 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */ 242 243 return ret; 244 } 245 246 static void sdma_v5_0_ring_patch_cond_exec(struct amdgpu_ring *ring, 247 unsigned offset) 248 { 249 unsigned cur; 250 251 BUG_ON(offset > ring->buf_mask); 252 BUG_ON(ring->ring[offset] != 0x55aa55aa); 253 254 cur = (ring->wptr - 1) & ring->buf_mask; 255 if (cur > offset) 256 ring->ring[offset] = cur - offset; 257 else 258 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 259 } 260 261 /** 262 * sdma_v5_0_ring_get_rptr - get the current read pointer 263 * 264 * @ring: amdgpu ring pointer 265 * 266 * Get the current rptr from the hardware (NAVI10+). 267 */ 268 static uint64_t sdma_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 269 { 270 u64 *rptr; 271 272 /* XXX check if swapping is necessary on BE */ 273 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]); 274 275 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr); 276 return ((*rptr) >> 2); 277 } 278 279 /** 280 * sdma_v5_0_ring_get_wptr - get the current write pointer 281 * 282 * @ring: amdgpu ring pointer 283 * 284 * Get the current wptr from the hardware (NAVI10+). 285 */ 286 static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 287 { 288 struct amdgpu_device *adev = ring->adev; 289 u64 *wptr = NULL; 290 uint64_t local_wptr = 0; 291 292 if (ring->use_doorbell) { 293 /* XXX check if swapping is necessary on BE */ 294 wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]); 295 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr); 296 *wptr = (*wptr) >> 2; 297 DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr); 298 } else { 299 u32 lowbit, highbit; 300 301 wptr = &local_wptr; 302 lowbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2; 303 highbit = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2; 304 305 DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n", 306 ring->me, highbit, lowbit); 307 *wptr = highbit; 308 *wptr = (*wptr) << 32; 309 *wptr |= lowbit; 310 } 311 312 return *wptr; 313 } 314 315 /** 316 * sdma_v5_0_ring_set_wptr - commit the write pointer 317 * 318 * @ring: amdgpu ring pointer 319 * 320 * Write the wptr back to the hardware (NAVI10+). 321 */ 322 static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 323 { 324 struct amdgpu_device *adev = ring->adev; 325 326 DRM_DEBUG("Setting write pointer\n"); 327 if (ring->use_doorbell) { 328 DRM_DEBUG("Using doorbell -- " 329 "wptr_offs == 0x%08x " 330 "lower_32_bits(ring->wptr) << 2 == 0x%08x " 331 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n", 332 ring->wptr_offs, 333 lower_32_bits(ring->wptr << 2), 334 upper_32_bits(ring->wptr << 2)); 335 /* XXX check if swapping is necessary on BE */ 336 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); 337 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); 338 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", 339 ring->doorbell_index, ring->wptr << 2); 340 WDOORBELL64(ring->doorbell_index, ring->wptr << 2); 341 } else { 342 DRM_DEBUG("Not using doorbell -- " 343 "mmSDMA%i_GFX_RB_WPTR == 0x%08x " 344 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n", 345 ring->me, 346 lower_32_bits(ring->wptr << 2), 347 ring->me, 348 upper_32_bits(ring->wptr << 2)); 349 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), 350 lower_32_bits(ring->wptr << 2)); 351 WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 352 upper_32_bits(ring->wptr << 2)); 353 } 354 } 355 356 static void sdma_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 357 { 358 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 359 int i; 360 361 for (i = 0; i < count; i++) 362 if (sdma && sdma->burst_nop && (i == 0)) 363 amdgpu_ring_write(ring, ring->funcs->nop | 364 SDMA_PKT_NOP_HEADER_COUNT(count - 1)); 365 else 366 amdgpu_ring_write(ring, ring->funcs->nop); 367 } 368 369 /** 370 * sdma_v5_0_ring_emit_ib - Schedule an IB on the DMA engine 371 * 372 * @ring: amdgpu ring pointer 373 * @ib: IB object to schedule 374 * 375 * Schedule an IB in the DMA ring (NAVI10). 376 */ 377 static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 378 struct amdgpu_job *job, 379 struct amdgpu_ib *ib, 380 uint32_t flags) 381 { 382 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 383 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid); 384 385 /* An IB packet must end on a 8 DW boundary--the next dword 386 * must be on a 8-dword boundary. Our IB packet below is 6 387 * dwords long, thus add x number of NOPs, such that, in 388 * modular arithmetic, 389 * wptr + 6 + x = 8k, k >= 0, which in C is, 390 * (wptr + 6 + x) % 8 = 0. 391 * The expression below, is a solution of x. 392 */ 393 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); 394 395 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) | 396 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)); 397 /* base must be 32 byte aligned */ 398 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 399 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 400 amdgpu_ring_write(ring, ib->length_dw); 401 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); 402 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); 403 } 404 405 /** 406 * sdma_v5_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 407 * 408 * @ring: amdgpu ring pointer 409 * 410 * Emit an hdp flush packet on the requested DMA ring. 411 */ 412 static void sdma_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 413 { 414 struct amdgpu_device *adev = ring->adev; 415 u32 ref_and_mask = 0; 416 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 417 418 if (ring->me == 0) 419 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; 420 else 421 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; 422 423 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 424 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) | 425 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */ 426 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2); 427 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2); 428 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 429 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 430 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 431 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ 432 } 433 434 /** 435 * sdma_v5_0_ring_emit_fence - emit a fence on the DMA ring 436 * 437 * @ring: amdgpu ring pointer 438 * @fence: amdgpu fence object 439 * 440 * Add a DMA fence packet to the ring to write 441 * the fence seq number and DMA trap packet to generate 442 * an interrupt if needed (NAVI10). 443 */ 444 static void sdma_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 445 unsigned flags) 446 { 447 struct amdgpu_device *adev = ring->adev; 448 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 449 /* write the fence */ 450 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 451 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */ 452 /* zero in first two bits */ 453 BUG_ON(addr & 0x3); 454 amdgpu_ring_write(ring, lower_32_bits(addr)); 455 amdgpu_ring_write(ring, upper_32_bits(addr)); 456 amdgpu_ring_write(ring, lower_32_bits(seq)); 457 458 /* optionally write high bits as well */ 459 if (write64bit) { 460 addr += 4; 461 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) | 462 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); 463 /* zero in first two bits */ 464 BUG_ON(addr & 0x3); 465 amdgpu_ring_write(ring, lower_32_bits(addr)); 466 amdgpu_ring_write(ring, upper_32_bits(addr)); 467 amdgpu_ring_write(ring, upper_32_bits(seq)); 468 } 469 470 /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */ 471 if ((flags & AMDGPU_FENCE_FLAG_INT) && adev->pdev->device != 0x50) { 472 /* generate an interrupt */ 473 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)); 474 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); 475 } 476 } 477 478 479 /** 480 * sdma_v5_0_gfx_stop - stop the gfx async dma engines 481 * 482 * @adev: amdgpu_device pointer 483 * 484 * Stop the gfx async dma ring buffers (NAVI10). 485 */ 486 static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev) 487 { 488 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 489 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 490 u32 rb_cntl, ib_cntl; 491 int i; 492 493 if ((adev->mman.buffer_funcs_ring == sdma0) || 494 (adev->mman.buffer_funcs_ring == sdma1)) 495 amdgpu_ttm_set_buffer_funcs_status(adev, false); 496 497 for (i = 0; i < adev->sdma.num_instances; i++) { 498 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 499 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); 500 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 501 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 502 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); 503 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 504 } 505 506 sdma0->sched.ready = false; 507 sdma1->sched.ready = false; 508 } 509 510 /** 511 * sdma_v5_0_rlc_stop - stop the compute async dma engines 512 * 513 * @adev: amdgpu_device pointer 514 * 515 * Stop the compute async dma queues (NAVI10). 516 */ 517 static void sdma_v5_0_rlc_stop(struct amdgpu_device *adev) 518 { 519 /* XXX todo */ 520 } 521 522 /** 523 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch 524 * 525 * @adev: amdgpu_device pointer 526 * @enable: enable/disable the DMA MEs context switch. 527 * 528 * Halt or unhalt the async dma engines context switch (NAVI10). 529 */ 530 static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 531 { 532 u32 f32_cntl, phase_quantum = 0; 533 int i; 534 535 if (amdgpu_sdma_phase_quantum) { 536 unsigned value = amdgpu_sdma_phase_quantum; 537 unsigned unit = 0; 538 539 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 540 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 541 value = (value + 1) >> 1; 542 unit++; 543 } 544 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 545 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 546 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 547 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 548 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 549 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 550 WARN_ONCE(1, 551 "clamping sdma_phase_quantum to %uK clock cycles\n", 552 value << unit); 553 } 554 phase_quantum = 555 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 556 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 557 } 558 559 for (i = 0; i < adev->sdma.num_instances; i++) { 560 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 561 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 562 AUTO_CTXSW_ENABLE, enable ? 1 : 0); 563 if (enable && amdgpu_sdma_phase_quantum) { 564 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM), 565 phase_quantum); 566 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM), 567 phase_quantum); 568 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), 569 phase_quantum); 570 } 571 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 572 } 573 574 } 575 576 /** 577 * sdma_v5_0_enable - stop the async dma engines 578 * 579 * @adev: amdgpu_device pointer 580 * @enable: enable/disable the DMA MEs. 581 * 582 * Halt or unhalt the async dma engines (NAVI10). 583 */ 584 static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable) 585 { 586 u32 f32_cntl; 587 int i; 588 589 if (enable == false) { 590 sdma_v5_0_gfx_stop(adev); 591 sdma_v5_0_rlc_stop(adev); 592 } 593 594 for (i = 0; i < adev->sdma.num_instances; i++) { 595 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 596 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 597 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); 598 } 599 } 600 601 /** 602 * sdma_v5_0_gfx_resume - setup and start the async dma engines 603 * 604 * @adev: amdgpu_device pointer 605 * 606 * Set up the gfx DMA ring buffers and enable them (NAVI10). 607 * Returns 0 for success, error for failure. 608 */ 609 static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) 610 { 611 struct amdgpu_ring *ring; 612 u32 rb_cntl, ib_cntl; 613 u32 rb_bufsz; 614 u32 wb_offset; 615 u32 doorbell; 616 u32 doorbell_offset; 617 u32 temp; 618 u32 wptr_poll_cntl; 619 u64 wptr_gpu_addr; 620 int i, r; 621 622 for (i = 0; i < adev->sdma.num_instances; i++) { 623 ring = &adev->sdma.instance[i].ring; 624 wb_offset = (ring->rptr_offs * 4); 625 626 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); 627 628 /* Set ring buffer size in dwords */ 629 rb_bufsz = order_base_2(ring->ring_size / 4); 630 rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); 631 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); 632 #ifdef __BIG_ENDIAN 633 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); 634 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, 635 RPTR_WRITEBACK_SWAP_ENABLE, 1); 636 #endif 637 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 638 639 /* Initialize the ring buffer's read and write pointers */ 640 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); 641 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); 642 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); 643 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 644 645 /* setup the wptr shadow polling */ 646 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 647 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), 648 lower_32_bits(wptr_gpu_addr)); 649 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), 650 upper_32_bits(wptr_gpu_addr)); 651 wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, 652 mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); 653 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, 654 SDMA0_GFX_RB_WPTR_POLL_CNTL, 655 F32_POLL_ENABLE, 1); 656 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), 657 wptr_poll_cntl); 658 659 /* set the wb address whether it's enabled or not */ 660 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), 661 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 662 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), 663 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 664 665 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); 666 667 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); 668 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); 669 670 ring->wptr = 0; 671 672 /* before programing wptr to a less value, need set minor_ptr_update first */ 673 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); 674 675 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ 676 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); 677 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); 678 } 679 680 doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); 681 doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); 682 683 if (ring->use_doorbell) { 684 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); 685 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, 686 OFFSET, ring->doorbell_index); 687 } else { 688 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); 689 } 690 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); 691 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); 692 693 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, 694 ring->doorbell_index, 20); 695 696 if (amdgpu_sriov_vf(adev)) 697 sdma_v5_0_ring_set_wptr(ring); 698 699 /* set minor_ptr_update to 0 after wptr programed */ 700 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); 701 702 /* set utc l1 enable flag always to 1 */ 703 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 704 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); 705 706 /* enable MCBP */ 707 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); 708 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); 709 710 /* Set up RESP_MODE to non-copy addresses */ 711 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); 712 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); 713 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); 714 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); 715 716 /* program default cache read and write policy */ 717 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); 718 /* clean read policy and write policy bits */ 719 temp &= 0xFF0FFF; 720 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); 721 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); 722 723 if (!amdgpu_sriov_vf(adev)) { 724 /* unhalt engine */ 725 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 726 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); 727 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); 728 } 729 730 /* enable DMA RB */ 731 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); 732 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); 733 734 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); 735 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); 736 #ifdef __BIG_ENDIAN 737 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); 738 #endif 739 /* enable DMA IBs */ 740 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); 741 742 ring->sched.ready = true; 743 744 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ 745 sdma_v5_0_ctx_switch_enable(adev, true); 746 sdma_v5_0_enable(adev, true); 747 } 748 749 r = amdgpu_ring_test_ring(ring); 750 if (r) { 751 ring->sched.ready = false; 752 return r; 753 } 754 755 if (adev->mman.buffer_funcs_ring == ring) 756 amdgpu_ttm_set_buffer_funcs_status(adev, true); 757 } 758 759 return 0; 760 } 761 762 /** 763 * sdma_v5_0_rlc_resume - setup and start the async dma engines 764 * 765 * @adev: amdgpu_device pointer 766 * 767 * Set up the compute DMA queues and enable them (NAVI10). 768 * Returns 0 for success, error for failure. 769 */ 770 static int sdma_v5_0_rlc_resume(struct amdgpu_device *adev) 771 { 772 return 0; 773 } 774 775 /** 776 * sdma_v5_0_load_microcode - load the sDMA ME ucode 777 * 778 * @adev: amdgpu_device pointer 779 * 780 * Loads the sDMA0/1 ucode. 781 * Returns 0 for success, -EINVAL if the ucode is not available. 782 */ 783 static int sdma_v5_0_load_microcode(struct amdgpu_device *adev) 784 { 785 const struct sdma_firmware_header_v1_0 *hdr; 786 const __le32 *fw_data; 787 u32 fw_size; 788 int i, j; 789 790 /* halt the MEs */ 791 sdma_v5_0_enable(adev, false); 792 793 for (i = 0; i < adev->sdma.num_instances; i++) { 794 if (!adev->sdma.instance[i].fw) 795 return -EINVAL; 796 797 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 798 amdgpu_ucode_print_sdma_hdr(&hdr->header); 799 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 800 801 fw_data = (const __le32 *) 802 (adev->sdma.instance[i].fw->data + 803 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 804 805 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0); 806 807 for (j = 0; j < fw_size; j++) { 808 if (amdgpu_emu_mode == 1 && j % 500 == 0) 809 msleep(1); 810 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++)); 811 } 812 813 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version); 814 } 815 816 return 0; 817 } 818 819 /** 820 * sdma_v5_0_start - setup and start the async dma engines 821 * 822 * @adev: amdgpu_device pointer 823 * 824 * Set up the DMA engines and enable them (NAVI10). 825 * Returns 0 for success, error for failure. 826 */ 827 static int sdma_v5_0_start(struct amdgpu_device *adev) 828 { 829 int r = 0; 830 831 if (amdgpu_sriov_vf(adev)) { 832 sdma_v5_0_ctx_switch_enable(adev, false); 833 sdma_v5_0_enable(adev, false); 834 835 /* set RB registers */ 836 r = sdma_v5_0_gfx_resume(adev); 837 return r; 838 } 839 840 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 841 r = sdma_v5_0_load_microcode(adev); 842 if (r) 843 return r; 844 845 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */ 846 if (amdgpu_emu_mode == 1 && adev->pdev->device == 0x4d) 847 msleep(1000); 848 } 849 850 /* unhalt the MEs */ 851 sdma_v5_0_enable(adev, true); 852 /* enable sdma ring preemption */ 853 sdma_v5_0_ctx_switch_enable(adev, true); 854 855 /* start the gfx rings and rlc compute queues */ 856 r = sdma_v5_0_gfx_resume(adev); 857 if (r) 858 return r; 859 r = sdma_v5_0_rlc_resume(adev); 860 861 return r; 862 } 863 864 /** 865 * sdma_v5_0_ring_test_ring - simple async dma engine test 866 * 867 * @ring: amdgpu_ring structure holding ring information 868 * 869 * Test the DMA engine by writing using it to write an 870 * value to memory. (NAVI10). 871 * Returns 0 for success, error for failure. 872 */ 873 static int sdma_v5_0_ring_test_ring(struct amdgpu_ring *ring) 874 { 875 struct amdgpu_device *adev = ring->adev; 876 unsigned i; 877 unsigned index; 878 int r; 879 u32 tmp; 880 u64 gpu_addr; 881 882 r = amdgpu_device_wb_get(adev, &index); 883 if (r) { 884 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 885 return r; 886 } 887 888 gpu_addr = adev->wb.gpu_addr + (index * 4); 889 tmp = 0xCAFEDEAD; 890 adev->wb.wb[index] = cpu_to_le32(tmp); 891 892 r = amdgpu_ring_alloc(ring, 5); 893 if (r) { 894 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 895 amdgpu_device_wb_free(adev, index); 896 return r; 897 } 898 899 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 900 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)); 901 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 902 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 903 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0)); 904 amdgpu_ring_write(ring, 0xDEADBEEF); 905 amdgpu_ring_commit(ring); 906 907 for (i = 0; i < adev->usec_timeout; i++) { 908 tmp = le32_to_cpu(adev->wb.wb[index]); 909 if (tmp == 0xDEADBEEF) 910 break; 911 if (amdgpu_emu_mode == 1) 912 msleep(1); 913 else 914 udelay(1); 915 } 916 917 if (i >= adev->usec_timeout) 918 r = -ETIMEDOUT; 919 920 amdgpu_device_wb_free(adev, index); 921 922 return r; 923 } 924 925 /** 926 * sdma_v5_0_ring_test_ib - test an IB on the DMA engine 927 * 928 * @ring: amdgpu_ring structure holding ring information 929 * 930 * Test a simple IB in the DMA ring (NAVI10). 931 * Returns 0 on success, error on failure. 932 */ 933 static int sdma_v5_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 934 { 935 struct amdgpu_device *adev = ring->adev; 936 struct amdgpu_ib ib; 937 struct dma_fence *f = NULL; 938 unsigned index; 939 long r; 940 u32 tmp = 0; 941 u64 gpu_addr; 942 943 r = amdgpu_device_wb_get(adev, &index); 944 if (r) { 945 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 946 return r; 947 } 948 949 gpu_addr = adev->wb.gpu_addr + (index * 4); 950 tmp = 0xCAFEDEAD; 951 adev->wb.wb[index] = cpu_to_le32(tmp); 952 memset(&ib, 0, sizeof(ib)); 953 r = amdgpu_ib_get(adev, NULL, 256, &ib); 954 if (r) { 955 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 956 goto err0; 957 } 958 959 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 960 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 961 ib.ptr[1] = lower_32_bits(gpu_addr); 962 ib.ptr[2] = upper_32_bits(gpu_addr); 963 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0); 964 ib.ptr[4] = 0xDEADBEEF; 965 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 966 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 967 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP); 968 ib.length_dw = 8; 969 970 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 971 if (r) 972 goto err1; 973 974 r = dma_fence_wait_timeout(f, false, timeout); 975 if (r == 0) { 976 DRM_ERROR("amdgpu: IB test timed out\n"); 977 r = -ETIMEDOUT; 978 goto err1; 979 } else if (r < 0) { 980 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 981 goto err1; 982 } 983 tmp = le32_to_cpu(adev->wb.wb[index]); 984 if (tmp == 0xDEADBEEF) 985 r = 0; 986 else 987 r = -EINVAL; 988 989 err1: 990 amdgpu_ib_free(adev, &ib, NULL); 991 dma_fence_put(f); 992 err0: 993 amdgpu_device_wb_free(adev, index); 994 return r; 995 } 996 997 998 /** 999 * sdma_v5_0_vm_copy_pte - update PTEs by copying them from the GART 1000 * 1001 * @ib: indirect buffer to fill with commands 1002 * @pe: addr of the page entry 1003 * @src: src addr to copy from 1004 * @count: number of page entries to update 1005 * 1006 * Update PTEs by copying them from the GART using sDMA (NAVI10). 1007 */ 1008 static void sdma_v5_0_vm_copy_pte(struct amdgpu_ib *ib, 1009 uint64_t pe, uint64_t src, 1010 unsigned count) 1011 { 1012 unsigned bytes = count * 8; 1013 1014 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1015 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1016 ib->ptr[ib->length_dw++] = bytes - 1; 1017 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1018 ib->ptr[ib->length_dw++] = lower_32_bits(src); 1019 ib->ptr[ib->length_dw++] = upper_32_bits(src); 1020 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1021 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1022 1023 } 1024 1025 /** 1026 * sdma_v5_0_vm_write_pte - update PTEs by writing them manually 1027 * 1028 * @ib: indirect buffer to fill with commands 1029 * @pe: addr of the page entry 1030 * @addr: dst addr to write into pe 1031 * @count: number of page entries to update 1032 * @incr: increase next addr by incr bytes 1033 * @flags: access flags 1034 * 1035 * Update PTEs by writing them manually using sDMA (NAVI10). 1036 */ 1037 static void sdma_v5_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 1038 uint64_t value, unsigned count, 1039 uint32_t incr) 1040 { 1041 unsigned ndw = count * 2; 1042 1043 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) | 1044 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR); 1045 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 1046 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1047 ib->ptr[ib->length_dw++] = ndw - 1; 1048 for (; ndw > 0; ndw -= 2) { 1049 ib->ptr[ib->length_dw++] = lower_32_bits(value); 1050 ib->ptr[ib->length_dw++] = upper_32_bits(value); 1051 value += incr; 1052 } 1053 } 1054 1055 /** 1056 * sdma_v5_0_vm_set_pte_pde - update the page tables using sDMA 1057 * 1058 * @ib: indirect buffer to fill with commands 1059 * @pe: addr of the page entry 1060 * @addr: dst addr to write into pe 1061 * @count: number of page entries to update 1062 * @incr: increase next addr by incr bytes 1063 * @flags: access flags 1064 * 1065 * Update the page tables using sDMA (NAVI10). 1066 */ 1067 static void sdma_v5_0_vm_set_pte_pde(struct amdgpu_ib *ib, 1068 uint64_t pe, 1069 uint64_t addr, unsigned count, 1070 uint32_t incr, uint64_t flags) 1071 { 1072 /* for physically contiguous pages (vram) */ 1073 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE); 1074 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 1075 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 1076 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 1077 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 1078 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 1079 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 1080 ib->ptr[ib->length_dw++] = incr; /* increment size */ 1081 ib->ptr[ib->length_dw++] = 0; 1082 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */ 1083 } 1084 1085 /** 1086 * sdma_v5_0_ring_pad_ib - pad the IB 1087 * @ib: indirect buffer to fill with padding 1088 * 1089 * Pad the IB with NOPs to a boundary multiple of 8. 1090 */ 1091 static void sdma_v5_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 1092 { 1093 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); 1094 u32 pad_count; 1095 int i; 1096 1097 pad_count = (-ib->length_dw) & 0x7; 1098 for (i = 0; i < pad_count; i++) 1099 if (sdma && sdma->burst_nop && (i == 0)) 1100 ib->ptr[ib->length_dw++] = 1101 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) | 1102 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1); 1103 else 1104 ib->ptr[ib->length_dw++] = 1105 SDMA_PKT_HEADER_OP(SDMA_OP_NOP); 1106 } 1107 1108 1109 /** 1110 * sdma_v5_0_ring_emit_pipeline_sync - sync the pipeline 1111 * 1112 * @ring: amdgpu_ring pointer 1113 * 1114 * Make sure all previous operations are completed (CIK). 1115 */ 1116 static void sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 1117 { 1118 uint32_t seq = ring->fence_drv.sync_seq; 1119 uint64_t addr = ring->fence_drv.gpu_addr; 1120 1121 /* wait for idle */ 1122 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1123 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1124 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */ 1125 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)); 1126 amdgpu_ring_write(ring, addr & 0xfffffffc); 1127 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 1128 amdgpu_ring_write(ring, seq); /* reference */ 1129 amdgpu_ring_write(ring, 0xffffffff); /* mask */ 1130 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1131 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ 1132 } 1133 1134 1135 /** 1136 * sdma_v5_0_ring_emit_vm_flush - vm flush using sDMA 1137 * 1138 * @ring: amdgpu_ring pointer 1139 * @vm: amdgpu_vm pointer 1140 * 1141 * Update the page table base and flush the VM TLB 1142 * using sDMA (NAVI10). 1143 */ 1144 static void sdma_v5_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 1145 unsigned vmid, uint64_t pd_addr) 1146 { 1147 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1148 } 1149 1150 static void sdma_v5_0_ring_emit_wreg(struct amdgpu_ring *ring, 1151 uint32_t reg, uint32_t val) 1152 { 1153 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | 1154 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); 1155 amdgpu_ring_write(ring, reg); 1156 amdgpu_ring_write(ring, val); 1157 } 1158 1159 static void sdma_v5_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 1160 uint32_t val, uint32_t mask) 1161 { 1162 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 1163 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) | 1164 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */ 1165 amdgpu_ring_write(ring, reg << 2); 1166 amdgpu_ring_write(ring, 0); 1167 amdgpu_ring_write(ring, val); /* reference */ 1168 amdgpu_ring_write(ring, mask); /* mask */ 1169 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | 1170 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); 1171 } 1172 1173 static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 1174 uint32_t reg0, uint32_t reg1, 1175 uint32_t ref, uint32_t mask) 1176 { 1177 amdgpu_ring_emit_wreg(ring, reg0, ref); 1178 /* wait for a cycle to reset vm_inv_eng*_ack */ 1179 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0); 1180 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); 1181 } 1182 1183 static int sdma_v5_0_early_init(void *handle) 1184 { 1185 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1186 1187 adev->sdma.num_instances = 2; 1188 1189 sdma_v5_0_set_ring_funcs(adev); 1190 sdma_v5_0_set_buffer_funcs(adev); 1191 sdma_v5_0_set_vm_pte_funcs(adev); 1192 sdma_v5_0_set_irq_funcs(adev); 1193 1194 return 0; 1195 } 1196 1197 1198 static int sdma_v5_0_sw_init(void *handle) 1199 { 1200 struct amdgpu_ring *ring; 1201 int r, i; 1202 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1203 1204 /* SDMA trap event */ 1205 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 1206 SDMA0_5_0__SRCID__SDMA_TRAP, 1207 &adev->sdma.trap_irq); 1208 if (r) 1209 return r; 1210 1211 /* SDMA trap event */ 1212 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 1213 SDMA1_5_0__SRCID__SDMA_TRAP, 1214 &adev->sdma.trap_irq); 1215 if (r) 1216 return r; 1217 1218 r = sdma_v5_0_init_microcode(adev); 1219 if (r) { 1220 DRM_ERROR("Failed to load sdma firmware!\n"); 1221 return r; 1222 } 1223 1224 for (i = 0; i < adev->sdma.num_instances; i++) { 1225 ring = &adev->sdma.instance[i].ring; 1226 ring->ring_obj = NULL; 1227 ring->use_doorbell = true; 1228 1229 DRM_INFO("use_doorbell being set to: [%s]\n", 1230 ring->use_doorbell?"true":"false"); 1231 1232 ring->doorbell_index = (i == 0) ? 1233 (adev->doorbell_index.sdma_engine[0] << 1) //get DWORD offset 1234 : (adev->doorbell_index.sdma_engine[1] << 1); // get DWORD offset 1235 1236 sprintf(ring->name, "sdma%d", i); 1237 r = amdgpu_ring_init(adev, ring, 1024, 1238 &adev->sdma.trap_irq, 1239 (i == 0) ? 1240 AMDGPU_SDMA_IRQ_INSTANCE0 : 1241 AMDGPU_SDMA_IRQ_INSTANCE1); 1242 if (r) 1243 return r; 1244 } 1245 1246 return r; 1247 } 1248 1249 static int sdma_v5_0_sw_fini(void *handle) 1250 { 1251 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1252 int i; 1253 1254 for (i = 0; i < adev->sdma.num_instances; i++) 1255 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1256 1257 return 0; 1258 } 1259 1260 static int sdma_v5_0_hw_init(void *handle) 1261 { 1262 int r; 1263 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1264 1265 sdma_v5_0_init_golden_registers(adev); 1266 1267 r = sdma_v5_0_start(adev); 1268 1269 return r; 1270 } 1271 1272 static int sdma_v5_0_hw_fini(void *handle) 1273 { 1274 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1275 1276 if (amdgpu_sriov_vf(adev)) 1277 return 0; 1278 1279 sdma_v5_0_ctx_switch_enable(adev, false); 1280 sdma_v5_0_enable(adev, false); 1281 1282 return 0; 1283 } 1284 1285 static int sdma_v5_0_suspend(void *handle) 1286 { 1287 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1288 1289 return sdma_v5_0_hw_fini(adev); 1290 } 1291 1292 static int sdma_v5_0_resume(void *handle) 1293 { 1294 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1295 1296 return sdma_v5_0_hw_init(adev); 1297 } 1298 1299 static bool sdma_v5_0_is_idle(void *handle) 1300 { 1301 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1302 u32 i; 1303 1304 for (i = 0; i < adev->sdma.num_instances; i++) { 1305 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); 1306 1307 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1308 return false; 1309 } 1310 1311 return true; 1312 } 1313 1314 static int sdma_v5_0_wait_for_idle(void *handle) 1315 { 1316 unsigned i; 1317 u32 sdma0, sdma1; 1318 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1319 1320 for (i = 0; i < adev->usec_timeout; i++) { 1321 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); 1322 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); 1323 1324 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) 1325 return 0; 1326 udelay(1); 1327 } 1328 return -ETIMEDOUT; 1329 } 1330 1331 static int sdma_v5_0_soft_reset(void *handle) 1332 { 1333 /* todo */ 1334 1335 return 0; 1336 } 1337 1338 static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring) 1339 { 1340 int i, r = 0; 1341 struct amdgpu_device *adev = ring->adev; 1342 u32 index = 0; 1343 u64 sdma_gfx_preempt; 1344 1345 amdgpu_sdma_get_index_from_ring(ring, &index); 1346 if (index == 0) 1347 sdma_gfx_preempt = mmSDMA0_GFX_PREEMPT; 1348 else 1349 sdma_gfx_preempt = mmSDMA1_GFX_PREEMPT; 1350 1351 /* assert preemption condition */ 1352 amdgpu_ring_set_preempt_cond_exec(ring, false); 1353 1354 /* emit the trailing fence */ 1355 ring->trail_seq += 1; 1356 amdgpu_ring_alloc(ring, 10); 1357 sdma_v5_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr, 1358 ring->trail_seq, 0); 1359 amdgpu_ring_commit(ring); 1360 1361 /* assert IB preemption */ 1362 WREG32(sdma_gfx_preempt, 1); 1363 1364 /* poll the trailing fence */ 1365 for (i = 0; i < adev->usec_timeout; i++) { 1366 if (ring->trail_seq == 1367 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 1368 break; 1369 udelay(1); 1370 } 1371 1372 if (i >= adev->usec_timeout) { 1373 r = -EINVAL; 1374 DRM_ERROR("ring %d failed to be preempted\n", ring->idx); 1375 } 1376 1377 /* deassert IB preemption */ 1378 WREG32(sdma_gfx_preempt, 0); 1379 1380 /* deassert the preemption condition */ 1381 amdgpu_ring_set_preempt_cond_exec(ring, true); 1382 return r; 1383 } 1384 1385 static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev, 1386 struct amdgpu_irq_src *source, 1387 unsigned type, 1388 enum amdgpu_interrupt_state state) 1389 { 1390 u32 sdma_cntl; 1391 1392 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ? 1393 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : 1394 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); 1395 1396 sdma_cntl = RREG32(reg_offset); 1397 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1398 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 1399 WREG32(reg_offset, sdma_cntl); 1400 1401 return 0; 1402 } 1403 1404 static int sdma_v5_0_process_trap_irq(struct amdgpu_device *adev, 1405 struct amdgpu_irq_src *source, 1406 struct amdgpu_iv_entry *entry) 1407 { 1408 DRM_DEBUG("IH: SDMA trap\n"); 1409 switch (entry->client_id) { 1410 case SOC15_IH_CLIENTID_SDMA0: 1411 switch (entry->ring_id) { 1412 case 0: 1413 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1414 break; 1415 case 1: 1416 /* XXX compute */ 1417 break; 1418 case 2: 1419 /* XXX compute */ 1420 break; 1421 case 3: 1422 /* XXX page queue*/ 1423 break; 1424 } 1425 break; 1426 case SOC15_IH_CLIENTID_SDMA1: 1427 switch (entry->ring_id) { 1428 case 0: 1429 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1430 break; 1431 case 1: 1432 /* XXX compute */ 1433 break; 1434 case 2: 1435 /* XXX compute */ 1436 break; 1437 case 3: 1438 /* XXX page queue*/ 1439 break; 1440 } 1441 break; 1442 } 1443 return 0; 1444 } 1445 1446 static int sdma_v5_0_process_illegal_inst_irq(struct amdgpu_device *adev, 1447 struct amdgpu_irq_src *source, 1448 struct amdgpu_iv_entry *entry) 1449 { 1450 return 0; 1451 } 1452 1453 static void sdma_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 1454 bool enable) 1455 { 1456 uint32_t data, def; 1457 int i; 1458 1459 for (i = 0; i < adev->sdma.num_instances; i++) { 1460 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 1461 /* Enable sdma clock gating */ 1462 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1463 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1464 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1465 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1466 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1467 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1468 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1469 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1470 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1471 if (def != data) 1472 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1473 } else { 1474 /* Disable sdma clock gating */ 1475 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); 1476 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK | 1477 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK | 1478 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK | 1479 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK | 1480 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK | 1481 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK | 1482 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK | 1483 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK); 1484 if (def != data) 1485 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); 1486 } 1487 } 1488 } 1489 1490 static void sdma_v5_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, 1491 bool enable) 1492 { 1493 uint32_t data, def; 1494 int i; 1495 1496 for (i = 0; i < adev->sdma.num_instances; i++) { 1497 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 1498 /* Enable sdma mem light sleep */ 1499 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1500 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1501 if (def != data) 1502 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1503 1504 } else { 1505 /* Disable sdma mem light sleep */ 1506 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1507 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK; 1508 if (def != data) 1509 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1510 1511 } 1512 } 1513 } 1514 1515 static int sdma_v5_0_set_clockgating_state(void *handle, 1516 enum amd_clockgating_state state) 1517 { 1518 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1519 1520 if (amdgpu_sriov_vf(adev)) 1521 return 0; 1522 1523 switch (adev->asic_type) { 1524 case CHIP_NAVI10: 1525 case CHIP_NAVI14: 1526 case CHIP_NAVI12: 1527 sdma_v5_0_update_medium_grain_clock_gating(adev, 1528 state == AMD_CG_STATE_GATE); 1529 sdma_v5_0_update_medium_grain_light_sleep(adev, 1530 state == AMD_CG_STATE_GATE); 1531 break; 1532 default: 1533 break; 1534 } 1535 1536 return 0; 1537 } 1538 1539 static int sdma_v5_0_set_powergating_state(void *handle, 1540 enum amd_powergating_state state) 1541 { 1542 return 0; 1543 } 1544 1545 static void sdma_v5_0_get_clockgating_state(void *handle, u32 *flags) 1546 { 1547 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1548 int data; 1549 1550 if (amdgpu_sriov_vf(adev)) 1551 *flags = 0; 1552 1553 /* AMD_CG_SUPPORT_SDMA_MGCG */ 1554 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); 1555 if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK)) 1556 *flags |= AMD_CG_SUPPORT_SDMA_MGCG; 1557 1558 /* AMD_CG_SUPPORT_SDMA_LS */ 1559 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); 1560 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK) 1561 *flags |= AMD_CG_SUPPORT_SDMA_LS; 1562 } 1563 1564 const struct amd_ip_funcs sdma_v5_0_ip_funcs = { 1565 .name = "sdma_v5_0", 1566 .early_init = sdma_v5_0_early_init, 1567 .late_init = NULL, 1568 .sw_init = sdma_v5_0_sw_init, 1569 .sw_fini = sdma_v5_0_sw_fini, 1570 .hw_init = sdma_v5_0_hw_init, 1571 .hw_fini = sdma_v5_0_hw_fini, 1572 .suspend = sdma_v5_0_suspend, 1573 .resume = sdma_v5_0_resume, 1574 .is_idle = sdma_v5_0_is_idle, 1575 .wait_for_idle = sdma_v5_0_wait_for_idle, 1576 .soft_reset = sdma_v5_0_soft_reset, 1577 .set_clockgating_state = sdma_v5_0_set_clockgating_state, 1578 .set_powergating_state = sdma_v5_0_set_powergating_state, 1579 .get_clockgating_state = sdma_v5_0_get_clockgating_state, 1580 }; 1581 1582 static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = { 1583 .type = AMDGPU_RING_TYPE_SDMA, 1584 .align_mask = 0xf, 1585 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 1586 .support_64bit_ptrs = true, 1587 .vmhub = AMDGPU_GFXHUB_0, 1588 .get_rptr = sdma_v5_0_ring_get_rptr, 1589 .get_wptr = sdma_v5_0_ring_get_wptr, 1590 .set_wptr = sdma_v5_0_ring_set_wptr, 1591 .emit_frame_size = 1592 5 + /* sdma_v5_0_ring_init_cond_exec */ 1593 6 + /* sdma_v5_0_ring_emit_hdp_flush */ 1594 3 + /* hdp_invalidate */ 1595 6 + /* sdma_v5_0_ring_emit_pipeline_sync */ 1596 /* sdma_v5_0_ring_emit_vm_flush */ 1597 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1598 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 * 2 + 1599 10 + 10 + 10, /* sdma_v5_0_ring_emit_fence x3 for user fence, vm fence */ 1600 .emit_ib_size = 7 + 6, /* sdma_v5_0_ring_emit_ib */ 1601 .emit_ib = sdma_v5_0_ring_emit_ib, 1602 .emit_fence = sdma_v5_0_ring_emit_fence, 1603 .emit_pipeline_sync = sdma_v5_0_ring_emit_pipeline_sync, 1604 .emit_vm_flush = sdma_v5_0_ring_emit_vm_flush, 1605 .emit_hdp_flush = sdma_v5_0_ring_emit_hdp_flush, 1606 .test_ring = sdma_v5_0_ring_test_ring, 1607 .test_ib = sdma_v5_0_ring_test_ib, 1608 .insert_nop = sdma_v5_0_ring_insert_nop, 1609 .pad_ib = sdma_v5_0_ring_pad_ib, 1610 .emit_wreg = sdma_v5_0_ring_emit_wreg, 1611 .emit_reg_wait = sdma_v5_0_ring_emit_reg_wait, 1612 .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait, 1613 .init_cond_exec = sdma_v5_0_ring_init_cond_exec, 1614 .patch_cond_exec = sdma_v5_0_ring_patch_cond_exec, 1615 .preempt_ib = sdma_v5_0_ring_preempt_ib, 1616 }; 1617 1618 static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev) 1619 { 1620 int i; 1621 1622 for (i = 0; i < adev->sdma.num_instances; i++) { 1623 adev->sdma.instance[i].ring.funcs = &sdma_v5_0_ring_funcs; 1624 adev->sdma.instance[i].ring.me = i; 1625 } 1626 } 1627 1628 static const struct amdgpu_irq_src_funcs sdma_v5_0_trap_irq_funcs = { 1629 .set = sdma_v5_0_set_trap_irq_state, 1630 .process = sdma_v5_0_process_trap_irq, 1631 }; 1632 1633 static const struct amdgpu_irq_src_funcs sdma_v5_0_illegal_inst_irq_funcs = { 1634 .process = sdma_v5_0_process_illegal_inst_irq, 1635 }; 1636 1637 static void sdma_v5_0_set_irq_funcs(struct amdgpu_device *adev) 1638 { 1639 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 + 1640 adev->sdma.num_instances; 1641 adev->sdma.trap_irq.funcs = &sdma_v5_0_trap_irq_funcs; 1642 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_0_illegal_inst_irq_funcs; 1643 } 1644 1645 /** 1646 * sdma_v5_0_emit_copy_buffer - copy buffer using the sDMA engine 1647 * 1648 * @ring: amdgpu_ring structure holding ring information 1649 * @src_offset: src GPU address 1650 * @dst_offset: dst GPU address 1651 * @byte_count: number of bytes to xfer 1652 * 1653 * Copy GPU buffers using the DMA engine (NAVI10). 1654 * Used by the amdgpu ttm implementation to move pages if 1655 * registered as the asic copy callback. 1656 */ 1657 static void sdma_v5_0_emit_copy_buffer(struct amdgpu_ib *ib, 1658 uint64_t src_offset, 1659 uint64_t dst_offset, 1660 uint32_t byte_count) 1661 { 1662 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) | 1663 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); 1664 ib->ptr[ib->length_dw++] = byte_count - 1; 1665 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1666 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1667 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1668 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1669 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1670 } 1671 1672 /** 1673 * sdma_v5_0_emit_fill_buffer - fill buffer using the sDMA engine 1674 * 1675 * @ring: amdgpu_ring structure holding ring information 1676 * @src_data: value to write to buffer 1677 * @dst_offset: dst GPU address 1678 * @byte_count: number of bytes to xfer 1679 * 1680 * Fill GPU buffers using the DMA engine (NAVI10). 1681 */ 1682 static void sdma_v5_0_emit_fill_buffer(struct amdgpu_ib *ib, 1683 uint32_t src_data, 1684 uint64_t dst_offset, 1685 uint32_t byte_count) 1686 { 1687 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL); 1688 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1689 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1690 ib->ptr[ib->length_dw++] = src_data; 1691 ib->ptr[ib->length_dw++] = byte_count - 1; 1692 } 1693 1694 static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = { 1695 .copy_max_bytes = 0x400000, 1696 .copy_num_dw = 7, 1697 .emit_copy_buffer = sdma_v5_0_emit_copy_buffer, 1698 1699 .fill_max_bytes = 0x400000, 1700 .fill_num_dw = 5, 1701 .emit_fill_buffer = sdma_v5_0_emit_fill_buffer, 1702 }; 1703 1704 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev) 1705 { 1706 if (adev->mman.buffer_funcs == NULL) { 1707 adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs; 1708 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1709 } 1710 } 1711 1712 static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = { 1713 .copy_pte_num_dw = 7, 1714 .copy_pte = sdma_v5_0_vm_copy_pte, 1715 .write_pte = sdma_v5_0_vm_write_pte, 1716 .set_pte_pde = sdma_v5_0_vm_set_pte_pde, 1717 }; 1718 1719 static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev) 1720 { 1721 unsigned i; 1722 1723 if (adev->vm_manager.vm_pte_funcs == NULL) { 1724 adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs; 1725 for (i = 0; i < adev->sdma.num_instances; i++) { 1726 adev->vm_manager.vm_pte_scheds[i] = 1727 &adev->sdma.instance[i].ring.sched; 1728 } 1729 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; 1730 } 1731 } 1732 1733 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = { 1734 .type = AMD_IP_BLOCK_TYPE_SDMA, 1735 .major = 5, 1736 .minor = 0, 1737 .rev = 0, 1738 .funcs = &sdma_v5_0_ip_funcs, 1739 }; 1740