1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Renesas Clock Pulse Generator / Module Standby and Software Reset
8
9maintainers:
10  - Geert Uytterhoeven <geert+renesas@glider.be>
11
12description: |
13  On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
14  and MSSR (Module Standby and Software Reset) blocks are intimately connected,
15  and share the same register block.
16
17  They provide the following functionalities:
18    - The CPG block generates various core clocks,
19    - The MSSR block provides two functions:
20        1. Module Standby, providing a Clock Domain to control the clock supply
21           to individual SoC devices,
22        2. Reset Control, to perform a software reset of individual SoC devices.
23
24properties:
25  compatible:
26    enum:
27      - renesas,r7s9210-cpg-mssr  # RZ/A2
28      - renesas,r8a7742-cpg-mssr  # RZ/G1H
29      - renesas,r8a7743-cpg-mssr  # RZ/G1M
30      - renesas,r8a7744-cpg-mssr  # RZ/G1N
31      - renesas,r8a7745-cpg-mssr  # RZ/G1E
32      - renesas,r8a77470-cpg-mssr # RZ/G1C
33      - renesas,r8a774a1-cpg-mssr # RZ/G2M
34      - renesas,r8a774b1-cpg-mssr # RZ/G2N
35      - renesas,r8a774c0-cpg-mssr # RZ/G2E
36      - renesas,r8a7790-cpg-mssr  # R-Car H2
37      - renesas,r8a7791-cpg-mssr  # R-Car M2-W
38      - renesas,r8a7792-cpg-mssr  # R-Car V2H
39      - renesas,r8a7793-cpg-mssr  # R-Car M2-N
40      - renesas,r8a7794-cpg-mssr  # R-Car E2
41      - renesas,r8a7795-cpg-mssr  # R-Car H3
42      - renesas,r8a7796-cpg-mssr  # R-Car M3-W
43      - renesas,r8a77961-cpg-mssr # R-Car M3-W+
44      - renesas,r8a77965-cpg-mssr # R-Car M3-N
45      - renesas,r8a77970-cpg-mssr # R-Car V3M
46      - renesas,r8a77980-cpg-mssr # R-Car V3H
47      - renesas,r8a77990-cpg-mssr # R-Car E3
48      - renesas,r8a77995-cpg-mssr # R-Car D3
49
50  reg:
51    maxItems: 1
52
53  clocks:
54    minItems: 1
55    maxItems: 2
56
57  clock-names:
58    minItems: 1
59    maxItems: 2
60    items:
61      enum:
62        - extal     # All
63        - extalr    # Most R-Car Gen3 and RZ/G2
64        - usb_extal # Most R-Car Gen2 and RZ/G1
65
66  '#clock-cells':
67    description: |
68      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
69        and a core clock reference, as defined in
70        <dt-bindings/clock/*-cpg-mssr.h>
71      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
72        a module number, as defined in the datasheet.
73    const: 2
74
75  '#power-domain-cells':
76    description:
77      SoC devices that are part of the CPG/MSSR Clock Domain and can be
78      power-managed through Module Standby should refer to the CPG device node
79      in their "power-domains" property, as documented by the generic PM Domain
80      bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
81    const: 0
82
83  '#reset-cells':
84    description:
85      The single reset specifier cell must be the module number, as defined in
86      the datasheet.
87    const: 1
88
89if:
90  not:
91    properties:
92      compatible:
93        items:
94          enum:
95            - renesas,r7s9210-cpg-mssr
96then:
97  required:
98    - '#reset-cells'
99
100required:
101  - compatible
102  - reg
103  - clocks
104  - clock-names
105  - '#clock-cells'
106  - '#power-domain-cells'
107
108additionalProperties: false
109
110examples:
111  - |
112    cpg: clock-controller@e6150000 {
113            compatible = "renesas,r8a7795-cpg-mssr";
114            reg = <0xe6150000 0x1000>;
115            clocks = <&extal_clk>, <&extalr_clk>;
116            clock-names = "extal", "extalr";
117            #clock-cells = <2>;
118            #power-domain-cells = <0>;
119            #reset-cells = <1>;
120    };
121