1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9 #undef DEBUG 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/string.h> 13 #include <linux/kernel.h> 14 #include <linux/slab.h> 15 #include <linux/delay.h> 16 #include <linux/tty.h> 17 #include <linux/serial_reg.h> 18 #include <linux/serial_core.h> 19 #include <linux/8250_pci.h> 20 #include <linux/bitops.h> 21 22 #include <asm/byteorder.h> 23 #include <asm/io.h> 24 25 #include "8250.h" 26 27 /* 28 * init function returns: 29 * > 0 - number of ports 30 * = 0 - use board->num_ports 31 * < 0 - error 32 */ 33 struct pci_serial_quirk { 34 u32 vendor; 35 u32 device; 36 u32 subvendor; 37 u32 subdevice; 38 int (*probe)(struct pci_dev *dev); 39 int (*init)(struct pci_dev *dev); 40 int (*setup)(struct serial_private *, 41 const struct pciserial_board *, 42 struct uart_8250_port *, int); 43 void (*exit)(struct pci_dev *dev); 44 }; 45 46 struct f815xxa_data { 47 spinlock_t lock; 48 int idx; 49 }; 50 51 struct serial_private { 52 struct pci_dev *dev; 53 unsigned int nr; 54 struct pci_serial_quirk *quirk; 55 const struct pciserial_board *board; 56 int line[0]; 57 }; 58 59 static const struct pci_device_id pci_use_msi[] = { 60 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 61 0xA000, 0x1000) }, 62 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 63 0xA000, 0x1000) }, 64 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 65 0xA000, 0x1000) }, 66 { } 67 }; 68 69 static int pci_default_setup(struct serial_private*, 70 const struct pciserial_board*, struct uart_8250_port *, int); 71 72 static void moan_device(const char *str, struct pci_dev *dev) 73 { 74 dev_err(&dev->dev, 75 "%s: %s\n" 76 "Please send the output of lspci -vv, this\n" 77 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 78 "manufacturer and name of serial board or\n" 79 "modem board to <linux-serial@vger.kernel.org>.\n", 80 pci_name(dev), str, dev->vendor, dev->device, 81 dev->subsystem_vendor, dev->subsystem_device); 82 } 83 84 static int 85 setup_port(struct serial_private *priv, struct uart_8250_port *port, 86 int bar, int offset, int regshift) 87 { 88 struct pci_dev *dev = priv->dev; 89 90 if (bar >= PCI_STD_NUM_BARS) 91 return -EINVAL; 92 93 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 94 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) 95 return -ENOMEM; 96 97 port->port.iotype = UPIO_MEM; 98 port->port.iobase = 0; 99 port->port.mapbase = pci_resource_start(dev, bar) + offset; 100 port->port.membase = pcim_iomap_table(dev)[bar] + offset; 101 port->port.regshift = regshift; 102 } else { 103 port->port.iotype = UPIO_PORT; 104 port->port.iobase = pci_resource_start(dev, bar) + offset; 105 port->port.mapbase = 0; 106 port->port.membase = NULL; 107 port->port.regshift = 0; 108 } 109 return 0; 110 } 111 112 /* 113 * ADDI-DATA GmbH communication cards <info@addi-data.com> 114 */ 115 static int addidata_apci7800_setup(struct serial_private *priv, 116 const struct pciserial_board *board, 117 struct uart_8250_port *port, int idx) 118 { 119 unsigned int bar = 0, offset = board->first_offset; 120 bar = FL_GET_BASE(board->flags); 121 122 if (idx < 2) { 123 offset += idx * board->uart_offset; 124 } else if ((idx >= 2) && (idx < 4)) { 125 bar += 1; 126 offset += ((idx - 2) * board->uart_offset); 127 } else if ((idx >= 4) && (idx < 6)) { 128 bar += 2; 129 offset += ((idx - 4) * board->uart_offset); 130 } else if (idx >= 6) { 131 bar += 3; 132 offset += ((idx - 6) * board->uart_offset); 133 } 134 135 return setup_port(priv, port, bar, offset, board->reg_shift); 136 } 137 138 /* 139 * AFAVLAB uses a different mixture of BARs and offsets 140 * Not that ugly ;) -- HW 141 */ 142 static int 143 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 144 struct uart_8250_port *port, int idx) 145 { 146 unsigned int bar, offset = board->first_offset; 147 148 bar = FL_GET_BASE(board->flags); 149 if (idx < 4) 150 bar += idx; 151 else { 152 bar = 4; 153 offset += (idx - 4) * board->uart_offset; 154 } 155 156 return setup_port(priv, port, bar, offset, board->reg_shift); 157 } 158 159 /* 160 * HP's Remote Management Console. The Diva chip came in several 161 * different versions. N-class, L2000 and A500 have two Diva chips, each 162 * with 3 UARTs (the third UART on the second chip is unused). Superdome 163 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 164 * one Diva chip, but it has been expanded to 5 UARTs. 165 */ 166 static int pci_hp_diva_init(struct pci_dev *dev) 167 { 168 int rc = 0; 169 170 switch (dev->subsystem_device) { 171 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 172 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 173 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 174 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 175 rc = 3; 176 break; 177 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 178 rc = 2; 179 break; 180 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 181 rc = 4; 182 break; 183 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 184 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 185 rc = 1; 186 break; 187 } 188 189 return rc; 190 } 191 192 /* 193 * HP's Diva chip puts the 4th/5th serial port further out, and 194 * some serial ports are supposed to be hidden on certain models. 195 */ 196 static int 197 pci_hp_diva_setup(struct serial_private *priv, 198 const struct pciserial_board *board, 199 struct uart_8250_port *port, int idx) 200 { 201 unsigned int offset = board->first_offset; 202 unsigned int bar = FL_GET_BASE(board->flags); 203 204 switch (priv->dev->subsystem_device) { 205 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 206 if (idx == 3) 207 idx++; 208 break; 209 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 210 if (idx > 0) 211 idx++; 212 if (idx > 2) 213 idx++; 214 break; 215 } 216 if (idx > 2) 217 offset = 0x18; 218 219 offset += idx * board->uart_offset; 220 221 return setup_port(priv, port, bar, offset, board->reg_shift); 222 } 223 224 /* 225 * Added for EKF Intel i960 serial boards 226 */ 227 static int pci_inteli960ni_init(struct pci_dev *dev) 228 { 229 u32 oldval; 230 231 if (!(dev->subsystem_device & 0x1000)) 232 return -ENODEV; 233 234 /* is firmware started? */ 235 pci_read_config_dword(dev, 0x44, &oldval); 236 if (oldval == 0x00001000L) { /* RESET value */ 237 dev_dbg(&dev->dev, "Local i960 firmware missing\n"); 238 return -ENODEV; 239 } 240 return 0; 241 } 242 243 /* 244 * Some PCI serial cards using the PLX 9050 PCI interface chip require 245 * that the card interrupt be explicitly enabled or disabled. This 246 * seems to be mainly needed on card using the PLX which also use I/O 247 * mapped memory. 248 */ 249 static int pci_plx9050_init(struct pci_dev *dev) 250 { 251 u8 irq_config; 252 void __iomem *p; 253 254 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 255 moan_device("no memory in bar 0", dev); 256 return 0; 257 } 258 259 irq_config = 0x41; 260 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 261 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 262 irq_config = 0x43; 263 264 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 265 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 266 /* 267 * As the megawolf cards have the int pins active 268 * high, and have 2 UART chips, both ints must be 269 * enabled on the 9050. Also, the UARTS are set in 270 * 16450 mode by default, so we have to enable the 271 * 16C950 'enhanced' mode so that we can use the 272 * deep FIFOs 273 */ 274 irq_config = 0x5b; 275 /* 276 * enable/disable interrupts 277 */ 278 p = ioremap(pci_resource_start(dev, 0), 0x80); 279 if (p == NULL) 280 return -ENOMEM; 281 writel(irq_config, p + 0x4c); 282 283 /* 284 * Read the register back to ensure that it took effect. 285 */ 286 readl(p + 0x4c); 287 iounmap(p); 288 289 return 0; 290 } 291 292 static void pci_plx9050_exit(struct pci_dev *dev) 293 { 294 u8 __iomem *p; 295 296 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 297 return; 298 299 /* 300 * disable interrupts 301 */ 302 p = ioremap(pci_resource_start(dev, 0), 0x80); 303 if (p != NULL) { 304 writel(0, p + 0x4c); 305 306 /* 307 * Read the register back to ensure that it took effect. 308 */ 309 readl(p + 0x4c); 310 iounmap(p); 311 } 312 } 313 314 #define NI8420_INT_ENABLE_REG 0x38 315 #define NI8420_INT_ENABLE_BIT 0x2000 316 317 static void pci_ni8420_exit(struct pci_dev *dev) 318 { 319 void __iomem *p; 320 unsigned int bar = 0; 321 322 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 323 moan_device("no memory in bar", dev); 324 return; 325 } 326 327 p = pci_ioremap_bar(dev, bar); 328 if (p == NULL) 329 return; 330 331 /* Disable the CPU Interrupt */ 332 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 333 p + NI8420_INT_ENABLE_REG); 334 iounmap(p); 335 } 336 337 338 /* MITE registers */ 339 #define MITE_IOWBSR1 0xc4 340 #define MITE_IOWCR1 0xf4 341 #define MITE_LCIMR1 0x08 342 #define MITE_LCIMR2 0x10 343 344 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 345 346 static void pci_ni8430_exit(struct pci_dev *dev) 347 { 348 void __iomem *p; 349 unsigned int bar = 0; 350 351 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 352 moan_device("no memory in bar", dev); 353 return; 354 } 355 356 p = pci_ioremap_bar(dev, bar); 357 if (p == NULL) 358 return; 359 360 /* Disable the CPU Interrupt */ 361 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 362 iounmap(p); 363 } 364 365 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 366 static int 367 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 368 struct uart_8250_port *port, int idx) 369 { 370 unsigned int bar, offset = board->first_offset; 371 372 bar = 0; 373 374 if (idx < 4) { 375 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 376 offset += idx * board->uart_offset; 377 } else if (idx < 8) { 378 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 379 offset += idx * board->uart_offset + 0xC00; 380 } else /* we have only 8 ports on PMC-OCTALPRO */ 381 return 1; 382 383 return setup_port(priv, port, bar, offset, board->reg_shift); 384 } 385 386 /* 387 * This does initialization for PMC OCTALPRO cards: 388 * maps the device memory, resets the UARTs (needed, bc 389 * if the module is removed and inserted again, the card 390 * is in the sleep mode) and enables global interrupt. 391 */ 392 393 /* global control register offset for SBS PMC-OctalPro */ 394 #define OCT_REG_CR_OFF 0x500 395 396 static int sbs_init(struct pci_dev *dev) 397 { 398 u8 __iomem *p; 399 400 p = pci_ioremap_bar(dev, 0); 401 402 if (p == NULL) 403 return -ENOMEM; 404 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 405 writeb(0x10, p + OCT_REG_CR_OFF); 406 udelay(50); 407 writeb(0x0, p + OCT_REG_CR_OFF); 408 409 /* Set bit-2 (INTENABLE) of Control Register */ 410 writeb(0x4, p + OCT_REG_CR_OFF); 411 iounmap(p); 412 413 return 0; 414 } 415 416 /* 417 * Disables the global interrupt of PMC-OctalPro 418 */ 419 420 static void sbs_exit(struct pci_dev *dev) 421 { 422 u8 __iomem *p; 423 424 p = pci_ioremap_bar(dev, 0); 425 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 426 if (p != NULL) 427 writeb(0, p + OCT_REG_CR_OFF); 428 iounmap(p); 429 } 430 431 /* 432 * SIIG serial cards have an PCI interface chip which also controls 433 * the UART clocking frequency. Each UART can be clocked independently 434 * (except cards equipped with 4 UARTs) and initial clocking settings 435 * are stored in the EEPROM chip. It can cause problems because this 436 * version of serial driver doesn't support differently clocked UART's 437 * on single PCI card. To prevent this, initialization functions set 438 * high frequency clocking for all UART's on given card. It is safe (I 439 * hope) because it doesn't touch EEPROM settings to prevent conflicts 440 * with other OSes (like M$ DOS). 441 * 442 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 443 * 444 * There is two family of SIIG serial cards with different PCI 445 * interface chip and different configuration methods: 446 * - 10x cards have control registers in IO and/or memory space; 447 * - 20x cards have control registers in standard PCI configuration space. 448 * 449 * Note: all 10x cards have PCI device ids 0x10.. 450 * all 20x cards have PCI device ids 0x20.. 451 * 452 * There are also Quartet Serial cards which use Oxford Semiconductor 453 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 454 * 455 * Note: some SIIG cards are probed by the parport_serial object. 456 */ 457 458 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 459 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 460 461 static int pci_siig10x_init(struct pci_dev *dev) 462 { 463 u16 data; 464 void __iomem *p; 465 466 switch (dev->device & 0xfff8) { 467 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 468 data = 0xffdf; 469 break; 470 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 471 data = 0xf7ff; 472 break; 473 default: /* 1S1P, 4S */ 474 data = 0xfffb; 475 break; 476 } 477 478 p = ioremap(pci_resource_start(dev, 0), 0x80); 479 if (p == NULL) 480 return -ENOMEM; 481 482 writew(readw(p + 0x28) & data, p + 0x28); 483 readw(p + 0x28); 484 iounmap(p); 485 return 0; 486 } 487 488 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 489 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 490 491 static int pci_siig20x_init(struct pci_dev *dev) 492 { 493 u8 data; 494 495 /* Change clock frequency for the first UART. */ 496 pci_read_config_byte(dev, 0x6f, &data); 497 pci_write_config_byte(dev, 0x6f, data & 0xef); 498 499 /* If this card has 2 UART, we have to do the same with second UART. */ 500 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 501 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 502 pci_read_config_byte(dev, 0x73, &data); 503 pci_write_config_byte(dev, 0x73, data & 0xef); 504 } 505 return 0; 506 } 507 508 static int pci_siig_init(struct pci_dev *dev) 509 { 510 unsigned int type = dev->device & 0xff00; 511 512 if (type == 0x1000) 513 return pci_siig10x_init(dev); 514 else if (type == 0x2000) 515 return pci_siig20x_init(dev); 516 517 moan_device("Unknown SIIG card", dev); 518 return -ENODEV; 519 } 520 521 static int pci_siig_setup(struct serial_private *priv, 522 const struct pciserial_board *board, 523 struct uart_8250_port *port, int idx) 524 { 525 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 526 527 if (idx > 3) { 528 bar = 4; 529 offset = (idx - 4) * 8; 530 } 531 532 return setup_port(priv, port, bar, offset, 0); 533 } 534 535 /* 536 * Timedia has an explosion of boards, and to avoid the PCI table from 537 * growing *huge*, we use this function to collapse some 70 entries 538 * in the PCI table into one, for sanity's and compactness's sake. 539 */ 540 static const unsigned short timedia_single_port[] = { 541 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 542 }; 543 544 static const unsigned short timedia_dual_port[] = { 545 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 546 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 547 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 548 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 549 0xD079, 0 550 }; 551 552 static const unsigned short timedia_quad_port[] = { 553 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 554 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 555 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 556 0xB157, 0 557 }; 558 559 static const unsigned short timedia_eight_port[] = { 560 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 561 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 562 }; 563 564 static const struct timedia_struct { 565 int num; 566 const unsigned short *ids; 567 } timedia_data[] = { 568 { 1, timedia_single_port }, 569 { 2, timedia_dual_port }, 570 { 4, timedia_quad_port }, 571 { 8, timedia_eight_port } 572 }; 573 574 /* 575 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 576 * listing them individually, this driver merely grabs them all with 577 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 578 * and should be left free to be claimed by parport_serial instead. 579 */ 580 static int pci_timedia_probe(struct pci_dev *dev) 581 { 582 /* 583 * Check the third digit of the subdevice ID 584 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 585 */ 586 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 587 dev_info(&dev->dev, 588 "ignoring Timedia subdevice %04x for parport_serial\n", 589 dev->subsystem_device); 590 return -ENODEV; 591 } 592 593 return 0; 594 } 595 596 static int pci_timedia_init(struct pci_dev *dev) 597 { 598 const unsigned short *ids; 599 int i, j; 600 601 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 602 ids = timedia_data[i].ids; 603 for (j = 0; ids[j]; j++) 604 if (dev->subsystem_device == ids[j]) 605 return timedia_data[i].num; 606 } 607 return 0; 608 } 609 610 /* 611 * Timedia/SUNIX uses a mixture of BARs and offsets 612 * Ugh, this is ugly as all hell --- TYT 613 */ 614 static int 615 pci_timedia_setup(struct serial_private *priv, 616 const struct pciserial_board *board, 617 struct uart_8250_port *port, int idx) 618 { 619 unsigned int bar = 0, offset = board->first_offset; 620 621 switch (idx) { 622 case 0: 623 bar = 0; 624 break; 625 case 1: 626 offset = board->uart_offset; 627 bar = 0; 628 break; 629 case 2: 630 bar = 1; 631 break; 632 case 3: 633 offset = board->uart_offset; 634 /* FALLTHROUGH */ 635 case 4: /* BAR 2 */ 636 case 5: /* BAR 3 */ 637 case 6: /* BAR 4 */ 638 case 7: /* BAR 5 */ 639 bar = idx - 2; 640 } 641 642 return setup_port(priv, port, bar, offset, board->reg_shift); 643 } 644 645 /* 646 * Some Titan cards are also a little weird 647 */ 648 static int 649 titan_400l_800l_setup(struct serial_private *priv, 650 const struct pciserial_board *board, 651 struct uart_8250_port *port, int idx) 652 { 653 unsigned int bar, offset = board->first_offset; 654 655 switch (idx) { 656 case 0: 657 bar = 1; 658 break; 659 case 1: 660 bar = 2; 661 break; 662 default: 663 bar = 4; 664 offset = (idx - 2) * board->uart_offset; 665 } 666 667 return setup_port(priv, port, bar, offset, board->reg_shift); 668 } 669 670 static int pci_xircom_init(struct pci_dev *dev) 671 { 672 msleep(100); 673 return 0; 674 } 675 676 static int pci_ni8420_init(struct pci_dev *dev) 677 { 678 void __iomem *p; 679 unsigned int bar = 0; 680 681 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 682 moan_device("no memory in bar", dev); 683 return 0; 684 } 685 686 p = pci_ioremap_bar(dev, bar); 687 if (p == NULL) 688 return -ENOMEM; 689 690 /* Enable CPU Interrupt */ 691 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 692 p + NI8420_INT_ENABLE_REG); 693 694 iounmap(p); 695 return 0; 696 } 697 698 #define MITE_IOWBSR1_WSIZE 0xa 699 #define MITE_IOWBSR1_WIN_OFFSET 0x800 700 #define MITE_IOWBSR1_WENAB (1 << 7) 701 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 702 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 703 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 704 705 static int pci_ni8430_init(struct pci_dev *dev) 706 { 707 void __iomem *p; 708 struct pci_bus_region region; 709 u32 device_window; 710 unsigned int bar = 0; 711 712 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 713 moan_device("no memory in bar", dev); 714 return 0; 715 } 716 717 p = pci_ioremap_bar(dev, bar); 718 if (p == NULL) 719 return -ENOMEM; 720 721 /* 722 * Set device window address and size in BAR0, while acknowledging that 723 * the resource structure may contain a translated address that differs 724 * from the address the device responds to. 725 */ 726 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 727 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 728 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 729 writel(device_window, p + MITE_IOWBSR1); 730 731 /* Set window access to go to RAMSEL IO address space */ 732 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 733 p + MITE_IOWCR1); 734 735 /* Enable IO Bus Interrupt 0 */ 736 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 737 738 /* Enable CPU Interrupt */ 739 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 740 741 iounmap(p); 742 return 0; 743 } 744 745 /* UART Port Control Register */ 746 #define NI8430_PORTCON 0x0f 747 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 748 749 static int 750 pci_ni8430_setup(struct serial_private *priv, 751 const struct pciserial_board *board, 752 struct uart_8250_port *port, int idx) 753 { 754 struct pci_dev *dev = priv->dev; 755 void __iomem *p; 756 unsigned int bar, offset = board->first_offset; 757 758 if (idx >= board->num_ports) 759 return 1; 760 761 bar = FL_GET_BASE(board->flags); 762 offset += idx * board->uart_offset; 763 764 p = pci_ioremap_bar(dev, bar); 765 if (!p) 766 return -ENOMEM; 767 768 /* enable the transceiver */ 769 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 770 p + offset + NI8430_PORTCON); 771 772 iounmap(p); 773 774 return setup_port(priv, port, bar, offset, board->reg_shift); 775 } 776 777 static int pci_netmos_9900_setup(struct serial_private *priv, 778 const struct pciserial_board *board, 779 struct uart_8250_port *port, int idx) 780 { 781 unsigned int bar; 782 783 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 784 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 785 /* netmos apparently orders BARs by datasheet layout, so serial 786 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 787 */ 788 bar = 3 * idx; 789 790 return setup_port(priv, port, bar, 0, board->reg_shift); 791 } else { 792 return pci_default_setup(priv, board, port, idx); 793 } 794 } 795 796 /* the 99xx series comes with a range of device IDs and a variety 797 * of capabilities: 798 * 799 * 9900 has varying capabilities and can cascade to sub-controllers 800 * (cascading should be purely internal) 801 * 9904 is hardwired with 4 serial ports 802 * 9912 and 9922 are hardwired with 2 serial ports 803 */ 804 static int pci_netmos_9900_numports(struct pci_dev *dev) 805 { 806 unsigned int c = dev->class; 807 unsigned int pi; 808 unsigned short sub_serports; 809 810 pi = c & 0xff; 811 812 if (pi == 2) 813 return 1; 814 815 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 816 /* two possibilities: 0x30ps encodes number of parallel and 817 * serial ports, or 0x1000 indicates *something*. This is not 818 * immediately obvious, since the 2s1p+4s configuration seems 819 * to offer all functionality on functions 0..2, while still 820 * advertising the same function 3 as the 4s+2s1p config. 821 */ 822 sub_serports = dev->subsystem_device & 0xf; 823 if (sub_serports > 0) 824 return sub_serports; 825 826 dev_err(&dev->dev, 827 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 828 return 0; 829 } 830 831 moan_device("unknown NetMos/Mostech program interface", dev); 832 return 0; 833 } 834 835 static int pci_netmos_init(struct pci_dev *dev) 836 { 837 /* subdevice 0x00PS means <P> parallel, <S> serial */ 838 unsigned int num_serial = dev->subsystem_device & 0xf; 839 840 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 841 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 842 return 0; 843 844 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 845 dev->subsystem_device == 0x0299) 846 return 0; 847 848 switch (dev->device) { /* FALLTHROUGH on all */ 849 case PCI_DEVICE_ID_NETMOS_9904: 850 case PCI_DEVICE_ID_NETMOS_9912: 851 case PCI_DEVICE_ID_NETMOS_9922: 852 case PCI_DEVICE_ID_NETMOS_9900: 853 num_serial = pci_netmos_9900_numports(dev); 854 break; 855 856 default: 857 break; 858 } 859 860 if (num_serial == 0) { 861 moan_device("unknown NetMos/Mostech device", dev); 862 return -ENODEV; 863 } 864 865 return num_serial; 866 } 867 868 /* 869 * These chips are available with optionally one parallel port and up to 870 * two serial ports. Unfortunately they all have the same product id. 871 * 872 * Basic configuration is done over a region of 32 I/O ports. The base 873 * ioport is called INTA or INTC, depending on docs/other drivers. 874 * 875 * The region of the 32 I/O ports is configured in POSIO0R... 876 */ 877 878 /* registers */ 879 #define ITE_887x_MISCR 0x9c 880 #define ITE_887x_INTCBAR 0x78 881 #define ITE_887x_UARTBAR 0x7c 882 #define ITE_887x_PS0BAR 0x10 883 #define ITE_887x_POSIO0 0x60 884 885 /* I/O space size */ 886 #define ITE_887x_IOSIZE 32 887 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 888 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 889 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 890 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 891 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 892 #define ITE_887x_POSIO_SPEED (3 << 29) 893 /* enable IO_Space bit */ 894 #define ITE_887x_POSIO_ENABLE (1 << 31) 895 896 static int pci_ite887x_init(struct pci_dev *dev) 897 { 898 /* inta_addr are the configuration addresses of the ITE */ 899 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 900 0x200, 0x280, 0 }; 901 int ret, i, type; 902 struct resource *iobase = NULL; 903 u32 miscr, uartbar, ioport; 904 905 /* search for the base-ioport */ 906 i = 0; 907 while (inta_addr[i] && iobase == NULL) { 908 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 909 "ite887x"); 910 if (iobase != NULL) { 911 /* write POSIO0R - speed | size | ioport */ 912 pci_write_config_dword(dev, ITE_887x_POSIO0, 913 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 914 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 915 /* write INTCBAR - ioport */ 916 pci_write_config_dword(dev, ITE_887x_INTCBAR, 917 inta_addr[i]); 918 ret = inb(inta_addr[i]); 919 if (ret != 0xff) { 920 /* ioport connected */ 921 break; 922 } 923 release_region(iobase->start, ITE_887x_IOSIZE); 924 iobase = NULL; 925 } 926 i++; 927 } 928 929 if (!inta_addr[i]) { 930 dev_err(&dev->dev, "ite887x: could not find iobase\n"); 931 return -ENODEV; 932 } 933 934 /* start of undocumented type checking (see parport_pc.c) */ 935 type = inb(iobase->start + 0x18) & 0x0f; 936 937 switch (type) { 938 case 0x2: /* ITE8871 (1P) */ 939 case 0xa: /* ITE8875 (1P) */ 940 ret = 0; 941 break; 942 case 0xe: /* ITE8872 (2S1P) */ 943 ret = 2; 944 break; 945 case 0x6: /* ITE8873 (1S) */ 946 ret = 1; 947 break; 948 case 0x8: /* ITE8874 (2S) */ 949 ret = 2; 950 break; 951 default: 952 moan_device("Unknown ITE887x", dev); 953 ret = -ENODEV; 954 } 955 956 /* configure all serial ports */ 957 for (i = 0; i < ret; i++) { 958 /* read the I/O port from the device */ 959 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 960 &ioport); 961 ioport &= 0x0000FF00; /* the actual base address */ 962 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 963 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 964 ITE_887x_POSIO_IOSIZE_8 | ioport); 965 966 /* write the ioport to the UARTBAR */ 967 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 968 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 969 uartbar |= (ioport << (16 * i)); /* set the ioport */ 970 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 971 972 /* get current config */ 973 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 974 /* disable interrupts (UARTx_Routing[3:0]) */ 975 miscr &= ~(0xf << (12 - 4 * i)); 976 /* activate the UART (UARTx_En) */ 977 miscr |= 1 << (23 - i); 978 /* write new config with activated UART */ 979 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 980 } 981 982 if (ret <= 0) { 983 /* the device has no UARTs if we get here */ 984 release_region(iobase->start, ITE_887x_IOSIZE); 985 } 986 987 return ret; 988 } 989 990 static void pci_ite887x_exit(struct pci_dev *dev) 991 { 992 u32 ioport; 993 /* the ioport is bit 0-15 in POSIO0R */ 994 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 995 ioport &= 0xffff; 996 release_region(ioport, ITE_887x_IOSIZE); 997 } 998 999 /* 1000 * EndRun Technologies. 1001 * Determine the number of ports available on the device. 1002 */ 1003 #define PCI_VENDOR_ID_ENDRUN 0x7401 1004 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 1005 1006 static int pci_endrun_init(struct pci_dev *dev) 1007 { 1008 u8 __iomem *p; 1009 unsigned long deviceID; 1010 unsigned int number_uarts = 0; 1011 1012 /* EndRun device is all 0xexxx */ 1013 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1014 (dev->device & 0xf000) != 0xe000) 1015 return 0; 1016 1017 p = pci_iomap(dev, 0, 5); 1018 if (p == NULL) 1019 return -ENOMEM; 1020 1021 deviceID = ioread32(p); 1022 /* EndRun device */ 1023 if (deviceID == 0x07000200) { 1024 number_uarts = ioread8(p + 4); 1025 dev_dbg(&dev->dev, 1026 "%d ports detected on EndRun PCI Express device\n", 1027 number_uarts); 1028 } 1029 pci_iounmap(dev, p); 1030 return number_uarts; 1031 } 1032 1033 /* 1034 * Oxford Semiconductor Inc. 1035 * Check that device is part of the Tornado range of devices, then determine 1036 * the number of ports available on the device. 1037 */ 1038 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1039 { 1040 u8 __iomem *p; 1041 unsigned long deviceID; 1042 unsigned int number_uarts = 0; 1043 1044 /* OxSemi Tornado devices are all 0xCxxx */ 1045 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1046 (dev->device & 0xF000) != 0xC000) 1047 return 0; 1048 1049 p = pci_iomap(dev, 0, 5); 1050 if (p == NULL) 1051 return -ENOMEM; 1052 1053 deviceID = ioread32(p); 1054 /* Tornado device */ 1055 if (deviceID == 0x07000200) { 1056 number_uarts = ioread8(p + 4); 1057 dev_dbg(&dev->dev, 1058 "%d ports detected on Oxford PCI Express device\n", 1059 number_uarts); 1060 } 1061 pci_iounmap(dev, p); 1062 return number_uarts; 1063 } 1064 1065 static int pci_asix_setup(struct serial_private *priv, 1066 const struct pciserial_board *board, 1067 struct uart_8250_port *port, int idx) 1068 { 1069 port->bugs |= UART_BUG_PARITY; 1070 return pci_default_setup(priv, board, port, idx); 1071 } 1072 1073 /* Quatech devices have their own extra interface features */ 1074 1075 struct quatech_feature { 1076 u16 devid; 1077 bool amcc; 1078 }; 1079 1080 #define QPCR_TEST_FOR1 0x3F 1081 #define QPCR_TEST_GET1 0x00 1082 #define QPCR_TEST_FOR2 0x40 1083 #define QPCR_TEST_GET2 0x40 1084 #define QPCR_TEST_FOR3 0x80 1085 #define QPCR_TEST_GET3 0x40 1086 #define QPCR_TEST_FOR4 0xC0 1087 #define QPCR_TEST_GET4 0x80 1088 1089 #define QOPR_CLOCK_X1 0x0000 1090 #define QOPR_CLOCK_X2 0x0001 1091 #define QOPR_CLOCK_X4 0x0002 1092 #define QOPR_CLOCK_X8 0x0003 1093 #define QOPR_CLOCK_RATE_MASK 0x0003 1094 1095 1096 static struct quatech_feature quatech_cards[] = { 1097 { PCI_DEVICE_ID_QUATECH_QSC100, 1 }, 1098 { PCI_DEVICE_ID_QUATECH_DSC100, 1 }, 1099 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 }, 1100 { PCI_DEVICE_ID_QUATECH_DSC200, 1 }, 1101 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 }, 1102 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 }, 1103 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 }, 1104 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 }, 1105 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 }, 1106 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 }, 1107 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 }, 1108 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 }, 1109 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 }, 1110 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 }, 1111 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 }, 1112 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 }, 1113 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 }, 1114 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 }, 1115 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 }, 1116 { 0, } 1117 }; 1118 1119 static int pci_quatech_amcc(u16 devid) 1120 { 1121 struct quatech_feature *qf = &quatech_cards[0]; 1122 while (qf->devid) { 1123 if (qf->devid == devid) 1124 return qf->amcc; 1125 qf++; 1126 } 1127 pr_err("quatech: unknown port type '0x%04X'.\n", devid); 1128 return 0; 1129 }; 1130 1131 static int pci_quatech_rqopr(struct uart_8250_port *port) 1132 { 1133 unsigned long base = port->port.iobase; 1134 u8 LCR, val; 1135 1136 LCR = inb(base + UART_LCR); 1137 outb(0xBF, base + UART_LCR); 1138 val = inb(base + UART_SCR); 1139 outb(LCR, base + UART_LCR); 1140 return val; 1141 } 1142 1143 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1144 { 1145 unsigned long base = port->port.iobase; 1146 u8 LCR; 1147 1148 LCR = inb(base + UART_LCR); 1149 outb(0xBF, base + UART_LCR); 1150 inb(base + UART_SCR); 1151 outb(qopr, base + UART_SCR); 1152 outb(LCR, base + UART_LCR); 1153 } 1154 1155 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1156 { 1157 unsigned long base = port->port.iobase; 1158 u8 LCR, val, qmcr; 1159 1160 LCR = inb(base + UART_LCR); 1161 outb(0xBF, base + UART_LCR); 1162 val = inb(base + UART_SCR); 1163 outb(val | 0x10, base + UART_SCR); 1164 qmcr = inb(base + UART_MCR); 1165 outb(val, base + UART_SCR); 1166 outb(LCR, base + UART_LCR); 1167 1168 return qmcr; 1169 } 1170 1171 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1172 { 1173 unsigned long base = port->port.iobase; 1174 u8 LCR, val; 1175 1176 LCR = inb(base + UART_LCR); 1177 outb(0xBF, base + UART_LCR); 1178 val = inb(base + UART_SCR); 1179 outb(val | 0x10, base + UART_SCR); 1180 outb(qmcr, base + UART_MCR); 1181 outb(val, base + UART_SCR); 1182 outb(LCR, base + UART_LCR); 1183 } 1184 1185 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1186 { 1187 unsigned long base = port->port.iobase; 1188 u8 LCR, val; 1189 1190 LCR = inb(base + UART_LCR); 1191 outb(0xBF, base + UART_LCR); 1192 val = inb(base + UART_SCR); 1193 if (val & 0x20) { 1194 outb(0x80, UART_LCR); 1195 if (!(inb(UART_SCR) & 0x20)) { 1196 outb(LCR, base + UART_LCR); 1197 return 1; 1198 } 1199 } 1200 return 0; 1201 } 1202 1203 static int pci_quatech_test(struct uart_8250_port *port) 1204 { 1205 u8 reg, qopr; 1206 1207 qopr = pci_quatech_rqopr(port); 1208 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1209 reg = pci_quatech_rqopr(port) & 0xC0; 1210 if (reg != QPCR_TEST_GET1) 1211 return -EINVAL; 1212 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1213 reg = pci_quatech_rqopr(port) & 0xC0; 1214 if (reg != QPCR_TEST_GET2) 1215 return -EINVAL; 1216 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1217 reg = pci_quatech_rqopr(port) & 0xC0; 1218 if (reg != QPCR_TEST_GET3) 1219 return -EINVAL; 1220 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1221 reg = pci_quatech_rqopr(port) & 0xC0; 1222 if (reg != QPCR_TEST_GET4) 1223 return -EINVAL; 1224 1225 pci_quatech_wqopr(port, qopr); 1226 return 0; 1227 } 1228 1229 static int pci_quatech_clock(struct uart_8250_port *port) 1230 { 1231 u8 qopr, reg, set; 1232 unsigned long clock; 1233 1234 if (pci_quatech_test(port) < 0) 1235 return 1843200; 1236 1237 qopr = pci_quatech_rqopr(port); 1238 1239 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1240 reg = pci_quatech_rqopr(port); 1241 if (reg & QOPR_CLOCK_X8) { 1242 clock = 1843200; 1243 goto out; 1244 } 1245 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1246 reg = pci_quatech_rqopr(port); 1247 if (!(reg & QOPR_CLOCK_X8)) { 1248 clock = 1843200; 1249 goto out; 1250 } 1251 reg &= QOPR_CLOCK_X8; 1252 if (reg == QOPR_CLOCK_X2) { 1253 clock = 3685400; 1254 set = QOPR_CLOCK_X2; 1255 } else if (reg == QOPR_CLOCK_X4) { 1256 clock = 7372800; 1257 set = QOPR_CLOCK_X4; 1258 } else if (reg == QOPR_CLOCK_X8) { 1259 clock = 14745600; 1260 set = QOPR_CLOCK_X8; 1261 } else { 1262 clock = 1843200; 1263 set = QOPR_CLOCK_X1; 1264 } 1265 qopr &= ~QOPR_CLOCK_RATE_MASK; 1266 qopr |= set; 1267 1268 out: 1269 pci_quatech_wqopr(port, qopr); 1270 return clock; 1271 } 1272 1273 static int pci_quatech_rs422(struct uart_8250_port *port) 1274 { 1275 u8 qmcr; 1276 int rs422 = 0; 1277 1278 if (!pci_quatech_has_qmcr(port)) 1279 return 0; 1280 qmcr = pci_quatech_rqmcr(port); 1281 pci_quatech_wqmcr(port, 0xFF); 1282 if (pci_quatech_rqmcr(port)) 1283 rs422 = 1; 1284 pci_quatech_wqmcr(port, qmcr); 1285 return rs422; 1286 } 1287 1288 static int pci_quatech_init(struct pci_dev *dev) 1289 { 1290 if (pci_quatech_amcc(dev->device)) { 1291 unsigned long base = pci_resource_start(dev, 0); 1292 if (base) { 1293 u32 tmp; 1294 1295 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1296 tmp = inl(base + 0x3c); 1297 outl(tmp | 0x01000000, base + 0x3c); 1298 outl(tmp &= ~0x01000000, base + 0x3c); 1299 } 1300 } 1301 return 0; 1302 } 1303 1304 static int pci_quatech_setup(struct serial_private *priv, 1305 const struct pciserial_board *board, 1306 struct uart_8250_port *port, int idx) 1307 { 1308 /* Needed by pci_quatech calls below */ 1309 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1310 /* Set up the clocking */ 1311 port->port.uartclk = pci_quatech_clock(port); 1312 /* For now just warn about RS422 */ 1313 if (pci_quatech_rs422(port)) 1314 pr_warn("quatech: software control of RS422 features not currently supported.\n"); 1315 return pci_default_setup(priv, board, port, idx); 1316 } 1317 1318 static void pci_quatech_exit(struct pci_dev *dev) 1319 { 1320 } 1321 1322 static int pci_default_setup(struct serial_private *priv, 1323 const struct pciserial_board *board, 1324 struct uart_8250_port *port, int idx) 1325 { 1326 unsigned int bar, offset = board->first_offset, maxnr; 1327 1328 bar = FL_GET_BASE(board->flags); 1329 if (board->flags & FL_BASE_BARS) 1330 bar += idx; 1331 else 1332 offset += idx * board->uart_offset; 1333 1334 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1335 (board->reg_shift + 3); 1336 1337 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1338 return 1; 1339 1340 return setup_port(priv, port, bar, offset, board->reg_shift); 1341 } 1342 static void 1343 pericom_do_set_divisor(struct uart_port *port, unsigned int baud, 1344 unsigned int quot, unsigned int quot_frac) 1345 { 1346 int scr; 1347 int lcr; 1348 int actual_baud; 1349 int tolerance; 1350 1351 for (scr = 5 ; scr <= 15 ; scr++) { 1352 actual_baud = 921600 * 16 / scr; 1353 tolerance = actual_baud / 50; 1354 1355 if ((baud < actual_baud + tolerance) && 1356 (baud > actual_baud - tolerance)) { 1357 1358 lcr = serial_port_in(port, UART_LCR); 1359 serial_port_out(port, UART_LCR, lcr | 0x80); 1360 1361 serial_port_out(port, UART_DLL, 1); 1362 serial_port_out(port, UART_DLM, 0); 1363 serial_port_out(port, 2, 16 - scr); 1364 serial_port_out(port, UART_LCR, lcr); 1365 return; 1366 } else if (baud > actual_baud) { 1367 break; 1368 } 1369 } 1370 serial8250_do_set_divisor(port, baud, quot, quot_frac); 1371 } 1372 static int pci_pericom_setup(struct serial_private *priv, 1373 const struct pciserial_board *board, 1374 struct uart_8250_port *port, int idx) 1375 { 1376 unsigned int bar, offset = board->first_offset, maxnr; 1377 1378 bar = FL_GET_BASE(board->flags); 1379 if (board->flags & FL_BASE_BARS) 1380 bar += idx; 1381 else 1382 offset += idx * board->uart_offset; 1383 1384 1385 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1386 (board->reg_shift + 3); 1387 1388 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1389 return 1; 1390 1391 port->port.set_divisor = pericom_do_set_divisor; 1392 1393 return setup_port(priv, port, bar, offset, board->reg_shift); 1394 } 1395 1396 static int pci_pericom_setup_four_at_eight(struct serial_private *priv, 1397 const struct pciserial_board *board, 1398 struct uart_8250_port *port, int idx) 1399 { 1400 unsigned int bar, offset = board->first_offset, maxnr; 1401 1402 bar = FL_GET_BASE(board->flags); 1403 if (board->flags & FL_BASE_BARS) 1404 bar += idx; 1405 else 1406 offset += idx * board->uart_offset; 1407 1408 if (idx==3) 1409 offset = 0x38; 1410 1411 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1412 (board->reg_shift + 3); 1413 1414 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1415 return 1; 1416 1417 port->port.set_divisor = pericom_do_set_divisor; 1418 1419 return setup_port(priv, port, bar, offset, board->reg_shift); 1420 } 1421 1422 static int 1423 ce4100_serial_setup(struct serial_private *priv, 1424 const struct pciserial_board *board, 1425 struct uart_8250_port *port, int idx) 1426 { 1427 int ret; 1428 1429 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1430 port->port.iotype = UPIO_MEM32; 1431 port->port.type = PORT_XSCALE; 1432 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1433 port->port.regshift = 2; 1434 1435 return ret; 1436 } 1437 1438 static int 1439 pci_omegapci_setup(struct serial_private *priv, 1440 const struct pciserial_board *board, 1441 struct uart_8250_port *port, int idx) 1442 { 1443 return setup_port(priv, port, 2, idx * 8, 0); 1444 } 1445 1446 static int 1447 pci_brcm_trumanage_setup(struct serial_private *priv, 1448 const struct pciserial_board *board, 1449 struct uart_8250_port *port, int idx) 1450 { 1451 int ret = pci_default_setup(priv, board, port, idx); 1452 1453 port->port.type = PORT_BRCM_TRUMANAGE; 1454 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1455 return ret; 1456 } 1457 1458 /* RTS will control by MCR if this bit is 0 */ 1459 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1460 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1461 #define FINTEK_RTS_INVERT BIT(5) 1462 1463 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1464 static int pci_fintek_rs485_config(struct uart_port *port, 1465 struct serial_rs485 *rs485) 1466 { 1467 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1468 u8 setting; 1469 u8 *index = (u8 *) port->private_data; 1470 1471 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1472 1473 if (!rs485) 1474 rs485 = &port->rs485; 1475 else if (rs485->flags & SER_RS485_ENABLED) 1476 memset(rs485->padding, 0, sizeof(rs485->padding)); 1477 else 1478 memset(rs485, 0, sizeof(*rs485)); 1479 1480 /* F81504/508/512 not support RTS delay before or after send */ 1481 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND; 1482 1483 if (rs485->flags & SER_RS485_ENABLED) { 1484 /* Enable RTS H/W control mode */ 1485 setting |= FINTEK_RTS_CONTROL_BY_HW; 1486 1487 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1488 /* RTS driving high on TX */ 1489 setting &= ~FINTEK_RTS_INVERT; 1490 } else { 1491 /* RTS driving low on TX */ 1492 setting |= FINTEK_RTS_INVERT; 1493 } 1494 1495 rs485->delay_rts_after_send = 0; 1496 rs485->delay_rts_before_send = 0; 1497 } else { 1498 /* Disable RTS H/W control mode */ 1499 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1500 } 1501 1502 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1503 1504 if (rs485 != &port->rs485) 1505 port->rs485 = *rs485; 1506 1507 return 0; 1508 } 1509 1510 static int pci_fintek_setup(struct serial_private *priv, 1511 const struct pciserial_board *board, 1512 struct uart_8250_port *port, int idx) 1513 { 1514 struct pci_dev *pdev = priv->dev; 1515 u8 *data; 1516 u8 config_base; 1517 u16 iobase; 1518 1519 config_base = 0x40 + 0x08 * idx; 1520 1521 /* Get the io address from configuration space */ 1522 pci_read_config_word(pdev, config_base + 4, &iobase); 1523 1524 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase); 1525 1526 port->port.iotype = UPIO_PORT; 1527 port->port.iobase = iobase; 1528 port->port.rs485_config = pci_fintek_rs485_config; 1529 1530 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1531 if (!data) 1532 return -ENOMEM; 1533 1534 /* preserve index in PCI configuration space */ 1535 *data = idx; 1536 port->port.private_data = data; 1537 1538 return 0; 1539 } 1540 1541 static int pci_fintek_init(struct pci_dev *dev) 1542 { 1543 unsigned long iobase; 1544 u32 max_port, i; 1545 resource_size_t bar_data[3]; 1546 u8 config_base; 1547 struct serial_private *priv = pci_get_drvdata(dev); 1548 struct uart_8250_port *port; 1549 1550 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1551 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1552 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1553 return -ENODEV; 1554 1555 switch (dev->device) { 1556 case 0x1104: /* 4 ports */ 1557 case 0x1108: /* 8 ports */ 1558 max_port = dev->device & 0xff; 1559 break; 1560 case 0x1112: /* 12 ports */ 1561 max_port = 12; 1562 break; 1563 default: 1564 return -EINVAL; 1565 } 1566 1567 /* Get the io address dispatch from the BIOS */ 1568 bar_data[0] = pci_resource_start(dev, 5); 1569 bar_data[1] = pci_resource_start(dev, 4); 1570 bar_data[2] = pci_resource_start(dev, 3); 1571 1572 for (i = 0; i < max_port; ++i) { 1573 /* UART0 configuration offset start from 0x40 */ 1574 config_base = 0x40 + 0x08 * i; 1575 1576 /* Calculate Real IO Port */ 1577 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1578 1579 /* Enable UART I/O port */ 1580 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1581 1582 /* Select 128-byte FIFO and 8x FIFO threshold */ 1583 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1584 1585 /* LSB UART */ 1586 pci_write_config_byte(dev, config_base + 0x04, 1587 (u8)(iobase & 0xff)); 1588 1589 /* MSB UART */ 1590 pci_write_config_byte(dev, config_base + 0x05, 1591 (u8)((iobase & 0xff00) >> 8)); 1592 1593 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1594 1595 if (priv) { 1596 /* re-apply RS232/485 mode when 1597 * pciserial_resume_ports() 1598 */ 1599 port = serial8250_get_port(priv->line[i]); 1600 pci_fintek_rs485_config(&port->port, NULL); 1601 } else { 1602 /* First init without port data 1603 * force init to RS232 Mode 1604 */ 1605 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1606 } 1607 } 1608 1609 return max_port; 1610 } 1611 1612 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value) 1613 { 1614 struct f815xxa_data *data = p->private_data; 1615 unsigned long flags; 1616 1617 spin_lock_irqsave(&data->lock, flags); 1618 writeb(value, p->membase + offset); 1619 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ 1620 spin_unlock_irqrestore(&data->lock, flags); 1621 } 1622 1623 static int pci_fintek_f815xxa_setup(struct serial_private *priv, 1624 const struct pciserial_board *board, 1625 struct uart_8250_port *port, int idx) 1626 { 1627 struct pci_dev *pdev = priv->dev; 1628 struct f815xxa_data *data; 1629 1630 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 1631 if (!data) 1632 return -ENOMEM; 1633 1634 data->idx = idx; 1635 spin_lock_init(&data->lock); 1636 1637 port->port.private_data = data; 1638 port->port.iotype = UPIO_MEM; 1639 port->port.flags |= UPF_IOREMAP; 1640 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; 1641 port->port.serial_out = f815xxa_mem_serial_out; 1642 1643 return 0; 1644 } 1645 1646 static int pci_fintek_f815xxa_init(struct pci_dev *dev) 1647 { 1648 u32 max_port, i; 1649 int config_base; 1650 1651 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) 1652 return -ENODEV; 1653 1654 switch (dev->device) { 1655 case 0x1204: /* 4 ports */ 1656 case 0x1208: /* 8 ports */ 1657 max_port = dev->device & 0xff; 1658 break; 1659 case 0x1212: /* 12 ports */ 1660 max_port = 12; 1661 break; 1662 default: 1663 return -EINVAL; 1664 } 1665 1666 /* Set to mmio decode */ 1667 pci_write_config_byte(dev, 0x209, 0x40); 1668 1669 for (i = 0; i < max_port; ++i) { 1670 /* UART0 configuration offset start from 0x2A0 */ 1671 config_base = 0x2A0 + 0x08 * i; 1672 1673 /* Select 128-byte FIFO and 8x FIFO threshold */ 1674 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1675 1676 /* Enable UART I/O port */ 1677 pci_write_config_byte(dev, config_base + 0, 0x01); 1678 } 1679 1680 return max_port; 1681 } 1682 1683 static int skip_tx_en_setup(struct serial_private *priv, 1684 const struct pciserial_board *board, 1685 struct uart_8250_port *port, int idx) 1686 { 1687 port->port.quirks |= UPQ_NO_TXEN_TEST; 1688 dev_dbg(&priv->dev->dev, 1689 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1690 priv->dev->vendor, priv->dev->device, 1691 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1692 1693 return pci_default_setup(priv, board, port, idx); 1694 } 1695 1696 static void kt_handle_break(struct uart_port *p) 1697 { 1698 struct uart_8250_port *up = up_to_u8250p(p); 1699 /* 1700 * On receipt of a BI, serial device in Intel ME (Intel 1701 * management engine) needs to have its fifos cleared for sane 1702 * SOL (Serial Over Lan) output. 1703 */ 1704 serial8250_clear_and_reinit_fifos(up); 1705 } 1706 1707 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1708 { 1709 struct uart_8250_port *up = up_to_u8250p(p); 1710 unsigned int val; 1711 1712 /* 1713 * When the Intel ME (management engine) gets reset its serial 1714 * port registers could return 0 momentarily. Functions like 1715 * serial8250_console_write, read and save the IER, perform 1716 * some operation and then restore it. In order to avoid 1717 * setting IER register inadvertently to 0, if the value read 1718 * is 0, double check with ier value in uart_8250_port and use 1719 * that instead. up->ier should be the same value as what is 1720 * currently configured. 1721 */ 1722 val = inb(p->iobase + offset); 1723 if (offset == UART_IER) { 1724 if (val == 0) 1725 val = up->ier; 1726 } 1727 return val; 1728 } 1729 1730 static int kt_serial_setup(struct serial_private *priv, 1731 const struct pciserial_board *board, 1732 struct uart_8250_port *port, int idx) 1733 { 1734 port->port.flags |= UPF_BUG_THRE; 1735 port->port.serial_in = kt_serial_in; 1736 port->port.handle_break = kt_handle_break; 1737 return skip_tx_en_setup(priv, board, port, idx); 1738 } 1739 1740 static int pci_eg20t_init(struct pci_dev *dev) 1741 { 1742 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1743 return -ENODEV; 1744 #else 1745 return 0; 1746 #endif 1747 } 1748 1749 static int 1750 pci_wch_ch353_setup(struct serial_private *priv, 1751 const struct pciserial_board *board, 1752 struct uart_8250_port *port, int idx) 1753 { 1754 port->port.flags |= UPF_FIXED_TYPE; 1755 port->port.type = PORT_16550A; 1756 return pci_default_setup(priv, board, port, idx); 1757 } 1758 1759 static int 1760 pci_wch_ch355_setup(struct serial_private *priv, 1761 const struct pciserial_board *board, 1762 struct uart_8250_port *port, int idx) 1763 { 1764 port->port.flags |= UPF_FIXED_TYPE; 1765 port->port.type = PORT_16550A; 1766 return pci_default_setup(priv, board, port, idx); 1767 } 1768 1769 static int 1770 pci_wch_ch38x_setup(struct serial_private *priv, 1771 const struct pciserial_board *board, 1772 struct uart_8250_port *port, int idx) 1773 { 1774 port->port.flags |= UPF_FIXED_TYPE; 1775 port->port.type = PORT_16850; 1776 return pci_default_setup(priv, board, port, idx); 1777 } 1778 1779 static int 1780 pci_sunix_setup(struct serial_private *priv, 1781 const struct pciserial_board *board, 1782 struct uart_8250_port *port, int idx) 1783 { 1784 int bar; 1785 int offset; 1786 1787 port->port.flags |= UPF_FIXED_TYPE; 1788 port->port.type = PORT_SUNIX; 1789 1790 if (idx < 4) { 1791 bar = 0; 1792 offset = idx * board->uart_offset; 1793 } else { 1794 bar = 1; 1795 idx -= 4; 1796 idx = div_s64_rem(idx, 4, &offset); 1797 offset = idx * 64 + offset * board->uart_offset; 1798 } 1799 1800 return setup_port(priv, port, bar, offset, 0); 1801 } 1802 1803 static int 1804 pci_moxa_setup(struct serial_private *priv, 1805 const struct pciserial_board *board, 1806 struct uart_8250_port *port, int idx) 1807 { 1808 unsigned int bar = FL_GET_BASE(board->flags); 1809 int offset; 1810 1811 if (board->num_ports == 4 && idx == 3) 1812 offset = 7 * board->uart_offset; 1813 else 1814 offset = idx * board->uart_offset; 1815 1816 return setup_port(priv, port, bar, offset, 0); 1817 } 1818 1819 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1820 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1821 #define PCI_DEVICE_ID_OCTPRO 0x0001 1822 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1823 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1824 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1825 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1826 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1827 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1828 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1829 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1830 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1831 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1832 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1833 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1834 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1835 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1836 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1837 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1838 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1839 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1840 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1841 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1842 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1843 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1844 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1845 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1846 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1847 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1848 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1849 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1850 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1851 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1852 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1853 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1854 #define PCI_VENDOR_ID_WCH 0x4348 1855 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1856 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1857 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1858 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1859 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1860 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 1861 #define PCI_VENDOR_ID_AGESTAR 0x5372 1862 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1863 #define PCI_VENDOR_ID_ASIX 0x9710 1864 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1865 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1866 1867 #define PCIE_VENDOR_ID_WCH 0x1c00 1868 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1869 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 1870 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 1871 1872 #define PCI_VENDOR_ID_PERICOM 0x12D8 1873 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951 1874 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952 1875 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954 1876 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958 1877 1878 #define PCI_VENDOR_ID_ACCESIO 0x494f 1879 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051 1880 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053 1881 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C 1882 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E 1883 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091 1884 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093 1885 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099 1886 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B 1887 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1 1888 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3 1889 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA 1890 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC 1891 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108 1892 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110 1893 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111 1894 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118 1895 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119 1896 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152 1897 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A 1898 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190 1899 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191 1900 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198 1901 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199 1902 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0 1903 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A 1904 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B 1905 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A 1906 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B 1907 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098 1908 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9 1909 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9 1910 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9 1911 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8 1912 1913 1914 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 1915 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 1916 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 1917 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 1918 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 1919 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 1920 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 1921 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 1922 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 1923 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 1924 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 1925 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 1926 1927 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1928 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1929 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 1930 1931 /* 1932 * Master list of serial port init/setup/exit quirks. 1933 * This does not describe the general nature of the port. 1934 * (ie, baud base, number and location of ports, etc) 1935 * 1936 * This list is ordered alphabetically by vendor then device. 1937 * Specific entries must come before more generic entries. 1938 */ 1939 static struct pci_serial_quirk pci_serial_quirks[] __refdata = { 1940 /* 1941 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1942 */ 1943 { 1944 .vendor = PCI_VENDOR_ID_AMCC, 1945 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 1946 .subvendor = PCI_ANY_ID, 1947 .subdevice = PCI_ANY_ID, 1948 .setup = addidata_apci7800_setup, 1949 }, 1950 /* 1951 * AFAVLAB cards - these may be called via parport_serial 1952 * It is not clear whether this applies to all products. 1953 */ 1954 { 1955 .vendor = PCI_VENDOR_ID_AFAVLAB, 1956 .device = PCI_ANY_ID, 1957 .subvendor = PCI_ANY_ID, 1958 .subdevice = PCI_ANY_ID, 1959 .setup = afavlab_setup, 1960 }, 1961 /* 1962 * HP Diva 1963 */ 1964 { 1965 .vendor = PCI_VENDOR_ID_HP, 1966 .device = PCI_DEVICE_ID_HP_DIVA, 1967 .subvendor = PCI_ANY_ID, 1968 .subdevice = PCI_ANY_ID, 1969 .init = pci_hp_diva_init, 1970 .setup = pci_hp_diva_setup, 1971 }, 1972 /* 1973 * Intel 1974 */ 1975 { 1976 .vendor = PCI_VENDOR_ID_INTEL, 1977 .device = PCI_DEVICE_ID_INTEL_80960_RP, 1978 .subvendor = 0xe4bf, 1979 .subdevice = PCI_ANY_ID, 1980 .init = pci_inteli960ni_init, 1981 .setup = pci_default_setup, 1982 }, 1983 { 1984 .vendor = PCI_VENDOR_ID_INTEL, 1985 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 1986 .subvendor = PCI_ANY_ID, 1987 .subdevice = PCI_ANY_ID, 1988 .setup = skip_tx_en_setup, 1989 }, 1990 { 1991 .vendor = PCI_VENDOR_ID_INTEL, 1992 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 1993 .subvendor = PCI_ANY_ID, 1994 .subdevice = PCI_ANY_ID, 1995 .setup = skip_tx_en_setup, 1996 }, 1997 { 1998 .vendor = PCI_VENDOR_ID_INTEL, 1999 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 2000 .subvendor = PCI_ANY_ID, 2001 .subdevice = PCI_ANY_ID, 2002 .setup = skip_tx_en_setup, 2003 }, 2004 { 2005 .vendor = PCI_VENDOR_ID_INTEL, 2006 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 2007 .subvendor = PCI_ANY_ID, 2008 .subdevice = PCI_ANY_ID, 2009 .setup = ce4100_serial_setup, 2010 }, 2011 { 2012 .vendor = PCI_VENDOR_ID_INTEL, 2013 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 2014 .subvendor = PCI_ANY_ID, 2015 .subdevice = PCI_ANY_ID, 2016 .setup = kt_serial_setup, 2017 }, 2018 /* 2019 * ITE 2020 */ 2021 { 2022 .vendor = PCI_VENDOR_ID_ITE, 2023 .device = PCI_DEVICE_ID_ITE_8872, 2024 .subvendor = PCI_ANY_ID, 2025 .subdevice = PCI_ANY_ID, 2026 .init = pci_ite887x_init, 2027 .setup = pci_default_setup, 2028 .exit = pci_ite887x_exit, 2029 }, 2030 /* 2031 * National Instruments 2032 */ 2033 { 2034 .vendor = PCI_VENDOR_ID_NI, 2035 .device = PCI_DEVICE_ID_NI_PCI23216, 2036 .subvendor = PCI_ANY_ID, 2037 .subdevice = PCI_ANY_ID, 2038 .init = pci_ni8420_init, 2039 .setup = pci_default_setup, 2040 .exit = pci_ni8420_exit, 2041 }, 2042 { 2043 .vendor = PCI_VENDOR_ID_NI, 2044 .device = PCI_DEVICE_ID_NI_PCI2328, 2045 .subvendor = PCI_ANY_ID, 2046 .subdevice = PCI_ANY_ID, 2047 .init = pci_ni8420_init, 2048 .setup = pci_default_setup, 2049 .exit = pci_ni8420_exit, 2050 }, 2051 { 2052 .vendor = PCI_VENDOR_ID_NI, 2053 .device = PCI_DEVICE_ID_NI_PCI2324, 2054 .subvendor = PCI_ANY_ID, 2055 .subdevice = PCI_ANY_ID, 2056 .init = pci_ni8420_init, 2057 .setup = pci_default_setup, 2058 .exit = pci_ni8420_exit, 2059 }, 2060 { 2061 .vendor = PCI_VENDOR_ID_NI, 2062 .device = PCI_DEVICE_ID_NI_PCI2322, 2063 .subvendor = PCI_ANY_ID, 2064 .subdevice = PCI_ANY_ID, 2065 .init = pci_ni8420_init, 2066 .setup = pci_default_setup, 2067 .exit = pci_ni8420_exit, 2068 }, 2069 { 2070 .vendor = PCI_VENDOR_ID_NI, 2071 .device = PCI_DEVICE_ID_NI_PCI2324I, 2072 .subvendor = PCI_ANY_ID, 2073 .subdevice = PCI_ANY_ID, 2074 .init = pci_ni8420_init, 2075 .setup = pci_default_setup, 2076 .exit = pci_ni8420_exit, 2077 }, 2078 { 2079 .vendor = PCI_VENDOR_ID_NI, 2080 .device = PCI_DEVICE_ID_NI_PCI2322I, 2081 .subvendor = PCI_ANY_ID, 2082 .subdevice = PCI_ANY_ID, 2083 .init = pci_ni8420_init, 2084 .setup = pci_default_setup, 2085 .exit = pci_ni8420_exit, 2086 }, 2087 { 2088 .vendor = PCI_VENDOR_ID_NI, 2089 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2090 .subvendor = PCI_ANY_ID, 2091 .subdevice = PCI_ANY_ID, 2092 .init = pci_ni8420_init, 2093 .setup = pci_default_setup, 2094 .exit = pci_ni8420_exit, 2095 }, 2096 { 2097 .vendor = PCI_VENDOR_ID_NI, 2098 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2099 .subvendor = PCI_ANY_ID, 2100 .subdevice = PCI_ANY_ID, 2101 .init = pci_ni8420_init, 2102 .setup = pci_default_setup, 2103 .exit = pci_ni8420_exit, 2104 }, 2105 { 2106 .vendor = PCI_VENDOR_ID_NI, 2107 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2108 .subvendor = PCI_ANY_ID, 2109 .subdevice = PCI_ANY_ID, 2110 .init = pci_ni8420_init, 2111 .setup = pci_default_setup, 2112 .exit = pci_ni8420_exit, 2113 }, 2114 { 2115 .vendor = PCI_VENDOR_ID_NI, 2116 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2117 .subvendor = PCI_ANY_ID, 2118 .subdevice = PCI_ANY_ID, 2119 .init = pci_ni8420_init, 2120 .setup = pci_default_setup, 2121 .exit = pci_ni8420_exit, 2122 }, 2123 { 2124 .vendor = PCI_VENDOR_ID_NI, 2125 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2126 .subvendor = PCI_ANY_ID, 2127 .subdevice = PCI_ANY_ID, 2128 .init = pci_ni8420_init, 2129 .setup = pci_default_setup, 2130 .exit = pci_ni8420_exit, 2131 }, 2132 { 2133 .vendor = PCI_VENDOR_ID_NI, 2134 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2135 .subvendor = PCI_ANY_ID, 2136 .subdevice = PCI_ANY_ID, 2137 .init = pci_ni8420_init, 2138 .setup = pci_default_setup, 2139 .exit = pci_ni8420_exit, 2140 }, 2141 { 2142 .vendor = PCI_VENDOR_ID_NI, 2143 .device = PCI_ANY_ID, 2144 .subvendor = PCI_ANY_ID, 2145 .subdevice = PCI_ANY_ID, 2146 .init = pci_ni8430_init, 2147 .setup = pci_ni8430_setup, 2148 .exit = pci_ni8430_exit, 2149 }, 2150 /* Quatech */ 2151 { 2152 .vendor = PCI_VENDOR_ID_QUATECH, 2153 .device = PCI_ANY_ID, 2154 .subvendor = PCI_ANY_ID, 2155 .subdevice = PCI_ANY_ID, 2156 .init = pci_quatech_init, 2157 .setup = pci_quatech_setup, 2158 .exit = pci_quatech_exit, 2159 }, 2160 /* 2161 * Panacom 2162 */ 2163 { 2164 .vendor = PCI_VENDOR_ID_PANACOM, 2165 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2166 .subvendor = PCI_ANY_ID, 2167 .subdevice = PCI_ANY_ID, 2168 .init = pci_plx9050_init, 2169 .setup = pci_default_setup, 2170 .exit = pci_plx9050_exit, 2171 }, 2172 { 2173 .vendor = PCI_VENDOR_ID_PANACOM, 2174 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2175 .subvendor = PCI_ANY_ID, 2176 .subdevice = PCI_ANY_ID, 2177 .init = pci_plx9050_init, 2178 .setup = pci_default_setup, 2179 .exit = pci_plx9050_exit, 2180 }, 2181 /* 2182 * Pericom (Only 7954 - It have a offset jump for port 4) 2183 */ 2184 { 2185 .vendor = PCI_VENDOR_ID_PERICOM, 2186 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954, 2187 .subvendor = PCI_ANY_ID, 2188 .subdevice = PCI_ANY_ID, 2189 .setup = pci_pericom_setup_four_at_eight, 2190 }, 2191 /* 2192 * PLX 2193 */ 2194 { 2195 .vendor = PCI_VENDOR_ID_PLX, 2196 .device = PCI_DEVICE_ID_PLX_9050, 2197 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2198 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2199 .init = pci_plx9050_init, 2200 .setup = pci_default_setup, 2201 .exit = pci_plx9050_exit, 2202 }, 2203 { 2204 .vendor = PCI_VENDOR_ID_PLX, 2205 .device = PCI_DEVICE_ID_PLX_9050, 2206 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2207 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2208 .init = pci_plx9050_init, 2209 .setup = pci_default_setup, 2210 .exit = pci_plx9050_exit, 2211 }, 2212 { 2213 .vendor = PCI_VENDOR_ID_PLX, 2214 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2215 .subvendor = PCI_VENDOR_ID_PLX, 2216 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2217 .init = pci_plx9050_init, 2218 .setup = pci_default_setup, 2219 .exit = pci_plx9050_exit, 2220 }, 2221 { 2222 .vendor = PCI_VENDOR_ID_ACCESIO, 2223 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB, 2224 .subvendor = PCI_ANY_ID, 2225 .subdevice = PCI_ANY_ID, 2226 .setup = pci_pericom_setup_four_at_eight, 2227 }, 2228 { 2229 .vendor = PCI_VENDOR_ID_ACCESIO, 2230 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S, 2231 .subvendor = PCI_ANY_ID, 2232 .subdevice = PCI_ANY_ID, 2233 .setup = pci_pericom_setup_four_at_eight, 2234 }, 2235 { 2236 .vendor = PCI_VENDOR_ID_ACCESIO, 2237 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB, 2238 .subvendor = PCI_ANY_ID, 2239 .subdevice = PCI_ANY_ID, 2240 .setup = pci_pericom_setup_four_at_eight, 2241 }, 2242 { 2243 .vendor = PCI_VENDOR_ID_ACCESIO, 2244 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4, 2245 .subvendor = PCI_ANY_ID, 2246 .subdevice = PCI_ANY_ID, 2247 .setup = pci_pericom_setup_four_at_eight, 2248 }, 2249 { 2250 .vendor = PCI_VENDOR_ID_ACCESIO, 2251 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB, 2252 .subvendor = PCI_ANY_ID, 2253 .subdevice = PCI_ANY_ID, 2254 .setup = pci_pericom_setup_four_at_eight, 2255 }, 2256 { 2257 .vendor = PCI_VENDOR_ID_ACCESIO, 2258 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM, 2259 .subvendor = PCI_ANY_ID, 2260 .subdevice = PCI_ANY_ID, 2261 .setup = pci_pericom_setup_four_at_eight, 2262 }, 2263 { 2264 .vendor = PCI_VENDOR_ID_ACCESIO, 2265 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4, 2266 .subvendor = PCI_ANY_ID, 2267 .subdevice = PCI_ANY_ID, 2268 .setup = pci_pericom_setup_four_at_eight, 2269 }, 2270 { 2271 .vendor = PCI_VENDOR_ID_ACCESIO, 2272 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4, 2273 .subvendor = PCI_ANY_ID, 2274 .subdevice = PCI_ANY_ID, 2275 .setup = pci_pericom_setup_four_at_eight, 2276 }, 2277 { 2278 .vendor = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S, 2279 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4, 2280 .subvendor = PCI_ANY_ID, 2281 .subdevice = PCI_ANY_ID, 2282 .setup = pci_pericom_setup_four_at_eight, 2283 }, 2284 { 2285 .vendor = PCI_VENDOR_ID_ACCESIO, 2286 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4, 2287 .subvendor = PCI_ANY_ID, 2288 .subdevice = PCI_ANY_ID, 2289 .setup = pci_pericom_setup_four_at_eight, 2290 }, 2291 { 2292 .vendor = PCI_VENDOR_ID_ACCESIO, 2293 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4, 2294 .subvendor = PCI_ANY_ID, 2295 .subdevice = PCI_ANY_ID, 2296 .setup = pci_pericom_setup_four_at_eight, 2297 }, 2298 { 2299 .vendor = PCI_VENDOR_ID_ACCESIO, 2300 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4, 2301 .subvendor = PCI_ANY_ID, 2302 .subdevice = PCI_ANY_ID, 2303 .setup = pci_pericom_setup_four_at_eight, 2304 }, 2305 { 2306 .vendor = PCI_VENDOR_ID_ACCESIO, 2307 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4, 2308 .subvendor = PCI_ANY_ID, 2309 .subdevice = PCI_ANY_ID, 2310 .setup = pci_pericom_setup_four_at_eight, 2311 }, 2312 { 2313 .vendor = PCI_VENDOR_ID_ACCESIO, 2314 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM, 2315 .subvendor = PCI_ANY_ID, 2316 .subdevice = PCI_ANY_ID, 2317 .setup = pci_pericom_setup_four_at_eight, 2318 }, 2319 { 2320 .vendor = PCI_VENDOR_ID_ACCESIO, 2321 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM, 2322 .subvendor = PCI_ANY_ID, 2323 .subdevice = PCI_ANY_ID, 2324 .setup = pci_pericom_setup_four_at_eight, 2325 }, 2326 { 2327 .vendor = PCI_VENDOR_ID_ACCESIO, 2328 .device = PCI_ANY_ID, 2329 .subvendor = PCI_ANY_ID, 2330 .subdevice = PCI_ANY_ID, 2331 .setup = pci_pericom_setup, 2332 }, /* 2333 * SBS Technologies, Inc., PMC-OCTALPRO 232 2334 */ 2335 { 2336 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2337 .device = PCI_DEVICE_ID_OCTPRO, 2338 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2339 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2340 .init = sbs_init, 2341 .setup = sbs_setup, 2342 .exit = sbs_exit, 2343 }, 2344 /* 2345 * SBS Technologies, Inc., PMC-OCTALPRO 422 2346 */ 2347 { 2348 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2349 .device = PCI_DEVICE_ID_OCTPRO, 2350 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2351 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2352 .init = sbs_init, 2353 .setup = sbs_setup, 2354 .exit = sbs_exit, 2355 }, 2356 /* 2357 * SBS Technologies, Inc., P-Octal 232 2358 */ 2359 { 2360 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2361 .device = PCI_DEVICE_ID_OCTPRO, 2362 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2363 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2364 .init = sbs_init, 2365 .setup = sbs_setup, 2366 .exit = sbs_exit, 2367 }, 2368 /* 2369 * SBS Technologies, Inc., P-Octal 422 2370 */ 2371 { 2372 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2373 .device = PCI_DEVICE_ID_OCTPRO, 2374 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2375 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2376 .init = sbs_init, 2377 .setup = sbs_setup, 2378 .exit = sbs_exit, 2379 }, 2380 /* 2381 * SIIG cards - these may be called via parport_serial 2382 */ 2383 { 2384 .vendor = PCI_VENDOR_ID_SIIG, 2385 .device = PCI_ANY_ID, 2386 .subvendor = PCI_ANY_ID, 2387 .subdevice = PCI_ANY_ID, 2388 .init = pci_siig_init, 2389 .setup = pci_siig_setup, 2390 }, 2391 /* 2392 * Titan cards 2393 */ 2394 { 2395 .vendor = PCI_VENDOR_ID_TITAN, 2396 .device = PCI_DEVICE_ID_TITAN_400L, 2397 .subvendor = PCI_ANY_ID, 2398 .subdevice = PCI_ANY_ID, 2399 .setup = titan_400l_800l_setup, 2400 }, 2401 { 2402 .vendor = PCI_VENDOR_ID_TITAN, 2403 .device = PCI_DEVICE_ID_TITAN_800L, 2404 .subvendor = PCI_ANY_ID, 2405 .subdevice = PCI_ANY_ID, 2406 .setup = titan_400l_800l_setup, 2407 }, 2408 /* 2409 * Timedia cards 2410 */ 2411 { 2412 .vendor = PCI_VENDOR_ID_TIMEDIA, 2413 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2414 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2415 .subdevice = PCI_ANY_ID, 2416 .probe = pci_timedia_probe, 2417 .init = pci_timedia_init, 2418 .setup = pci_timedia_setup, 2419 }, 2420 { 2421 .vendor = PCI_VENDOR_ID_TIMEDIA, 2422 .device = PCI_ANY_ID, 2423 .subvendor = PCI_ANY_ID, 2424 .subdevice = PCI_ANY_ID, 2425 .setup = pci_timedia_setup, 2426 }, 2427 /* 2428 * Sunix PCI serial boards 2429 */ 2430 { 2431 .vendor = PCI_VENDOR_ID_SUNIX, 2432 .device = PCI_DEVICE_ID_SUNIX_1999, 2433 .subvendor = PCI_VENDOR_ID_SUNIX, 2434 .subdevice = PCI_ANY_ID, 2435 .setup = pci_sunix_setup, 2436 }, 2437 /* 2438 * Xircom cards 2439 */ 2440 { 2441 .vendor = PCI_VENDOR_ID_XIRCOM, 2442 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2443 .subvendor = PCI_ANY_ID, 2444 .subdevice = PCI_ANY_ID, 2445 .init = pci_xircom_init, 2446 .setup = pci_default_setup, 2447 }, 2448 /* 2449 * Netmos cards - these may be called via parport_serial 2450 */ 2451 { 2452 .vendor = PCI_VENDOR_ID_NETMOS, 2453 .device = PCI_ANY_ID, 2454 .subvendor = PCI_ANY_ID, 2455 .subdevice = PCI_ANY_ID, 2456 .init = pci_netmos_init, 2457 .setup = pci_netmos_9900_setup, 2458 }, 2459 /* 2460 * EndRun Technologies 2461 */ 2462 { 2463 .vendor = PCI_VENDOR_ID_ENDRUN, 2464 .device = PCI_ANY_ID, 2465 .subvendor = PCI_ANY_ID, 2466 .subdevice = PCI_ANY_ID, 2467 .init = pci_endrun_init, 2468 .setup = pci_default_setup, 2469 }, 2470 /* 2471 * For Oxford Semiconductor Tornado based devices 2472 */ 2473 { 2474 .vendor = PCI_VENDOR_ID_OXSEMI, 2475 .device = PCI_ANY_ID, 2476 .subvendor = PCI_ANY_ID, 2477 .subdevice = PCI_ANY_ID, 2478 .init = pci_oxsemi_tornado_init, 2479 .setup = pci_default_setup, 2480 }, 2481 { 2482 .vendor = PCI_VENDOR_ID_MAINPINE, 2483 .device = PCI_ANY_ID, 2484 .subvendor = PCI_ANY_ID, 2485 .subdevice = PCI_ANY_ID, 2486 .init = pci_oxsemi_tornado_init, 2487 .setup = pci_default_setup, 2488 }, 2489 { 2490 .vendor = PCI_VENDOR_ID_DIGI, 2491 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2492 .subvendor = PCI_SUBVENDOR_ID_IBM, 2493 .subdevice = PCI_ANY_ID, 2494 .init = pci_oxsemi_tornado_init, 2495 .setup = pci_default_setup, 2496 }, 2497 { 2498 .vendor = PCI_VENDOR_ID_INTEL, 2499 .device = 0x8811, 2500 .subvendor = PCI_ANY_ID, 2501 .subdevice = PCI_ANY_ID, 2502 .init = pci_eg20t_init, 2503 .setup = pci_default_setup, 2504 }, 2505 { 2506 .vendor = PCI_VENDOR_ID_INTEL, 2507 .device = 0x8812, 2508 .subvendor = PCI_ANY_ID, 2509 .subdevice = PCI_ANY_ID, 2510 .init = pci_eg20t_init, 2511 .setup = pci_default_setup, 2512 }, 2513 { 2514 .vendor = PCI_VENDOR_ID_INTEL, 2515 .device = 0x8813, 2516 .subvendor = PCI_ANY_ID, 2517 .subdevice = PCI_ANY_ID, 2518 .init = pci_eg20t_init, 2519 .setup = pci_default_setup, 2520 }, 2521 { 2522 .vendor = PCI_VENDOR_ID_INTEL, 2523 .device = 0x8814, 2524 .subvendor = PCI_ANY_ID, 2525 .subdevice = PCI_ANY_ID, 2526 .init = pci_eg20t_init, 2527 .setup = pci_default_setup, 2528 }, 2529 { 2530 .vendor = 0x10DB, 2531 .device = 0x8027, 2532 .subvendor = PCI_ANY_ID, 2533 .subdevice = PCI_ANY_ID, 2534 .init = pci_eg20t_init, 2535 .setup = pci_default_setup, 2536 }, 2537 { 2538 .vendor = 0x10DB, 2539 .device = 0x8028, 2540 .subvendor = PCI_ANY_ID, 2541 .subdevice = PCI_ANY_ID, 2542 .init = pci_eg20t_init, 2543 .setup = pci_default_setup, 2544 }, 2545 { 2546 .vendor = 0x10DB, 2547 .device = 0x8029, 2548 .subvendor = PCI_ANY_ID, 2549 .subdevice = PCI_ANY_ID, 2550 .init = pci_eg20t_init, 2551 .setup = pci_default_setup, 2552 }, 2553 { 2554 .vendor = 0x10DB, 2555 .device = 0x800C, 2556 .subvendor = PCI_ANY_ID, 2557 .subdevice = PCI_ANY_ID, 2558 .init = pci_eg20t_init, 2559 .setup = pci_default_setup, 2560 }, 2561 { 2562 .vendor = 0x10DB, 2563 .device = 0x800D, 2564 .subvendor = PCI_ANY_ID, 2565 .subdevice = PCI_ANY_ID, 2566 .init = pci_eg20t_init, 2567 .setup = pci_default_setup, 2568 }, 2569 /* 2570 * Cronyx Omega PCI (PLX-chip based) 2571 */ 2572 { 2573 .vendor = PCI_VENDOR_ID_PLX, 2574 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2575 .subvendor = PCI_ANY_ID, 2576 .subdevice = PCI_ANY_ID, 2577 .setup = pci_omegapci_setup, 2578 }, 2579 /* WCH CH353 1S1P card (16550 clone) */ 2580 { 2581 .vendor = PCI_VENDOR_ID_WCH, 2582 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2583 .subvendor = PCI_ANY_ID, 2584 .subdevice = PCI_ANY_ID, 2585 .setup = pci_wch_ch353_setup, 2586 }, 2587 /* WCH CH353 2S1P card (16550 clone) */ 2588 { 2589 .vendor = PCI_VENDOR_ID_WCH, 2590 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2591 .subvendor = PCI_ANY_ID, 2592 .subdevice = PCI_ANY_ID, 2593 .setup = pci_wch_ch353_setup, 2594 }, 2595 /* WCH CH353 4S card (16550 clone) */ 2596 { 2597 .vendor = PCI_VENDOR_ID_WCH, 2598 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2599 .subvendor = PCI_ANY_ID, 2600 .subdevice = PCI_ANY_ID, 2601 .setup = pci_wch_ch353_setup, 2602 }, 2603 /* WCH CH353 2S1PF card (16550 clone) */ 2604 { 2605 .vendor = PCI_VENDOR_ID_WCH, 2606 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2607 .subvendor = PCI_ANY_ID, 2608 .subdevice = PCI_ANY_ID, 2609 .setup = pci_wch_ch353_setup, 2610 }, 2611 /* WCH CH352 2S card (16550 clone) */ 2612 { 2613 .vendor = PCI_VENDOR_ID_WCH, 2614 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2615 .subvendor = PCI_ANY_ID, 2616 .subdevice = PCI_ANY_ID, 2617 .setup = pci_wch_ch353_setup, 2618 }, 2619 /* WCH CH355 4S card (16550 clone) */ 2620 { 2621 .vendor = PCI_VENDOR_ID_WCH, 2622 .device = PCI_DEVICE_ID_WCH_CH355_4S, 2623 .subvendor = PCI_ANY_ID, 2624 .subdevice = PCI_ANY_ID, 2625 .setup = pci_wch_ch355_setup, 2626 }, 2627 /* WCH CH382 2S card (16850 clone) */ 2628 { 2629 .vendor = PCIE_VENDOR_ID_WCH, 2630 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2631 .subvendor = PCI_ANY_ID, 2632 .subdevice = PCI_ANY_ID, 2633 .setup = pci_wch_ch38x_setup, 2634 }, 2635 /* WCH CH382 2S1P card (16850 clone) */ 2636 { 2637 .vendor = PCIE_VENDOR_ID_WCH, 2638 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2639 .subvendor = PCI_ANY_ID, 2640 .subdevice = PCI_ANY_ID, 2641 .setup = pci_wch_ch38x_setup, 2642 }, 2643 /* WCH CH384 4S card (16850 clone) */ 2644 { 2645 .vendor = PCIE_VENDOR_ID_WCH, 2646 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2647 .subvendor = PCI_ANY_ID, 2648 .subdevice = PCI_ANY_ID, 2649 .setup = pci_wch_ch38x_setup, 2650 }, 2651 /* 2652 * ASIX devices with FIFO bug 2653 */ 2654 { 2655 .vendor = PCI_VENDOR_ID_ASIX, 2656 .device = PCI_ANY_ID, 2657 .subvendor = PCI_ANY_ID, 2658 .subdevice = PCI_ANY_ID, 2659 .setup = pci_asix_setup, 2660 }, 2661 /* 2662 * Broadcom TruManage (NetXtreme) 2663 */ 2664 { 2665 .vendor = PCI_VENDOR_ID_BROADCOM, 2666 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2667 .subvendor = PCI_ANY_ID, 2668 .subdevice = PCI_ANY_ID, 2669 .setup = pci_brcm_trumanage_setup, 2670 }, 2671 { 2672 .vendor = 0x1c29, 2673 .device = 0x1104, 2674 .subvendor = PCI_ANY_ID, 2675 .subdevice = PCI_ANY_ID, 2676 .setup = pci_fintek_setup, 2677 .init = pci_fintek_init, 2678 }, 2679 { 2680 .vendor = 0x1c29, 2681 .device = 0x1108, 2682 .subvendor = PCI_ANY_ID, 2683 .subdevice = PCI_ANY_ID, 2684 .setup = pci_fintek_setup, 2685 .init = pci_fintek_init, 2686 }, 2687 { 2688 .vendor = 0x1c29, 2689 .device = 0x1112, 2690 .subvendor = PCI_ANY_ID, 2691 .subdevice = PCI_ANY_ID, 2692 .setup = pci_fintek_setup, 2693 .init = pci_fintek_init, 2694 }, 2695 /* 2696 * MOXA 2697 */ 2698 { 2699 .vendor = PCI_VENDOR_ID_MOXA, 2700 .device = PCI_ANY_ID, 2701 .subvendor = PCI_ANY_ID, 2702 .subdevice = PCI_ANY_ID, 2703 .setup = pci_moxa_setup, 2704 }, 2705 { 2706 .vendor = 0x1c29, 2707 .device = 0x1204, 2708 .subvendor = PCI_ANY_ID, 2709 .subdevice = PCI_ANY_ID, 2710 .setup = pci_fintek_f815xxa_setup, 2711 .init = pci_fintek_f815xxa_init, 2712 }, 2713 { 2714 .vendor = 0x1c29, 2715 .device = 0x1208, 2716 .subvendor = PCI_ANY_ID, 2717 .subdevice = PCI_ANY_ID, 2718 .setup = pci_fintek_f815xxa_setup, 2719 .init = pci_fintek_f815xxa_init, 2720 }, 2721 { 2722 .vendor = 0x1c29, 2723 .device = 0x1212, 2724 .subvendor = PCI_ANY_ID, 2725 .subdevice = PCI_ANY_ID, 2726 .setup = pci_fintek_f815xxa_setup, 2727 .init = pci_fintek_f815xxa_init, 2728 }, 2729 2730 /* 2731 * Default "match everything" terminator entry 2732 */ 2733 { 2734 .vendor = PCI_ANY_ID, 2735 .device = PCI_ANY_ID, 2736 .subvendor = PCI_ANY_ID, 2737 .subdevice = PCI_ANY_ID, 2738 .setup = pci_default_setup, 2739 } 2740 }; 2741 2742 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2743 { 2744 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2745 } 2746 2747 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2748 { 2749 struct pci_serial_quirk *quirk; 2750 2751 for (quirk = pci_serial_quirks; ; quirk++) 2752 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2753 quirk_id_matches(quirk->device, dev->device) && 2754 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2755 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2756 break; 2757 return quirk; 2758 } 2759 2760 static inline int get_pci_irq(struct pci_dev *dev, 2761 const struct pciserial_board *board) 2762 { 2763 if (board->flags & FL_NOIRQ) 2764 return 0; 2765 else 2766 return dev->irq; 2767 } 2768 2769 /* 2770 * This is the configuration table for all of the PCI serial boards 2771 * which we support. It is directly indexed by the pci_board_num_t enum 2772 * value, which is encoded in the pci_device_id PCI probe table's 2773 * driver_data member. 2774 * 2775 * The makeup of these names are: 2776 * pbn_bn{_bt}_n_baud{_offsetinhex} 2777 * 2778 * bn = PCI BAR number 2779 * bt = Index using PCI BARs 2780 * n = number of serial ports 2781 * baud = baud rate 2782 * offsetinhex = offset for each sequential port (in hex) 2783 * 2784 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2785 * 2786 * Please note: in theory if n = 1, _bt infix should make no difference. 2787 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2788 */ 2789 enum pci_board_num_t { 2790 pbn_default = 0, 2791 2792 pbn_b0_1_115200, 2793 pbn_b0_2_115200, 2794 pbn_b0_4_115200, 2795 pbn_b0_5_115200, 2796 pbn_b0_8_115200, 2797 2798 pbn_b0_1_921600, 2799 pbn_b0_2_921600, 2800 pbn_b0_4_921600, 2801 2802 pbn_b0_2_1130000, 2803 2804 pbn_b0_4_1152000, 2805 2806 pbn_b0_4_1250000, 2807 2808 pbn_b0_2_1843200, 2809 pbn_b0_4_1843200, 2810 2811 pbn_b0_1_4000000, 2812 2813 pbn_b0_bt_1_115200, 2814 pbn_b0_bt_2_115200, 2815 pbn_b0_bt_4_115200, 2816 pbn_b0_bt_8_115200, 2817 2818 pbn_b0_bt_1_460800, 2819 pbn_b0_bt_2_460800, 2820 pbn_b0_bt_4_460800, 2821 2822 pbn_b0_bt_1_921600, 2823 pbn_b0_bt_2_921600, 2824 pbn_b0_bt_4_921600, 2825 pbn_b0_bt_8_921600, 2826 2827 pbn_b1_1_115200, 2828 pbn_b1_2_115200, 2829 pbn_b1_4_115200, 2830 pbn_b1_8_115200, 2831 pbn_b1_16_115200, 2832 2833 pbn_b1_1_921600, 2834 pbn_b1_2_921600, 2835 pbn_b1_4_921600, 2836 pbn_b1_8_921600, 2837 2838 pbn_b1_2_1250000, 2839 2840 pbn_b1_bt_1_115200, 2841 pbn_b1_bt_2_115200, 2842 pbn_b1_bt_4_115200, 2843 2844 pbn_b1_bt_2_921600, 2845 2846 pbn_b1_1_1382400, 2847 pbn_b1_2_1382400, 2848 pbn_b1_4_1382400, 2849 pbn_b1_8_1382400, 2850 2851 pbn_b2_1_115200, 2852 pbn_b2_2_115200, 2853 pbn_b2_4_115200, 2854 pbn_b2_8_115200, 2855 2856 pbn_b2_1_460800, 2857 pbn_b2_4_460800, 2858 pbn_b2_8_460800, 2859 pbn_b2_16_460800, 2860 2861 pbn_b2_1_921600, 2862 pbn_b2_4_921600, 2863 pbn_b2_8_921600, 2864 2865 pbn_b2_8_1152000, 2866 2867 pbn_b2_bt_1_115200, 2868 pbn_b2_bt_2_115200, 2869 pbn_b2_bt_4_115200, 2870 2871 pbn_b2_bt_2_921600, 2872 pbn_b2_bt_4_921600, 2873 2874 pbn_b3_2_115200, 2875 pbn_b3_4_115200, 2876 pbn_b3_8_115200, 2877 2878 pbn_b4_bt_2_921600, 2879 pbn_b4_bt_4_921600, 2880 pbn_b4_bt_8_921600, 2881 2882 /* 2883 * Board-specific versions. 2884 */ 2885 pbn_panacom, 2886 pbn_panacom2, 2887 pbn_panacom4, 2888 pbn_plx_romulus, 2889 pbn_endrun_2_4000000, 2890 pbn_oxsemi, 2891 pbn_oxsemi_1_4000000, 2892 pbn_oxsemi_2_4000000, 2893 pbn_oxsemi_4_4000000, 2894 pbn_oxsemi_8_4000000, 2895 pbn_intel_i960, 2896 pbn_sgi_ioc3, 2897 pbn_computone_4, 2898 pbn_computone_6, 2899 pbn_computone_8, 2900 pbn_sbsxrsio, 2901 pbn_pasemi_1682M, 2902 pbn_ni8430_2, 2903 pbn_ni8430_4, 2904 pbn_ni8430_8, 2905 pbn_ni8430_16, 2906 pbn_ADDIDATA_PCIe_1_3906250, 2907 pbn_ADDIDATA_PCIe_2_3906250, 2908 pbn_ADDIDATA_PCIe_4_3906250, 2909 pbn_ADDIDATA_PCIe_8_3906250, 2910 pbn_ce4100_1_115200, 2911 pbn_omegapci, 2912 pbn_NETMOS9900_2s_115200, 2913 pbn_brcm_trumanage, 2914 pbn_fintek_4, 2915 pbn_fintek_8, 2916 pbn_fintek_12, 2917 pbn_fintek_F81504A, 2918 pbn_fintek_F81508A, 2919 pbn_fintek_F81512A, 2920 pbn_wch382_2, 2921 pbn_wch384_4, 2922 pbn_pericom_PI7C9X7951, 2923 pbn_pericom_PI7C9X7952, 2924 pbn_pericom_PI7C9X7954, 2925 pbn_pericom_PI7C9X7958, 2926 pbn_sunix_pci_1s, 2927 pbn_sunix_pci_2s, 2928 pbn_sunix_pci_4s, 2929 pbn_sunix_pci_8s, 2930 pbn_sunix_pci_16s, 2931 pbn_moxa8250_2p, 2932 pbn_moxa8250_4p, 2933 pbn_moxa8250_8p, 2934 }; 2935 2936 /* 2937 * uart_offset - the space between channels 2938 * reg_shift - describes how the UART registers are mapped 2939 * to PCI memory by the card. 2940 * For example IER register on SBS, Inc. PMC-OctPro is located at 2941 * offset 0x10 from the UART base, while UART_IER is defined as 1 2942 * in include/linux/serial_reg.h, 2943 * see first lines of serial_in() and serial_out() in 8250.c 2944 */ 2945 2946 static struct pciserial_board pci_boards[] = { 2947 [pbn_default] = { 2948 .flags = FL_BASE0, 2949 .num_ports = 1, 2950 .base_baud = 115200, 2951 .uart_offset = 8, 2952 }, 2953 [pbn_b0_1_115200] = { 2954 .flags = FL_BASE0, 2955 .num_ports = 1, 2956 .base_baud = 115200, 2957 .uart_offset = 8, 2958 }, 2959 [pbn_b0_2_115200] = { 2960 .flags = FL_BASE0, 2961 .num_ports = 2, 2962 .base_baud = 115200, 2963 .uart_offset = 8, 2964 }, 2965 [pbn_b0_4_115200] = { 2966 .flags = FL_BASE0, 2967 .num_ports = 4, 2968 .base_baud = 115200, 2969 .uart_offset = 8, 2970 }, 2971 [pbn_b0_5_115200] = { 2972 .flags = FL_BASE0, 2973 .num_ports = 5, 2974 .base_baud = 115200, 2975 .uart_offset = 8, 2976 }, 2977 [pbn_b0_8_115200] = { 2978 .flags = FL_BASE0, 2979 .num_ports = 8, 2980 .base_baud = 115200, 2981 .uart_offset = 8, 2982 }, 2983 [pbn_b0_1_921600] = { 2984 .flags = FL_BASE0, 2985 .num_ports = 1, 2986 .base_baud = 921600, 2987 .uart_offset = 8, 2988 }, 2989 [pbn_b0_2_921600] = { 2990 .flags = FL_BASE0, 2991 .num_ports = 2, 2992 .base_baud = 921600, 2993 .uart_offset = 8, 2994 }, 2995 [pbn_b0_4_921600] = { 2996 .flags = FL_BASE0, 2997 .num_ports = 4, 2998 .base_baud = 921600, 2999 .uart_offset = 8, 3000 }, 3001 3002 [pbn_b0_2_1130000] = { 3003 .flags = FL_BASE0, 3004 .num_ports = 2, 3005 .base_baud = 1130000, 3006 .uart_offset = 8, 3007 }, 3008 3009 [pbn_b0_4_1152000] = { 3010 .flags = FL_BASE0, 3011 .num_ports = 4, 3012 .base_baud = 1152000, 3013 .uart_offset = 8, 3014 }, 3015 3016 [pbn_b0_4_1250000] = { 3017 .flags = FL_BASE0, 3018 .num_ports = 4, 3019 .base_baud = 1250000, 3020 .uart_offset = 8, 3021 }, 3022 3023 [pbn_b0_2_1843200] = { 3024 .flags = FL_BASE0, 3025 .num_ports = 2, 3026 .base_baud = 1843200, 3027 .uart_offset = 8, 3028 }, 3029 [pbn_b0_4_1843200] = { 3030 .flags = FL_BASE0, 3031 .num_ports = 4, 3032 .base_baud = 1843200, 3033 .uart_offset = 8, 3034 }, 3035 3036 [pbn_b0_1_4000000] = { 3037 .flags = FL_BASE0, 3038 .num_ports = 1, 3039 .base_baud = 4000000, 3040 .uart_offset = 8, 3041 }, 3042 3043 [pbn_b0_bt_1_115200] = { 3044 .flags = FL_BASE0|FL_BASE_BARS, 3045 .num_ports = 1, 3046 .base_baud = 115200, 3047 .uart_offset = 8, 3048 }, 3049 [pbn_b0_bt_2_115200] = { 3050 .flags = FL_BASE0|FL_BASE_BARS, 3051 .num_ports = 2, 3052 .base_baud = 115200, 3053 .uart_offset = 8, 3054 }, 3055 [pbn_b0_bt_4_115200] = { 3056 .flags = FL_BASE0|FL_BASE_BARS, 3057 .num_ports = 4, 3058 .base_baud = 115200, 3059 .uart_offset = 8, 3060 }, 3061 [pbn_b0_bt_8_115200] = { 3062 .flags = FL_BASE0|FL_BASE_BARS, 3063 .num_ports = 8, 3064 .base_baud = 115200, 3065 .uart_offset = 8, 3066 }, 3067 3068 [pbn_b0_bt_1_460800] = { 3069 .flags = FL_BASE0|FL_BASE_BARS, 3070 .num_ports = 1, 3071 .base_baud = 460800, 3072 .uart_offset = 8, 3073 }, 3074 [pbn_b0_bt_2_460800] = { 3075 .flags = FL_BASE0|FL_BASE_BARS, 3076 .num_ports = 2, 3077 .base_baud = 460800, 3078 .uart_offset = 8, 3079 }, 3080 [pbn_b0_bt_4_460800] = { 3081 .flags = FL_BASE0|FL_BASE_BARS, 3082 .num_ports = 4, 3083 .base_baud = 460800, 3084 .uart_offset = 8, 3085 }, 3086 3087 [pbn_b0_bt_1_921600] = { 3088 .flags = FL_BASE0|FL_BASE_BARS, 3089 .num_ports = 1, 3090 .base_baud = 921600, 3091 .uart_offset = 8, 3092 }, 3093 [pbn_b0_bt_2_921600] = { 3094 .flags = FL_BASE0|FL_BASE_BARS, 3095 .num_ports = 2, 3096 .base_baud = 921600, 3097 .uart_offset = 8, 3098 }, 3099 [pbn_b0_bt_4_921600] = { 3100 .flags = FL_BASE0|FL_BASE_BARS, 3101 .num_ports = 4, 3102 .base_baud = 921600, 3103 .uart_offset = 8, 3104 }, 3105 [pbn_b0_bt_8_921600] = { 3106 .flags = FL_BASE0|FL_BASE_BARS, 3107 .num_ports = 8, 3108 .base_baud = 921600, 3109 .uart_offset = 8, 3110 }, 3111 3112 [pbn_b1_1_115200] = { 3113 .flags = FL_BASE1, 3114 .num_ports = 1, 3115 .base_baud = 115200, 3116 .uart_offset = 8, 3117 }, 3118 [pbn_b1_2_115200] = { 3119 .flags = FL_BASE1, 3120 .num_ports = 2, 3121 .base_baud = 115200, 3122 .uart_offset = 8, 3123 }, 3124 [pbn_b1_4_115200] = { 3125 .flags = FL_BASE1, 3126 .num_ports = 4, 3127 .base_baud = 115200, 3128 .uart_offset = 8, 3129 }, 3130 [pbn_b1_8_115200] = { 3131 .flags = FL_BASE1, 3132 .num_ports = 8, 3133 .base_baud = 115200, 3134 .uart_offset = 8, 3135 }, 3136 [pbn_b1_16_115200] = { 3137 .flags = FL_BASE1, 3138 .num_ports = 16, 3139 .base_baud = 115200, 3140 .uart_offset = 8, 3141 }, 3142 3143 [pbn_b1_1_921600] = { 3144 .flags = FL_BASE1, 3145 .num_ports = 1, 3146 .base_baud = 921600, 3147 .uart_offset = 8, 3148 }, 3149 [pbn_b1_2_921600] = { 3150 .flags = FL_BASE1, 3151 .num_ports = 2, 3152 .base_baud = 921600, 3153 .uart_offset = 8, 3154 }, 3155 [pbn_b1_4_921600] = { 3156 .flags = FL_BASE1, 3157 .num_ports = 4, 3158 .base_baud = 921600, 3159 .uart_offset = 8, 3160 }, 3161 [pbn_b1_8_921600] = { 3162 .flags = FL_BASE1, 3163 .num_ports = 8, 3164 .base_baud = 921600, 3165 .uart_offset = 8, 3166 }, 3167 [pbn_b1_2_1250000] = { 3168 .flags = FL_BASE1, 3169 .num_ports = 2, 3170 .base_baud = 1250000, 3171 .uart_offset = 8, 3172 }, 3173 3174 [pbn_b1_bt_1_115200] = { 3175 .flags = FL_BASE1|FL_BASE_BARS, 3176 .num_ports = 1, 3177 .base_baud = 115200, 3178 .uart_offset = 8, 3179 }, 3180 [pbn_b1_bt_2_115200] = { 3181 .flags = FL_BASE1|FL_BASE_BARS, 3182 .num_ports = 2, 3183 .base_baud = 115200, 3184 .uart_offset = 8, 3185 }, 3186 [pbn_b1_bt_4_115200] = { 3187 .flags = FL_BASE1|FL_BASE_BARS, 3188 .num_ports = 4, 3189 .base_baud = 115200, 3190 .uart_offset = 8, 3191 }, 3192 3193 [pbn_b1_bt_2_921600] = { 3194 .flags = FL_BASE1|FL_BASE_BARS, 3195 .num_ports = 2, 3196 .base_baud = 921600, 3197 .uart_offset = 8, 3198 }, 3199 3200 [pbn_b1_1_1382400] = { 3201 .flags = FL_BASE1, 3202 .num_ports = 1, 3203 .base_baud = 1382400, 3204 .uart_offset = 8, 3205 }, 3206 [pbn_b1_2_1382400] = { 3207 .flags = FL_BASE1, 3208 .num_ports = 2, 3209 .base_baud = 1382400, 3210 .uart_offset = 8, 3211 }, 3212 [pbn_b1_4_1382400] = { 3213 .flags = FL_BASE1, 3214 .num_ports = 4, 3215 .base_baud = 1382400, 3216 .uart_offset = 8, 3217 }, 3218 [pbn_b1_8_1382400] = { 3219 .flags = FL_BASE1, 3220 .num_ports = 8, 3221 .base_baud = 1382400, 3222 .uart_offset = 8, 3223 }, 3224 3225 [pbn_b2_1_115200] = { 3226 .flags = FL_BASE2, 3227 .num_ports = 1, 3228 .base_baud = 115200, 3229 .uart_offset = 8, 3230 }, 3231 [pbn_b2_2_115200] = { 3232 .flags = FL_BASE2, 3233 .num_ports = 2, 3234 .base_baud = 115200, 3235 .uart_offset = 8, 3236 }, 3237 [pbn_b2_4_115200] = { 3238 .flags = FL_BASE2, 3239 .num_ports = 4, 3240 .base_baud = 115200, 3241 .uart_offset = 8, 3242 }, 3243 [pbn_b2_8_115200] = { 3244 .flags = FL_BASE2, 3245 .num_ports = 8, 3246 .base_baud = 115200, 3247 .uart_offset = 8, 3248 }, 3249 3250 [pbn_b2_1_460800] = { 3251 .flags = FL_BASE2, 3252 .num_ports = 1, 3253 .base_baud = 460800, 3254 .uart_offset = 8, 3255 }, 3256 [pbn_b2_4_460800] = { 3257 .flags = FL_BASE2, 3258 .num_ports = 4, 3259 .base_baud = 460800, 3260 .uart_offset = 8, 3261 }, 3262 [pbn_b2_8_460800] = { 3263 .flags = FL_BASE2, 3264 .num_ports = 8, 3265 .base_baud = 460800, 3266 .uart_offset = 8, 3267 }, 3268 [pbn_b2_16_460800] = { 3269 .flags = FL_BASE2, 3270 .num_ports = 16, 3271 .base_baud = 460800, 3272 .uart_offset = 8, 3273 }, 3274 3275 [pbn_b2_1_921600] = { 3276 .flags = FL_BASE2, 3277 .num_ports = 1, 3278 .base_baud = 921600, 3279 .uart_offset = 8, 3280 }, 3281 [pbn_b2_4_921600] = { 3282 .flags = FL_BASE2, 3283 .num_ports = 4, 3284 .base_baud = 921600, 3285 .uart_offset = 8, 3286 }, 3287 [pbn_b2_8_921600] = { 3288 .flags = FL_BASE2, 3289 .num_ports = 8, 3290 .base_baud = 921600, 3291 .uart_offset = 8, 3292 }, 3293 3294 [pbn_b2_8_1152000] = { 3295 .flags = FL_BASE2, 3296 .num_ports = 8, 3297 .base_baud = 1152000, 3298 .uart_offset = 8, 3299 }, 3300 3301 [pbn_b2_bt_1_115200] = { 3302 .flags = FL_BASE2|FL_BASE_BARS, 3303 .num_ports = 1, 3304 .base_baud = 115200, 3305 .uart_offset = 8, 3306 }, 3307 [pbn_b2_bt_2_115200] = { 3308 .flags = FL_BASE2|FL_BASE_BARS, 3309 .num_ports = 2, 3310 .base_baud = 115200, 3311 .uart_offset = 8, 3312 }, 3313 [pbn_b2_bt_4_115200] = { 3314 .flags = FL_BASE2|FL_BASE_BARS, 3315 .num_ports = 4, 3316 .base_baud = 115200, 3317 .uart_offset = 8, 3318 }, 3319 3320 [pbn_b2_bt_2_921600] = { 3321 .flags = FL_BASE2|FL_BASE_BARS, 3322 .num_ports = 2, 3323 .base_baud = 921600, 3324 .uart_offset = 8, 3325 }, 3326 [pbn_b2_bt_4_921600] = { 3327 .flags = FL_BASE2|FL_BASE_BARS, 3328 .num_ports = 4, 3329 .base_baud = 921600, 3330 .uart_offset = 8, 3331 }, 3332 3333 [pbn_b3_2_115200] = { 3334 .flags = FL_BASE3, 3335 .num_ports = 2, 3336 .base_baud = 115200, 3337 .uart_offset = 8, 3338 }, 3339 [pbn_b3_4_115200] = { 3340 .flags = FL_BASE3, 3341 .num_ports = 4, 3342 .base_baud = 115200, 3343 .uart_offset = 8, 3344 }, 3345 [pbn_b3_8_115200] = { 3346 .flags = FL_BASE3, 3347 .num_ports = 8, 3348 .base_baud = 115200, 3349 .uart_offset = 8, 3350 }, 3351 3352 [pbn_b4_bt_2_921600] = { 3353 .flags = FL_BASE4, 3354 .num_ports = 2, 3355 .base_baud = 921600, 3356 .uart_offset = 8, 3357 }, 3358 [pbn_b4_bt_4_921600] = { 3359 .flags = FL_BASE4, 3360 .num_ports = 4, 3361 .base_baud = 921600, 3362 .uart_offset = 8, 3363 }, 3364 [pbn_b4_bt_8_921600] = { 3365 .flags = FL_BASE4, 3366 .num_ports = 8, 3367 .base_baud = 921600, 3368 .uart_offset = 8, 3369 }, 3370 3371 /* 3372 * Entries following this are board-specific. 3373 */ 3374 3375 /* 3376 * Panacom - IOMEM 3377 */ 3378 [pbn_panacom] = { 3379 .flags = FL_BASE2, 3380 .num_ports = 2, 3381 .base_baud = 921600, 3382 .uart_offset = 0x400, 3383 .reg_shift = 7, 3384 }, 3385 [pbn_panacom2] = { 3386 .flags = FL_BASE2|FL_BASE_BARS, 3387 .num_ports = 2, 3388 .base_baud = 921600, 3389 .uart_offset = 0x400, 3390 .reg_shift = 7, 3391 }, 3392 [pbn_panacom4] = { 3393 .flags = FL_BASE2|FL_BASE_BARS, 3394 .num_ports = 4, 3395 .base_baud = 921600, 3396 .uart_offset = 0x400, 3397 .reg_shift = 7, 3398 }, 3399 3400 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3401 [pbn_plx_romulus] = { 3402 .flags = FL_BASE2, 3403 .num_ports = 4, 3404 .base_baud = 921600, 3405 .uart_offset = 8 << 2, 3406 .reg_shift = 2, 3407 .first_offset = 0x03, 3408 }, 3409 3410 /* 3411 * EndRun Technologies 3412 * Uses the size of PCI Base region 0 to 3413 * signal now many ports are available 3414 * 2 port 952 Uart support 3415 */ 3416 [pbn_endrun_2_4000000] = { 3417 .flags = FL_BASE0, 3418 .num_ports = 2, 3419 .base_baud = 4000000, 3420 .uart_offset = 0x200, 3421 .first_offset = 0x1000, 3422 }, 3423 3424 /* 3425 * This board uses the size of PCI Base region 0 to 3426 * signal now many ports are available 3427 */ 3428 [pbn_oxsemi] = { 3429 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3430 .num_ports = 32, 3431 .base_baud = 115200, 3432 .uart_offset = 8, 3433 }, 3434 [pbn_oxsemi_1_4000000] = { 3435 .flags = FL_BASE0, 3436 .num_ports = 1, 3437 .base_baud = 4000000, 3438 .uart_offset = 0x200, 3439 .first_offset = 0x1000, 3440 }, 3441 [pbn_oxsemi_2_4000000] = { 3442 .flags = FL_BASE0, 3443 .num_ports = 2, 3444 .base_baud = 4000000, 3445 .uart_offset = 0x200, 3446 .first_offset = 0x1000, 3447 }, 3448 [pbn_oxsemi_4_4000000] = { 3449 .flags = FL_BASE0, 3450 .num_ports = 4, 3451 .base_baud = 4000000, 3452 .uart_offset = 0x200, 3453 .first_offset = 0x1000, 3454 }, 3455 [pbn_oxsemi_8_4000000] = { 3456 .flags = FL_BASE0, 3457 .num_ports = 8, 3458 .base_baud = 4000000, 3459 .uart_offset = 0x200, 3460 .first_offset = 0x1000, 3461 }, 3462 3463 3464 /* 3465 * EKF addition for i960 Boards form EKF with serial port. 3466 * Max 256 ports. 3467 */ 3468 [pbn_intel_i960] = { 3469 .flags = FL_BASE0, 3470 .num_ports = 32, 3471 .base_baud = 921600, 3472 .uart_offset = 8 << 2, 3473 .reg_shift = 2, 3474 .first_offset = 0x10000, 3475 }, 3476 [pbn_sgi_ioc3] = { 3477 .flags = FL_BASE0|FL_NOIRQ, 3478 .num_ports = 1, 3479 .base_baud = 458333, 3480 .uart_offset = 8, 3481 .reg_shift = 0, 3482 .first_offset = 0x20178, 3483 }, 3484 3485 /* 3486 * Computone - uses IOMEM. 3487 */ 3488 [pbn_computone_4] = { 3489 .flags = FL_BASE0, 3490 .num_ports = 4, 3491 .base_baud = 921600, 3492 .uart_offset = 0x40, 3493 .reg_shift = 2, 3494 .first_offset = 0x200, 3495 }, 3496 [pbn_computone_6] = { 3497 .flags = FL_BASE0, 3498 .num_ports = 6, 3499 .base_baud = 921600, 3500 .uart_offset = 0x40, 3501 .reg_shift = 2, 3502 .first_offset = 0x200, 3503 }, 3504 [pbn_computone_8] = { 3505 .flags = FL_BASE0, 3506 .num_ports = 8, 3507 .base_baud = 921600, 3508 .uart_offset = 0x40, 3509 .reg_shift = 2, 3510 .first_offset = 0x200, 3511 }, 3512 [pbn_sbsxrsio] = { 3513 .flags = FL_BASE0, 3514 .num_ports = 8, 3515 .base_baud = 460800, 3516 .uart_offset = 256, 3517 .reg_shift = 4, 3518 }, 3519 /* 3520 * PA Semi PWRficient PA6T-1682M on-chip UART 3521 */ 3522 [pbn_pasemi_1682M] = { 3523 .flags = FL_BASE0, 3524 .num_ports = 1, 3525 .base_baud = 8333333, 3526 }, 3527 /* 3528 * National Instruments 843x 3529 */ 3530 [pbn_ni8430_16] = { 3531 .flags = FL_BASE0, 3532 .num_ports = 16, 3533 .base_baud = 3686400, 3534 .uart_offset = 0x10, 3535 .first_offset = 0x800, 3536 }, 3537 [pbn_ni8430_8] = { 3538 .flags = FL_BASE0, 3539 .num_ports = 8, 3540 .base_baud = 3686400, 3541 .uart_offset = 0x10, 3542 .first_offset = 0x800, 3543 }, 3544 [pbn_ni8430_4] = { 3545 .flags = FL_BASE0, 3546 .num_ports = 4, 3547 .base_baud = 3686400, 3548 .uart_offset = 0x10, 3549 .first_offset = 0x800, 3550 }, 3551 [pbn_ni8430_2] = { 3552 .flags = FL_BASE0, 3553 .num_ports = 2, 3554 .base_baud = 3686400, 3555 .uart_offset = 0x10, 3556 .first_offset = 0x800, 3557 }, 3558 /* 3559 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3560 */ 3561 [pbn_ADDIDATA_PCIe_1_3906250] = { 3562 .flags = FL_BASE0, 3563 .num_ports = 1, 3564 .base_baud = 3906250, 3565 .uart_offset = 0x200, 3566 .first_offset = 0x1000, 3567 }, 3568 [pbn_ADDIDATA_PCIe_2_3906250] = { 3569 .flags = FL_BASE0, 3570 .num_ports = 2, 3571 .base_baud = 3906250, 3572 .uart_offset = 0x200, 3573 .first_offset = 0x1000, 3574 }, 3575 [pbn_ADDIDATA_PCIe_4_3906250] = { 3576 .flags = FL_BASE0, 3577 .num_ports = 4, 3578 .base_baud = 3906250, 3579 .uart_offset = 0x200, 3580 .first_offset = 0x1000, 3581 }, 3582 [pbn_ADDIDATA_PCIe_8_3906250] = { 3583 .flags = FL_BASE0, 3584 .num_ports = 8, 3585 .base_baud = 3906250, 3586 .uart_offset = 0x200, 3587 .first_offset = 0x1000, 3588 }, 3589 [pbn_ce4100_1_115200] = { 3590 .flags = FL_BASE_BARS, 3591 .num_ports = 2, 3592 .base_baud = 921600, 3593 .reg_shift = 2, 3594 }, 3595 [pbn_omegapci] = { 3596 .flags = FL_BASE0, 3597 .num_ports = 8, 3598 .base_baud = 115200, 3599 .uart_offset = 0x200, 3600 }, 3601 [pbn_NETMOS9900_2s_115200] = { 3602 .flags = FL_BASE0, 3603 .num_ports = 2, 3604 .base_baud = 115200, 3605 }, 3606 [pbn_brcm_trumanage] = { 3607 .flags = FL_BASE0, 3608 .num_ports = 1, 3609 .reg_shift = 2, 3610 .base_baud = 115200, 3611 }, 3612 [pbn_fintek_4] = { 3613 .num_ports = 4, 3614 .uart_offset = 8, 3615 .base_baud = 115200, 3616 .first_offset = 0x40, 3617 }, 3618 [pbn_fintek_8] = { 3619 .num_ports = 8, 3620 .uart_offset = 8, 3621 .base_baud = 115200, 3622 .first_offset = 0x40, 3623 }, 3624 [pbn_fintek_12] = { 3625 .num_ports = 12, 3626 .uart_offset = 8, 3627 .base_baud = 115200, 3628 .first_offset = 0x40, 3629 }, 3630 [pbn_fintek_F81504A] = { 3631 .num_ports = 4, 3632 .uart_offset = 8, 3633 .base_baud = 115200, 3634 }, 3635 [pbn_fintek_F81508A] = { 3636 .num_ports = 8, 3637 .uart_offset = 8, 3638 .base_baud = 115200, 3639 }, 3640 [pbn_fintek_F81512A] = { 3641 .num_ports = 12, 3642 .uart_offset = 8, 3643 .base_baud = 115200, 3644 }, 3645 [pbn_wch382_2] = { 3646 .flags = FL_BASE0, 3647 .num_ports = 2, 3648 .base_baud = 115200, 3649 .uart_offset = 8, 3650 .first_offset = 0xC0, 3651 }, 3652 [pbn_wch384_4] = { 3653 .flags = FL_BASE0, 3654 .num_ports = 4, 3655 .base_baud = 115200, 3656 .uart_offset = 8, 3657 .first_offset = 0xC0, 3658 }, 3659 /* 3660 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 3661 */ 3662 [pbn_pericom_PI7C9X7951] = { 3663 .flags = FL_BASE0, 3664 .num_ports = 1, 3665 .base_baud = 921600, 3666 .uart_offset = 0x8, 3667 }, 3668 [pbn_pericom_PI7C9X7952] = { 3669 .flags = FL_BASE0, 3670 .num_ports = 2, 3671 .base_baud = 921600, 3672 .uart_offset = 0x8, 3673 }, 3674 [pbn_pericom_PI7C9X7954] = { 3675 .flags = FL_BASE0, 3676 .num_ports = 4, 3677 .base_baud = 921600, 3678 .uart_offset = 0x8, 3679 }, 3680 [pbn_pericom_PI7C9X7958] = { 3681 .flags = FL_BASE0, 3682 .num_ports = 8, 3683 .base_baud = 921600, 3684 .uart_offset = 0x8, 3685 }, 3686 [pbn_sunix_pci_1s] = { 3687 .num_ports = 1, 3688 .base_baud = 921600, 3689 .uart_offset = 0x8, 3690 }, 3691 [pbn_sunix_pci_2s] = { 3692 .num_ports = 2, 3693 .base_baud = 921600, 3694 .uart_offset = 0x8, 3695 }, 3696 [pbn_sunix_pci_4s] = { 3697 .num_ports = 4, 3698 .base_baud = 921600, 3699 .uart_offset = 0x8, 3700 }, 3701 [pbn_sunix_pci_8s] = { 3702 .num_ports = 8, 3703 .base_baud = 921600, 3704 .uart_offset = 0x8, 3705 }, 3706 [pbn_sunix_pci_16s] = { 3707 .num_ports = 16, 3708 .base_baud = 921600, 3709 .uart_offset = 0x8, 3710 }, 3711 [pbn_moxa8250_2p] = { 3712 .flags = FL_BASE1, 3713 .num_ports = 2, 3714 .base_baud = 921600, 3715 .uart_offset = 0x200, 3716 }, 3717 [pbn_moxa8250_4p] = { 3718 .flags = FL_BASE1, 3719 .num_ports = 4, 3720 .base_baud = 921600, 3721 .uart_offset = 0x200, 3722 }, 3723 [pbn_moxa8250_8p] = { 3724 .flags = FL_BASE1, 3725 .num_ports = 8, 3726 .base_baud = 921600, 3727 .uart_offset = 0x200, 3728 }, 3729 }; 3730 3731 static const struct pci_device_id blacklist[] = { 3732 /* softmodems */ 3733 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3734 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3735 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3736 3737 /* multi-io cards handled by parport_serial */ 3738 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ 3739 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ 3740 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */ 3741 3742 /* Intel platforms with MID UART */ 3743 { PCI_VDEVICE(INTEL, 0x081b), }, 3744 { PCI_VDEVICE(INTEL, 0x081c), }, 3745 { PCI_VDEVICE(INTEL, 0x081d), }, 3746 { PCI_VDEVICE(INTEL, 0x1191), }, 3747 { PCI_VDEVICE(INTEL, 0x18d8), }, 3748 { PCI_VDEVICE(INTEL, 0x19d8), }, 3749 3750 /* Intel platforms with DesignWare UART */ 3751 { PCI_VDEVICE(INTEL, 0x0936), }, 3752 { PCI_VDEVICE(INTEL, 0x0f0a), }, 3753 { PCI_VDEVICE(INTEL, 0x0f0c), }, 3754 { PCI_VDEVICE(INTEL, 0x228a), }, 3755 { PCI_VDEVICE(INTEL, 0x228c), }, 3756 { PCI_VDEVICE(INTEL, 0x9ce3), }, 3757 { PCI_VDEVICE(INTEL, 0x9ce4), }, 3758 3759 /* Exar devices */ 3760 { PCI_VDEVICE(EXAR, PCI_ANY_ID), }, 3761 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), }, 3762 3763 /* End of the black list */ 3764 { } 3765 }; 3766 3767 static int serial_pci_is_class_communication(struct pci_dev *dev) 3768 { 3769 /* 3770 * If it is not a communications device or the programming 3771 * interface is greater than 6, give up. 3772 */ 3773 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3774 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 3775 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3776 (dev->class & 0xff) > 6) 3777 return -ENODEV; 3778 3779 return 0; 3780 } 3781 3782 /* 3783 * Given a complete unknown PCI device, try to use some heuristics to 3784 * guess what the configuration might be, based on the pitiful PCI 3785 * serial specs. Returns 0 on success, -ENODEV on failure. 3786 */ 3787 static int 3788 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3789 { 3790 int num_iomem, num_port, first_port = -1, i; 3791 int rc; 3792 3793 rc = serial_pci_is_class_communication(dev); 3794 if (rc) 3795 return rc; 3796 3797 /* 3798 * Should we try to make guesses for multiport serial devices later? 3799 */ 3800 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 3801 return -ENODEV; 3802 3803 num_iomem = num_port = 0; 3804 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3805 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3806 num_port++; 3807 if (first_port == -1) 3808 first_port = i; 3809 } 3810 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3811 num_iomem++; 3812 } 3813 3814 /* 3815 * If there is 1 or 0 iomem regions, and exactly one port, 3816 * use it. We guess the number of ports based on the IO 3817 * region size. 3818 */ 3819 if (num_iomem <= 1 && num_port == 1) { 3820 board->flags = first_port; 3821 board->num_ports = pci_resource_len(dev, first_port) / 8; 3822 return 0; 3823 } 3824 3825 /* 3826 * Now guess if we've got a board which indexes by BARs. 3827 * Each IO BAR should be 8 bytes, and they should follow 3828 * consecutively. 3829 */ 3830 first_port = -1; 3831 num_port = 0; 3832 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3833 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3834 pci_resource_len(dev, i) == 8 && 3835 (first_port == -1 || (first_port + num_port) == i)) { 3836 num_port++; 3837 if (first_port == -1) 3838 first_port = i; 3839 } 3840 } 3841 3842 if (num_port > 1) { 3843 board->flags = first_port | FL_BASE_BARS; 3844 board->num_ports = num_port; 3845 return 0; 3846 } 3847 3848 return -ENODEV; 3849 } 3850 3851 static inline int 3852 serial_pci_matches(const struct pciserial_board *board, 3853 const struct pciserial_board *guessed) 3854 { 3855 return 3856 board->num_ports == guessed->num_ports && 3857 board->base_baud == guessed->base_baud && 3858 board->uart_offset == guessed->uart_offset && 3859 board->reg_shift == guessed->reg_shift && 3860 board->first_offset == guessed->first_offset; 3861 } 3862 3863 struct serial_private * 3864 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3865 { 3866 struct uart_8250_port uart; 3867 struct serial_private *priv; 3868 struct pci_serial_quirk *quirk; 3869 int rc, nr_ports, i; 3870 3871 nr_ports = board->num_ports; 3872 3873 /* 3874 * Find an init and setup quirks. 3875 */ 3876 quirk = find_quirk(dev); 3877 3878 /* 3879 * Run the new-style initialization function. 3880 * The initialization function returns: 3881 * <0 - error 3882 * 0 - use board->num_ports 3883 * >0 - number of ports 3884 */ 3885 if (quirk->init) { 3886 rc = quirk->init(dev); 3887 if (rc < 0) { 3888 priv = ERR_PTR(rc); 3889 goto err_out; 3890 } 3891 if (rc) 3892 nr_ports = rc; 3893 } 3894 3895 priv = kzalloc(sizeof(struct serial_private) + 3896 sizeof(unsigned int) * nr_ports, 3897 GFP_KERNEL); 3898 if (!priv) { 3899 priv = ERR_PTR(-ENOMEM); 3900 goto err_deinit; 3901 } 3902 3903 priv->dev = dev; 3904 priv->quirk = quirk; 3905 3906 memset(&uart, 0, sizeof(uart)); 3907 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3908 uart.port.uartclk = board->base_baud * 16; 3909 3910 if (pci_match_id(pci_use_msi, dev)) { 3911 dev_dbg(&dev->dev, "Using MSI(-X) interrupts\n"); 3912 pci_set_master(dev); 3913 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); 3914 } else { 3915 dev_dbg(&dev->dev, "Using legacy interrupts\n"); 3916 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY); 3917 } 3918 if (rc < 0) { 3919 kfree(priv); 3920 priv = ERR_PTR(rc); 3921 goto err_deinit; 3922 } 3923 3924 uart.port.irq = pci_irq_vector(dev, 0); 3925 uart.port.dev = &dev->dev; 3926 3927 for (i = 0; i < nr_ports; i++) { 3928 if (quirk->setup(priv, board, &uart, i)) 3929 break; 3930 3931 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3932 uart.port.iobase, uart.port.irq, uart.port.iotype); 3933 3934 priv->line[i] = serial8250_register_8250_port(&uart); 3935 if (priv->line[i] < 0) { 3936 dev_err(&dev->dev, 3937 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 3938 uart.port.iobase, uart.port.irq, 3939 uart.port.iotype, priv->line[i]); 3940 break; 3941 } 3942 } 3943 priv->nr = i; 3944 priv->board = board; 3945 return priv; 3946 3947 err_deinit: 3948 if (quirk->exit) 3949 quirk->exit(dev); 3950 err_out: 3951 return priv; 3952 } 3953 EXPORT_SYMBOL_GPL(pciserial_init_ports); 3954 3955 static void pciserial_detach_ports(struct serial_private *priv) 3956 { 3957 struct pci_serial_quirk *quirk; 3958 int i; 3959 3960 for (i = 0; i < priv->nr; i++) 3961 serial8250_unregister_port(priv->line[i]); 3962 3963 /* 3964 * Find the exit quirks. 3965 */ 3966 quirk = find_quirk(priv->dev); 3967 if (quirk->exit) 3968 quirk->exit(priv->dev); 3969 } 3970 3971 void pciserial_remove_ports(struct serial_private *priv) 3972 { 3973 pciserial_detach_ports(priv); 3974 kfree(priv); 3975 } 3976 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 3977 3978 void pciserial_suspend_ports(struct serial_private *priv) 3979 { 3980 int i; 3981 3982 for (i = 0; i < priv->nr; i++) 3983 if (priv->line[i] >= 0) 3984 serial8250_suspend_port(priv->line[i]); 3985 3986 /* 3987 * Ensure that every init quirk is properly torn down 3988 */ 3989 if (priv->quirk->exit) 3990 priv->quirk->exit(priv->dev); 3991 } 3992 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 3993 3994 void pciserial_resume_ports(struct serial_private *priv) 3995 { 3996 int i; 3997 3998 /* 3999 * Ensure that the board is correctly configured. 4000 */ 4001 if (priv->quirk->init) 4002 priv->quirk->init(priv->dev); 4003 4004 for (i = 0; i < priv->nr; i++) 4005 if (priv->line[i] >= 0) 4006 serial8250_resume_port(priv->line[i]); 4007 } 4008 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 4009 4010 /* 4011 * Probe one serial board. Unfortunately, there is no rhyme nor reason 4012 * to the arrangement of serial ports on a PCI card. 4013 */ 4014 static int 4015 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 4016 { 4017 struct pci_serial_quirk *quirk; 4018 struct serial_private *priv; 4019 const struct pciserial_board *board; 4020 const struct pci_device_id *exclude; 4021 struct pciserial_board tmp; 4022 int rc; 4023 4024 quirk = find_quirk(dev); 4025 if (quirk->probe) { 4026 rc = quirk->probe(dev); 4027 if (rc) 4028 return rc; 4029 } 4030 4031 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 4032 dev_err(&dev->dev, "invalid driver_data: %ld\n", 4033 ent->driver_data); 4034 return -EINVAL; 4035 } 4036 4037 board = &pci_boards[ent->driver_data]; 4038 4039 exclude = pci_match_id(blacklist, dev); 4040 if (exclude) 4041 return -ENODEV; 4042 4043 rc = pcim_enable_device(dev); 4044 pci_save_state(dev); 4045 if (rc) 4046 return rc; 4047 4048 if (ent->driver_data == pbn_default) { 4049 /* 4050 * Use a copy of the pci_board entry for this; 4051 * avoid changing entries in the table. 4052 */ 4053 memcpy(&tmp, board, sizeof(struct pciserial_board)); 4054 board = &tmp; 4055 4056 /* 4057 * We matched one of our class entries. Try to 4058 * determine the parameters of this board. 4059 */ 4060 rc = serial_pci_guess_board(dev, &tmp); 4061 if (rc) 4062 return rc; 4063 } else { 4064 /* 4065 * We matched an explicit entry. If we are able to 4066 * detect this boards settings with our heuristic, 4067 * then we no longer need this entry. 4068 */ 4069 memcpy(&tmp, &pci_boards[pbn_default], 4070 sizeof(struct pciserial_board)); 4071 rc = serial_pci_guess_board(dev, &tmp); 4072 if (rc == 0 && serial_pci_matches(board, &tmp)) 4073 moan_device("Redundant entry in serial pci_table.", 4074 dev); 4075 } 4076 4077 priv = pciserial_init_ports(dev, board); 4078 if (IS_ERR(priv)) 4079 return PTR_ERR(priv); 4080 4081 pci_set_drvdata(dev, priv); 4082 return 0; 4083 } 4084 4085 static void pciserial_remove_one(struct pci_dev *dev) 4086 { 4087 struct serial_private *priv = pci_get_drvdata(dev); 4088 4089 pciserial_remove_ports(priv); 4090 } 4091 4092 #ifdef CONFIG_PM_SLEEP 4093 static int pciserial_suspend_one(struct device *dev) 4094 { 4095 struct serial_private *priv = dev_get_drvdata(dev); 4096 4097 if (priv) 4098 pciserial_suspend_ports(priv); 4099 4100 return 0; 4101 } 4102 4103 static int pciserial_resume_one(struct device *dev) 4104 { 4105 struct pci_dev *pdev = to_pci_dev(dev); 4106 struct serial_private *priv = pci_get_drvdata(pdev); 4107 int err; 4108 4109 if (priv) { 4110 /* 4111 * The device may have been disabled. Re-enable it. 4112 */ 4113 err = pci_enable_device(pdev); 4114 /* FIXME: We cannot simply error out here */ 4115 if (err) 4116 dev_err(dev, "Unable to re-enable ports, trying to continue.\n"); 4117 pciserial_resume_ports(priv); 4118 } 4119 return 0; 4120 } 4121 #endif 4122 4123 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4124 pciserial_resume_one); 4125 4126 static const struct pci_device_id serial_pci_tbl[] = { 4127 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4128 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4129 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4130 pbn_b2_8_921600 }, 4131 /* Advantech also use 0x3618 and 0xf618 */ 4132 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4133 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4134 pbn_b0_4_921600 }, 4135 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4136 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4137 pbn_b0_4_921600 }, 4138 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4139 PCI_SUBVENDOR_ID_CONNECT_TECH, 4140 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4141 pbn_b1_8_1382400 }, 4142 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4143 PCI_SUBVENDOR_ID_CONNECT_TECH, 4144 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4145 pbn_b1_4_1382400 }, 4146 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4147 PCI_SUBVENDOR_ID_CONNECT_TECH, 4148 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4149 pbn_b1_2_1382400 }, 4150 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4151 PCI_SUBVENDOR_ID_CONNECT_TECH, 4152 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4153 pbn_b1_8_1382400 }, 4154 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4155 PCI_SUBVENDOR_ID_CONNECT_TECH, 4156 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4157 pbn_b1_4_1382400 }, 4158 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4159 PCI_SUBVENDOR_ID_CONNECT_TECH, 4160 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4161 pbn_b1_2_1382400 }, 4162 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4163 PCI_SUBVENDOR_ID_CONNECT_TECH, 4164 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4165 pbn_b1_8_921600 }, 4166 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4167 PCI_SUBVENDOR_ID_CONNECT_TECH, 4168 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4169 pbn_b1_8_921600 }, 4170 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4171 PCI_SUBVENDOR_ID_CONNECT_TECH, 4172 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4173 pbn_b1_4_921600 }, 4174 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4175 PCI_SUBVENDOR_ID_CONNECT_TECH, 4176 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4177 pbn_b1_4_921600 }, 4178 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4179 PCI_SUBVENDOR_ID_CONNECT_TECH, 4180 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4181 pbn_b1_2_921600 }, 4182 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4183 PCI_SUBVENDOR_ID_CONNECT_TECH, 4184 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4185 pbn_b1_8_921600 }, 4186 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4187 PCI_SUBVENDOR_ID_CONNECT_TECH, 4188 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4189 pbn_b1_8_921600 }, 4190 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4191 PCI_SUBVENDOR_ID_CONNECT_TECH, 4192 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4193 pbn_b1_4_921600 }, 4194 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4195 PCI_SUBVENDOR_ID_CONNECT_TECH, 4196 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4197 pbn_b1_2_1250000 }, 4198 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4199 PCI_SUBVENDOR_ID_CONNECT_TECH, 4200 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4201 pbn_b0_2_1843200 }, 4202 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4203 PCI_SUBVENDOR_ID_CONNECT_TECH, 4204 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4205 pbn_b0_4_1843200 }, 4206 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4207 PCI_VENDOR_ID_AFAVLAB, 4208 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4209 pbn_b0_4_1152000 }, 4210 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4212 pbn_b2_bt_1_115200 }, 4213 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4215 pbn_b2_bt_2_115200 }, 4216 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4218 pbn_b2_bt_4_115200 }, 4219 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4221 pbn_b2_bt_2_115200 }, 4222 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4224 pbn_b2_bt_4_115200 }, 4225 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4227 pbn_b2_8_115200 }, 4228 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4230 pbn_b2_8_460800 }, 4231 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4233 pbn_b2_8_115200 }, 4234 4235 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4237 pbn_b2_bt_2_115200 }, 4238 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4240 pbn_b2_bt_2_921600 }, 4241 /* 4242 * VScom SPCOM800, from sl@s.pl 4243 */ 4244 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4245 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4246 pbn_b2_8_921600 }, 4247 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4249 pbn_b2_4_921600 }, 4250 /* Unknown card - subdevice 0x1584 */ 4251 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4252 PCI_VENDOR_ID_PLX, 4253 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4254 pbn_b2_4_115200 }, 4255 /* Unknown card - subdevice 0x1588 */ 4256 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4257 PCI_VENDOR_ID_PLX, 4258 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4259 pbn_b2_8_115200 }, 4260 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4261 PCI_SUBVENDOR_ID_KEYSPAN, 4262 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4263 pbn_panacom }, 4264 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4265 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4266 pbn_panacom4 }, 4267 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4269 pbn_panacom2 }, 4270 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4271 PCI_VENDOR_ID_ESDGMBH, 4272 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4273 pbn_b2_4_115200 }, 4274 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4275 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4276 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4277 pbn_b2_4_460800 }, 4278 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4279 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4280 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4281 pbn_b2_8_460800 }, 4282 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4283 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4284 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4285 pbn_b2_16_460800 }, 4286 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4287 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4288 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4289 pbn_b2_16_460800 }, 4290 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4291 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4292 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4293 pbn_b2_4_460800 }, 4294 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4295 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4296 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4297 pbn_b2_8_460800 }, 4298 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4299 PCI_SUBVENDOR_ID_EXSYS, 4300 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4301 pbn_b2_4_115200 }, 4302 /* 4303 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4304 * (Exoray@isys.ca) 4305 */ 4306 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4307 0x10b5, 0x106a, 0, 0, 4308 pbn_plx_romulus }, 4309 /* 4310 * EndRun Technologies. PCI express device range. 4311 * EndRun PTP/1588 has 2 Native UARTs. 4312 */ 4313 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4315 pbn_endrun_2_4000000 }, 4316 /* 4317 * Quatech cards. These actually have configurable clocks but for 4318 * now we just use the default. 4319 * 4320 * 100 series are RS232, 200 series RS422, 4321 */ 4322 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4323 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4324 pbn_b1_4_115200 }, 4325 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4327 pbn_b1_2_115200 }, 4328 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4329 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4330 pbn_b2_2_115200 }, 4331 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4332 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4333 pbn_b1_2_115200 }, 4334 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4335 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4336 pbn_b2_2_115200 }, 4337 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4339 pbn_b1_4_115200 }, 4340 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4342 pbn_b1_8_115200 }, 4343 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4344 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4345 pbn_b1_8_115200 }, 4346 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4348 pbn_b1_4_115200 }, 4349 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4350 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4351 pbn_b1_2_115200 }, 4352 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4353 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4354 pbn_b1_4_115200 }, 4355 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4356 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4357 pbn_b1_2_115200 }, 4358 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4359 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4360 pbn_b2_4_115200 }, 4361 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4362 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4363 pbn_b2_2_115200 }, 4364 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4365 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4366 pbn_b2_1_115200 }, 4367 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4368 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4369 pbn_b2_4_115200 }, 4370 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4371 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4372 pbn_b2_2_115200 }, 4373 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4374 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4375 pbn_b2_1_115200 }, 4376 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4377 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4378 pbn_b0_8_115200 }, 4379 4380 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4381 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4382 0, 0, 4383 pbn_b0_4_921600 }, 4384 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4385 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4386 0, 0, 4387 pbn_b0_4_1152000 }, 4388 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4389 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4390 pbn_b0_bt_2_921600 }, 4391 4392 /* 4393 * The below card is a little controversial since it is the 4394 * subject of a PCI vendor/device ID clash. (See 4395 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4396 * For now just used the hex ID 0x950a. 4397 */ 4398 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4399 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4400 0, 0, pbn_b0_2_115200 }, 4401 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4402 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4403 0, 0, pbn_b0_2_115200 }, 4404 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4405 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4406 pbn_b0_2_1130000 }, 4407 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4408 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4409 pbn_b0_1_921600 }, 4410 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4412 pbn_b0_4_115200 }, 4413 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4415 pbn_b0_bt_2_921600 }, 4416 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4418 pbn_b2_8_1152000 }, 4419 4420 /* 4421 * Oxford Semiconductor Inc. Tornado PCI express device range. 4422 */ 4423 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4424 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4425 pbn_b0_1_4000000 }, 4426 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4427 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4428 pbn_b0_1_4000000 }, 4429 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4430 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4431 pbn_oxsemi_1_4000000 }, 4432 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4433 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4434 pbn_oxsemi_1_4000000 }, 4435 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4436 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4437 pbn_b0_1_4000000 }, 4438 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4439 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4440 pbn_b0_1_4000000 }, 4441 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4442 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4443 pbn_oxsemi_1_4000000 }, 4444 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4445 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4446 pbn_oxsemi_1_4000000 }, 4447 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4448 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4449 pbn_b0_1_4000000 }, 4450 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4452 pbn_b0_1_4000000 }, 4453 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4454 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4455 pbn_b0_1_4000000 }, 4456 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4457 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4458 pbn_b0_1_4000000 }, 4459 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4460 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4461 pbn_oxsemi_2_4000000 }, 4462 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4463 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4464 pbn_oxsemi_2_4000000 }, 4465 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4466 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4467 pbn_oxsemi_4_4000000 }, 4468 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4469 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4470 pbn_oxsemi_4_4000000 }, 4471 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4472 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4473 pbn_oxsemi_8_4000000 }, 4474 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4475 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4476 pbn_oxsemi_8_4000000 }, 4477 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4478 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4479 pbn_oxsemi_1_4000000 }, 4480 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4481 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4482 pbn_oxsemi_1_4000000 }, 4483 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4484 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4485 pbn_oxsemi_1_4000000 }, 4486 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4487 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4488 pbn_oxsemi_1_4000000 }, 4489 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4491 pbn_oxsemi_1_4000000 }, 4492 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4494 pbn_oxsemi_1_4000000 }, 4495 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4497 pbn_oxsemi_1_4000000 }, 4498 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4500 pbn_oxsemi_1_4000000 }, 4501 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4503 pbn_oxsemi_1_4000000 }, 4504 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4505 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4506 pbn_oxsemi_1_4000000 }, 4507 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4508 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4509 pbn_oxsemi_1_4000000 }, 4510 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4511 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4512 pbn_oxsemi_1_4000000 }, 4513 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4514 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4515 pbn_oxsemi_1_4000000 }, 4516 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4517 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4518 pbn_oxsemi_1_4000000 }, 4519 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4520 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4521 pbn_oxsemi_1_4000000 }, 4522 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4523 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4524 pbn_oxsemi_1_4000000 }, 4525 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4526 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4527 pbn_oxsemi_1_4000000 }, 4528 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4529 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4530 pbn_oxsemi_1_4000000 }, 4531 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4532 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4533 pbn_oxsemi_1_4000000 }, 4534 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4535 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4536 pbn_oxsemi_1_4000000 }, 4537 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4538 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4539 pbn_oxsemi_1_4000000 }, 4540 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4541 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4542 pbn_oxsemi_1_4000000 }, 4543 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4544 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4545 pbn_oxsemi_1_4000000 }, 4546 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4547 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4548 pbn_oxsemi_1_4000000 }, 4549 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4550 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4551 pbn_oxsemi_1_4000000 }, 4552 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4553 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4554 pbn_oxsemi_1_4000000 }, 4555 /* 4556 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4557 */ 4558 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4559 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4560 pbn_oxsemi_1_4000000 }, 4561 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4562 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4563 pbn_oxsemi_2_4000000 }, 4564 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4565 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4566 pbn_oxsemi_4_4000000 }, 4567 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4568 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4569 pbn_oxsemi_8_4000000 }, 4570 4571 /* 4572 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4573 */ 4574 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4575 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4576 pbn_oxsemi_2_4000000 }, 4577 4578 /* 4579 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4580 * from skokodyn@yahoo.com 4581 */ 4582 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4583 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4584 pbn_sbsxrsio }, 4585 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4586 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4587 pbn_sbsxrsio }, 4588 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4589 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4590 pbn_sbsxrsio }, 4591 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4592 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4593 pbn_sbsxrsio }, 4594 4595 /* 4596 * Digitan DS560-558, from jimd@esoft.com 4597 */ 4598 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4599 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4600 pbn_b1_1_115200 }, 4601 4602 /* 4603 * Titan Electronic cards 4604 * The 400L and 800L have a custom setup quirk. 4605 */ 4606 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4608 pbn_b0_1_921600 }, 4609 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4611 pbn_b0_2_921600 }, 4612 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4614 pbn_b0_4_921600 }, 4615 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4617 pbn_b0_4_921600 }, 4618 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4620 pbn_b1_1_921600 }, 4621 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4623 pbn_b1_bt_2_921600 }, 4624 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4625 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4626 pbn_b0_bt_4_921600 }, 4627 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4628 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4629 pbn_b0_bt_8_921600 }, 4630 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4632 pbn_b4_bt_2_921600 }, 4633 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4634 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4635 pbn_b4_bt_4_921600 }, 4636 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4637 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4638 pbn_b4_bt_8_921600 }, 4639 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4640 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4641 pbn_b0_4_921600 }, 4642 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4643 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4644 pbn_b0_4_921600 }, 4645 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4646 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4647 pbn_b0_4_921600 }, 4648 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4649 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4650 pbn_oxsemi_1_4000000 }, 4651 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4652 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4653 pbn_oxsemi_2_4000000 }, 4654 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4655 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4656 pbn_oxsemi_4_4000000 }, 4657 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4658 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4659 pbn_oxsemi_8_4000000 }, 4660 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4661 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4662 pbn_oxsemi_2_4000000 }, 4663 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4664 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4665 pbn_oxsemi_2_4000000 }, 4666 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4667 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4668 pbn_b0_bt_2_921600 }, 4669 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4670 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4671 pbn_b0_4_921600 }, 4672 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4673 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4674 pbn_b0_4_921600 }, 4675 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4676 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4677 pbn_b0_4_921600 }, 4678 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4679 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4680 pbn_b0_4_921600 }, 4681 4682 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4684 pbn_b2_1_460800 }, 4685 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4687 pbn_b2_1_460800 }, 4688 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4690 pbn_b2_1_460800 }, 4691 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4693 pbn_b2_bt_2_921600 }, 4694 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4695 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4696 pbn_b2_bt_2_921600 }, 4697 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4699 pbn_b2_bt_2_921600 }, 4700 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4701 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4702 pbn_b2_bt_4_921600 }, 4703 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4704 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4705 pbn_b2_bt_4_921600 }, 4706 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4707 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4708 pbn_b2_bt_4_921600 }, 4709 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4710 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4711 pbn_b0_1_921600 }, 4712 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4713 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4714 pbn_b0_1_921600 }, 4715 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4716 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4717 pbn_b0_1_921600 }, 4718 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4719 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4720 pbn_b0_bt_2_921600 }, 4721 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4722 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4723 pbn_b0_bt_2_921600 }, 4724 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4726 pbn_b0_bt_2_921600 }, 4727 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4728 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4729 pbn_b0_bt_4_921600 }, 4730 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4731 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4732 pbn_b0_bt_4_921600 }, 4733 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4734 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4735 pbn_b0_bt_4_921600 }, 4736 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4737 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4738 pbn_b0_bt_8_921600 }, 4739 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4740 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4741 pbn_b0_bt_8_921600 }, 4742 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4743 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4744 pbn_b0_bt_8_921600 }, 4745 4746 /* 4747 * Computone devices submitted by Doug McNash dmcnash@computone.com 4748 */ 4749 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4750 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4751 0, 0, pbn_computone_4 }, 4752 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4753 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4754 0, 0, pbn_computone_8 }, 4755 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4756 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4757 0, 0, pbn_computone_6 }, 4758 4759 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4760 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4761 pbn_oxsemi }, 4762 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4763 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4764 pbn_b0_bt_1_921600 }, 4765 4766 /* 4767 * Sunix PCI serial boards 4768 */ 4769 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4770 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0, 4771 pbn_sunix_pci_1s }, 4772 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4773 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0, 4774 pbn_sunix_pci_2s }, 4775 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4776 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0, 4777 pbn_sunix_pci_4s }, 4778 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4779 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0, 4780 pbn_sunix_pci_4s }, 4781 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4782 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0, 4783 pbn_sunix_pci_8s }, 4784 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4785 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0, 4786 pbn_sunix_pci_8s }, 4787 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4788 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0, 4789 pbn_sunix_pci_16s }, 4790 4791 /* 4792 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4793 */ 4794 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4795 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4796 pbn_b0_bt_8_115200 }, 4797 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4799 pbn_b0_bt_8_115200 }, 4800 4801 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4802 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4803 pbn_b0_bt_2_115200 }, 4804 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4805 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4806 pbn_b0_bt_2_115200 }, 4807 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4808 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4809 pbn_b0_bt_2_115200 }, 4810 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4811 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4812 pbn_b0_bt_2_115200 }, 4813 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4814 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4815 pbn_b0_bt_2_115200 }, 4816 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4817 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4818 pbn_b0_bt_4_460800 }, 4819 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4820 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4821 pbn_b0_bt_4_460800 }, 4822 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4823 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4824 pbn_b0_bt_2_460800 }, 4825 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4826 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4827 pbn_b0_bt_2_460800 }, 4828 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4829 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4830 pbn_b0_bt_2_460800 }, 4831 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4832 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4833 pbn_b0_bt_1_115200 }, 4834 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4835 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4836 pbn_b0_bt_1_460800 }, 4837 4838 /* 4839 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4840 * Cards are identified by their subsystem vendor IDs, which 4841 * (in hex) match the model number. 4842 * 4843 * Note that JC140x are RS422/485 cards which require ox950 4844 * ACR = 0x10, and as such are not currently fully supported. 4845 */ 4846 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4847 0x1204, 0x0004, 0, 0, 4848 pbn_b0_4_921600 }, 4849 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4850 0x1208, 0x0004, 0, 0, 4851 pbn_b0_4_921600 }, 4852 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4853 0x1402, 0x0002, 0, 0, 4854 pbn_b0_2_921600 }, */ 4855 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4856 0x1404, 0x0004, 0, 0, 4857 pbn_b0_4_921600 }, */ 4858 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4859 0x1208, 0x0004, 0, 0, 4860 pbn_b0_4_921600 }, 4861 4862 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4863 0x1204, 0x0004, 0, 0, 4864 pbn_b0_4_921600 }, 4865 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4866 0x1208, 0x0004, 0, 0, 4867 pbn_b0_4_921600 }, 4868 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4869 0x1208, 0x0004, 0, 0, 4870 pbn_b0_4_921600 }, 4871 /* 4872 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4873 */ 4874 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4875 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4876 pbn_b1_1_1382400 }, 4877 4878 /* 4879 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4880 */ 4881 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4882 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4883 pbn_b1_1_1382400 }, 4884 4885 /* 4886 * RAStel 2 port modem, gerg@moreton.com.au 4887 */ 4888 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4889 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4890 pbn_b2_bt_2_115200 }, 4891 4892 /* 4893 * EKF addition for i960 Boards form EKF with serial port 4894 */ 4895 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4896 0xE4BF, PCI_ANY_ID, 0, 0, 4897 pbn_intel_i960 }, 4898 4899 /* 4900 * Xircom Cardbus/Ethernet combos 4901 */ 4902 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4903 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4904 pbn_b0_1_115200 }, 4905 /* 4906 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4907 */ 4908 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4909 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4910 pbn_b0_1_115200 }, 4911 4912 /* 4913 * Untested PCI modems, sent in from various folks... 4914 */ 4915 4916 /* 4917 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4918 */ 4919 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4920 0x1048, 0x1500, 0, 0, 4921 pbn_b1_1_115200 }, 4922 4923 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4924 0xFF00, 0, 0, 0, 4925 pbn_sgi_ioc3 }, 4926 4927 /* 4928 * HP Diva card 4929 */ 4930 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4931 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4932 pbn_b1_1_115200 }, 4933 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4934 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4935 pbn_b0_5_115200 }, 4936 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4937 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4938 pbn_b2_1_115200 }, 4939 4940 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 4941 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4942 pbn_b3_2_115200 }, 4943 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 4944 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4945 pbn_b3_4_115200 }, 4946 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 4947 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4948 pbn_b3_8_115200 }, 4949 /* 4950 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 4951 */ 4952 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951, 4953 PCI_ANY_ID, PCI_ANY_ID, 4954 0, 4955 0, pbn_pericom_PI7C9X7951 }, 4956 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952, 4957 PCI_ANY_ID, PCI_ANY_ID, 4958 0, 4959 0, pbn_pericom_PI7C9X7952 }, 4960 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954, 4961 PCI_ANY_ID, PCI_ANY_ID, 4962 0, 4963 0, pbn_pericom_PI7C9X7954 }, 4964 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958, 4965 PCI_ANY_ID, PCI_ANY_ID, 4966 0, 4967 0, pbn_pericom_PI7C9X7958 }, 4968 /* 4969 * ACCES I/O Products quad 4970 */ 4971 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB, 4972 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4973 pbn_pericom_PI7C9X7952 }, 4974 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S, 4975 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4976 pbn_pericom_PI7C9X7952 }, 4977 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB, 4978 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4979 pbn_pericom_PI7C9X7954 }, 4980 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S, 4981 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4982 pbn_pericom_PI7C9X7954 }, 4983 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB, 4984 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4985 pbn_pericom_PI7C9X7952 }, 4986 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2, 4987 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4988 pbn_pericom_PI7C9X7952 }, 4989 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB, 4990 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4991 pbn_pericom_PI7C9X7954 }, 4992 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4, 4993 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4994 pbn_pericom_PI7C9X7954 }, 4995 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB, 4996 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4997 pbn_pericom_PI7C9X7952 }, 4998 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM, 4999 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5000 pbn_pericom_PI7C9X7952 }, 5001 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB, 5002 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5003 pbn_pericom_PI7C9X7954 }, 5004 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM, 5005 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5006 pbn_pericom_PI7C9X7954 }, 5007 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1, 5008 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5009 pbn_pericom_PI7C9X7951 }, 5010 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2, 5011 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5012 pbn_pericom_PI7C9X7952 }, 5013 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2, 5014 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5015 pbn_pericom_PI7C9X7952 }, 5016 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4, 5017 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5018 pbn_pericom_PI7C9X7954 }, 5019 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4, 5020 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5021 pbn_pericom_PI7C9X7954 }, 5022 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S, 5023 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5024 pbn_pericom_PI7C9X7952 }, 5025 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S, 5026 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5027 pbn_pericom_PI7C9X7954 }, 5028 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2, 5029 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5030 pbn_pericom_PI7C9X7952 }, 5031 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2, 5032 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5033 pbn_pericom_PI7C9X7952 }, 5034 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4, 5035 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5036 pbn_pericom_PI7C9X7954 }, 5037 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4, 5038 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5039 pbn_pericom_PI7C9X7954 }, 5040 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM, 5041 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5042 pbn_pericom_PI7C9X7952 }, 5043 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4, 5044 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5045 pbn_pericom_PI7C9X7954 }, 5046 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4, 5047 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5048 pbn_pericom_PI7C9X7954 }, 5049 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8, 5050 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5051 pbn_pericom_PI7C9X7958 }, 5052 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8, 5053 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5054 pbn_pericom_PI7C9X7958 }, 5055 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4, 5056 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5057 pbn_pericom_PI7C9X7954 }, 5058 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8, 5059 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5060 pbn_pericom_PI7C9X7958 }, 5061 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM, 5062 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5063 pbn_pericom_PI7C9X7954 }, 5064 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM, 5065 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5066 pbn_pericom_PI7C9X7958 }, 5067 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM, 5068 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5069 pbn_pericom_PI7C9X7954 }, 5070 /* 5071 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 5072 */ 5073 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 5074 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5075 pbn_b0_1_115200 }, 5076 /* 5077 * ITE 5078 */ 5079 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 5080 PCI_ANY_ID, PCI_ANY_ID, 5081 0, 0, 5082 pbn_b1_bt_1_115200 }, 5083 5084 /* 5085 * IntaShield IS-200 5086 */ 5087 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 5088 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 5089 pbn_b2_2_115200 }, 5090 /* 5091 * IntaShield IS-400 5092 */ 5093 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 5094 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 5095 pbn_b2_4_115200 }, 5096 /* 5097 * BrainBoxes UC-260 5098 */ 5099 { PCI_VENDOR_ID_INTASHIELD, 0x0D21, 5100 PCI_ANY_ID, PCI_ANY_ID, 5101 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5102 pbn_b2_4_115200 }, 5103 { PCI_VENDOR_ID_INTASHIELD, 0x0E34, 5104 PCI_ANY_ID, PCI_ANY_ID, 5105 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5106 pbn_b2_4_115200 }, 5107 /* 5108 * Perle PCI-RAS cards 5109 */ 5110 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5111 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5112 0, 0, pbn_b2_4_921600 }, 5113 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5114 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5115 0, 0, pbn_b2_8_921600 }, 5116 5117 /* 5118 * Mainpine series cards: Fairly standard layout but fools 5119 * parts of the autodetect in some cases and uses otherwise 5120 * unmatched communications subclasses in the PCI Express case 5121 */ 5122 5123 { /* RockForceDUO */ 5124 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5125 PCI_VENDOR_ID_MAINPINE, 0x0200, 5126 0, 0, pbn_b0_2_115200 }, 5127 { /* RockForceQUATRO */ 5128 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5129 PCI_VENDOR_ID_MAINPINE, 0x0300, 5130 0, 0, pbn_b0_4_115200 }, 5131 { /* RockForceDUO+ */ 5132 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5133 PCI_VENDOR_ID_MAINPINE, 0x0400, 5134 0, 0, pbn_b0_2_115200 }, 5135 { /* RockForceQUATRO+ */ 5136 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5137 PCI_VENDOR_ID_MAINPINE, 0x0500, 5138 0, 0, pbn_b0_4_115200 }, 5139 { /* RockForce+ */ 5140 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5141 PCI_VENDOR_ID_MAINPINE, 0x0600, 5142 0, 0, pbn_b0_2_115200 }, 5143 { /* RockForce+ */ 5144 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5145 PCI_VENDOR_ID_MAINPINE, 0x0700, 5146 0, 0, pbn_b0_4_115200 }, 5147 { /* RockForceOCTO+ */ 5148 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5149 PCI_VENDOR_ID_MAINPINE, 0x0800, 5150 0, 0, pbn_b0_8_115200 }, 5151 { /* RockForceDUO+ */ 5152 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5153 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5154 0, 0, pbn_b0_2_115200 }, 5155 { /* RockForceQUARTRO+ */ 5156 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5157 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5158 0, 0, pbn_b0_4_115200 }, 5159 { /* RockForceOCTO+ */ 5160 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5161 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5162 0, 0, pbn_b0_8_115200 }, 5163 { /* RockForceD1 */ 5164 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5165 PCI_VENDOR_ID_MAINPINE, 0x2000, 5166 0, 0, pbn_b0_1_115200 }, 5167 { /* RockForceF1 */ 5168 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5169 PCI_VENDOR_ID_MAINPINE, 0x2100, 5170 0, 0, pbn_b0_1_115200 }, 5171 { /* RockForceD2 */ 5172 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5173 PCI_VENDOR_ID_MAINPINE, 0x2200, 5174 0, 0, pbn_b0_2_115200 }, 5175 { /* RockForceF2 */ 5176 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5177 PCI_VENDOR_ID_MAINPINE, 0x2300, 5178 0, 0, pbn_b0_2_115200 }, 5179 { /* RockForceD4 */ 5180 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5181 PCI_VENDOR_ID_MAINPINE, 0x2400, 5182 0, 0, pbn_b0_4_115200 }, 5183 { /* RockForceF4 */ 5184 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5185 PCI_VENDOR_ID_MAINPINE, 0x2500, 5186 0, 0, pbn_b0_4_115200 }, 5187 { /* RockForceD8 */ 5188 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5189 PCI_VENDOR_ID_MAINPINE, 0x2600, 5190 0, 0, pbn_b0_8_115200 }, 5191 { /* RockForceF8 */ 5192 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5193 PCI_VENDOR_ID_MAINPINE, 0x2700, 5194 0, 0, pbn_b0_8_115200 }, 5195 { /* IQ Express D1 */ 5196 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5197 PCI_VENDOR_ID_MAINPINE, 0x3000, 5198 0, 0, pbn_b0_1_115200 }, 5199 { /* IQ Express F1 */ 5200 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5201 PCI_VENDOR_ID_MAINPINE, 0x3100, 5202 0, 0, pbn_b0_1_115200 }, 5203 { /* IQ Express D2 */ 5204 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5205 PCI_VENDOR_ID_MAINPINE, 0x3200, 5206 0, 0, pbn_b0_2_115200 }, 5207 { /* IQ Express F2 */ 5208 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5209 PCI_VENDOR_ID_MAINPINE, 0x3300, 5210 0, 0, pbn_b0_2_115200 }, 5211 { /* IQ Express D4 */ 5212 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5213 PCI_VENDOR_ID_MAINPINE, 0x3400, 5214 0, 0, pbn_b0_4_115200 }, 5215 { /* IQ Express F4 */ 5216 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5217 PCI_VENDOR_ID_MAINPINE, 0x3500, 5218 0, 0, pbn_b0_4_115200 }, 5219 { /* IQ Express D8 */ 5220 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5221 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5222 0, 0, pbn_b0_8_115200 }, 5223 { /* IQ Express F8 */ 5224 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5225 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5226 0, 0, pbn_b0_8_115200 }, 5227 5228 5229 /* 5230 * PA Semi PA6T-1682M on-chip UART 5231 */ 5232 { PCI_VENDOR_ID_PASEMI, 0xa004, 5233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5234 pbn_pasemi_1682M }, 5235 5236 /* 5237 * National Instruments 5238 */ 5239 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5241 pbn_b1_16_115200 }, 5242 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5244 pbn_b1_8_115200 }, 5245 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5247 pbn_b1_bt_4_115200 }, 5248 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5249 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5250 pbn_b1_bt_2_115200 }, 5251 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5253 pbn_b1_bt_4_115200 }, 5254 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5255 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5256 pbn_b1_bt_2_115200 }, 5257 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5259 pbn_b1_16_115200 }, 5260 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5262 pbn_b1_8_115200 }, 5263 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5265 pbn_b1_bt_4_115200 }, 5266 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5267 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5268 pbn_b1_bt_2_115200 }, 5269 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5271 pbn_b1_bt_4_115200 }, 5272 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5273 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5274 pbn_b1_bt_2_115200 }, 5275 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5276 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5277 pbn_ni8430_2 }, 5278 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5279 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5280 pbn_ni8430_2 }, 5281 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5282 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5283 pbn_ni8430_4 }, 5284 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5285 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5286 pbn_ni8430_4 }, 5287 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5288 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5289 pbn_ni8430_8 }, 5290 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5291 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5292 pbn_ni8430_8 }, 5293 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5294 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5295 pbn_ni8430_16 }, 5296 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5297 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5298 pbn_ni8430_16 }, 5299 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5301 pbn_ni8430_2 }, 5302 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5303 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5304 pbn_ni8430_2 }, 5305 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5307 pbn_ni8430_4 }, 5308 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5309 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5310 pbn_ni8430_4 }, 5311 5312 /* 5313 * MOXA 5314 */ 5315 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E, 5316 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5317 pbn_moxa8250_2p }, 5318 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL, 5319 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5320 pbn_moxa8250_2p }, 5321 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A, 5322 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5323 pbn_moxa8250_4p }, 5324 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL, 5325 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5326 pbn_moxa8250_4p }, 5327 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A, 5328 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5329 pbn_moxa8250_8p }, 5330 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B, 5331 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5332 pbn_moxa8250_8p }, 5333 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A, 5334 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5335 pbn_moxa8250_8p }, 5336 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I, 5337 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5338 pbn_moxa8250_8p }, 5339 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL, 5340 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5341 pbn_moxa8250_2p }, 5342 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A, 5343 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5344 pbn_moxa8250_4p }, 5345 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A, 5346 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5347 pbn_moxa8250_8p }, 5348 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A, 5349 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5350 pbn_moxa8250_8p }, 5351 5352 /* 5353 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5354 */ 5355 { PCI_VENDOR_ID_ADDIDATA, 5356 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5357 PCI_ANY_ID, 5358 PCI_ANY_ID, 5359 0, 5360 0, 5361 pbn_b0_4_115200 }, 5362 5363 { PCI_VENDOR_ID_ADDIDATA, 5364 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5365 PCI_ANY_ID, 5366 PCI_ANY_ID, 5367 0, 5368 0, 5369 pbn_b0_2_115200 }, 5370 5371 { PCI_VENDOR_ID_ADDIDATA, 5372 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5373 PCI_ANY_ID, 5374 PCI_ANY_ID, 5375 0, 5376 0, 5377 pbn_b0_1_115200 }, 5378 5379 { PCI_VENDOR_ID_AMCC, 5380 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5381 PCI_ANY_ID, 5382 PCI_ANY_ID, 5383 0, 5384 0, 5385 pbn_b1_8_115200 }, 5386 5387 { PCI_VENDOR_ID_ADDIDATA, 5388 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5389 PCI_ANY_ID, 5390 PCI_ANY_ID, 5391 0, 5392 0, 5393 pbn_b0_4_115200 }, 5394 5395 { PCI_VENDOR_ID_ADDIDATA, 5396 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5397 PCI_ANY_ID, 5398 PCI_ANY_ID, 5399 0, 5400 0, 5401 pbn_b0_2_115200 }, 5402 5403 { PCI_VENDOR_ID_ADDIDATA, 5404 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5405 PCI_ANY_ID, 5406 PCI_ANY_ID, 5407 0, 5408 0, 5409 pbn_b0_1_115200 }, 5410 5411 { PCI_VENDOR_ID_ADDIDATA, 5412 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5413 PCI_ANY_ID, 5414 PCI_ANY_ID, 5415 0, 5416 0, 5417 pbn_b0_4_115200 }, 5418 5419 { PCI_VENDOR_ID_ADDIDATA, 5420 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5421 PCI_ANY_ID, 5422 PCI_ANY_ID, 5423 0, 5424 0, 5425 pbn_b0_2_115200 }, 5426 5427 { PCI_VENDOR_ID_ADDIDATA, 5428 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5429 PCI_ANY_ID, 5430 PCI_ANY_ID, 5431 0, 5432 0, 5433 pbn_b0_1_115200 }, 5434 5435 { PCI_VENDOR_ID_ADDIDATA, 5436 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5437 PCI_ANY_ID, 5438 PCI_ANY_ID, 5439 0, 5440 0, 5441 pbn_b0_8_115200 }, 5442 5443 { PCI_VENDOR_ID_ADDIDATA, 5444 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5445 PCI_ANY_ID, 5446 PCI_ANY_ID, 5447 0, 5448 0, 5449 pbn_ADDIDATA_PCIe_4_3906250 }, 5450 5451 { PCI_VENDOR_ID_ADDIDATA, 5452 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5453 PCI_ANY_ID, 5454 PCI_ANY_ID, 5455 0, 5456 0, 5457 pbn_ADDIDATA_PCIe_2_3906250 }, 5458 5459 { PCI_VENDOR_ID_ADDIDATA, 5460 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5461 PCI_ANY_ID, 5462 PCI_ANY_ID, 5463 0, 5464 0, 5465 pbn_ADDIDATA_PCIe_1_3906250 }, 5466 5467 { PCI_VENDOR_ID_ADDIDATA, 5468 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5469 PCI_ANY_ID, 5470 PCI_ANY_ID, 5471 0, 5472 0, 5473 pbn_ADDIDATA_PCIe_8_3906250 }, 5474 5475 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5476 PCI_VENDOR_ID_IBM, 0x0299, 5477 0, 0, pbn_b0_bt_2_115200 }, 5478 5479 /* 5480 * other NetMos 9835 devices are most likely handled by the 5481 * parport_serial driver, check drivers/parport/parport_serial.c 5482 * before adding them here. 5483 */ 5484 5485 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5486 0xA000, 0x1000, 5487 0, 0, pbn_b0_1_115200 }, 5488 5489 /* the 9901 is a rebranded 9912 */ 5490 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5491 0xA000, 0x1000, 5492 0, 0, pbn_b0_1_115200 }, 5493 5494 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5495 0xA000, 0x1000, 5496 0, 0, pbn_b0_1_115200 }, 5497 5498 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5499 0xA000, 0x1000, 5500 0, 0, pbn_b0_1_115200 }, 5501 5502 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5503 0xA000, 0x1000, 5504 0, 0, pbn_b0_1_115200 }, 5505 5506 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5507 0xA000, 0x3002, 5508 0, 0, pbn_NETMOS9900_2s_115200 }, 5509 5510 /* 5511 * Best Connectivity and Rosewill PCI Multi I/O cards 5512 */ 5513 5514 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5515 0xA000, 0x1000, 5516 0, 0, pbn_b0_1_115200 }, 5517 5518 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5519 0xA000, 0x3002, 5520 0, 0, pbn_b0_bt_2_115200 }, 5521 5522 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5523 0xA000, 0x3004, 5524 0, 0, pbn_b0_bt_4_115200 }, 5525 /* Intel CE4100 */ 5526 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5527 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5528 pbn_ce4100_1_115200 }, 5529 5530 /* 5531 * Cronyx Omega PCI 5532 */ 5533 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5534 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5535 pbn_omegapci }, 5536 5537 /* 5538 * Broadcom TruManage 5539 */ 5540 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5541 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5542 pbn_brcm_trumanage }, 5543 5544 /* 5545 * AgeStar as-prs2-009 5546 */ 5547 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5548 PCI_ANY_ID, PCI_ANY_ID, 5549 0, 0, pbn_b0_bt_2_115200 }, 5550 5551 /* 5552 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5553 * so not listed here. 5554 */ 5555 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5556 PCI_ANY_ID, PCI_ANY_ID, 5557 0, 0, pbn_b0_bt_4_115200 }, 5558 5559 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5560 PCI_ANY_ID, PCI_ANY_ID, 5561 0, 0, pbn_b0_bt_2_115200 }, 5562 5563 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 5564 PCI_ANY_ID, PCI_ANY_ID, 5565 0, 0, pbn_b0_bt_4_115200 }, 5566 5567 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5568 PCI_ANY_ID, PCI_ANY_ID, 5569 0, 0, pbn_wch382_2 }, 5570 5571 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5572 PCI_ANY_ID, PCI_ANY_ID, 5573 0, 0, pbn_wch384_4 }, 5574 5575 /* Fintek PCI serial cards */ 5576 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5577 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5578 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5579 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A }, 5580 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A }, 5581 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A }, 5582 5583 /* MKS Tenta SCOM-080x serial cards */ 5584 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, 5585 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, 5586 5587 /* Amazon PCI serial device */ 5588 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, 5589 5590 /* 5591 * These entries match devices with class COMMUNICATION_SERIAL, 5592 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5593 */ 5594 { PCI_ANY_ID, PCI_ANY_ID, 5595 PCI_ANY_ID, PCI_ANY_ID, 5596 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5597 0xffff00, pbn_default }, 5598 { PCI_ANY_ID, PCI_ANY_ID, 5599 PCI_ANY_ID, PCI_ANY_ID, 5600 PCI_CLASS_COMMUNICATION_MODEM << 8, 5601 0xffff00, pbn_default }, 5602 { PCI_ANY_ID, PCI_ANY_ID, 5603 PCI_ANY_ID, PCI_ANY_ID, 5604 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5605 0xffff00, pbn_default }, 5606 { 0, } 5607 }; 5608 5609 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5610 pci_channel_state_t state) 5611 { 5612 struct serial_private *priv = pci_get_drvdata(dev); 5613 5614 if (state == pci_channel_io_perm_failure) 5615 return PCI_ERS_RESULT_DISCONNECT; 5616 5617 if (priv) 5618 pciserial_detach_ports(priv); 5619 5620 pci_disable_device(dev); 5621 5622 return PCI_ERS_RESULT_NEED_RESET; 5623 } 5624 5625 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5626 { 5627 int rc; 5628 5629 rc = pci_enable_device(dev); 5630 5631 if (rc) 5632 return PCI_ERS_RESULT_DISCONNECT; 5633 5634 pci_restore_state(dev); 5635 pci_save_state(dev); 5636 5637 return PCI_ERS_RESULT_RECOVERED; 5638 } 5639 5640 static void serial8250_io_resume(struct pci_dev *dev) 5641 { 5642 struct serial_private *priv = pci_get_drvdata(dev); 5643 struct serial_private *new; 5644 5645 if (!priv) 5646 return; 5647 5648 new = pciserial_init_ports(dev, priv->board); 5649 if (!IS_ERR(new)) { 5650 pci_set_drvdata(dev, new); 5651 kfree(priv); 5652 } 5653 } 5654 5655 static const struct pci_error_handlers serial8250_err_handler = { 5656 .error_detected = serial8250_io_error_detected, 5657 .slot_reset = serial8250_io_slot_reset, 5658 .resume = serial8250_io_resume, 5659 }; 5660 5661 static struct pci_driver serial_pci_driver = { 5662 .name = "serial", 5663 .probe = pciserial_init_one, 5664 .remove = pciserial_remove_one, 5665 .driver = { 5666 .pm = &pciserial_pm_ops, 5667 }, 5668 .id_table = serial_pci_tbl, 5669 .err_handler = &serial8250_err_handler, 5670 }; 5671 5672 module_pci_driver(serial_pci_driver); 5673 5674 MODULE_LICENSE("GPL"); 5675 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5676 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5677